drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Zou Nan hai <[email protected]>
  26  *    Xiang Hai hao<[email protected]>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "i915_gem_render_state.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39 #include "intel_workarounds.h"
  40
  41 /* Rough estimate of the typical request size, performing a flush,
  42  * set-context and then emitting the batch.
  43  */
  44 #define LEGACY_REQUEST_SIZE 200
  45
  46 static unsigned int __intel_ring_space(unsigned int head,
  47                                        unsigned int tail,
  48                                        unsigned int size)
  49 {
  50         /*
  51          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  52          * same cacheline, the Head Pointer must not be greater than the Tail
  53          * Pointer."
  54          */
  55         GEM_BUG_ON(!is_power_of_2(size));
  56         return (head - tail - CACHELINE_BYTES) & (size - 1);
  57 }
  58
  59 unsigned int intel_ring_update_space(struct intel_ring *ring)
  60 {
  61         unsigned int space;
  62
  63         space = __intel_ring_space(ring->head, ring->emit, ring->size);
  64
  65         ring->space = space;
  66         return space;
  67 }
  68
  69 static int
  70 gen2_render_ring_flush(struct i915_request *rq, u32 mode)
  71 {
  72         u32 cmd, *cs;
  73
  74         cmd = MI_FLUSH;
  75
  76         if (mode & EMIT_INVALIDATE)
  77                 cmd |= MI_READ_FLUSH;
  78
  79         cs = intel_ring_begin(rq, 2);
  80         if (IS_ERR(cs))
  81                 return PTR_ERR(cs);
  82
  83         *cs++ = cmd;
  84         *cs++ = MI_NOOP;
  85         intel_ring_advance(rq, cs);
  86
  87         return 0;
  88 }
  89
  90 static int
  91 gen4_render_ring_flush(struct i915_request *rq, u32 mode)
  92 {
  93         u32 cmd, *cs;
  94
  95         /*
  96          * read/write caches:
  97          *
  98          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  99          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 100          * also flushed at 2d versus 3d pipeline switches.
 101          *
 102          * read-only caches:
 103          *
 104          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 105          * MI_READ_FLUSH is set, and is always flushed on 965.
 106          *
 107          * I915_GEM_DOMAIN_COMMAND may not exist?
 108          *
 109          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 110          * invalidated when MI_EXE_FLUSH is set.
 111          *
 112          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 113          * invalidated with every MI_FLUSH.
 114          *
 115          * TLBs:
 116          *
 117          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 118          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 119          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 120          * are flushed at any MI_FLUSH.
 121          */
 122
 123         cmd = MI_FLUSH;
 124         if (mode & EMIT_INVALIDATE) {
 125                 cmd |= MI_EXE_FLUSH;
 126                 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
 127                         cmd |= MI_INVALIDATE_ISP;
 128         }
 129
 130         cs = intel_ring_begin(rq, 2);
 131         if (IS_ERR(cs))
 132                 return PTR_ERR(cs);
 133
 134         *cs++ = cmd;
 135         *cs++ = MI_NOOP;
 136         intel_ring_advance(rq, cs);
 137
 138         return 0;
 139 }
 140
 141 /*
 142  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 143  * implementing two workarounds on gen6.  From section 1.4.7.1
 144  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 145  *
 146  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 147  * produced by non-pipelined state commands), software needs to first
 148  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 149  * 0.
 150  *
 151  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 152  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 153  *
 154  * And the workaround for these two requires this workaround first:
 155  *
 156  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 157  * BEFORE the pipe-control with a post-sync op and no write-cache
 158  * flushes.
 159  *
 160  * And this last workaround is tricky because of the requirements on
 161  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 162  * volume 2 part 1:
 163  *
 164  *     "1 of the following must also be set:
 165  *      - Render Target Cache Flush Enable ([12] of DW1)
 166  *      - Depth Cache Flush Enable ([0] of DW1)
 167  *      - Stall at Pixel Scoreboard ([1] of DW1)
 168  *      - Depth Stall ([13] of DW1)
 169  *      - Post-Sync Operation ([13] of DW1)
 170  *      - Notify Enable ([8] of DW1)"
 171  *
 172  * The cache flushes require the workaround flush that triggered this
 173  * one, so we can't use it.  Depth stall would trigger the same.
 174  * Post-sync nonzero is what triggered this second workaround, so we
 175  * can't use that one either.  Notify enable is IRQs, which aren't
 176  * really our business.  That leaves only stall at scoreboard.
 177  */
 178 static int
 179 intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 180 {
 181         u32 scratch_addr =
 182                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 183         u32 *cs;
 184
 185         cs = intel_ring_begin(rq, 6);
 186         if (IS_ERR(cs))
 187                 return PTR_ERR(cs);
 188
 189         *cs++ = GFX_OP_PIPE_CONTROL(5);
 190         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 191         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 192         *cs++ = 0; /* low dword */
 193         *cs++ = 0; /* high dword */
 194         *cs++ = MI_NOOP;
 195         intel_ring_advance(rq, cs);
 196
 197         cs = intel_ring_begin(rq, 6);
 198         if (IS_ERR(cs))
 199                 return PTR_ERR(cs);
 200
 201         *cs++ = GFX_OP_PIPE_CONTROL(5);
 202         *cs++ = PIPE_CONTROL_QW_WRITE;
 203         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 204         *cs++ = 0;
 205         *cs++ = 0;
 206         *cs++ = MI_NOOP;
 207         intel_ring_advance(rq, cs);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 214 {
 215         u32 scratch_addr =
 216                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 217         u32 *cs, flags = 0;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(rq);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (mode & EMIT_FLUSH) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (mode & EMIT_INVALIDATE) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         cs = intel_ring_begin(rq, 4);
 252         if (IS_ERR(cs))
 253                 return PTR_ERR(cs);
 254
 255         *cs++ = GFX_OP_PIPE_CONTROL(4);
 256         *cs++ = flags;
 257         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 258         *cs++ = 0;
 259         intel_ring_advance(rq, cs);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 266 {
 267         u32 *cs;
 268
 269         cs = intel_ring_begin(rq, 4);
 270         if (IS_ERR(cs))
 271                 return PTR_ERR(cs);
 272
 273         *cs++ = GFX_OP_PIPE_CONTROL(4);
 274         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 275         *cs++ = 0;
 276         *cs++ = 0;
 277         intel_ring_advance(rq, cs);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 284 {
 285         u32 scratch_addr =
 286                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 287         u32 *cs, flags = 0;
 288
 289         /*
 290          * Ensure that any following seqno writes only happen when the render
 291          * cache is indeed flushed.
 292          *
 293          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 294          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 295          * don't try to be clever and just set it unconditionally.
 296          */
 297         flags |= PIPE_CONTROL_CS_STALL;
 298
 299         /* Just flush everything.  Experiments have shown that reducing the
 300          * number of bits based on the write domains has little performance
 301          * impact.
 302          */
 303         if (mode & EMIT_FLUSH) {
 304                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 305                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 306                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 307                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 308         }
 309         if (mode & EMIT_INVALIDATE) {
 310                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 311                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 312                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 324
 325                 /* Workaround: we must issue a pipe_control with CS-stall bit
 326                  * set before a pipe_control command that has the state cache
 327                  * invalidate bit set. */
 328                 gen7_render_ring_cs_stall_wa(rq);
 329         }
 330
 331         cs = intel_ring_begin(rq, 4);
 332         if (IS_ERR(cs))
 333                 return PTR_ERR(cs);
 334
 335         *cs++ = GFX_OP_PIPE_CONTROL(4);
 336         *cs++ = flags;
 337         *cs++ = scratch_addr;
 338         *cs++ = 0;
 339         intel_ring_advance(rq, cs);
 340
 341         return 0;
 342 }
 343
 344 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 345 {
 346         struct drm_i915_private *dev_priv = engine->i915;
 347         u32 addr;
 348
 349         addr = dev_priv->status_page_dmah->busaddr;
 350         if (INTEL_GEN(dev_priv) >= 4)
 351                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 352         I915_WRITE(HWS_PGA, addr);
 353 }
 354
 355 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 356 {
 357         struct drm_i915_private *dev_priv = engine->i915;
 358         i915_reg_t mmio;
 359
 360         /* The ring status page addresses are no longer next to the rest of
 361          * the ring registers as of gen7.
 362          */
 363         if (IS_GEN7(dev_priv)) {
 364                 switch (engine->id) {
 365                 /*
 366                  * No more rings exist on Gen7. Default case is only to shut up
 367                  * gcc switch check warning.
 368                  */
 369                 default:
 370                         GEM_BUG_ON(engine->id);
 371                 case RCS:
 372                         mmio = RENDER_HWS_PGA_GEN7;
 373                         break;
 374                 case BCS:
 375                         mmio = BLT_HWS_PGA_GEN7;
 376                         break;
 377                 case VCS:
 378                         mmio = BSD_HWS_PGA_GEN7;
 379                         break;
 380                 case VECS:
 381                         mmio = VEBOX_HWS_PGA_GEN7;
 382                         break;
 383                 }
 384         } else if (IS_GEN6(dev_priv)) {
 385                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 386         } else {
 387                 mmio = RING_HWS_PGA(engine->mmio_base);
 388         }
 389
 390         if (INTEL_GEN(dev_priv) >= 6)
 391                 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 392
 393         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 394         POSTING_READ(mmio);
 395
 396         /* Flush the TLB for this page */
 397         if (IS_GEN(dev_priv, 6, 7)) {
 398                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 399
 400                 /* ring should be idle before issuing a sync flush*/
 401                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 402
 403                 I915_WRITE(reg,
 404                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 405                                               INSTPM_SYNC_FLUSH));
 406                 if (intel_wait_for_register(dev_priv,
 407                                             reg, INSTPM_SYNC_FLUSH, 0,
 408                                             1000))
 409                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 410                                   engine->name);
 411         }
 412 }
 413
 414 static bool stop_ring(struct intel_engine_cs *engine)
 415 {
 416         struct drm_i915_private *dev_priv = engine->i915;
 417
 418         if (INTEL_GEN(dev_priv) > 2) {
 419                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 420                 if (intel_wait_for_register(dev_priv,
 421                                             RING_MI_MODE(engine->mmio_base),
 422                                             MODE_IDLE,
 423                                             MODE_IDLE,
 424                                             1000)) {
 425                         DRM_ERROR("%s : timed out trying to stop ring\n",
 426                                   engine->name);
 427                         /* Sometimes we observe that the idle flag is not
 428                          * set even though the ring is empty. So double
 429                          * check before giving up.
 430                          */
 431                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 432                                 return false;
 433                 }
 434         }
 435
 436         I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
 437
 438         I915_WRITE_HEAD(engine, 0);
 439         I915_WRITE_TAIL(engine, 0);
 440
 441         /* The ring must be empty before it is disabled */
 442         I915_WRITE_CTL(engine, 0);
 443
 444         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 445 }
 446
 447 static int init_ring_common(struct intel_engine_cs *engine)
 448 {
 449         struct drm_i915_private *dev_priv = engine->i915;
 450         struct intel_ring *ring = engine->buffer;
 451         int ret = 0;
 452
 453         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 454
 455         if (!stop_ring(engine)) {
 456                 /* G45 ring initialization often fails to reset head to zero */
 457                 DRM_DEBUG_DRIVER("%s head not reset to zero "
 458                                 "ctl %08x head %08x tail %08x start %08x\n",
 459                                 engine->name,
 460                                 I915_READ_CTL(engine),
 461                                 I915_READ_HEAD(engine),
 462                                 I915_READ_TAIL(engine),
 463                                 I915_READ_START(engine));
 464
 465                 if (!stop_ring(engine)) {
 466                         DRM_ERROR("failed to set %s head to zero "
 467                                   "ctl %08x head %08x tail %08x start %08x\n",
 468                                   engine->name,
 469                                   I915_READ_CTL(engine),
 470                                   I915_READ_HEAD(engine),
 471                                   I915_READ_TAIL(engine),
 472                                   I915_READ_START(engine));
 473                         ret = -EIO;
 474                         goto out;
 475                 }
 476         }
 477
 478         if (HWS_NEEDS_PHYSICAL(dev_priv))
 479                 ring_setup_phys_status_page(engine);
 480         else
 481                 intel_ring_setup_status_page(engine);
 482
 483         intel_engine_reset_breadcrumbs(engine);
 484
 485         /* Enforce ordering by reading HEAD register back */
 486         I915_READ_HEAD(engine);
 487
 488         /* Initialize the ring. This must happen _after_ we've cleared the ring
 489          * registers with the above sequence (the readback of the HEAD registers
 490          * also enforces ordering), otherwise the hw might lose the new ring
 491          * register values. */
 492         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 493
 494         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 495         if (I915_READ_HEAD(engine))
 496                 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
 497                                  engine->name, I915_READ_HEAD(engine));
 498
 499         /* Check that the ring offsets point within the ring! */
 500         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
 501         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
 502
 503         intel_ring_update_space(ring);
 504         I915_WRITE_HEAD(engine, ring->head);
 505         I915_WRITE_TAIL(engine, ring->tail);
 506         (void)I915_READ_TAIL(engine);
 507
 508         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 509
 510         /* If the head is still not zero, the ring is dead */
 511         if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
 512                                     RING_VALID, RING_VALID,
 513                                     50)) {
 514                 DRM_ERROR("%s initialization failed "
 515                           "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
 516                           engine->name,
 517                           I915_READ_CTL(engine),
 518                           I915_READ_CTL(engine) & RING_VALID,
 519                           I915_READ_HEAD(engine), ring->head,
 520                           I915_READ_TAIL(engine), ring->tail,
 521                           I915_READ_START(engine),
 522                           i915_ggtt_offset(ring->vma));
 523                 ret = -EIO;
 524                 goto out;
 525         }
 526
 527         intel_engine_init_hangcheck(engine);
 528
 529         if (INTEL_GEN(dev_priv) > 2)
 530                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 531
 532 out:
 533         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 534
 535         return ret;
 536 }
 537
 538 static struct i915_request *reset_prepare(struct intel_engine_cs *engine)
 539 {
 540         intel_engine_stop_cs(engine);
 541
 542         if (engine->irq_seqno_barrier)
 543                 engine->irq_seqno_barrier(engine);
 544
 545         return i915_gem_find_active_request(engine);
 546 }
 547
 548 static void skip_request(struct i915_request *rq)
 549 {
 550         void *vaddr = rq->ring->vaddr;
 551         u32 head;
 552
 553         head = rq->infix;
 554         if (rq->postfix < head) {
 555                 memset32(vaddr + head, MI_NOOP,
 556                          (rq->ring->size - head) / sizeof(u32));
 557                 head = 0;
 558         }
 559         memset32(vaddr + head, MI_NOOP, (rq->postfix - head) / sizeof(u32));
 560 }
 561
 562 static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq)
 563 {
 564         GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0);
 565
 566         /*
 567          * Try to restore the logical GPU state to match the continuation
 568          * of the request queue. If we skip the context/PD restore, then
 569          * the next request may try to execute assuming that its context
 570          * is valid and loaded on the GPU and so may try to access invalid
 571          * memory, prompting repeated GPU hangs.
 572          *
 573          * If the request was guilty, we still restore the logical state
 574          * in case the next request requires it (e.g. the aliasing ppgtt),
 575          * but skip over the hung batch.
 576          *
 577          * If the request was innocent, we try to replay the request with
 578          * the restored context.
 579          */
 580         if (rq) {
 581                 /* If the rq hung, jump to its breadcrumb and skip the batch */
 582                 rq->ring->head = intel_ring_wrap(rq->ring, rq->head);
 583                 if (rq->fence.error == -EIO)
 584                         skip_request(rq);
 585         }
 586 }
 587
 588 static void reset_finish(struct intel_engine_cs *engine)
 589 {
 590 }
 591
 592 static int intel_rcs_ctx_init(struct i915_request *rq)
 593 {
 594         int ret;
 595
 596         ret = intel_ctx_workarounds_emit(rq);
 597         if (ret != 0)
 598                 return ret;
 599
 600         ret = i915_gem_render_state_emit(rq);
 601         if (ret)
 602                 return ret;
 603
 604         return 0;
 605 }
 606
 607 static int init_render_ring(struct intel_engine_cs *engine)
 608 {
 609         struct drm_i915_private *dev_priv = engine->i915;
 610         int ret = init_ring_common(engine);
 611         if (ret)
 612                 return ret;
 613
 614         intel_whitelist_workarounds_apply(engine);
 615
 616         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 617         if (IS_GEN(dev_priv, 4, 6))
 618                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 619
 620         /* We need to disable the AsyncFlip performance optimisations in order
 621          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 622          * programmed to '1' on all products.
 623          *
 624          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 625          */
 626         if (IS_GEN(dev_priv, 6, 7))
 627                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 628
 629         /* Required for the hardware to program scanline values for waiting */
 630         /* WaEnableFlushTlbInvalidationMode:snb */
 631         if (IS_GEN6(dev_priv))
 632                 I915_WRITE(GFX_MODE,
 633                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 634
 635         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 636         if (IS_GEN7(dev_priv))
 637                 I915_WRITE(GFX_MODE_GEN7,
 638                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 639                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 640
 641         if (IS_GEN6(dev_priv)) {
 642                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 643                  * "If this bit is set, STCunit will have LRA as replacement
 644                  *  policy. [...] This bit must be reset.  LRA replacement
 645                  *  policy is not supported."
 646                  */
 647                 I915_WRITE(CACHE_MODE_0,
 648                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 649         }
 650
 651         if (IS_GEN(dev_priv, 6, 7))
 652                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 653
 654         if (INTEL_GEN(dev_priv) >= 6)
 655                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 656
 657         return 0;
 658 }
 659
 660 static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
 661 {
 662         struct drm_i915_private *dev_priv = rq->i915;
 663         struct intel_engine_cs *engine;
 664         enum intel_engine_id id;
 665         int num_rings = 0;
 666
 667         for_each_engine(engine, dev_priv, id) {
 668                 i915_reg_t mbox_reg;
 669
 670                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
 671                         continue;
 672
 673                 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
 674                 if (i915_mmio_reg_valid(mbox_reg)) {
 675                         *cs++ = MI_LOAD_REGISTER_IMM(1);
 676                         *cs++ = i915_mmio_reg_offset(mbox_reg);
 677                         *cs++ = rq->global_seqno;
 678                         num_rings++;
 679                 }
 680         }
 681         if (num_rings & 1)
 682                 *cs++ = MI_NOOP;
 683
 684         return cs;
 685 }
 686
 687 static void cancel_requests(struct intel_engine_cs *engine)
 688 {
 689         struct i915_request *request;
 690         unsigned long flags;
 691
 692         spin_lock_irqsave(&engine->timeline.lock, flags);
 693
 694         /* Mark all submitted requests as skipped. */
 695         list_for_each_entry(request, &engine->timeline.requests, link) {
 696                 GEM_BUG_ON(!request->global_seqno);
 697                 if (!i915_request_completed(request))
 698                         dma_fence_set_error(&request->fence, -EIO);
 699         }
 700         /* Remaining _unready_ requests will be nop'ed when submitted */
 701
 702         spin_unlock_irqrestore(&engine->timeline.lock, flags);
 703 }
 704
 705 static void i9xx_submit_request(struct i915_request *request)
 706 {
 707         struct drm_i915_private *dev_priv = request->i915;
 708
 709         i915_request_submit(request);
 710
 711         I915_WRITE_TAIL(request->engine,
 712                         intel_ring_set_tail(request->ring, request->tail));
 713 }
 714
 715 static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 716 {
 717         *cs++ = MI_STORE_DWORD_INDEX;
 718         *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
 719         *cs++ = rq->global_seqno;
 720         *cs++ = MI_USER_INTERRUPT;
 721
 722         rq->tail = intel_ring_offset(rq, cs);
 723         assert_ring_tail_valid(rq->ring, rq->tail);
 724 }
 725
 726 static const int i9xx_emit_breadcrumb_sz = 4;
 727
 728 static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 729 {
 730         return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
 731 }
 732
 733 static int
 734 gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
 735 {
 736         u32 dw1 = MI_SEMAPHORE_MBOX |
 737                   MI_SEMAPHORE_COMPARE |
 738                   MI_SEMAPHORE_REGISTER;
 739         u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
 740         u32 *cs;
 741
 742         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 743
 744         cs = intel_ring_begin(rq, 4);
 745         if (IS_ERR(cs))
 746                 return PTR_ERR(cs);
 747
 748         *cs++ = dw1 | wait_mbox;
 749         /* Throughout all of the GEM code, seqno passed implies our current
 750          * seqno is >= the last seqno executed. However for hardware the
 751          * comparison is strictly greater than.
 752          */
 753         *cs++ = signal->global_seqno - 1;
 754         *cs++ = 0;
 755         *cs++ = MI_NOOP;
 756         intel_ring_advance(rq, cs);
 757
 758         return 0;
 759 }
 760
 761 static void
 762 gen5_seqno_barrier(struct intel_engine_cs *engine)
 763 {
 764         /* MI_STORE are internally buffered by the GPU and not flushed
 765          * either by MI_FLUSH or SyncFlush or any other combination of
 766          * MI commands.
 767          *
 768          * "Only the submission of the store operation is guaranteed.
 769          * The write result will be complete (coherent) some time later
 770          * (this is practically a finite period but there is no guaranteed
 771          * latency)."
 772          *
 773          * Empirically, we observe that we need a delay of at least 75us to
 774          * be sure that the seqno write is visible by the CPU.
 775          */
 776         usleep_range(125, 250);
 777 }
 778
 779 static void
 780 gen6_seqno_barrier(struct intel_engine_cs *engine)
 781 {
 782         struct drm_i915_private *dev_priv = engine->i915;
 783
 784         /* Workaround to force correct ordering between irq and seqno writes on
 785          * ivb (and maybe also on snb) by reading from a CS register (like
 786          * ACTHD) before reading the status page.
 787          *
 788          * Note that this effectively stalls the read by the time it takes to
 789          * do a memory transaction, which more or less ensures that the write
 790          * from the GPU has sufficient time to invalidate the CPU cacheline.
 791          * Alternatively we could delay the interrupt from the CS ring to give
 792          * the write time to land, but that would incur a delay after every
 793          * batch i.e. much more frequent than a delay when waiting for the
 794          * interrupt (with the same net latency).
 795          *
 796          * Also note that to prevent whole machine hangs on gen7, we have to
 797          * take the spinlock to guard against concurrent cacheline access.
 798          */
 799         spin_lock_irq(&dev_priv->uncore.lock);
 800         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
 801         spin_unlock_irq(&dev_priv->uncore.lock);
 802 }
 803
 804 static void
 805 gen5_irq_enable(struct intel_engine_cs *engine)
 806 {
 807         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
 808 }
 809
 810 static void
 811 gen5_irq_disable(struct intel_engine_cs *engine)
 812 {
 813         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
 814 }
 815
 816 static void
 817 i9xx_irq_enable(struct intel_engine_cs *engine)
 818 {
 819         struct drm_i915_private *dev_priv = engine->i915;
 820
 821         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 822         I915_WRITE(IMR, dev_priv->irq_mask);
 823         POSTING_READ_FW(RING_IMR(engine->mmio_base));
 824 }
 825
 826 static void
 827 i9xx_irq_disable(struct intel_engine_cs *engine)
 828 {
 829         struct drm_i915_private *dev_priv = engine->i915;
 830
 831         dev_priv->irq_mask |= engine->irq_enable_mask;
 832         I915_WRITE(IMR, dev_priv->irq_mask);
 833 }
 834
 835 static void
 836 i8xx_irq_enable(struct intel_engine_cs *engine)
 837 {
 838         struct drm_i915_private *dev_priv = engine->i915;
 839
 840         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 841         I915_WRITE16(IMR, dev_priv->irq_mask);
 842         POSTING_READ16(RING_IMR(engine->mmio_base));
 843 }
 844
 845 static void
 846 i8xx_irq_disable(struct intel_engine_cs *engine)
 847 {
 848         struct drm_i915_private *dev_priv = engine->i915;
 849
 850         dev_priv->irq_mask |= engine->irq_enable_mask;
 851         I915_WRITE16(IMR, dev_priv->irq_mask);
 852 }
 853
 854 static int
 855 bsd_ring_flush(struct i915_request *rq, u32 mode)
 856 {
 857         u32 *cs;
 858
 859         cs = intel_ring_begin(rq, 2);
 860         if (IS_ERR(cs))
 861                 return PTR_ERR(cs);
 862
 863         *cs++ = MI_FLUSH;
 864         *cs++ = MI_NOOP;
 865         intel_ring_advance(rq, cs);
 866         return 0;
 867 }
 868
 869 static void
 870 gen6_irq_enable(struct intel_engine_cs *engine)
 871 {
 872         struct drm_i915_private *dev_priv = engine->i915;
 873
 874         I915_WRITE_IMR(engine,
 875                        ~(engine->irq_enable_mask |
 876                          engine->irq_keep_mask));
 877         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 878 }
 879
 880 static void
 881 gen6_irq_disable(struct intel_engine_cs *engine)
 882 {
 883         struct drm_i915_private *dev_priv = engine->i915;
 884
 885         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 886         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 887 }
 888
 889 static void
 890 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
 891 {
 892         struct drm_i915_private *dev_priv = engine->i915;
 893
 894         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
 895         gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
 896 }
 897
 898 static void
 899 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 900 {
 901         struct drm_i915_private *dev_priv = engine->i915;
 902
 903         I915_WRITE_IMR(engine, ~0);
 904         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 905 }
 906
 907 static int
 908 i965_emit_bb_start(struct i915_request *rq,
 909                    u64 offset, u32 length,
 910                    unsigned int dispatch_flags)
 911 {
 912         u32 *cs;
 913
 914         cs = intel_ring_begin(rq, 2);
 915         if (IS_ERR(cs))
 916                 return PTR_ERR(cs);
 917
 918         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
 919                 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
 920         *cs++ = offset;
 921         intel_ring_advance(rq, cs);
 922
 923         return 0;
 924 }
 925
 926 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 927 #define I830_BATCH_LIMIT (256*1024)
 928 #define I830_TLB_ENTRIES (2)
 929 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 930 static int
 931 i830_emit_bb_start(struct i915_request *rq,
 932                    u64 offset, u32 len,
 933                    unsigned int dispatch_flags)
 934 {
 935         u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
 936
 937         cs = intel_ring_begin(rq, 6);
 938         if (IS_ERR(cs))
 939                 return PTR_ERR(cs);
 940
 941         /* Evict the invalid PTE TLBs */
 942         *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
 943         *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
 944         *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
 945         *cs++ = cs_offset;
 946         *cs++ = 0xdeadbeef;
 947         *cs++ = MI_NOOP;
 948         intel_ring_advance(rq, cs);
 949
 950         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
 951                 if (len > I830_BATCH_LIMIT)
 952                         return -ENOSPC;
 953
 954                 cs = intel_ring_begin(rq, 6 + 2);
 955                 if (IS_ERR(cs))
 956                         return PTR_ERR(cs);
 957
 958                 /* Blit the batch (which has now all relocs applied) to the
 959                  * stable batch scratch bo area (so that the CS never
 960                  * stumbles over its tlb invalidation bug) ...
 961                  */
 962                 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
 963                 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
 964                 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
 965                 *cs++ = cs_offset;
 966                 *cs++ = 4096;
 967                 *cs++ = offset;
 968
 969                 *cs++ = MI_FLUSH;
 970                 *cs++ = MI_NOOP;
 971                 intel_ring_advance(rq, cs);
 972
 973                 /* ... and execute it. */
 974                 offset = cs_offset;
 975         }
 976
 977         cs = intel_ring_begin(rq, 2);
 978         if (IS_ERR(cs))
 979                 return PTR_ERR(cs);
 980
 981         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
 982         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
 983                 MI_BATCH_NON_SECURE);
 984         intel_ring_advance(rq, cs);
 985
 986         return 0;
 987 }
 988
 989 static int
 990 i915_emit_bb_start(struct i915_request *rq,
 991                    u64 offset, u32 len,
 992                    unsigned int dispatch_flags)
 993 {
 994         u32 *cs;
 995
 996         cs = intel_ring_begin(rq, 2);
 997         if (IS_ERR(cs))
 998                 return PTR_ERR(cs);
 999
1000         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1001         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1002                 MI_BATCH_NON_SECURE);
1003         intel_ring_advance(rq, cs);
1004
1005         return 0;
1006 }
1007
1008
1009
1010 int intel_ring_pin(struct intel_ring *ring,
1011                    struct drm_i915_private *i915,
1012                    unsigned int offset_bias)
1013 {
1014         enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1015         struct i915_vma *vma = ring->vma;
1016         unsigned int flags;
1017         void *addr;
1018         int ret;
1019
1020         GEM_BUG_ON(ring->vaddr);
1021
1022
1023         flags = PIN_GLOBAL;
1024         if (offset_bias)
1025                 flags |= PIN_OFFSET_BIAS | offset_bias;
1026         if (vma->obj->stolen)
1027                 flags |= PIN_MAPPABLE;
1028         else
1029                 flags |= PIN_HIGH;
1030
1031         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1032                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1033                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1034                 else
1035                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1036                 if (unlikely(ret))
1037                         return ret;
1038         }
1039
1040         ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1041         if (unlikely(ret))
1042                 return ret;
1043
1044         if (i915_vma_is_map_and_fenceable(vma))
1045                 addr = (void __force *)i915_vma_pin_iomap(vma);
1046         else
1047                 addr = i915_gem_object_pin_map(vma->obj, map);
1048         if (IS_ERR(addr))
1049                 goto err;
1050
1051         vma->obj->pin_global++;
1052
1053         ring->vaddr = addr;
1054         return 0;
1055
1056 err:
1057         i915_vma_unpin(vma);
1058         return PTR_ERR(addr);
1059 }
1060
1061 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1062 {
1063         GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
1064
1065         ring->tail = tail;
1066         ring->head = tail;
1067         ring->emit = tail;
1068         intel_ring_update_space(ring);
1069 }
1070
1071 void intel_ring_unpin(struct intel_ring *ring)
1072 {
1073         GEM_BUG_ON(!ring->vma);
1074         GEM_BUG_ON(!ring->vaddr);
1075
1076         /* Discard any unused bytes beyond that submitted to hw. */
1077         intel_ring_reset(ring, ring->tail);
1078
1079         if (i915_vma_is_map_and_fenceable(ring->vma))
1080                 i915_vma_unpin_iomap(ring->vma);
1081         else
1082                 i915_gem_object_unpin_map(ring->vma->obj);
1083         ring->vaddr = NULL;
1084
1085         ring->vma->obj->pin_global--;
1086         i915_vma_unpin(ring->vma);
1087 }
1088
1089 static struct i915_vma *
1090 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1091 {
1092         struct drm_i915_gem_object *obj;
1093         struct i915_vma *vma;
1094
1095         obj = i915_gem_object_create_stolen(dev_priv, size);
1096         if (!obj)
1097                 obj = i915_gem_object_create_internal(dev_priv, size);
1098         if (IS_ERR(obj))
1099                 return ERR_CAST(obj);
1100
1101         /* mark ring buffers as read-only from GPU side by default */
1102         obj->gt_ro = 1;
1103
1104         vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
1105         if (IS_ERR(vma))
1106                 goto err;
1107
1108         return vma;
1109
1110 err:
1111         i915_gem_object_put(obj);
1112         return vma;
1113 }
1114
1115 struct intel_ring *
1116 intel_engine_create_ring(struct intel_engine_cs *engine,
1117                          struct i915_timeline *timeline,
1118                          int size)
1119 {
1120         struct intel_ring *ring;
1121         struct i915_vma *vma;
1122
1123         GEM_BUG_ON(!is_power_of_2(size));
1124         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1125         GEM_BUG_ON(timeline == &engine->timeline);
1126         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1127
1128         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1129         if (!ring)
1130                 return ERR_PTR(-ENOMEM);
1131
1132         INIT_LIST_HEAD(&ring->request_list);
1133         ring->timeline = i915_timeline_get(timeline);
1134
1135         ring->size = size;
1136         /* Workaround an erratum on the i830 which causes a hang if
1137          * the TAIL pointer points to within the last 2 cachelines
1138          * of the buffer.
1139          */
1140         ring->effective_size = size;
1141         if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1142                 ring->effective_size -= 2 * CACHELINE_BYTES;
1143
1144         intel_ring_update_space(ring);
1145
1146         vma = intel_ring_create_vma(engine->i915, size);
1147         if (IS_ERR(vma)) {
1148                 kfree(ring);
1149                 return ERR_CAST(vma);
1150         }
1151         ring->vma = vma;
1152
1153         return ring;
1154 }
1155
1156 void
1157 intel_ring_free(struct intel_ring *ring)
1158 {
1159         struct drm_i915_gem_object *obj = ring->vma->obj;
1160
1161         i915_vma_close(ring->vma);
1162         __i915_gem_object_release_unless_active(obj);
1163
1164         i915_timeline_put(ring->timeline);
1165         kfree(ring);
1166 }
1167
1168 static void intel_ring_context_destroy(struct intel_context *ce)
1169 {
1170         GEM_BUG_ON(ce->pin_count);
1171
1172         if (!ce->state)
1173                 return;
1174
1175         GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1176         i915_gem_object_put(ce->state->obj);
1177 }
1178
1179 static int __context_pin_ppgtt(struct i915_gem_context *ctx)
1180 {
1181         struct i915_hw_ppgtt *ppgtt;
1182         int err = 0;
1183
1184         ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1185         if (ppgtt)
1186                 err = gen6_ppgtt_pin(ppgtt);
1187
1188         return err;
1189 }
1190
1191 static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
1192 {
1193         struct i915_hw_ppgtt *ppgtt;
1194
1195         ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1196         if (ppgtt)
1197                 gen6_ppgtt_unpin(ppgtt);
1198 }
1199
1200 static int __context_pin(struct intel_context *ce)
1201 {
1202         struct i915_vma *vma;
1203         int err;
1204
1205         vma = ce->state;
1206         if (!vma)
1207                 return 0;
1208
1209         /*
1210          * Clear this page out of any CPU caches for coherent swap-in/out.
1211          * We only want to do this on the first bind so that we do not stall
1212          * on an active context (which by nature is already on the GPU).
1213          */
1214         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1215                 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1216                 if (err)
1217                         return err;
1218         }
1219
1220         err = i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1221                            PIN_GLOBAL | PIN_HIGH);
1222         if (err)
1223                 return err;
1224
1225         /*
1226          * And mark is as a globally pinned object to let the shrinker know
1227          * it cannot reclaim the object until we release it.
1228          */
1229         vma->obj->pin_global++;
1230
1231         return 0;
1232 }
1233
1234 static void __context_unpin(struct intel_context *ce)
1235 {
1236         struct i915_vma *vma;
1237
1238         vma = ce->state;
1239         if (!vma)
1240                 return;
1241
1242         vma->obj->pin_global--;
1243         i915_vma_unpin(vma);
1244 }
1245
1246 static void intel_ring_context_unpin(struct intel_context *ce)
1247 {
1248         __context_unpin_ppgtt(ce->gem_context);
1249         __context_unpin(ce);
1250
1251         i915_gem_context_put(ce->gem_context);
1252 }
1253
1254 static struct i915_vma *
1255 alloc_context_vma(struct intel_engine_cs *engine)
1256 {
1257         struct drm_i915_private *i915 = engine->i915;
1258         struct drm_i915_gem_object *obj;
1259         struct i915_vma *vma;
1260         int err;
1261
1262         obj = i915_gem_object_create(i915, engine->context_size);
1263         if (IS_ERR(obj))
1264                 return ERR_CAST(obj);
1265
1266         if (engine->default_state) {
1267                 void *defaults, *vaddr;
1268
1269                 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1270                 if (IS_ERR(vaddr)) {
1271                         err = PTR_ERR(vaddr);
1272                         goto err_obj;
1273                 }
1274
1275                 defaults = i915_gem_object_pin_map(engine->default_state,
1276                                                    I915_MAP_WB);
1277                 if (IS_ERR(defaults)) {
1278                         err = PTR_ERR(defaults);
1279                         goto err_map;
1280                 }
1281
1282                 memcpy(vaddr, defaults, engine->context_size);
1283
1284                 i915_gem_object_unpin_map(engine->default_state);
1285                 i915_gem_object_unpin_map(obj);
1286         }
1287
1288         /*
1289          * Try to make the context utilize L3 as well as LLC.
1290          *
1291          * On VLV we don't have L3 controls in the PTEs so we
1292          * shouldn't touch the cache level, especially as that
1293          * would make the object snooped which might have a
1294          * negative performance impact.
1295          *
1296          * Snooping is required on non-llc platforms in execlist
1297          * mode, but since all GGTT accesses use PAT entry 0 we
1298          * get snooping anyway regardless of cache_level.
1299          *
1300          * This is only applicable for Ivy Bridge devices since
1301          * later platforms don't have L3 control bits in the PTE.
1302          */
1303         if (IS_IVYBRIDGE(i915)) {
1304                 /* Ignore any error, regard it as a simple optimisation */
1305                 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1306         }
1307
1308         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1309         if (IS_ERR(vma)) {
1310                 err = PTR_ERR(vma);
1311                 goto err_obj;
1312         }
1313
1314         return vma;
1315
1316 err_map:
1317         i915_gem_object_unpin_map(obj);
1318 err_obj:
1319         i915_gem_object_put(obj);
1320         return ERR_PTR(err);
1321 }
1322
1323 static struct intel_context *
1324 __ring_context_pin(struct intel_engine_cs *engine,
1325                    struct i915_gem_context *ctx,
1326                    struct intel_context *ce)
1327 {
1328         int err;
1329
1330         if (!ce->state && engine->context_size) {
1331                 struct i915_vma *vma;
1332
1333                 vma = alloc_context_vma(engine);
1334                 if (IS_ERR(vma)) {
1335                         err = PTR_ERR(vma);
1336                         goto err;
1337                 }
1338
1339                 ce->state = vma;
1340         }
1341
1342         err = __context_pin(ce);
1343         if (err)
1344                 goto err;
1345
1346         err = __context_pin_ppgtt(ce->gem_context);
1347         if (err)
1348                 goto err_unpin;
1349
1350         i915_gem_context_get(ctx);
1351
1352         /* One ringbuffer to rule them all */
1353         GEM_BUG_ON(!engine->buffer);
1354         ce->ring = engine->buffer;
1355
1356         return ce;
1357
1358 err_unpin:
1359         __context_unpin(ce);
1360 err:
1361         ce->pin_count = 0;
1362         return ERR_PTR(err);
1363 }
1364
1365 static const struct intel_context_ops ring_context_ops = {
1366         .unpin = intel_ring_context_unpin,
1367         .destroy = intel_ring_context_destroy,
1368 };
1369
1370 static struct intel_context *
1371 intel_ring_context_pin(struct intel_engine_cs *engine,
1372                        struct i915_gem_context *ctx)
1373 {
1374         struct intel_context *ce = to_intel_context(ctx, engine);
1375
1376         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1377
1378         if (likely(ce->pin_count++))
1379                 return ce;
1380         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1381
1382         ce->ops = &ring_context_ops;
1383
1384         return __ring_context_pin(engine, ctx, ce);
1385 }
1386
1387 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1388 {
1389         struct i915_timeline *timeline;
1390         struct intel_ring *ring;
1391         unsigned int size;
1392         int err;
1393
1394         intel_engine_setup_common(engine);
1395
1396         timeline = i915_timeline_create(engine->i915, engine->name);
1397         if (IS_ERR(timeline)) {
1398                 err = PTR_ERR(timeline);
1399                 goto err;
1400         }
1401
1402         ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
1403         i915_timeline_put(timeline);
1404         if (IS_ERR(ring)) {
1405                 err = PTR_ERR(ring);
1406                 goto err;
1407         }
1408
1409         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1410         err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1411         if (err)
1412                 goto err_ring;
1413
1414         GEM_BUG_ON(engine->buffer);
1415         engine->buffer = ring;
1416
1417         size = PAGE_SIZE;
1418         if (HAS_BROKEN_CS_TLB(engine->i915))
1419                 size = I830_WA_SIZE;
1420         err = intel_engine_create_scratch(engine, size);
1421         if (err)
1422                 goto err_unpin;
1423
1424         err = intel_engine_init_common(engine);
1425         if (err)
1426                 goto err_scratch;
1427
1428         return 0;
1429
1430 err_scratch:
1431         intel_engine_cleanup_scratch(engine);
1432 err_unpin:
1433         intel_ring_unpin(ring);
1434 err_ring:
1435         intel_ring_free(ring);
1436 err:
1437         intel_engine_cleanup_common(engine);
1438         return err;
1439 }
1440
1441 void intel_engine_cleanup(struct intel_engine_cs *engine)
1442 {
1443         struct drm_i915_private *dev_priv = engine->i915;
1444
1445         WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1446                 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1447
1448         intel_ring_unpin(engine->buffer);
1449         intel_ring_free(engine->buffer);
1450
1451         if (engine->cleanup)
1452                 engine->cleanup(engine);
1453
1454         intel_engine_cleanup_common(engine);
1455
1456         dev_priv->engine[engine->id] = NULL;
1457         kfree(engine);
1458 }
1459
1460 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1461 {
1462         struct intel_engine_cs *engine;
1463         enum intel_engine_id id;
1464
1465         /* Restart from the beginning of the rings for convenience */
1466         for_each_engine(engine, dev_priv, id)
1467                 intel_ring_reset(engine->buffer, 0);
1468 }
1469
1470 static int load_pd_dir(struct i915_request *rq,
1471                        const struct i915_hw_ppgtt *ppgtt)
1472 {
1473         const struct intel_engine_cs * const engine = rq->engine;
1474         u32 *cs;
1475
1476         cs = intel_ring_begin(rq, 6);
1477         if (IS_ERR(cs))
1478                 return PTR_ERR(cs);
1479
1480         *cs++ = MI_LOAD_REGISTER_IMM(1);
1481         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1482         *cs++ = PP_DIR_DCLV_2G;
1483
1484         *cs++ = MI_LOAD_REGISTER_IMM(1);
1485         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1486         *cs++ = ppgtt->pd.base.ggtt_offset << 10;
1487
1488         intel_ring_advance(rq, cs);
1489
1490         return 0;
1491 }
1492
1493 static int flush_pd_dir(struct i915_request *rq)
1494 {
1495         const struct intel_engine_cs * const engine = rq->engine;
1496         u32 *cs;
1497
1498         cs = intel_ring_begin(rq, 4);
1499         if (IS_ERR(cs))
1500                 return PTR_ERR(cs);
1501
1502         /* Stall until the page table load is complete */
1503         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1504         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1505         *cs++ = i915_ggtt_offset(engine->scratch);
1506         *cs++ = MI_NOOP;
1507
1508         intel_ring_advance(rq, cs);
1509         return 0;
1510 }
1511
1512 static inline int mi_set_context(struct i915_request *rq, u32 flags)
1513 {
1514         struct drm_i915_private *i915 = rq->i915;
1515         struct intel_engine_cs *engine = rq->engine;
1516         enum intel_engine_id id;
1517         const int num_rings =
1518                 /* Use an extended w/a on gen7 if signalling from other rings */
1519                 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1520                 INTEL_INFO(i915)->num_rings - 1 :
1521                 0;
1522         bool force_restore = false;
1523         int len;
1524         u32 *cs;
1525
1526         flags |= MI_MM_SPACE_GTT;
1527         if (IS_HASWELL(i915))
1528                 /* These flags are for resource streamer on HSW+ */
1529                 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1530         else
1531                 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1532
1533         len = 4;
1534         if (IS_GEN7(i915))
1535                 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1536         if (flags & MI_FORCE_RESTORE) {
1537                 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1538                 flags &= ~MI_FORCE_RESTORE;
1539                 force_restore = true;
1540                 len += 2;
1541         }
1542
1543         cs = intel_ring_begin(rq, len);
1544         if (IS_ERR(cs))
1545                 return PTR_ERR(cs);
1546
1547         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1548         if (IS_GEN7(i915)) {
1549                 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1550                 if (num_rings) {
1551                         struct intel_engine_cs *signaller;
1552
1553                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1554                         for_each_engine(signaller, i915, id) {
1555                                 if (signaller == engine)
1556                                         continue;
1557
1558                                 *cs++ = i915_mmio_reg_offset(
1559                                            RING_PSMI_CTL(signaller->mmio_base));
1560                                 *cs++ = _MASKED_BIT_ENABLE(
1561                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1562                         }
1563                 }
1564         }
1565
1566         if (force_restore) {
1567                 /*
1568                  * The HW doesn't handle being told to restore the current
1569                  * context very well. Quite often it likes goes to go off and
1570                  * sulk, especially when it is meant to be reloading PP_DIR.
1571                  * A very simple fix to force the reload is to simply switch
1572                  * away from the current context and back again.
1573                  *
1574                  * Note that the kernel_context will contain random state
1575                  * following the INHIBIT_RESTORE. We accept this since we
1576                  * never use the kernel_context state; it is merely a
1577                  * placeholder we use to flush other contexts.
1578                  */
1579                 *cs++ = MI_SET_CONTEXT;
1580                 *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
1581                                                           engine)->state) |
1582                         MI_MM_SPACE_GTT |
1583                         MI_RESTORE_INHIBIT;
1584         }
1585
1586         *cs++ = MI_NOOP;
1587         *cs++ = MI_SET_CONTEXT;
1588         *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1589         /*
1590          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1591          * WaMiSetContext_Hang:snb,ivb,vlv
1592          */
1593         *cs++ = MI_NOOP;
1594
1595         if (IS_GEN7(i915)) {
1596                 if (num_rings) {
1597                         struct intel_engine_cs *signaller;
1598                         i915_reg_t last_reg = {}; /* keep gcc quiet */
1599
1600                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1601                         for_each_engine(signaller, i915, id) {
1602                                 if (signaller == engine)
1603                                         continue;
1604
1605                                 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1606                                 *cs++ = i915_mmio_reg_offset(last_reg);
1607                                 *cs++ = _MASKED_BIT_DISABLE(
1608                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1609                         }
1610
1611                         /* Insert a delay before the next switch! */
1612                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1613                         *cs++ = i915_mmio_reg_offset(last_reg);
1614                         *cs++ = i915_ggtt_offset(engine->scratch);
1615                         *cs++ = MI_NOOP;
1616                 }
1617                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1618         }
1619
1620         intel_ring_advance(rq, cs);
1621
1622         return 0;
1623 }
1624
1625 static int remap_l3(struct i915_request *rq, int slice)
1626 {
1627         u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1628         int i;
1629
1630         if (!remap_info)
1631                 return 0;
1632
1633         cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1634         if (IS_ERR(cs))
1635                 return PTR_ERR(cs);
1636
1637         /*
1638          * Note: We do not worry about the concurrent register cacheline hang
1639          * here because no other code should access these registers other than
1640          * at initialization time.
1641          */
1642         *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1643         for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1644                 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1645                 *cs++ = remap_info[i];
1646         }
1647         *cs++ = MI_NOOP;
1648         intel_ring_advance(rq, cs);
1649
1650         return 0;
1651 }
1652
1653 static int switch_context(struct i915_request *rq)
1654 {
1655         struct intel_engine_cs *engine = rq->engine;
1656         struct i915_gem_context *ctx = rq->gem_context;
1657         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1658         unsigned int unwind_mm = 0;
1659         u32 hw_flags = 0;
1660         int ret, i;
1661
1662         lockdep_assert_held(&rq->i915->drm.struct_mutex);
1663         GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1664
1665         if (ppgtt) {
1666                 ret = load_pd_dir(rq, ppgtt);
1667                 if (ret)
1668                         goto err;
1669
1670                 if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
1671                         unwind_mm = intel_engine_flag(engine);
1672                         ppgtt->pd_dirty_rings &= ~unwind_mm;
1673                         hw_flags = MI_FORCE_RESTORE;
1674                 }
1675         }
1676
1677         if (rq->hw_context->state) {
1678                 GEM_BUG_ON(engine->id != RCS);
1679
1680                 /*
1681                  * The kernel context(s) is treated as pure scratch and is not
1682                  * expected to retain any state (as we sacrifice it during
1683                  * suspend and on resume it may be corrupted). This is ok,
1684                  * as nothing actually executes using the kernel context; it
1685                  * is purely used for flushing user contexts.
1686                  */
1687                 if (i915_gem_context_is_kernel(ctx))
1688                         hw_flags = MI_RESTORE_INHIBIT;
1689
1690                 ret = mi_set_context(rq, hw_flags);
1691                 if (ret)
1692                         goto err_mm;
1693         }
1694
1695         if (ppgtt) {
1696                 ret = flush_pd_dir(rq);
1697                 if (ret)
1698                         goto err_mm;
1699         }
1700
1701         if (ctx->remap_slice) {
1702                 for (i = 0; i < MAX_L3_SLICES; i++) {
1703                         if (!(ctx->remap_slice & BIT(i)))
1704                                 continue;
1705
1706                         ret = remap_l3(rq, i);
1707                         if (ret)
1708                                 goto err_mm;
1709                 }
1710
1711                 ctx->remap_slice = 0;
1712         }
1713
1714         return 0;
1715
1716 err_mm:
1717         if (unwind_mm)
1718                 ppgtt->pd_dirty_rings |= unwind_mm;
1719 err:
1720         return ret;
1721 }
1722
1723 static int ring_request_alloc(struct i915_request *request)
1724 {
1725         int ret;
1726
1727         GEM_BUG_ON(!request->hw_context->pin_count);
1728
1729         /* Flush enough space to reduce the likelihood of waiting after
1730          * we start building the request - in which case we will just
1731          * have to repeat work.
1732          */
1733         request->reserved_space += LEGACY_REQUEST_SIZE;
1734
1735         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1736         if (ret)
1737                 return ret;
1738
1739         ret = switch_context(request);
1740         if (ret)
1741                 return ret;
1742
1743         request->reserved_space -= LEGACY_REQUEST_SIZE;
1744         return 0;
1745 }
1746
1747 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1748 {
1749         struct i915_request *target;
1750         long timeout;
1751
1752         lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1753
1754         if (intel_ring_update_space(ring) >= bytes)
1755                 return 0;
1756
1757         GEM_BUG_ON(list_empty(&ring->request_list));
1758         list_for_each_entry(target, &ring->request_list, ring_link) {
1759                 /* Would completion of this request free enough space? */
1760                 if (bytes <= __intel_ring_space(target->postfix,
1761                                                 ring->emit, ring->size))
1762                         break;
1763         }
1764
1765         if (WARN_ON(&target->ring_link == &ring->request_list))
1766                 return -ENOSPC;
1767
1768         timeout = i915_request_wait(target,
1769                                     I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1770                                     MAX_SCHEDULE_TIMEOUT);
1771         if (timeout < 0)
1772                 return timeout;
1773
1774         i915_request_retire_upto(target);
1775
1776         intel_ring_update_space(ring);
1777         GEM_BUG_ON(ring->space < bytes);
1778         return 0;
1779 }
1780
1781 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1782 {
1783         GEM_BUG_ON(bytes > ring->effective_size);
1784         if (unlikely(bytes > ring->effective_size - ring->emit))
1785                 bytes += ring->size - ring->emit;
1786
1787         if (unlikely(bytes > ring->space)) {
1788                 int ret = wait_for_space(ring, bytes);
1789                 if (unlikely(ret))
1790                         return ret;
1791         }
1792
1793         GEM_BUG_ON(ring->space < bytes);
1794         return 0;
1795 }
1796
1797 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1798 {
1799         struct intel_ring *ring = rq->ring;
1800         const unsigned int remain_usable = ring->effective_size - ring->emit;
1801         const unsigned int bytes = num_dwords * sizeof(u32);
1802         unsigned int need_wrap = 0;
1803         unsigned int total_bytes;
1804         u32 *cs;
1805
1806         /* Packets must be qword aligned. */
1807         GEM_BUG_ON(num_dwords & 1);
1808
1809         total_bytes = bytes + rq->reserved_space;
1810         GEM_BUG_ON(total_bytes > ring->effective_size);
1811
1812         if (unlikely(total_bytes > remain_usable)) {
1813                 const int remain_actual = ring->size - ring->emit;
1814
1815                 if (bytes > remain_usable) {
1816                         /*
1817                          * Not enough space for the basic request. So need to
1818                          * flush out the remainder and then wait for
1819                          * base + reserved.
1820                          */
1821                         total_bytes += remain_actual;
1822                         need_wrap = remain_actual | 1;
1823                 } else  {
1824                         /*
1825                          * The base request will fit but the reserved space
1826                          * falls off the end. So we don't need an immediate
1827                          * wrap and only need to effectively wait for the
1828                          * reserved size from the start of ringbuffer.
1829                          */
1830                         total_bytes = rq->reserved_space + remain_actual;
1831                 }
1832         }
1833
1834         if (unlikely(total_bytes > ring->space)) {
1835                 int ret;
1836
1837                 /*
1838                  * Space is reserved in the ringbuffer for finalising the
1839                  * request, as that cannot be allowed to fail. During request
1840                  * finalisation, reserved_space is set to 0 to stop the
1841                  * overallocation and the assumption is that then we never need
1842                  * to wait (which has the risk of failing with EINTR).
1843                  *
1844                  * See also i915_request_alloc() and i915_request_add().
1845                  */
1846                 GEM_BUG_ON(!rq->reserved_space);
1847
1848                 ret = wait_for_space(ring, total_bytes);
1849                 if (unlikely(ret))
1850                         return ERR_PTR(ret);
1851         }
1852
1853         if (unlikely(need_wrap)) {
1854                 need_wrap &= ~1;
1855                 GEM_BUG_ON(need_wrap > ring->space);
1856                 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1857                 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
1858
1859                 /* Fill the tail with MI_NOOP */
1860                 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
1861                 ring->space -= need_wrap;
1862                 ring->emit = 0;
1863         }
1864
1865         GEM_BUG_ON(ring->emit > ring->size - bytes);
1866         GEM_BUG_ON(ring->space < bytes);
1867         cs = ring->vaddr + ring->emit;
1868         GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
1869         ring->emit += bytes;
1870         ring->space -= bytes;
1871
1872         return cs;
1873 }
1874
1875 /* Align the ring tail to a cacheline boundary */
1876 int intel_ring_cacheline_align(struct i915_request *rq)
1877 {
1878         int num_dwords;
1879         void *cs;
1880
1881         num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1882         if (num_dwords == 0)
1883                 return 0;
1884
1885         num_dwords = CACHELINE_DWORDS - num_dwords;
1886         GEM_BUG_ON(num_dwords & 1);
1887
1888         cs = intel_ring_begin(rq, num_dwords);
1889         if (IS_ERR(cs))
1890                 return PTR_ERR(cs);
1891
1892         memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
1893         intel_ring_advance(rq, cs);
1894
1895         GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
1896         return 0;
1897 }
1898
1899 static void gen6_bsd_submit_request(struct i915_request *request)
1900 {
1901         struct drm_i915_private *dev_priv = request->i915;
1902
1903         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1904
1905        /* Every tail move must follow the sequence below */
1906
1907         /* Disable notification that the ring is IDLE. The GT
1908          * will then assume that it is busy and bring it out of rc6.
1909          */
1910         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1911                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1912
1913         /* Clear the context id. Here be magic! */
1914         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1915
1916         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1917         if (__intel_wait_for_register_fw(dev_priv,
1918                                          GEN6_BSD_SLEEP_PSMI_CONTROL,
1919                                          GEN6_BSD_SLEEP_INDICATOR,
1920                                          0,
1921                                          1000, 0, NULL))
1922                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1923
1924         /* Now that the ring is fully powered up, update the tail */
1925         i9xx_submit_request(request);
1926
1927         /* Let the ring send IDLE messages to the GT again,
1928          * and so let it sleep to conserve power when idle.
1929          */
1930         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1931                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1932
1933         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1934 }
1935
1936 static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
1937 {
1938         u32 cmd, *cs;
1939
1940         cs = intel_ring_begin(rq, 4);
1941         if (IS_ERR(cs))
1942                 return PTR_ERR(cs);
1943
1944         cmd = MI_FLUSH_DW;
1945
1946         /* We always require a command barrier so that subsequent
1947          * commands, such as breadcrumb interrupts, are strictly ordered
1948          * wrt the contents of the write cache being flushed to memory
1949          * (and thus being coherent from the CPU).
1950          */
1951         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1952
1953         /*
1954          * Bspec vol 1c.5 - video engine command streamer:
1955          * "If ENABLED, all TLBs will be invalidated once the flush
1956          * operation is complete. This bit is only valid when the
1957          * Post-Sync Operation field is a value of 1h or 3h."
1958          */
1959         if (mode & EMIT_INVALIDATE)
1960                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1961
1962         *cs++ = cmd;
1963         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1964         *cs++ = 0;
1965         *cs++ = MI_NOOP;
1966         intel_ring_advance(rq, cs);
1967         return 0;
1968 }
1969
1970 static int
1971 hsw_emit_bb_start(struct i915_request *rq,
1972                   u64 offset, u32 len,
1973                   unsigned int dispatch_flags)
1974 {
1975         u32 *cs;
1976
1977         cs = intel_ring_begin(rq, 2);
1978         if (IS_ERR(cs))
1979                 return PTR_ERR(cs);
1980
1981         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1982                 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
1983                 (dispatch_flags & I915_DISPATCH_RS ?
1984                 MI_BATCH_RESOURCE_STREAMER : 0);
1985         /* bit0-7 is the length on GEN6+ */
1986         *cs++ = offset;
1987         intel_ring_advance(rq, cs);
1988
1989         return 0;
1990 }
1991
1992 static int
1993 gen6_emit_bb_start(struct i915_request *rq,
1994                    u64 offset, u32 len,
1995                    unsigned int dispatch_flags)
1996 {
1997         u32 *cs;
1998
1999         cs = intel_ring_begin(rq, 2);
2000         if (IS_ERR(cs))
2001                 return PTR_ERR(cs);
2002
2003         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2004                 0 : MI_BATCH_NON_SECURE_I965);
2005         /* bit0-7 is the length on GEN6+ */
2006         *cs++ = offset;
2007         intel_ring_advance(rq, cs);
2008
2009         return 0;
2010 }
2011
2012 /* Blitter support (SandyBridge+) */
2013
2014 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
2015 {
2016         u32 cmd, *cs;
2017
2018         cs = intel_ring_begin(rq, 4);
2019         if (IS_ERR(cs))
2020                 return PTR_ERR(cs);
2021
2022         cmd = MI_FLUSH_DW;
2023
2024         /* We always require a command barrier so that subsequent
2025          * commands, such as breadcrumb interrupts, are strictly ordered
2026          * wrt the contents of the write cache being flushed to memory
2027          * (and thus being coherent from the CPU).
2028          */
2029         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2030
2031         /*
2032          * Bspec vol 1c.3 - blitter engine command streamer:
2033          * "If ENABLED, all TLBs will be invalidated once the flush
2034          * operation is complete. This bit is only valid when the
2035          * Post-Sync Operation field is a value of 1h or 3h."
2036          */
2037         if (mode & EMIT_INVALIDATE)
2038                 cmd |= MI_INVALIDATE_TLB;
2039         *cs++ = cmd;
2040         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2041         *cs++ = 0;
2042         *cs++ = MI_NOOP;
2043         intel_ring_advance(rq, cs);
2044
2045         return 0;
2046 }
2047
2048 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2049                                        struct intel_engine_cs *engine)
2050 {
2051         int i;
2052
2053         if (!HAS_LEGACY_SEMAPHORES(dev_priv))
2054                 return;
2055
2056         GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
2057         engine->semaphore.sync_to = gen6_ring_sync_to;
2058         engine->semaphore.signal = gen6_signal;
2059
2060         /*
2061          * The current semaphore is only applied on pre-gen8
2062          * platform.  And there is no VCS2 ring on the pre-gen8
2063          * platform. So the semaphore between RCS and VCS2 is
2064          * initialized as INVALID.
2065          */
2066         for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2067                 static const struct {
2068                         u32 wait_mbox;
2069                         i915_reg_t mbox_reg;
2070                 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2071                         [RCS_HW] = {
2072                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2073                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2074                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2075                         },
2076                         [VCS_HW] = {
2077                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2078                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2079                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2080                         },
2081                         [BCS_HW] = {
2082                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2083                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2084                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2085                         },
2086                         [VECS_HW] = {
2087                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2088                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2089                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2090                         },
2091                 };
2092                 u32 wait_mbox;
2093                 i915_reg_t mbox_reg;
2094
2095                 if (i == engine->hw_id) {
2096                         wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2097                         mbox_reg = GEN6_NOSYNC;
2098                 } else {
2099                         wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2100                         mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2101                 }
2102
2103                 engine->semaphore.mbox.wait[i] = wait_mbox;
2104                 engine->semaphore.mbox.signal[i] = mbox_reg;
2105         }
2106 }
2107
2108 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2109                                 struct intel_engine_cs *engine)
2110 {
2111         if (INTEL_GEN(dev_priv) >= 6) {
2112                 engine->irq_enable = gen6_irq_enable;
2113                 engine->irq_disable = gen6_irq_disable;
2114                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2115         } else if (INTEL_GEN(dev_priv) >= 5) {
2116                 engine->irq_enable = gen5_irq_enable;
2117                 engine->irq_disable = gen5_irq_disable;
2118                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2119         } else if (INTEL_GEN(dev_priv) >= 3) {
2120                 engine->irq_enable = i9xx_irq_enable;
2121                 engine->irq_disable = i9xx_irq_disable;
2122         } else {
2123                 engine->irq_enable = i8xx_irq_enable;
2124                 engine->irq_disable = i8xx_irq_disable;
2125         }
2126 }
2127
2128 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2129 {
2130         engine->submit_request = i9xx_submit_request;
2131         engine->cancel_requests = cancel_requests;
2132
2133         engine->park = NULL;
2134         engine->unpark = NULL;
2135 }
2136
2137 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2138 {
2139         i9xx_set_default_submission(engine);
2140         engine->submit_request = gen6_bsd_submit_request;
2141 }
2142
2143 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2144                                       struct intel_engine_cs *engine)
2145 {
2146         /* gen8+ are only supported with execlists */
2147         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
2148
2149         intel_ring_init_irq(dev_priv, engine);
2150         intel_ring_init_semaphores(dev_priv, engine);
2151
2152         engine->init_hw = init_ring_common;
2153         engine->reset.prepare = reset_prepare;
2154         engine->reset.reset = reset_ring;
2155         engine->reset.finish = reset_finish;
2156
2157         engine->context_pin = intel_ring_context_pin;
2158         engine->request_alloc = ring_request_alloc;
2159
2160         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2161         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2162         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2163                 int num_rings;
2164
2165                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2166
2167                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2168                 engine->emit_breadcrumb_sz += num_rings * 3;
2169                 if (num_rings & 1)
2170                         engine->emit_breadcrumb_sz++;
2171         }
2172
2173         engine->set_default_submission = i9xx_set_default_submission;
2174
2175         if (INTEL_GEN(dev_priv) >= 6)
2176                 engine->emit_bb_start = gen6_emit_bb_start;
2177         else if (INTEL_GEN(dev_priv) >= 4)
2178                 engine->emit_bb_start = i965_emit_bb_start;
2179         else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2180                 engine->emit_bb_start = i830_emit_bb_start;
2181         else
2182                 engine->emit_bb_start = i915_emit_bb_start;
2183 }
2184
2185 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2186 {
2187         struct drm_i915_private *dev_priv = engine->i915;
2188         int ret;
2189
2190         intel_ring_default_vfuncs(dev_priv, engine);
2191
2192         if (HAS_L3_DPF(dev_priv))
2193                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2194
2195         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2196
2197         if (INTEL_GEN(dev_priv) >= 6) {
2198                 engine->init_context = intel_rcs_ctx_init;
2199                 engine->emit_flush = gen7_render_ring_flush;
2200                 if (IS_GEN6(dev_priv))
2201                         engine->emit_flush = gen6_render_ring_flush;
2202         } else if (IS_GEN5(dev_priv)) {
2203                 engine->emit_flush = gen4_render_ring_flush;
2204         } else {
2205                 if (INTEL_GEN(dev_priv) < 4)
2206                         engine->emit_flush = gen2_render_ring_flush;
2207                 else
2208                         engine->emit_flush = gen4_render_ring_flush;
2209                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2210         }
2211
2212         if (IS_HASWELL(dev_priv))
2213                 engine->emit_bb_start = hsw_emit_bb_start;
2214
2215         engine->init_hw = init_render_ring;
2216
2217         ret = intel_init_ring_buffer(engine);
2218         if (ret)
2219                 return ret;
2220
2221         return 0;
2222 }
2223
2224 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2225 {
2226         struct drm_i915_private *dev_priv = engine->i915;
2227
2228         intel_ring_default_vfuncs(dev_priv, engine);
2229
2230         if (INTEL_GEN(dev_priv) >= 6) {
2231                 /* gen6 bsd needs a special wa for tail updates */
2232                 if (IS_GEN6(dev_priv))
2233                         engine->set_default_submission = gen6_bsd_set_default_submission;
2234                 engine->emit_flush = gen6_bsd_ring_flush;
2235                 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2236         } else {
2237                 engine->emit_flush = bsd_ring_flush;
2238                 if (IS_GEN5(dev_priv))
2239                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2240                 else
2241                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2242         }
2243
2244         return intel_init_ring_buffer(engine);
2245 }
2246
2247 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2248 {
2249         struct drm_i915_private *dev_priv = engine->i915;
2250
2251         intel_ring_default_vfuncs(dev_priv, engine);
2252
2253         engine->emit_flush = gen6_ring_flush;
2254         engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2255
2256         return intel_init_ring_buffer(engine);
2257 }
2258
2259 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2260 {
2261         struct drm_i915_private *dev_priv = engine->i915;
2262
2263         intel_ring_default_vfuncs(dev_priv, engine);
2264
2265         engine->emit_flush = gen6_ring_flush;
2266         engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2267         engine->irq_enable = hsw_vebox_irq_enable;
2268         engine->irq_disable = hsw_vebox_irq_disable;
2269
2270         return intel_init_ring_buffer(engine);
2271 }