drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v14_0.h"
  30
  31 #include "mp/mp_14_0_2_offset.h"
  32 #include "mp/mp_14_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin");
  36
  37 /* For large FW files the time to complete can be very long */
  38 #define USBC_PD_POLLING_LIMIT_S 240
  39
  40 /* Read USB-PD from LFB */
  41 #define GFX_CMD_USB_PD_USE_LFB 0x480
  42
  43 /* VBIOS gfl defines */
  44 #define MBOX_READY_MASK 0x80000000
  45 #define MBOX_STATUS_MASK 0x0000FFFF
  46 #define MBOX_COMMAND_MASK 0x00FF0000
  47 #define MBOX_READY_FLAG 0x80000000
  48 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  49 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  50 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  51
  52 /* memory training timeout define */
  53 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  54
  55 static int psp_v14_0_init_microcode(struct psp_context *psp)
  56 {
  57         struct amdgpu_device *adev = psp->adev;
  58         char ucode_prefix[30];
  59         int err = 0;
  60
  61         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  62
  63         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
  64         case IP_VERSION(14, 0, 2):
  65         case IP_VERSION(14, 0, 3):
  66                 err = psp_init_sos_microcode(psp, ucode_prefix);
  67                 if (err)
  68                         return err;
  69                 break;
  70         default:
  71                 BUG();
  72         }
  73
  74         return 0;
  75 }
  76
  77 static bool psp_v14_0_is_sos_alive(struct psp_context *psp)
  78 {
  79         struct amdgpu_device *adev = psp->adev;
  80         uint32_t sol_reg;
  81
  82         sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
  83
  84         return sol_reg != 0x0;
  85 }
  86
  87 static int psp_v14_0_wait_for_bootloader(struct psp_context *psp)
  88 {
  89         struct amdgpu_device *adev = psp->adev;
  90
  91         int ret;
  92         int retry_loop;
  93
  94         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
  95                 /* Wait for bootloader to signify that is
  96                     ready having bit 31 of C2PMSG_35 set to 1 */
  97                 ret = psp_wait_for(psp,
  98                                    SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
  99                                    0x80000000,
 100                                    0x80000000,
 101                                    false);
 102
 103                 if (ret == 0)
 104                         return 0;
 105         }
 106
 107         return ret;
 108 }
 109
 110 static int psp_v14_0_bootloader_load_component(struct psp_context       *psp,
 111                                                struct psp_bin_desc      *bin_desc,
 112                                                enum psp_bootloader_cmd  bl_cmd)
 113 {
 114         int ret;
 115         uint32_t psp_gfxdrv_command_reg = 0;
 116         struct amdgpu_device *adev = psp->adev;
 117
 118         /* Check tOS sign of life register to confirm sys driver and sOS
 119          * are already been loaded.
 120          */
 121         if (psp_v14_0_is_sos_alive(psp))
 122                 return 0;
 123
 124         ret = psp_v14_0_wait_for_bootloader(psp);
 125         if (ret)
 126                 return ret;
 127
 128         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 129
 130         /* Copy PSP KDB binary to memory */
 131         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 132
 133         /* Provide the PSP KDB to bootloader */
 134         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
 135                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 136         psp_gfxdrv_command_reg = bl_cmd;
 137         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
 138                psp_gfxdrv_command_reg);
 139
 140         ret = psp_v14_0_wait_for_bootloader(psp);
 141
 142         return ret;
 143 }
 144
 145 static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp)
 146 {
 147         return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 148 }
 149
 150 static int psp_v14_0_bootloader_load_spl(struct psp_context *psp)
 151 {
 152         return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 153 }
 154
 155 static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp)
 156 {
 157         return psp_v14_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 158 }
 159
 160 static int psp_v14_0_bootloader_load_soc_drv(struct psp_context *psp)
 161 {
 162         return psp_v14_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 163 }
 164
 165 static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp)
 166 {
 167         return psp_v14_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 168 }
 169
 170 static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp)
 171 {
 172         /* dbg_drv was renamed to had_drv in psp v14 */
 173         return psp_v14_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_HADDRV);
 174 }
 175
 176 static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)
 177 {
 178         return psp_v14_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 179 }
 180
 181 static int psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context *psp)
 182 {
 183         return psp_v14_0_bootloader_load_component(psp, &psp->ipkeymgr_drv, PSP_BL__LOAD_IPKEYMGRDRV);
 184 }
 185
 186 static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)
 187 {
 188         int ret;
 189         unsigned int psp_gfxdrv_command_reg = 0;
 190         struct amdgpu_device *adev = psp->adev;
 191
 192         /* Check sOS sign of life register to confirm sys driver and sOS
 193          * are already been loaded.
 194          */
 195         if (psp_v14_0_is_sos_alive(psp))
 196                 return 0;
 197
 198         ret = psp_v14_0_wait_for_bootloader(psp);
 199         if (ret)
 200                 return ret;
 201
 202         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 203
 204         /* Copy Secure OS binary to PSP memory */
 205         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 206
 207         /* Provide the PSP secure OS to bootloader */
 208         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
 209                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 210         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 211         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
 212                psp_gfxdrv_command_reg);
 213
 214         /* there might be handshake issue with hardware which needs delay */
 215         mdelay(20);
 216         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
 217                            RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81),
 218                            0, true);
 219
 220         return ret;
 221 }
 222
 223 static int psp_v14_0_ring_stop(struct psp_context *psp,
 224                                enum psp_ring_type ring_type)
 225 {
 226         int ret = 0;
 227         struct amdgpu_device *adev = psp->adev;
 228
 229         if (amdgpu_sriov_vf(adev)) {
 230                 /* Write the ring destroy command*/
 231                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
 232                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 233                 /* there might be handshake issue with hardware which needs delay */
 234                 mdelay(20);
 235                 /* Wait for response flag (bit 31) */
 236                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
 237                                    0x80000000, 0x80000000, false);
 238         } else {
 239                 /* Write the ring destroy command*/
 240                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
 241                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 242                 /* there might be handshake issue with hardware which needs delay */
 243                 mdelay(20);
 244                 /* Wait for response flag (bit 31) */
 245                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
 246                                    0x80000000, 0x80000000, false);
 247         }
 248
 249         return ret;
 250 }
 251
 252 static int psp_v14_0_ring_create(struct psp_context *psp,
 253                                  enum psp_ring_type ring_type)
 254 {
 255         int ret = 0;
 256         unsigned int psp_ring_reg = 0;
 257         struct psp_ring *ring = &psp->km_ring;
 258         struct amdgpu_device *adev = psp->adev;
 259
 260         if (amdgpu_sriov_vf(adev)) {
 261                 ret = psp_v14_0_ring_stop(psp, ring_type);
 262                 if (ret) {
 263                         DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
 264                         return ret;
 265                 }
 266
 267                 /* Write low address of the ring to C2PMSG_102 */
 268                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 269                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
 270                 /* Write high address of the ring to C2PMSG_103 */
 271                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 272                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
 273
 274                 /* Write the ring initialization command to C2PMSG_101 */
 275                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
 276                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 277
 278                 /* there might be handshake issue with hardware which needs delay */
 279                 mdelay(20);
 280
 281                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 282                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
 283                                    0x80000000, 0x8000FFFF, false);
 284
 285         } else {
 286                 /* Wait for sOS ready for ring creation */
 287                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
 288                                    0x80000000, 0x80000000, false);
 289                 if (ret) {
 290                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 291                         return ret;
 292                 }
 293
 294                 /* Write low address of the ring to C2PMSG_69 */
 295                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 296                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
 297                 /* Write high address of the ring to C2PMSG_70 */
 298                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 299                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
 300                 /* Write size of ring to C2PMSG_71 */
 301                 psp_ring_reg = ring->ring_size;
 302                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
 303                 /* Write the ring initialization command to C2PMSG_64 */
 304                 psp_ring_reg = ring_type;
 305                 psp_ring_reg = psp_ring_reg << 16;
 306                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
 307
 308                 /* there might be handshake issue with hardware which needs delay */
 309                 mdelay(20);
 310
 311                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 312                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
 313                                    0x80000000, 0x8000FFFF, false);
 314         }
 315
 316         return ret;
 317 }
 318
 319 static int psp_v14_0_ring_destroy(struct psp_context *psp,
 320                                   enum psp_ring_type ring_type)
 321 {
 322         int ret = 0;
 323         struct psp_ring *ring = &psp->km_ring;
 324         struct amdgpu_device *adev = psp->adev;
 325
 326         ret = psp_v14_0_ring_stop(psp, ring_type);
 327         if (ret)
 328                 DRM_ERROR("Fail to stop psp ring\n");
 329
 330         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 331                               &ring->ring_mem_mc_addr,
 332                               (void **)&ring->ring_mem);
 333
 334         return ret;
 335 }
 336
 337 static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp)
 338 {
 339         uint32_t data;
 340         struct amdgpu_device *adev = psp->adev;
 341
 342         if (amdgpu_sriov_vf(adev))
 343                 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
 344         else
 345                 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
 346
 347         return data;
 348 }
 349
 350 static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 351 {
 352         struct amdgpu_device *adev = psp->adev;
 353
 354         if (amdgpu_sriov_vf(adev)) {
 355                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
 356                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
 357                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 358         } else
 359                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
 360 }
 361
 362 static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg)
 363 {
 364         int ret;
 365         int i;
 366         uint32_t data_32;
 367         int max_wait;
 368         struct amdgpu_device *adev = psp->adev;
 369
 370         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 371         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, data_32);
 372         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, msg);
 373
 374         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 375         for (i = 0; i < max_wait; i++) {
 376                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
 377                                    0x80000000, 0x80000000, false);
 378                 if (ret == 0)
 379                         break;
 380         }
 381         if (i < max_wait)
 382                 ret = 0;
 383         else
 384                 ret = -ETIME;
 385
 386         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 387                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 388                   (ret == 0) ? "succeed" : "failed",
 389                   i, adev->usec_timeout/1000);
 390         return ret;
 391 }
 392
 393
 394 static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
 395 {
 396         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 397         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 398         struct amdgpu_device *adev = psp->adev;
 399         uint32_t p2c_header[4];
 400         uint32_t sz;
 401         void *buf;
 402         int ret, idx;
 403
 404         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 405                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 406                 return 0;
 407         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 408                 dev_err(adev->dev, "Memory training initialization failure.\n");
 409                 return -EINVAL;
 410         }
 411
 412         if (psp_v14_0_is_sos_alive(psp)) {
 413                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 414                 return 0;
 415         }
 416
 417         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 418         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 419                   pcache[0], pcache[1], pcache[2], pcache[3],
 420                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 421
 422         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 423                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 424                 ops |= PSP_MEM_TRAIN_RESTORE;
 425         }
 426
 427         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 428             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 429                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 430                 ops |= PSP_MEM_TRAIN_SAVE;
 431         }
 432
 433         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 434             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 435               pcache[3] == p2c_header[3])) {
 436                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 437                 ops |= PSP_MEM_TRAIN_SAVE;
 438         }
 439
 440         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 441             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 442                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 443                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 444         }
 445
 446         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 447                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 448                 ops |= PSP_MEM_TRAIN_SAVE;
 449         }
 450
 451         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 452
 453         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 454                 /*
 455                  * Long training will encroach a certain amount on the bottom of VRAM;
 456                  * save the content from the bottom of VRAM to system memory
 457                  * before training, and restore it after training to avoid
 458                  * VRAM corruption.
 459                  */
 460                 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
 461
 462                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 463                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 464                                   adev->gmc.visible_vram_size,
 465                                   adev->mman.aper_base_kaddr);
 466                         return -EINVAL;
 467                 }
 468
 469                 buf = vmalloc(sz);
 470                 if (!buf) {
 471                         dev_err(adev->dev, "failed to allocate system memory.\n");
 472                         return -ENOMEM;
 473                 }
 474
 475                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 476                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 477                         ret = psp_v14_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 478                         if (ret) {
 479                                 DRM_ERROR("Send long training msg failed.\n");
 480                                 vfree(buf);
 481                                 drm_dev_exit(idx);
 482                                 return ret;
 483                         }
 484
 485                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 486                         adev->hdp.funcs->flush_hdp(adev, NULL);
 487                         vfree(buf);
 488                         drm_dev_exit(idx);
 489                 } else {
 490                         vfree(buf);
 491                         return -ENODEV;
 492                 }
 493         }
 494
 495         if (ops & PSP_MEM_TRAIN_SAVE) {
 496                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 497         }
 498
 499         if (ops & PSP_MEM_TRAIN_RESTORE) {
 500                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 501         }
 502
 503         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 504                 ret = psp_v14_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 505                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 506                 if (ret) {
 507                         dev_err(adev->dev, "send training msg failed.\n");
 508                         return ret;
 509                 }
 510         }
 511         ctx->training_cnt++;
 512         return 0;
 513 }
 514
 515 static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 516 {
 517         struct amdgpu_device *adev = psp->adev;
 518         uint32_t reg_status;
 519         int ret, i = 0;
 520
 521         /*
 522          * LFB address which is aligned to 1MB address and has to be
 523          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 524          * register
 525          */
 526         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 527
 528         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
 529                              0x80000000, 0x80000000, false);
 530         if (ret)
 531                 return ret;
 532
 533         /* Fireup interrupt so PSP can pick up the address */
 534         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 535
 536         /* FW load takes very long time */
 537         do {
 538                 msleep(1000);
 539                 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);
 540
 541                 if (reg_status & 0x80000000)
 542                         goto done;
 543
 544         } while (++i < USBC_PD_POLLING_LIMIT_S);
 545
 546         return -ETIME;
 547 done:
 548
 549         if ((reg_status & 0xFFFF) != 0) {
 550                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 551                                 reg_status & 0xFFFF);
 552                 return -EIO;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 559 {
 560         struct amdgpu_device *adev = psp->adev;
 561         int ret;
 562
 563         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 564
 565         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
 566                                      0x80000000, 0x80000000, false);
 567         if (!ret)
 568                 *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);
 569
 570         return ret;
 571 }
 572
 573 static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 574 {
 575         uint32_t reg_status = 0, reg_val = 0;
 576         struct amdgpu_device *adev = psp->adev;
 577         int ret;
 578
 579         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 580         reg_val |= (cmd << 16);
 581         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115,  reg_val);
 582
 583         /* Ring the doorbell */
 584         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_73, 1);
 585
 586         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 587                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 588                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 589         else
 590                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 591                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 592
 593         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 594                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 595         if (ret) {
 596                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 597                 return ret;
 598         }
 599
 600         reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
 601         if ((reg_status & 0xFFFF) != 0) {
 602                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 603                                 cmd, reg_status & 0xFFFF);
 604                 return -EIO;
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int psp_v14_0_update_spirom(struct psp_context *psp,
 611                                    uint64_t fw_pri_mc_addr)
 612 {
 613         struct amdgpu_device *adev = psp->adev;
 614         int ret;
 615
 616         /* Confirm PSP is ready to start */
 617         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 618                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 619         if (ret) {
 620                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 621                 return ret;
 622         }
 623
 624         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 625
 626         ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 627         if (ret)
 628                 return ret;
 629
 630         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 631
 632         ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 633         if (ret)
 634                 return ret;
 635
 636         psp->vbflash_done = true;
 637
 638         ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 639         if (ret)
 640                 return ret;
 641
 642         return 0;
 643 }
 644
 645 static int psp_v14_0_vbflash_status(struct psp_context *psp)
 646 {
 647         struct amdgpu_device *adev = psp->adev;
 648
 649         return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
 650 }
 651
 652 static const struct psp_funcs psp_v14_0_funcs = {
 653         .init_microcode = psp_v14_0_init_microcode,
 654         .bootloader_load_kdb = psp_v14_0_bootloader_load_kdb,
 655         .bootloader_load_spl = psp_v14_0_bootloader_load_spl,
 656         .bootloader_load_sysdrv = psp_v14_0_bootloader_load_sysdrv,
 657         .bootloader_load_soc_drv = psp_v14_0_bootloader_load_soc_drv,
 658         .bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv,
 659         .bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv,
 660         .bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv,
 661         .bootloader_load_ipkeymgr_drv = psp_v14_0_bootloader_load_ipkeymgr_drv,
 662         .bootloader_load_sos = psp_v14_0_bootloader_load_sos,
 663         .ring_create = psp_v14_0_ring_create,
 664         .ring_stop = psp_v14_0_ring_stop,
 665         .ring_destroy = psp_v14_0_ring_destroy,
 666         .ring_get_wptr = psp_v14_0_ring_get_wptr,
 667         .ring_set_wptr = psp_v14_0_ring_set_wptr,
 668         .mem_training = psp_v14_0_memory_training,
 669         .load_usbc_pd_fw = psp_v14_0_load_usbc_pd_fw,
 670         .read_usbc_pd_fw = psp_v14_0_read_usbc_pd_fw,
 671         .update_spirom = psp_v14_0_update_spirom,
 672         .vbflash_stat = psp_v14_0_vbflash_status
 673 };
 674
 675 void psp_v14_0_set_psp_funcs(struct psp_context *psp)
 676 {
 677         psp->funcs = &psp_v14_0_funcs;
 678 }