drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc_link_dp.h"
  32 #include "link_enc_cfg.h"
  33 #include "dc/inc/core_types.h"
  34 #include "dal_asic_id.h"
  35 #include "dmub/dmub_srv.h"
  36 #include "dc/inc/hw/dmcu.h"
  37 #include "dc/inc/hw/abm.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "dc/dc_edid_parser.h"
  40 #include "dc/dc_stat.h"
  41 #include "amdgpu_dm_trace.h"
  42
  43 #include "vid.h"
  44 #include "amdgpu.h"
  45 #include "amdgpu_display.h"
  46 #include "amdgpu_ucode.h"
  47 #include "atom.h"
  48 #include "amdgpu_dm.h"
  49 #include "amdgpu_dm_plane.h"
  50 #include "amdgpu_dm_crtc.h"
  51 #ifdef CONFIG_DRM_AMD_DC_HDCP
  52 #include "amdgpu_dm_hdcp.h"
  53 #include <drm/display/drm_hdcp_helper.h>
  54 #endif
  55 #include "amdgpu_pm.h"
  56 #include "amdgpu_atombios.h"
  57
  58 #include "amd_shared.h"
  59 #include "amdgpu_dm_irq.h"
  60 #include "dm_helpers.h"
  61 #include "amdgpu_dm_mst_types.h"
  62 #if defined(CONFIG_DEBUG_FS)
  63 #include "amdgpu_dm_debugfs.h"
  64 #endif
  65 #include "amdgpu_dm_psr.h"
  66
  67 #include "ivsrcid/ivsrcid_vislands30.h"
  68
  69 #include "i2caux_interface.h"
  70 #include <linux/module.h>
  71 #include <linux/moduleparam.h>
  72 #include <linux/types.h>
  73 #include <linux/pm_runtime.h>
  74 #include <linux/pci.h>
  75 #include <linux/firmware.h>
  76 #include <linux/component.h>
  77 #include <linux/dmi.h>
  78
  79 #include <drm/display/drm_dp_mst_helper.h>
  80 #include <drm/display/drm_hdmi_helper.h>
  81 #include <drm/drm_atomic.h>
  82 #include <drm/drm_atomic_uapi.h>
  83 #include <drm/drm_atomic_helper.h>
  84 #include <drm/drm_blend.h>
  85 #include <drm/drm_fourcc.h>
  86 #include <drm/drm_edid.h>
  87 #include <drm/drm_vblank.h>
  88 #include <drm/drm_audio_component.h>
  89 #include <drm/drm_gem_atomic_helper.h>
  90 #include <drm/drm_plane_helper.h>
  91
  92 #include <acpi/video.h>
  93
  94 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  95
  96 #include "dcn/dcn_1_0_offset.h"
  97 #include "dcn/dcn_1_0_sh_mask.h"
  98 #include "soc15_hw_ip.h"
  99 #include "soc15_common.h"
 100 #include "vega10_ip_offset.h"
 101
 102 #include "gc/gc_11_0_0_offset.h"
 103 #include "gc/gc_11_0_0_sh_mask.h"
 104
 105 #include "modules/inc/mod_freesync.h"
 106 #include "modules/power/power_helpers.h"
 107 #include "modules/inc/mod_info_packet.h"
 108
 109 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 110 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 111 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 112 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 113 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 115 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 117 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 119 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 121 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 123 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 125 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 127 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 129 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 131
 132 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 134 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 136
 137 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 138 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 139
 140 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 141 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 142
 143 /* Number of bytes in PSP header for firmware. */
 144 #define PSP_HEADER_BYTES 0x100
 145
 146 /* Number of bytes in PSP footer for firmware. */
 147 #define PSP_FOOTER_BYTES 0x100
 148
 149 /**
 150  * DOC: overview
 151  *
 152  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 153  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 154  * requests into DC requests, and DC responses into DRM responses.
 155  *
 156  * The root control structure is &struct amdgpu_display_manager.
 157  */
 158
 159 /* basic init/fini API */
 160 static int amdgpu_dm_init(struct amdgpu_device *adev);
 161 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 162 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 163
 164 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 165 {
 166         switch (link->dpcd_caps.dongle_type) {
 167         case DISPLAY_DONGLE_NONE:
 168                 return DRM_MODE_SUBCONNECTOR_Native;
 169         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 170                 return DRM_MODE_SUBCONNECTOR_VGA;
 171         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 172         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 173                 return DRM_MODE_SUBCONNECTOR_DVID;
 174         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 175         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 176                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 177         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 178         default:
 179                 return DRM_MODE_SUBCONNECTOR_Unknown;
 180         }
 181 }
 182
 183 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 184 {
 185         struct dc_link *link = aconnector->dc_link;
 186         struct drm_connector *connector = &aconnector->base;
 187         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 188
 189         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 190                 return;
 191
 192         if (aconnector->dc_sink)
 193                 subconnector = get_subconnector_type(link);
 194
 195         drm_object_property_set_value(&connector->base,
 196                         connector->dev->mode_config.dp_subconnector_property,
 197                         subconnector);
 198 }
 199
 200 /*
 201  * initializes drm_device display related structures, based on the information
 202  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 203  * drm_encoder, drm_mode_config
 204  *
 205  * Returns 0 on success
 206  */
 207 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 208 /* removes and deallocates the drm structures, created by the above function */
 209 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 210
 211 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 212                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 213                                     uint32_t link_index,
 214                                     struct amdgpu_encoder *amdgpu_encoder);
 215 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 216                                   struct amdgpu_encoder *aencoder,
 217                                   uint32_t link_index);
 218
 219 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 220
 221 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 222
 223 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 224                                   struct drm_atomic_state *state);
 225
 226 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 227 static void handle_hpd_rx_irq(void *param);
 228
 229 static bool
 230 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 231                                  struct drm_crtc_state *new_crtc_state);
 232 /*
 233  * dm_vblank_get_counter
 234  *
 235  * @brief
 236  * Get counter for number of vertical blanks
 237  *
 238  * @param
 239  * struct amdgpu_device *adev - [in] desired amdgpu device
 240  * int disp_idx - [in] which CRTC to get the counter from
 241  *
 242  * @return
 243  * Counter for vertical blanks
 244  */
 245 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 246 {
 247         if (crtc >= adev->mode_info.num_crtc)
 248                 return 0;
 249         else {
 250                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 251
 252                 if (acrtc->dm_irq_params.stream == NULL) {
 253                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 254                                   crtc);
 255                         return 0;
 256                 }
 257
 258                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 259         }
 260 }
 261
 262 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 263                                   u32 *vbl, u32 *position)
 264 {
 265         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 266
 267         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 268                 return -EINVAL;
 269         else {
 270                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 271
 272                 if (acrtc->dm_irq_params.stream ==  NULL) {
 273                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 274                                   crtc);
 275                         return 0;
 276                 }
 277
 278                 /*
 279                  * TODO rework base driver to use values directly.
 280                  * for now parse it back into reg-format
 281                  */
 282                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 283                                          &v_blank_start,
 284                                          &v_blank_end,
 285                                          &h_position,
 286                                          &v_position);
 287
 288                 *position = v_position | (h_position << 16);
 289                 *vbl = v_blank_start | (v_blank_end << 16);
 290         }
 291
 292         return 0;
 293 }
 294
 295 static bool dm_is_idle(void *handle)
 296 {
 297         /* XXX todo */
 298         return true;
 299 }
 300
 301 static int dm_wait_for_idle(void *handle)
 302 {
 303         /* XXX todo */
 304         return 0;
 305 }
 306
 307 static bool dm_check_soft_reset(void *handle)
 308 {
 309         return false;
 310 }
 311
 312 static int dm_soft_reset(void *handle)
 313 {
 314         /* XXX todo */
 315         return 0;
 316 }
 317
 318 static struct amdgpu_crtc *
 319 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 320                      int otg_inst)
 321 {
 322         struct drm_device *dev = adev_to_drm(adev);
 323         struct drm_crtc *crtc;
 324         struct amdgpu_crtc *amdgpu_crtc;
 325
 326         if (WARN_ON(otg_inst == -1))
 327                 return adev->mode_info.crtcs[0];
 328
 329         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 330                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 331
 332                 if (amdgpu_crtc->otg_inst == otg_inst)
 333                         return amdgpu_crtc;
 334         }
 335
 336         return NULL;
 337 }
 338
 339 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 340                                               struct dm_crtc_state *new_state)
 341 {
 342         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 343                 return true;
 344         else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
 345                 return true;
 346         else
 347                 return false;
 348 }
 349
 350 /**
 351  * dm_pflip_high_irq() - Handle pageflip interrupt
 352  * @interrupt_params: ignored
 353  *
 354  * Handles the pageflip interrupt by notifying all interested parties
 355  * that the pageflip has been completed.
 356  */
 357 static void dm_pflip_high_irq(void *interrupt_params)
 358 {
 359         struct amdgpu_crtc *amdgpu_crtc;
 360         struct common_irq_params *irq_params = interrupt_params;
 361         struct amdgpu_device *adev = irq_params->adev;
 362         unsigned long flags;
 363         struct drm_pending_vblank_event *e;
 364         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 365         bool vrr_active;
 366
 367         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 368
 369         /* IRQ could occur when in initial stage */
 370         /* TODO work and BO cleanup */
 371         if (amdgpu_crtc == NULL) {
 372                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 373                 return;
 374         }
 375
 376         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 377
 378         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 379                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 380                                                  amdgpu_crtc->pflip_status,
 381                                                  AMDGPU_FLIP_SUBMITTED,
 382                                                  amdgpu_crtc->crtc_id,
 383                                                  amdgpu_crtc);
 384                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 385                 return;
 386         }
 387
 388         /* page flip completed. */
 389         e = amdgpu_crtc->event;
 390         amdgpu_crtc->event = NULL;
 391
 392         WARN_ON(!e);
 393
 394         vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
 395
 396         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 397         if (!vrr_active ||
 398             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 399                                       &v_blank_end, &hpos, &vpos) ||
 400             (vpos < v_blank_start)) {
 401                 /* Update to correct count and vblank timestamp if racing with
 402                  * vblank irq. This also updates to the correct vblank timestamp
 403                  * even in VRR mode, as scanout is past the front-porch atm.
 404                  */
 405                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 406
 407                 /* Wake up userspace by sending the pageflip event with proper
 408                  * count and timestamp of vblank of flip completion.
 409                  */
 410                 if (e) {
 411                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 412
 413                         /* Event sent, so done with vblank for this flip */
 414                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 415                 }
 416         } else if (e) {
 417                 /* VRR active and inside front-porch: vblank count and
 418                  * timestamp for pageflip event will only be up to date after
 419                  * drm_crtc_handle_vblank() has been executed from late vblank
 420                  * irq handler after start of back-porch (vline 0). We queue the
 421                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 422                  * updated timestamp and count, once it runs after us.
 423                  *
 424                  * We need to open-code this instead of using the helper
 425                  * drm_crtc_arm_vblank_event(), as that helper would
 426                  * call drm_crtc_accurate_vblank_count(), which we must
 427                  * not call in VRR mode while we are in front-porch!
 428                  */
 429
 430                 /* sequence will be replaced by real count during send-out. */
 431                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 432                 e->pipe = amdgpu_crtc->crtc_id;
 433
 434                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 435                 e = NULL;
 436         }
 437
 438         /* Keep track of vblank of this flip for flip throttling. We use the
 439          * cooked hw counter, as that one incremented at start of this vblank
 440          * of pageflip completion, so last_flip_vblank is the forbidden count
 441          * for queueing new pageflips if vsync + VRR is enabled.
 442          */
 443         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 444                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 445
 446         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 447         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 448
 449         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 450                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 451                      vrr_active, (int) !e);
 452 }
 453
 454 static void dm_vupdate_high_irq(void *interrupt_params)
 455 {
 456         struct common_irq_params *irq_params = interrupt_params;
 457         struct amdgpu_device *adev = irq_params->adev;
 458         struct amdgpu_crtc *acrtc;
 459         struct drm_device *drm_dev;
 460         struct drm_vblank_crtc *vblank;
 461         ktime_t frame_duration_ns, previous_timestamp;
 462         unsigned long flags;
 463         int vrr_active;
 464
 465         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 466
 467         if (acrtc) {
 468                 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 469                 drm_dev = acrtc->base.dev;
 470                 vblank = &drm_dev->vblank[acrtc->base.index];
 471                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 472                 frame_duration_ns = vblank->time - previous_timestamp;
 473
 474                 if (frame_duration_ns > 0) {
 475                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 476                                                 frame_duration_ns,
 477                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 478                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 479                 }
 480
 481                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 482                               acrtc->crtc_id,
 483                               vrr_active);
 484
 485                 /* Core vblank handling is done here after end of front-porch in
 486                  * vrr mode, as vblank timestamping will give valid results
 487                  * while now done after front-porch. This will also deliver
 488                  * page-flip completion events that have been queued to us
 489                  * if a pageflip happened inside front-porch.
 490                  */
 491                 if (vrr_active) {
 492                         dm_crtc_handle_vblank(acrtc);
 493
 494                         /* BTR processing for pre-DCE12 ASICs */
 495                         if (acrtc->dm_irq_params.stream &&
 496                             adev->family < AMDGPU_FAMILY_AI) {
 497                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 498                                 mod_freesync_handle_v_update(
 499                                     adev->dm.freesync_module,
 500                                     acrtc->dm_irq_params.stream,
 501                                     &acrtc->dm_irq_params.vrr_params);
 502
 503                                 dc_stream_adjust_vmin_vmax(
 504                                     adev->dm.dc,
 505                                     acrtc->dm_irq_params.stream,
 506                                     &acrtc->dm_irq_params.vrr_params.adjust);
 507                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 508                         }
 509                 }
 510         }
 511 }
 512
 513 /**
 514  * dm_crtc_high_irq() - Handles CRTC interrupt
 515  * @interrupt_params: used for determining the CRTC instance
 516  *
 517  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 518  * event handler.
 519  */
 520 static void dm_crtc_high_irq(void *interrupt_params)
 521 {
 522         struct common_irq_params *irq_params = interrupt_params;
 523         struct amdgpu_device *adev = irq_params->adev;
 524         struct amdgpu_crtc *acrtc;
 525         unsigned long flags;
 526         int vrr_active;
 527
 528         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 529         if (!acrtc)
 530                 return;
 531
 532         vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 533
 534         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 535                       vrr_active, acrtc->dm_irq_params.active_planes);
 536
 537         /**
 538          * Core vblank handling at start of front-porch is only possible
 539          * in non-vrr mode, as only there vblank timestamping will give
 540          * valid results while done in front-porch. Otherwise defer it
 541          * to dm_vupdate_high_irq after end of front-porch.
 542          */
 543         if (!vrr_active)
 544                 dm_crtc_handle_vblank(acrtc);
 545
 546         /**
 547          * Following stuff must happen at start of vblank, for crc
 548          * computation and below-the-range btr support in vrr mode.
 549          */
 550         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 551
 552         /* BTR updates need to happen before VUPDATE on Vega and above. */
 553         if (adev->family < AMDGPU_FAMILY_AI)
 554                 return;
 555
 556         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 557
 558         if (acrtc->dm_irq_params.stream &&
 559             acrtc->dm_irq_params.vrr_params.supported &&
 560             acrtc->dm_irq_params.freesync_config.state ==
 561                     VRR_STATE_ACTIVE_VARIABLE) {
 562                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 563                                              acrtc->dm_irq_params.stream,
 564                                              &acrtc->dm_irq_params.vrr_params);
 565
 566                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 567                                            &acrtc->dm_irq_params.vrr_params.adjust);
 568         }
 569
 570         /*
 571          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 572          * In that case, pageflip completion interrupts won't fire and pageflip
 573          * completion events won't get delivered. Prevent this by sending
 574          * pending pageflip events from here if a flip is still pending.
 575          *
 576          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 577          * avoid race conditions between flip programming and completion,
 578          * which could cause too early flip completion events.
 579          */
 580         if (adev->family >= AMDGPU_FAMILY_RV &&
 581             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 582             acrtc->dm_irq_params.active_planes == 0) {
 583                 if (acrtc->event) {
 584                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 585                         acrtc->event = NULL;
 586                         drm_crtc_vblank_put(&acrtc->base);
 587                 }
 588                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 589         }
 590
 591         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 592 }
 593
 594 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 595 /**
 596  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 597  * DCN generation ASICs
 598  * @interrupt_params: interrupt parameters
 599  *
 600  * Used to set crc window/read out crc value at vertical line 0 position
 601  */
 602 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 603 {
 604         struct common_irq_params *irq_params = interrupt_params;
 605         struct amdgpu_device *adev = irq_params->adev;
 606         struct amdgpu_crtc *acrtc;
 607
 608         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 609
 610         if (!acrtc)
 611                 return;
 612
 613         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 614 }
 615 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 616
 617 /**
 618  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 619  * @adev: amdgpu_device pointer
 620  * @notify: dmub notification structure
 621  *
 622  * Dmub AUX or SET_CONFIG command completion processing callback
 623  * Copies dmub notification to DM which is to be read by AUX command.
 624  * issuing thread and also signals the event to wake up the thread.
 625  */
 626 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 627                                         struct dmub_notification *notify)
 628 {
 629         if (adev->dm.dmub_notify)
 630                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 631         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 632                 complete(&adev->dm.dmub_aux_transfer_done);
 633 }
 634
 635 /**
 636  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 637  * @adev: amdgpu_device pointer
 638  * @notify: dmub notification structure
 639  *
 640  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 641  * ink index and calls helper to do the processing.
 642  */
 643 static void dmub_hpd_callback(struct amdgpu_device *adev,
 644                               struct dmub_notification *notify)
 645 {
 646         struct amdgpu_dm_connector *aconnector;
 647         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 648         struct drm_connector *connector;
 649         struct drm_connector_list_iter iter;
 650         struct dc_link *link;
 651         uint8_t link_index = 0;
 652         struct drm_device *dev;
 653
 654         if (adev == NULL)
 655                 return;
 656
 657         if (notify == NULL) {
 658                 DRM_ERROR("DMUB HPD callback notification was NULL");
 659                 return;
 660         }
 661
 662         if (notify->link_index > adev->dm.dc->link_count) {
 663                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 664                 return;
 665         }
 666
 667         link_index = notify->link_index;
 668         link = adev->dm.dc->links[link_index];
 669         dev = adev->dm.ddev;
 670
 671         drm_connector_list_iter_begin(dev, &iter);
 672         drm_for_each_connector_iter(connector, &iter) {
 673                 aconnector = to_amdgpu_dm_connector(connector);
 674                 if (link && aconnector->dc_link == link) {
 675                         DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 676                         hpd_aconnector = aconnector;
 677                         break;
 678                 }
 679         }
 680         drm_connector_list_iter_end(&iter);
 681
 682         if (hpd_aconnector) {
 683                 if (notify->type == DMUB_NOTIFICATION_HPD)
 684                         handle_hpd_irq_helper(hpd_aconnector);
 685                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 686                         handle_hpd_rx_irq(hpd_aconnector);
 687         }
 688 }
 689
 690 /**
 691  * register_dmub_notify_callback - Sets callback for DMUB notify
 692  * @adev: amdgpu_device pointer
 693  * @type: Type of dmub notification
 694  * @callback: Dmub interrupt callback function
 695  * @dmub_int_thread_offload: offload indicator
 696  *
 697  * API to register a dmub callback handler for a dmub notification
 698  * Also sets indicator whether callback processing to be offloaded.
 699  * to dmub interrupt handling thread
 700  * Return: true if successfully registered, false if there is existing registration
 701  */
 702 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 703                                           enum dmub_notification_type type,
 704                                           dmub_notify_interrupt_callback_t callback,
 705                                           bool dmub_int_thread_offload)
 706 {
 707         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 708                 adev->dm.dmub_callback[type] = callback;
 709                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 710         } else
 711                 return false;
 712
 713         return true;
 714 }
 715
 716 static void dm_handle_hpd_work(struct work_struct *work)
 717 {
 718         struct dmub_hpd_work *dmub_hpd_wrk;
 719
 720         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 721
 722         if (!dmub_hpd_wrk->dmub_notify) {
 723                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 724                 return;
 725         }
 726
 727         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 728                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 729                 dmub_hpd_wrk->dmub_notify);
 730         }
 731
 732         kfree(dmub_hpd_wrk->dmub_notify);
 733         kfree(dmub_hpd_wrk);
 734
 735 }
 736
 737 #define DMUB_TRACE_MAX_READ 64
 738 /**
 739  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 740  * @interrupt_params: used for determining the Outbox instance
 741  *
 742  * Handles the Outbox Interrupt
 743  * event handler.
 744  */
 745 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 746 {
 747         struct dmub_notification notify;
 748         struct common_irq_params *irq_params = interrupt_params;
 749         struct amdgpu_device *adev = irq_params->adev;
 750         struct amdgpu_display_manager *dm = &adev->dm;
 751         struct dmcub_trace_buf_entry entry = { 0 };
 752         uint32_t count = 0;
 753         struct dmub_hpd_work *dmub_hpd_wrk;
 754         struct dc_link *plink = NULL;
 755
 756         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 757                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 758
 759                 do {
 760                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 761                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 762                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 763                                 continue;
 764                         }
 765                         if (!dm->dmub_callback[notify.type]) {
 766                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 767                                 continue;
 768                         }
 769                         if (dm->dmub_thread_offload[notify.type] == true) {
 770                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 771                                 if (!dmub_hpd_wrk) {
 772                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 773                                         return;
 774                                 }
 775                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 776                                 if (!dmub_hpd_wrk->dmub_notify) {
 777                                         kfree(dmub_hpd_wrk);
 778                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 779                                         return;
 780                                 }
 781                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 782                                 if (dmub_hpd_wrk->dmub_notify)
 783                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 784                                 dmub_hpd_wrk->adev = adev;
 785                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 786                                         plink = adev->dm.dc->links[notify.link_index];
 787                                         if (plink) {
 788                                                 plink->hpd_status =
 789                                                         notify.hpd_status == DP_HPD_PLUG;
 790                                         }
 791                                 }
 792                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 793                         } else {
 794                                 dm->dmub_callback[notify.type](adev, &notify);
 795                         }
 796                 } while (notify.pending_notification);
 797         }
 798
 799
 800         do {
 801                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 802                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 803                                                         entry.param0, entry.param1);
 804
 805                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 806                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 807                 } else
 808                         break;
 809
 810                 count++;
 811
 812         } while (count <= DMUB_TRACE_MAX_READ);
 813
 814         if (count > DMUB_TRACE_MAX_READ)
 815                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 816 }
 817
 818 static int dm_set_clockgating_state(void *handle,
 819                   enum amd_clockgating_state state)
 820 {
 821         return 0;
 822 }
 823
 824 static int dm_set_powergating_state(void *handle,
 825                   enum amd_powergating_state state)
 826 {
 827         return 0;
 828 }
 829
 830 /* Prototypes of private functions */
 831 static int dm_early_init(void* handle);
 832
 833 /* Allocate memory for FBC compressed data  */
 834 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 835 {
 836         struct drm_device *dev = connector->dev;
 837         struct amdgpu_device *adev = drm_to_adev(dev);
 838         struct dm_compressor_info *compressor = &adev->dm.compressor;
 839         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 840         struct drm_display_mode *mode;
 841         unsigned long max_size = 0;
 842
 843         if (adev->dm.dc->fbc_compressor == NULL)
 844                 return;
 845
 846         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 847                 return;
 848
 849         if (compressor->bo_ptr)
 850                 return;
 851
 852
 853         list_for_each_entry(mode, &connector->modes, head) {
 854                 if (max_size < mode->htotal * mode->vtotal)
 855                         max_size = mode->htotal * mode->vtotal;
 856         }
 857
 858         if (max_size) {
 859                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 860                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 861                             &compressor->gpu_addr, &compressor->cpu_addr);
 862
 863                 if (r)
 864                         DRM_ERROR("DM: Failed to initialize FBC\n");
 865                 else {
 866                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 867                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 868                 }
 869
 870         }
 871
 872 }
 873
 874 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 875                                           int pipe, bool *enabled,
 876                                           unsigned char *buf, int max_bytes)
 877 {
 878         struct drm_device *dev = dev_get_drvdata(kdev);
 879         struct amdgpu_device *adev = drm_to_adev(dev);
 880         struct drm_connector *connector;
 881         struct drm_connector_list_iter conn_iter;
 882         struct amdgpu_dm_connector *aconnector;
 883         int ret = 0;
 884
 885         *enabled = false;
 886
 887         mutex_lock(&adev->dm.audio_lock);
 888
 889         drm_connector_list_iter_begin(dev, &conn_iter);
 890         drm_for_each_connector_iter(connector, &conn_iter) {
 891                 aconnector = to_amdgpu_dm_connector(connector);
 892                 if (aconnector->audio_inst != port)
 893                         continue;
 894
 895                 *enabled = true;
 896                 ret = drm_eld_size(connector->eld);
 897                 memcpy(buf, connector->eld, min(max_bytes, ret));
 898
 899                 break;
 900         }
 901         drm_connector_list_iter_end(&conn_iter);
 902
 903         mutex_unlock(&adev->dm.audio_lock);
 904
 905         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 906
 907         return ret;
 908 }
 909
 910 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 911         .get_eld = amdgpu_dm_audio_component_get_eld,
 912 };
 913
 914 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 915                                        struct device *hda_kdev, void *data)
 916 {
 917         struct drm_device *dev = dev_get_drvdata(kdev);
 918         struct amdgpu_device *adev = drm_to_adev(dev);
 919         struct drm_audio_component *acomp = data;
 920
 921         acomp->ops = &amdgpu_dm_audio_component_ops;
 922         acomp->dev = kdev;
 923         adev->dm.audio_component = acomp;
 924
 925         return 0;
 926 }
 927
 928 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 929                                           struct device *hda_kdev, void *data)
 930 {
 931         struct drm_device *dev = dev_get_drvdata(kdev);
 932         struct amdgpu_device *adev = drm_to_adev(dev);
 933         struct drm_audio_component *acomp = data;
 934
 935         acomp->ops = NULL;
 936         acomp->dev = NULL;
 937         adev->dm.audio_component = NULL;
 938 }
 939
 940 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 941         .bind   = amdgpu_dm_audio_component_bind,
 942         .unbind = amdgpu_dm_audio_component_unbind,
 943 };
 944
 945 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 946 {
 947         int i, ret;
 948
 949         if (!amdgpu_audio)
 950                 return 0;
 951
 952         adev->mode_info.audio.enabled = true;
 953
 954         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 955
 956         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 957                 adev->mode_info.audio.pin[i].channels = -1;
 958                 adev->mode_info.audio.pin[i].rate = -1;
 959                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 960                 adev->mode_info.audio.pin[i].status_bits = 0;
 961                 adev->mode_info.audio.pin[i].category_code = 0;
 962                 adev->mode_info.audio.pin[i].connected = false;
 963                 adev->mode_info.audio.pin[i].id =
 964                         adev->dm.dc->res_pool->audios[i]->inst;
 965                 adev->mode_info.audio.pin[i].offset = 0;
 966         }
 967
 968         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 969         if (ret < 0)
 970                 return ret;
 971
 972         adev->dm.audio_registered = true;
 973
 974         return 0;
 975 }
 976
 977 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 978 {
 979         if (!amdgpu_audio)
 980                 return;
 981
 982         if (!adev->mode_info.audio.enabled)
 983                 return;
 984
 985         if (adev->dm.audio_registered) {
 986                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 987                 adev->dm.audio_registered = false;
 988         }
 989
 990         /* TODO: Disable audio? */
 991
 992         adev->mode_info.audio.enabled = false;
 993 }
 994
 995 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 996 {
 997         struct drm_audio_component *acomp = adev->dm.audio_component;
 998
 999         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1000                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1001
1002                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1003                                                  pin, -1);
1004         }
1005 }
1006
1007 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1008 {
1009         const struct dmcub_firmware_header_v1_0 *hdr;
1010         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1011         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1012         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1013         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1014         struct abm *abm = adev->dm.dc->res_pool->abm;
1015         struct dmub_srv_hw_params hw_params;
1016         enum dmub_status status;
1017         const unsigned char *fw_inst_const, *fw_bss_data;
1018         uint32_t i, fw_inst_const_size, fw_bss_data_size;
1019         bool has_hw_support;
1020
1021         if (!dmub_srv)
1022                 /* DMUB isn't supported on the ASIC. */
1023                 return 0;
1024
1025         if (!fb_info) {
1026                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1027                 return -EINVAL;
1028         }
1029
1030         if (!dmub_fw) {
1031                 /* Firmware required for DMUB support. */
1032                 DRM_ERROR("No firmware provided for DMUB.\n");
1033                 return -EINVAL;
1034         }
1035
1036         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1037         if (status != DMUB_STATUS_OK) {
1038                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1039                 return -EINVAL;
1040         }
1041
1042         if (!has_hw_support) {
1043                 DRM_INFO("DMUB unsupported on ASIC\n");
1044                 return 0;
1045         }
1046
1047         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1048         status = dmub_srv_hw_reset(dmub_srv);
1049         if (status != DMUB_STATUS_OK)
1050                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1051
1052         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1053
1054         fw_inst_const = dmub_fw->data +
1055                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1056                         PSP_HEADER_BYTES;
1057
1058         fw_bss_data = dmub_fw->data +
1059                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1060                       le32_to_cpu(hdr->inst_const_bytes);
1061
1062         /* Copy firmware and bios info into FB memory. */
1063         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1064                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1065
1066         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1067
1068         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1069          * amdgpu_ucode_init_single_fw will load dmub firmware
1070          * fw_inst_const part to cw0; otherwise, the firmware back door load
1071          * will be done by dm_dmub_hw_init
1072          */
1073         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1074                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1075                                 fw_inst_const_size);
1076         }
1077
1078         if (fw_bss_data_size)
1079                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1080                        fw_bss_data, fw_bss_data_size);
1081
1082         /* Copy firmware bios info into FB memory. */
1083         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1084                adev->bios_size);
1085
1086         /* Reset regions that need to be reset. */
1087         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1088         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1089
1090         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1091                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1092
1093         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1094                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1095
1096         /* Initialize hardware. */
1097         memset(&hw_params, 0, sizeof(hw_params));
1098         hw_params.fb_base = adev->gmc.fb_start;
1099         hw_params.fb_offset = adev->gmc.aper_base;
1100
1101         /* backdoor load firmware and trigger dmub running */
1102         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1103                 hw_params.load_inst_const = true;
1104
1105         if (dmcu)
1106                 hw_params.psp_version = dmcu->psp_version;
1107
1108         for (i = 0; i < fb_info->num_fb; ++i)
1109                 hw_params.fb[i] = &fb_info->fb[i];
1110
1111         switch (adev->ip_versions[DCE_HWIP][0]) {
1112         case IP_VERSION(3, 1, 3):
1113         case IP_VERSION(3, 1, 4):
1114                 hw_params.dpia_supported = true;
1115                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1116                 break;
1117         default:
1118                 break;
1119         }
1120
1121         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1122         if (status != DMUB_STATUS_OK) {
1123                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1124                 return -EINVAL;
1125         }
1126
1127         /* Wait for firmware load to finish. */
1128         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1129         if (status != DMUB_STATUS_OK)
1130                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1131
1132         /* Init DMCU and ABM if available. */
1133         if (dmcu && abm) {
1134                 dmcu->funcs->dmcu_init(dmcu);
1135                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1136         }
1137
1138         if (!adev->dm.dc->ctx->dmub_srv)
1139                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1140         if (!adev->dm.dc->ctx->dmub_srv) {
1141                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1142                 return -ENOMEM;
1143         }
1144
1145         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1146                  adev->dm.dmcub_fw_version);
1147
1148         return 0;
1149 }
1150
1151 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1152 {
1153         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1154         enum dmub_status status;
1155         bool init;
1156
1157         if (!dmub_srv) {
1158                 /* DMUB isn't supported on the ASIC. */
1159                 return;
1160         }
1161
1162         status = dmub_srv_is_hw_init(dmub_srv, &init);
1163         if (status != DMUB_STATUS_OK)
1164                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1165
1166         if (status == DMUB_STATUS_OK && init) {
1167                 /* Wait for firmware load to finish. */
1168                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1169                 if (status != DMUB_STATUS_OK)
1170                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1171         } else {
1172                 /* Perform the full hardware initialization. */
1173                 dm_dmub_hw_init(adev);
1174         }
1175 }
1176
1177 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1178 {
1179         uint64_t pt_base;
1180         uint32_t logical_addr_low;
1181         uint32_t logical_addr_high;
1182         uint32_t agp_base, agp_bot, agp_top;
1183         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1184
1185         memset(pa_config, 0, sizeof(*pa_config));
1186
1187         logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1188         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1189
1190         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1191                 /*
1192                  * Raven2 has a HW issue that it is unable to use the vram which
1193                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1194                  * workaround that increase system aperture high address (add 1)
1195                  * to get rid of the VM fault and hardware hang.
1196                  */
1197                 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1198         else
1199                 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1200
1201         agp_base = 0;
1202         agp_bot = adev->gmc.agp_start >> 24;
1203         agp_top = adev->gmc.agp_end >> 24;
1204
1205
1206         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1207         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1208         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1209         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1210         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1211         page_table_base.low_part = lower_32_bits(pt_base);
1212
1213         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1214         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1215
1216         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1217         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1218         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1219
1220         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1221         pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
1222         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1223
1224         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1225         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1226         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1227
1228         pa_config->is_hvm_enabled = 0;
1229
1230 }
1231
1232 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1233 {
1234         struct hpd_rx_irq_offload_work *offload_work;
1235         struct amdgpu_dm_connector *aconnector;
1236         struct dc_link *dc_link;
1237         struct amdgpu_device *adev;
1238         enum dc_connection_type new_connection_type = dc_connection_none;
1239         unsigned long flags;
1240
1241         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1242         aconnector = offload_work->offload_wq->aconnector;
1243
1244         if (!aconnector) {
1245                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1246                 goto skip;
1247         }
1248
1249         adev = drm_to_adev(aconnector->base.dev);
1250         dc_link = aconnector->dc_link;
1251
1252         mutex_lock(&aconnector->hpd_lock);
1253         if (!dc_link_detect_sink(dc_link, &new_connection_type))
1254                 DRM_ERROR("KMS: Failed to detect connector\n");
1255         mutex_unlock(&aconnector->hpd_lock);
1256
1257         if (new_connection_type == dc_connection_none)
1258                 goto skip;
1259
1260         if (amdgpu_in_reset(adev))
1261                 goto skip;
1262
1263         mutex_lock(&adev->dm.dc_lock);
1264         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST)
1265                 dc_link_dp_handle_automated_test(dc_link);
1266         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1267                         hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
1268                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1269                 dc_link_dp_handle_link_loss(dc_link);
1270                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1271                 offload_work->offload_wq->is_handling_link_loss = false;
1272                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1273         }
1274         mutex_unlock(&adev->dm.dc_lock);
1275
1276 skip:
1277         kfree(offload_work);
1278
1279 }
1280
1281 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1282 {
1283         int max_caps = dc->caps.max_links;
1284         int i = 0;
1285         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1286
1287         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1288
1289         if (!hpd_rx_offload_wq)
1290                 return NULL;
1291
1292
1293         for (i = 0; i < max_caps; i++) {
1294                 hpd_rx_offload_wq[i].wq =
1295                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1296
1297                 if (hpd_rx_offload_wq[i].wq == NULL) {
1298                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1299                         goto out_err;
1300                 }
1301
1302                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1303         }
1304
1305         return hpd_rx_offload_wq;
1306
1307 out_err:
1308         for (i = 0; i < max_caps; i++) {
1309                 if (hpd_rx_offload_wq[i].wq)
1310                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1311         }
1312         kfree(hpd_rx_offload_wq);
1313         return NULL;
1314 }
1315
1316 struct amdgpu_stutter_quirk {
1317         u16 chip_vendor;
1318         u16 chip_device;
1319         u16 subsys_vendor;
1320         u16 subsys_device;
1321         u8 revision;
1322 };
1323
1324 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1325         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1326         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1327         { 0, 0, 0, 0, 0 },
1328 };
1329
1330 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1331 {
1332         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1333
1334         while (p && p->chip_device != 0) {
1335                 if (pdev->vendor == p->chip_vendor &&
1336                     pdev->device == p->chip_device &&
1337                     pdev->subsystem_vendor == p->subsys_vendor &&
1338                     pdev->subsystem_device == p->subsys_device &&
1339                     pdev->revision == p->revision) {
1340                         return true;
1341                 }
1342                 ++p;
1343         }
1344         return false;
1345 }
1346
1347 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1348         {
1349                 .matches = {
1350                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1351                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1352                 },
1353         },
1354         {
1355                 .matches = {
1356                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1357                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1358                 },
1359         },
1360         {
1361                 .matches = {
1362                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1363                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1364                 },
1365         },
1366         {}
1367 };
1368
1369 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1370 {
1371         const struct dmi_system_id *dmi_id;
1372
1373         dm->aux_hpd_discon_quirk = false;
1374
1375         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1376         if (dmi_id) {
1377                 dm->aux_hpd_discon_quirk = true;
1378                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1379         }
1380 }
1381
1382 static int amdgpu_dm_init(struct amdgpu_device *adev)
1383 {
1384         struct dc_init_data init_data;
1385 #ifdef CONFIG_DRM_AMD_DC_HDCP
1386         struct dc_callback_init init_params;
1387 #endif
1388         int r;
1389
1390         adev->dm.ddev = adev_to_drm(adev);
1391         adev->dm.adev = adev;
1392
1393         /* Zero all the fields */
1394         memset(&init_data, 0, sizeof(init_data));
1395 #ifdef CONFIG_DRM_AMD_DC_HDCP
1396         memset(&init_params, 0, sizeof(init_params));
1397 #endif
1398
1399         mutex_init(&adev->dm.dc_lock);
1400         mutex_init(&adev->dm.audio_lock);
1401
1402         if(amdgpu_dm_irq_init(adev)) {
1403                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1404                 goto error;
1405         }
1406
1407         init_data.asic_id.chip_family = adev->family;
1408
1409         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1410         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1411         init_data.asic_id.chip_id = adev->pdev->device;
1412
1413         init_data.asic_id.vram_width = adev->gmc.vram_width;
1414         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1415         init_data.asic_id.atombios_base_address =
1416                 adev->mode_info.atom_context->bios;
1417
1418         init_data.driver = adev;
1419
1420         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1421
1422         if (!adev->dm.cgs_device) {
1423                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1424                 goto error;
1425         }
1426
1427         init_data.cgs_device = adev->dm.cgs_device;
1428
1429         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1430
1431         switch (adev->ip_versions[DCE_HWIP][0]) {
1432         case IP_VERSION(2, 1, 0):
1433                 switch (adev->dm.dmcub_fw_version) {
1434                 case 0: /* development */
1435                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1436                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1437                         init_data.flags.disable_dmcu = false;
1438                         break;
1439                 default:
1440                         init_data.flags.disable_dmcu = true;
1441                 }
1442                 break;
1443         case IP_VERSION(2, 0, 3):
1444                 init_data.flags.disable_dmcu = true;
1445                 break;
1446         default:
1447                 break;
1448         }
1449
1450         switch (adev->asic_type) {
1451         case CHIP_CARRIZO:
1452         case CHIP_STONEY:
1453                 init_data.flags.gpu_vm_support = true;
1454                 break;
1455         default:
1456                 switch (adev->ip_versions[DCE_HWIP][0]) {
1457                 case IP_VERSION(1, 0, 0):
1458                 case IP_VERSION(1, 0, 1):
1459                         /* enable S/G on PCO and RV2 */
1460                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1461                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1462                                 init_data.flags.gpu_vm_support = true;
1463                         break;
1464                 case IP_VERSION(2, 1, 0):
1465                 case IP_VERSION(3, 0, 1):
1466                 case IP_VERSION(3, 1, 2):
1467                 case IP_VERSION(3, 1, 3):
1468                 case IP_VERSION(3, 1, 5):
1469                 case IP_VERSION(3, 1, 6):
1470                         init_data.flags.gpu_vm_support = true;
1471                         break;
1472                 default:
1473                         break;
1474                 }
1475                 break;
1476         }
1477
1478         if (init_data.flags.gpu_vm_support)
1479                 adev->mode_info.gpu_vm_support = true;
1480
1481         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1482                 init_data.flags.fbc_support = true;
1483
1484         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1485                 init_data.flags.multi_mon_pp_mclk_switch = true;
1486
1487         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1488                 init_data.flags.disable_fractional_pwm = true;
1489
1490         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1491                 init_data.flags.edp_no_power_sequencing = true;
1492
1493         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1494                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1495         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1496                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1497
1498         init_data.flags.seamless_boot_edp_requested = false;
1499
1500         if (check_seamless_boot_capability(adev)) {
1501                 init_data.flags.seamless_boot_edp_requested = true;
1502                 init_data.flags.allow_seamless_boot_optimization = true;
1503                 DRM_INFO("Seamless boot condition check passed\n");
1504         }
1505
1506         init_data.flags.enable_mipi_converter_optimization = true;
1507
1508         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1509         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1510
1511         INIT_LIST_HEAD(&adev->dm.da_list);
1512
1513         retrieve_dmi_info(&adev->dm);
1514
1515         /* Display Core create. */
1516         adev->dm.dc = dc_create(&init_data);
1517
1518         if (adev->dm.dc) {
1519                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1520         } else {
1521                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1522                 goto error;
1523         }
1524
1525         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1526                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1527                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1528         }
1529
1530         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1531                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1532         if (dm_should_disable_stutter(adev->pdev))
1533                 adev->dm.dc->debug.disable_stutter = true;
1534
1535         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1536                 adev->dm.dc->debug.disable_stutter = true;
1537
1538         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1539                 adev->dm.dc->debug.disable_dsc = true;
1540         }
1541
1542         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1543                 adev->dm.dc->debug.disable_clock_gate = true;
1544
1545         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1546                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1547
1548         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1549
1550         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1551         adev->dm.dc->debug.ignore_cable_id = true;
1552
1553         r = dm_dmub_hw_init(adev);
1554         if (r) {
1555                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1556                 goto error;
1557         }
1558
1559         dc_hardware_init(adev->dm.dc);
1560
1561         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1562         if (!adev->dm.hpd_rx_offload_wq) {
1563                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1564                 goto error;
1565         }
1566
1567         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1568                 struct dc_phy_addr_space_config pa_config;
1569
1570                 mmhub_read_system_context(adev, &pa_config);
1571
1572                 // Call the DC init_memory func
1573                 dc_setup_system_context(adev->dm.dc, &pa_config);
1574         }
1575
1576         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1577         if (!adev->dm.freesync_module) {
1578                 DRM_ERROR(
1579                 "amdgpu: failed to initialize freesync_module.\n");
1580         } else
1581                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1582                                 adev->dm.freesync_module);
1583
1584         amdgpu_dm_init_color_mod();
1585
1586         if (adev->dm.dc->caps.max_links > 0) {
1587                 adev->dm.vblank_control_workqueue =
1588                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1589                 if (!adev->dm.vblank_control_workqueue)
1590                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1591         }
1592
1593 #ifdef CONFIG_DRM_AMD_DC_HDCP
1594         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1595                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1596
1597                 if (!adev->dm.hdcp_workqueue)
1598                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1599                 else
1600                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1601
1602                 dc_init_callbacks(adev->dm.dc, &init_params);
1603         }
1604 #endif
1605 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1606         adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1607 #endif
1608         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1609                 init_completion(&adev->dm.dmub_aux_transfer_done);
1610                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1611                 if (!adev->dm.dmub_notify) {
1612                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1613                         goto error;
1614                 }
1615
1616                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1617                 if (!adev->dm.delayed_hpd_wq) {
1618                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1619                         goto error;
1620                 }
1621
1622                 amdgpu_dm_outbox_init(adev);
1623                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1624                         dmub_aux_setconfig_callback, false)) {
1625                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1626                         goto error;
1627                 }
1628                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1629                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1630                         goto error;
1631                 }
1632                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1633                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1634                         goto error;
1635                 }
1636         }
1637
1638         if (amdgpu_dm_initialize_drm_device(adev)) {
1639                 DRM_ERROR(
1640                 "amdgpu: failed to initialize sw for display support.\n");
1641                 goto error;
1642         }
1643
1644         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1645          * It is expected that DMUB will resend any pending notifications at this point, for
1646          * example HPD from DPIA.
1647          */
1648         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1649                 dc_enable_dmub_outbox(adev->dm.dc);
1650
1651         /* create fake encoders for MST */
1652         dm_dp_create_fake_mst_encoders(adev);
1653
1654         /* TODO: Add_display_info? */
1655
1656         /* TODO use dynamic cursor width */
1657         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1658         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1659
1660         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1661                 DRM_ERROR(
1662                 "amdgpu: failed to initialize sw for display support.\n");
1663                 goto error;
1664         }
1665
1666
1667         DRM_DEBUG_DRIVER("KMS initialized.\n");
1668
1669         return 0;
1670 error:
1671         amdgpu_dm_fini(adev);
1672
1673         return -EINVAL;
1674 }
1675
1676 static int amdgpu_dm_early_fini(void *handle)
1677 {
1678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1679
1680         amdgpu_dm_audio_fini(adev);
1681
1682         return 0;
1683 }
1684
1685 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1686 {
1687         int i;
1688
1689         if (adev->dm.vblank_control_workqueue) {
1690                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1691                 adev->dm.vblank_control_workqueue = NULL;
1692         }
1693
1694         for (i = 0; i < adev->dm.display_indexes_num; i++) {
1695                 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1696         }
1697
1698         amdgpu_dm_destroy_drm_device(&adev->dm);
1699
1700 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1701         if (adev->dm.crc_rd_wrk) {
1702                 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1703                 kfree(adev->dm.crc_rd_wrk);
1704                 adev->dm.crc_rd_wrk = NULL;
1705         }
1706 #endif
1707 #ifdef CONFIG_DRM_AMD_DC_HDCP
1708         if (adev->dm.hdcp_workqueue) {
1709                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1710                 adev->dm.hdcp_workqueue = NULL;
1711         }
1712
1713         if (adev->dm.dc)
1714                 dc_deinit_callbacks(adev->dm.dc);
1715 #endif
1716
1717         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1718
1719         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1720                 kfree(adev->dm.dmub_notify);
1721                 adev->dm.dmub_notify = NULL;
1722                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1723                 adev->dm.delayed_hpd_wq = NULL;
1724         }
1725
1726         if (adev->dm.dmub_bo)
1727                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1728                                       &adev->dm.dmub_bo_gpu_addr,
1729                                       &adev->dm.dmub_bo_cpu_addr);
1730
1731         if (adev->dm.hpd_rx_offload_wq) {
1732                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1733                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1734                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1735                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1736                         }
1737                 }
1738
1739                 kfree(adev->dm.hpd_rx_offload_wq);
1740                 adev->dm.hpd_rx_offload_wq = NULL;
1741         }
1742
1743         /* DC Destroy TODO: Replace destroy DAL */
1744         if (adev->dm.dc)
1745                 dc_destroy(&adev->dm.dc);
1746         /*
1747          * TODO: pageflip, vlank interrupt
1748          *
1749          * amdgpu_dm_irq_fini(adev);
1750          */
1751
1752         if (adev->dm.cgs_device) {
1753                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1754                 adev->dm.cgs_device = NULL;
1755         }
1756         if (adev->dm.freesync_module) {
1757                 mod_freesync_destroy(adev->dm.freesync_module);
1758                 adev->dm.freesync_module = NULL;
1759         }
1760
1761         mutex_destroy(&adev->dm.audio_lock);
1762         mutex_destroy(&adev->dm.dc_lock);
1763
1764         return;
1765 }
1766
1767 static int load_dmcu_fw(struct amdgpu_device *adev)
1768 {
1769         const char *fw_name_dmcu = NULL;
1770         int r;
1771         const struct dmcu_firmware_header_v1_0 *hdr;
1772
1773         switch(adev->asic_type) {
1774 #if defined(CONFIG_DRM_AMD_DC_SI)
1775         case CHIP_TAHITI:
1776         case CHIP_PITCAIRN:
1777         case CHIP_VERDE:
1778         case CHIP_OLAND:
1779 #endif
1780         case CHIP_BONAIRE:
1781         case CHIP_HAWAII:
1782         case CHIP_KAVERI:
1783         case CHIP_KABINI:
1784         case CHIP_MULLINS:
1785         case CHIP_TONGA:
1786         case CHIP_FIJI:
1787         case CHIP_CARRIZO:
1788         case CHIP_STONEY:
1789         case CHIP_POLARIS11:
1790         case CHIP_POLARIS10:
1791         case CHIP_POLARIS12:
1792         case CHIP_VEGAM:
1793         case CHIP_VEGA10:
1794         case CHIP_VEGA12:
1795         case CHIP_VEGA20:
1796                 return 0;
1797         case CHIP_NAVI12:
1798                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1799                 break;
1800         case CHIP_RAVEN:
1801                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1802                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1803                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1804                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1805                 else
1806                         return 0;
1807                 break;
1808         default:
1809                 switch (adev->ip_versions[DCE_HWIP][0]) {
1810                 case IP_VERSION(2, 0, 2):
1811                 case IP_VERSION(2, 0, 3):
1812                 case IP_VERSION(2, 0, 0):
1813                 case IP_VERSION(2, 1, 0):
1814                 case IP_VERSION(3, 0, 0):
1815                 case IP_VERSION(3, 0, 2):
1816                 case IP_VERSION(3, 0, 3):
1817                 case IP_VERSION(3, 0, 1):
1818                 case IP_VERSION(3, 1, 2):
1819                 case IP_VERSION(3, 1, 3):
1820                 case IP_VERSION(3, 1, 4):
1821                 case IP_VERSION(3, 1, 5):
1822                 case IP_VERSION(3, 1, 6):
1823                 case IP_VERSION(3, 2, 0):
1824                 case IP_VERSION(3, 2, 1):
1825                         return 0;
1826                 default:
1827                         break;
1828                 }
1829                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1830                 return -EINVAL;
1831         }
1832
1833         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1834                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1835                 return 0;
1836         }
1837
1838         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1839         if (r == -ENOENT) {
1840                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1841                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1842                 adev->dm.fw_dmcu = NULL;
1843                 return 0;
1844         }
1845         if (r) {
1846                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1847                         fw_name_dmcu);
1848                 return r;
1849         }
1850
1851         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1852         if (r) {
1853                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1854                         fw_name_dmcu);
1855                 release_firmware(adev->dm.fw_dmcu);
1856                 adev->dm.fw_dmcu = NULL;
1857                 return r;
1858         }
1859
1860         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1861         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1862         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1863         adev->firmware.fw_size +=
1864                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1865
1866         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1867         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1868         adev->firmware.fw_size +=
1869                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1870
1871         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1872
1873         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1874
1875         return 0;
1876 }
1877
1878 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1879 {
1880         struct amdgpu_device *adev = ctx;
1881
1882         return dm_read_reg(adev->dm.dc->ctx, address);
1883 }
1884
1885 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1886                                      uint32_t value)
1887 {
1888         struct amdgpu_device *adev = ctx;
1889
1890         return dm_write_reg(adev->dm.dc->ctx, address, value);
1891 }
1892
1893 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1894 {
1895         struct dmub_srv_create_params create_params;
1896         struct dmub_srv_region_params region_params;
1897         struct dmub_srv_region_info region_info;
1898         struct dmub_srv_fb_params fb_params;
1899         struct dmub_srv_fb_info *fb_info;
1900         struct dmub_srv *dmub_srv;
1901         const struct dmcub_firmware_header_v1_0 *hdr;
1902         const char *fw_name_dmub;
1903         enum dmub_asic dmub_asic;
1904         enum dmub_status status;
1905         int r;
1906
1907         switch (adev->ip_versions[DCE_HWIP][0]) {
1908         case IP_VERSION(2, 1, 0):
1909                 dmub_asic = DMUB_ASIC_DCN21;
1910                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1911                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1912                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1913                 break;
1914         case IP_VERSION(3, 0, 0):
1915                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
1916                         dmub_asic = DMUB_ASIC_DCN30;
1917                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1918                 } else {
1919                         dmub_asic = DMUB_ASIC_DCN30;
1920                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1921                 }
1922                 break;
1923         case IP_VERSION(3, 0, 1):
1924                 dmub_asic = DMUB_ASIC_DCN301;
1925                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1926                 break;
1927         case IP_VERSION(3, 0, 2):
1928                 dmub_asic = DMUB_ASIC_DCN302;
1929                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1930                 break;
1931         case IP_VERSION(3, 0, 3):
1932                 dmub_asic = DMUB_ASIC_DCN303;
1933                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
1934                 break;
1935         case IP_VERSION(3, 1, 2):
1936         case IP_VERSION(3, 1, 3):
1937                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1938                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
1939                 break;
1940         case IP_VERSION(3, 1, 4):
1941                 dmub_asic = DMUB_ASIC_DCN314;
1942                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
1943                 break;
1944         case IP_VERSION(3, 1, 5):
1945                 dmub_asic = DMUB_ASIC_DCN315;
1946                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
1947                 break;
1948         case IP_VERSION(3, 1, 6):
1949                 dmub_asic = DMUB_ASIC_DCN316;
1950                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
1951                 break;
1952         case IP_VERSION(3, 2, 0):
1953                 dmub_asic = DMUB_ASIC_DCN32;
1954                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
1955                 break;
1956         case IP_VERSION(3, 2, 1):
1957                 dmub_asic = DMUB_ASIC_DCN321;
1958                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
1959                 break;
1960         default:
1961                 /* ASIC doesn't support DMUB. */
1962                 return 0;
1963         }
1964
1965         r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1966         if (r) {
1967                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1968                 return 0;
1969         }
1970
1971         r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1972         if (r) {
1973                 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1974                 return 0;
1975         }
1976
1977         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1978         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1979
1980         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1981                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1982                         AMDGPU_UCODE_ID_DMCUB;
1983                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1984                         adev->dm.dmub_fw;
1985                 adev->firmware.fw_size +=
1986                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1987
1988                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1989                          adev->dm.dmcub_fw_version);
1990         }
1991
1992
1993         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1994         dmub_srv = adev->dm.dmub_srv;
1995
1996         if (!dmub_srv) {
1997                 DRM_ERROR("Failed to allocate DMUB service!\n");
1998                 return -ENOMEM;
1999         }
2000
2001         memset(&create_params, 0, sizeof(create_params));
2002         create_params.user_ctx = adev;
2003         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2004         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2005         create_params.asic = dmub_asic;
2006
2007         /* Create the DMUB service. */
2008         status = dmub_srv_create(dmub_srv, &create_params);
2009         if (status != DMUB_STATUS_OK) {
2010                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2011                 return -EINVAL;
2012         }
2013
2014         /* Calculate the size of all the regions for the DMUB service. */
2015         memset(&region_params, 0, sizeof(region_params));
2016
2017         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2018                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2019         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2020         region_params.vbios_size = adev->bios_size;
2021         region_params.fw_bss_data = region_params.bss_data_size ?
2022                 adev->dm.dmub_fw->data +
2023                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2024                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2025         region_params.fw_inst_const =
2026                 adev->dm.dmub_fw->data +
2027                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2028                 PSP_HEADER_BYTES;
2029
2030         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2031                                            &region_info);
2032
2033         if (status != DMUB_STATUS_OK) {
2034                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2035                 return -EINVAL;
2036         }
2037
2038         /*
2039          * Allocate a framebuffer based on the total size of all the regions.
2040          * TODO: Move this into GART.
2041          */
2042         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2043                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
2044                                     &adev->dm.dmub_bo_gpu_addr,
2045                                     &adev->dm.dmub_bo_cpu_addr);
2046         if (r)
2047                 return r;
2048
2049         /* Rebase the regions on the framebuffer address. */
2050         memset(&fb_params, 0, sizeof(fb_params));
2051         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2052         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2053         fb_params.region_info = &region_info;
2054
2055         adev->dm.dmub_fb_info =
2056                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2057         fb_info = adev->dm.dmub_fb_info;
2058
2059         if (!fb_info) {
2060                 DRM_ERROR(
2061                         "Failed to allocate framebuffer info for DMUB service!\n");
2062                 return -ENOMEM;
2063         }
2064
2065         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2066         if (status != DMUB_STATUS_OK) {
2067                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2068                 return -EINVAL;
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int dm_sw_init(void *handle)
2075 {
2076         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2077         int r;
2078
2079         r = dm_dmub_sw_init(adev);
2080         if (r)
2081                 return r;
2082
2083         return load_dmcu_fw(adev);
2084 }
2085
2086 static int dm_sw_fini(void *handle)
2087 {
2088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2089
2090         kfree(adev->dm.dmub_fb_info);
2091         adev->dm.dmub_fb_info = NULL;
2092
2093         if (adev->dm.dmub_srv) {
2094                 dmub_srv_destroy(adev->dm.dmub_srv);
2095                 adev->dm.dmub_srv = NULL;
2096         }
2097
2098         release_firmware(adev->dm.dmub_fw);
2099         adev->dm.dmub_fw = NULL;
2100
2101         release_firmware(adev->dm.fw_dmcu);
2102         adev->dm.fw_dmcu = NULL;
2103
2104         return 0;
2105 }
2106
2107 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2108 {
2109         struct amdgpu_dm_connector *aconnector;
2110         struct drm_connector *connector;
2111         struct drm_connector_list_iter iter;
2112         int ret = 0;
2113
2114         drm_connector_list_iter_begin(dev, &iter);
2115         drm_for_each_connector_iter(connector, &iter) {
2116                 aconnector = to_amdgpu_dm_connector(connector);
2117                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2118                     aconnector->mst_mgr.aux) {
2119                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2120                                          aconnector,
2121                                          aconnector->base.base.id);
2122
2123                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2124                         if (ret < 0) {
2125                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2126                                 aconnector->dc_link->type =
2127                                         dc_connection_single;
2128                                 break;
2129                         }
2130                 }
2131         }
2132         drm_connector_list_iter_end(&iter);
2133
2134         return ret;
2135 }
2136
2137 static int dm_late_init(void *handle)
2138 {
2139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2140
2141         struct dmcu_iram_parameters params;
2142         unsigned int linear_lut[16];
2143         int i;
2144         struct dmcu *dmcu = NULL;
2145
2146         dmcu = adev->dm.dc->res_pool->dmcu;
2147
2148         for (i = 0; i < 16; i++)
2149                 linear_lut[i] = 0xFFFF * i / 15;
2150
2151         params.set = 0;
2152         params.backlight_ramping_override = false;
2153         params.backlight_ramping_start = 0xCCCC;
2154         params.backlight_ramping_reduction = 0xCCCCCCCC;
2155         params.backlight_lut_array_size = 16;
2156         params.backlight_lut_array = linear_lut;
2157
2158         /* Min backlight level after ABM reduction,  Don't allow below 1%
2159          * 0xFFFF x 0.01 = 0x28F
2160          */
2161         params.min_abm_backlight = 0x28F;
2162         /* In the case where abm is implemented on dmcub,
2163         * dmcu object will be null.
2164         * ABM 2.4 and up are implemented on dmcub.
2165         */
2166         if (dmcu) {
2167                 if (!dmcu_load_iram(dmcu, params))
2168                         return -EINVAL;
2169         } else if (adev->dm.dc->ctx->dmub_srv) {
2170                 struct dc_link *edp_links[MAX_NUM_EDP];
2171                 int edp_num;
2172
2173                 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2174                 for (i = 0; i < edp_num; i++) {
2175                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2176                                 return -EINVAL;
2177                 }
2178         }
2179
2180         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2181 }
2182
2183 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2184 {
2185         struct amdgpu_dm_connector *aconnector;
2186         struct drm_connector *connector;
2187         struct drm_connector_list_iter iter;
2188         struct drm_dp_mst_topology_mgr *mgr;
2189         int ret;
2190         bool need_hotplug = false;
2191
2192         drm_connector_list_iter_begin(dev, &iter);
2193         drm_for_each_connector_iter(connector, &iter) {
2194                 aconnector = to_amdgpu_dm_connector(connector);
2195                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2196                     aconnector->mst_port)
2197                         continue;
2198
2199                 mgr = &aconnector->mst_mgr;
2200
2201                 if (suspend) {
2202                         drm_dp_mst_topology_mgr_suspend(mgr);
2203                 } else {
2204                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2205                         if (ret < 0) {
2206                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2207                                         aconnector->dc_link);
2208                                 need_hotplug = true;
2209                         }
2210                 }
2211         }
2212         drm_connector_list_iter_end(&iter);
2213
2214         if (need_hotplug)
2215                 drm_kms_helper_hotplug_event(dev);
2216 }
2217
2218 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2219 {
2220         int ret = 0;
2221
2222         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2223          * on window driver dc implementation.
2224          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2225          * should be passed to smu during boot up and resume from s3.
2226          * boot up: dc calculate dcn watermark clock settings within dc_create,
2227          * dcn20_resource_construct
2228          * then call pplib functions below to pass the settings to smu:
2229          * smu_set_watermarks_for_clock_ranges
2230          * smu_set_watermarks_table
2231          * navi10_set_watermarks_table
2232          * smu_write_watermarks_table
2233          *
2234          * For Renoir, clock settings of dcn watermark are also fixed values.
2235          * dc has implemented different flow for window driver:
2236          * dc_hardware_init / dc_set_power_state
2237          * dcn10_init_hw
2238          * notify_wm_ranges
2239          * set_wm_ranges
2240          * -- Linux
2241          * smu_set_watermarks_for_clock_ranges
2242          * renoir_set_watermarks_table
2243          * smu_write_watermarks_table
2244          *
2245          * For Linux,
2246          * dc_hardware_init -> amdgpu_dm_init
2247          * dc_set_power_state --> dm_resume
2248          *
2249          * therefore, this function apply to navi10/12/14 but not Renoir
2250          * *
2251          */
2252         switch (adev->ip_versions[DCE_HWIP][0]) {
2253         case IP_VERSION(2, 0, 2):
2254         case IP_VERSION(2, 0, 0):
2255                 break;
2256         default:
2257                 return 0;
2258         }
2259
2260         ret = amdgpu_dpm_write_watermarks_table(adev);
2261         if (ret) {
2262                 DRM_ERROR("Failed to update WMTABLE!\n");
2263                 return ret;
2264         }
2265
2266         return 0;
2267 }
2268
2269 /**
2270  * dm_hw_init() - Initialize DC device
2271  * @handle: The base driver device containing the amdgpu_dm device.
2272  *
2273  * Initialize the &struct amdgpu_display_manager device. This involves calling
2274  * the initializers of each DM component, then populating the struct with them.
2275  *
2276  * Although the function implies hardware initialization, both hardware and
2277  * software are initialized here. Splitting them out to their relevant init
2278  * hooks is a future TODO item.
2279  *
2280  * Some notable things that are initialized here:
2281  *
2282  * - Display Core, both software and hardware
2283  * - DC modules that we need (freesync and color management)
2284  * - DRM software states
2285  * - Interrupt sources and handlers
2286  * - Vblank support
2287  * - Debug FS entries, if enabled
2288  */
2289 static int dm_hw_init(void *handle)
2290 {
2291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2292         /* Create DAL display manager */
2293         amdgpu_dm_init(adev);
2294         amdgpu_dm_hpd_init(adev);
2295
2296         return 0;
2297 }
2298
2299 /**
2300  * dm_hw_fini() - Teardown DC device
2301  * @handle: The base driver device containing the amdgpu_dm device.
2302  *
2303  * Teardown components within &struct amdgpu_display_manager that require
2304  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2305  * were loaded. Also flush IRQ workqueues and disable them.
2306  */
2307 static int dm_hw_fini(void *handle)
2308 {
2309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2310
2311         amdgpu_dm_hpd_fini(adev);
2312
2313         amdgpu_dm_irq_fini(adev);
2314         amdgpu_dm_fini(adev);
2315         return 0;
2316 }
2317
2318
2319 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2320                                  struct dc_state *state, bool enable)
2321 {
2322         enum dc_irq_source irq_source;
2323         struct amdgpu_crtc *acrtc;
2324         int rc = -EBUSY;
2325         int i = 0;
2326
2327         for (i = 0; i < state->stream_count; i++) {
2328                 acrtc = get_crtc_by_otg_inst(
2329                                 adev, state->stream_status[i].primary_otg_inst);
2330
2331                 if (acrtc && state->stream_status[i].plane_count != 0) {
2332                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2333                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2334                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2335                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2336                         if (rc)
2337                                 DRM_WARN("Failed to %s pflip interrupts\n",
2338                                          enable ? "enable" : "disable");
2339
2340                         if (enable) {
2341                                 rc = dm_enable_vblank(&acrtc->base);
2342                                 if (rc)
2343                                         DRM_WARN("Failed to enable vblank interrupts\n");
2344                         } else {
2345                                 dm_disable_vblank(&acrtc->base);
2346                         }
2347
2348                 }
2349         }
2350
2351 }
2352
2353 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2354 {
2355         struct dc_state *context = NULL;
2356         enum dc_status res = DC_ERROR_UNEXPECTED;
2357         int i;
2358         struct dc_stream_state *del_streams[MAX_PIPES];
2359         int del_streams_count = 0;
2360
2361         memset(del_streams, 0, sizeof(del_streams));
2362
2363         context = dc_create_state(dc);
2364         if (context == NULL)
2365                 goto context_alloc_fail;
2366
2367         dc_resource_state_copy_construct_current(dc, context);
2368
2369         /* First remove from context all streams */
2370         for (i = 0; i < context->stream_count; i++) {
2371                 struct dc_stream_state *stream = context->streams[i];
2372
2373                 del_streams[del_streams_count++] = stream;
2374         }
2375
2376         /* Remove all planes for removed streams and then remove the streams */
2377         for (i = 0; i < del_streams_count; i++) {
2378                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2379                         res = DC_FAIL_DETACH_SURFACES;
2380                         goto fail;
2381                 }
2382
2383                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2384                 if (res != DC_OK)
2385                         goto fail;
2386         }
2387
2388         res = dc_commit_state(dc, context);
2389
2390 fail:
2391         dc_release_state(context);
2392
2393 context_alloc_fail:
2394         return res;
2395 }
2396
2397 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2398 {
2399         int i;
2400
2401         if (dm->hpd_rx_offload_wq) {
2402                 for (i = 0; i < dm->dc->caps.max_links; i++)
2403                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2404         }
2405 }
2406
2407 static int dm_suspend(void *handle)
2408 {
2409         struct amdgpu_device *adev = handle;
2410         struct amdgpu_display_manager *dm = &adev->dm;
2411         int ret = 0;
2412
2413         if (amdgpu_in_reset(adev)) {
2414                 mutex_lock(&dm->dc_lock);
2415
2416                 dc_allow_idle_optimizations(adev->dm.dc, false);
2417
2418                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2419
2420                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2421
2422                 amdgpu_dm_commit_zero_streams(dm->dc);
2423
2424                 amdgpu_dm_irq_suspend(adev);
2425
2426                 hpd_rx_irq_work_suspend(dm);
2427
2428                 return ret;
2429         }
2430
2431         WARN_ON(adev->dm.cached_state);
2432         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2433
2434         s3_handle_mst(adev_to_drm(adev), true);
2435
2436         amdgpu_dm_irq_suspend(adev);
2437
2438         hpd_rx_irq_work_suspend(dm);
2439
2440         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2441
2442         return 0;
2443 }
2444
2445 struct amdgpu_dm_connector *
2446 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2447                                              struct drm_crtc *crtc)
2448 {
2449         uint32_t i;
2450         struct drm_connector_state *new_con_state;
2451         struct drm_connector *connector;
2452         struct drm_crtc *crtc_from_state;
2453
2454         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2455                 crtc_from_state = new_con_state->crtc;
2456
2457                 if (crtc_from_state == crtc)
2458                         return to_amdgpu_dm_connector(connector);
2459         }
2460
2461         return NULL;
2462 }
2463
2464 static void emulated_link_detect(struct dc_link *link)
2465 {
2466         struct dc_sink_init_data sink_init_data = { 0 };
2467         struct display_sink_capability sink_caps = { 0 };
2468         enum dc_edid_status edid_status;
2469         struct dc_context *dc_ctx = link->ctx;
2470         struct dc_sink *sink = NULL;
2471         struct dc_sink *prev_sink = NULL;
2472
2473         link->type = dc_connection_none;
2474         prev_sink = link->local_sink;
2475
2476         if (prev_sink)
2477                 dc_sink_release(prev_sink);
2478
2479         switch (link->connector_signal) {
2480         case SIGNAL_TYPE_HDMI_TYPE_A: {
2481                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2482                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2483                 break;
2484         }
2485
2486         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2487                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2488                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2489                 break;
2490         }
2491
2492         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2493                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2494                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2495                 break;
2496         }
2497
2498         case SIGNAL_TYPE_LVDS: {
2499                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2500                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2501                 break;
2502         }
2503
2504         case SIGNAL_TYPE_EDP: {
2505                 sink_caps.transaction_type =
2506                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2507                 sink_caps.signal = SIGNAL_TYPE_EDP;
2508                 break;
2509         }
2510
2511         case SIGNAL_TYPE_DISPLAY_PORT: {
2512                 sink_caps.transaction_type =
2513                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2514                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2515                 break;
2516         }
2517
2518         default:
2519                 DC_ERROR("Invalid connector type! signal:%d\n",
2520                         link->connector_signal);
2521                 return;
2522         }
2523
2524         sink_init_data.link = link;
2525         sink_init_data.sink_signal = sink_caps.signal;
2526
2527         sink = dc_sink_create(&sink_init_data);
2528         if (!sink) {
2529                 DC_ERROR("Failed to create sink!\n");
2530                 return;
2531         }
2532
2533         /* dc_sink_create returns a new reference */
2534         link->local_sink = sink;
2535
2536         edid_status = dm_helpers_read_local_edid(
2537                         link->ctx,
2538                         link,
2539                         sink);
2540
2541         if (edid_status != EDID_OK)
2542                 DC_ERROR("Failed to read EDID");
2543
2544 }
2545
2546 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2547                                      struct amdgpu_display_manager *dm)
2548 {
2549         struct {
2550                 struct dc_surface_update surface_updates[MAX_SURFACES];
2551                 struct dc_plane_info plane_infos[MAX_SURFACES];
2552                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2553                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2554                 struct dc_stream_update stream_update;
2555         } * bundle;
2556         int k, m;
2557
2558         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2559
2560         if (!bundle) {
2561                 dm_error("Failed to allocate update bundle\n");
2562                 goto cleanup;
2563         }
2564
2565         for (k = 0; k < dc_state->stream_count; k++) {
2566                 bundle->stream_update.stream = dc_state->streams[k];
2567
2568                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2569                         bundle->surface_updates[m].surface =
2570                                 dc_state->stream_status->plane_states[m];
2571                         bundle->surface_updates[m].surface->force_full_update =
2572                                 true;
2573                 }
2574                 dc_commit_updates_for_stream(
2575                         dm->dc, bundle->surface_updates,
2576                         dc_state->stream_status->plane_count,
2577                         dc_state->streams[k], &bundle->stream_update, dc_state);
2578         }
2579
2580 cleanup:
2581         kfree(bundle);
2582
2583         return;
2584 }
2585
2586 static int dm_resume(void *handle)
2587 {
2588         struct amdgpu_device *adev = handle;
2589         struct drm_device *ddev = adev_to_drm(adev);
2590         struct amdgpu_display_manager *dm = &adev->dm;
2591         struct amdgpu_dm_connector *aconnector;
2592         struct drm_connector *connector;
2593         struct drm_connector_list_iter iter;
2594         struct drm_crtc *crtc;
2595         struct drm_crtc_state *new_crtc_state;
2596         struct dm_crtc_state *dm_new_crtc_state;
2597         struct drm_plane *plane;
2598         struct drm_plane_state *new_plane_state;
2599         struct dm_plane_state *dm_new_plane_state;
2600         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2601         enum dc_connection_type new_connection_type = dc_connection_none;
2602         struct dc_state *dc_state;
2603         int i, r, j;
2604
2605         if (amdgpu_in_reset(adev)) {
2606                 dc_state = dm->cached_dc_state;
2607
2608                 /*
2609                  * The dc->current_state is backed up into dm->cached_dc_state
2610                  * before we commit 0 streams.
2611                  *
2612                  * DC will clear link encoder assignments on the real state
2613                  * but the changes won't propagate over to the copy we made
2614                  * before the 0 streams commit.
2615                  *
2616                  * DC expects that link encoder assignments are *not* valid
2617                  * when committing a state, so as a workaround we can copy
2618                  * off of the current state.
2619                  *
2620                  * We lose the previous assignments, but we had already
2621                  * commit 0 streams anyway.
2622                  */
2623                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2624
2625                 r = dm_dmub_hw_init(adev);
2626                 if (r)
2627                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2628
2629                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2630                 dc_resume(dm->dc);
2631
2632                 amdgpu_dm_irq_resume_early(adev);
2633
2634                 for (i = 0; i < dc_state->stream_count; i++) {
2635                         dc_state->streams[i]->mode_changed = true;
2636                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2637                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2638                                         = 0xffffffff;
2639                         }
2640                 }
2641
2642                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2643                         amdgpu_dm_outbox_init(adev);
2644                         dc_enable_dmub_outbox(adev->dm.dc);
2645                 }
2646
2647                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2648
2649                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2650
2651                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2652
2653                 dc_release_state(dm->cached_dc_state);
2654                 dm->cached_dc_state = NULL;
2655
2656                 amdgpu_dm_irq_resume_late(adev);
2657
2658                 mutex_unlock(&dm->dc_lock);
2659
2660                 return 0;
2661         }
2662         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2663         dc_release_state(dm_state->context);
2664         dm_state->context = dc_create_state(dm->dc);
2665         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2666         dc_resource_state_construct(dm->dc, dm_state->context);
2667
2668         /* Before powering on DC we need to re-initialize DMUB. */
2669         dm_dmub_hw_resume(adev);
2670
2671         /* Re-enable outbox interrupts for DPIA. */
2672         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2673                 amdgpu_dm_outbox_init(adev);
2674                 dc_enable_dmub_outbox(adev->dm.dc);
2675         }
2676
2677         /* power on hardware */
2678         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2679
2680         /* program HPD filter */
2681         dc_resume(dm->dc);
2682
2683         /*
2684          * early enable HPD Rx IRQ, should be done before set mode as short
2685          * pulse interrupts are used for MST
2686          */
2687         amdgpu_dm_irq_resume_early(adev);
2688
2689         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2690         s3_handle_mst(ddev, false);
2691
2692         /* Do detection*/
2693         drm_connector_list_iter_begin(ddev, &iter);
2694         drm_for_each_connector_iter(connector, &iter) {
2695                 aconnector = to_amdgpu_dm_connector(connector);
2696
2697                 /*
2698                  * this is the case when traversing through already created
2699                  * MST connectors, should be skipped
2700                  */
2701                 if (aconnector->dc_link &&
2702                     aconnector->dc_link->type == dc_connection_mst_branch)
2703                         continue;
2704
2705                 mutex_lock(&aconnector->hpd_lock);
2706                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2707                         DRM_ERROR("KMS: Failed to detect connector\n");
2708
2709                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2710                         emulated_link_detect(aconnector->dc_link);
2711                 } else {
2712                         mutex_lock(&dm->dc_lock);
2713                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2714                         mutex_unlock(&dm->dc_lock);
2715                 }
2716
2717                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2718                         aconnector->fake_enable = false;
2719
2720                 if (aconnector->dc_sink)
2721                         dc_sink_release(aconnector->dc_sink);
2722                 aconnector->dc_sink = NULL;
2723                 amdgpu_dm_update_connector_after_detect(aconnector);
2724                 mutex_unlock(&aconnector->hpd_lock);
2725         }
2726         drm_connector_list_iter_end(&iter);
2727
2728         /* Force mode set in atomic commit */
2729         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2730                 new_crtc_state->active_changed = true;
2731
2732         /*
2733          * atomic_check is expected to create the dc states. We need to release
2734          * them here, since they were duplicated as part of the suspend
2735          * procedure.
2736          */
2737         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2738                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2739                 if (dm_new_crtc_state->stream) {
2740                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2741                         dc_stream_release(dm_new_crtc_state->stream);
2742                         dm_new_crtc_state->stream = NULL;
2743                 }
2744         }
2745
2746         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2747                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2748                 if (dm_new_plane_state->dc_state) {
2749                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2750                         dc_plane_state_release(dm_new_plane_state->dc_state);
2751                         dm_new_plane_state->dc_state = NULL;
2752                 }
2753         }
2754
2755         drm_atomic_helper_resume(ddev, dm->cached_state);
2756
2757         dm->cached_state = NULL;
2758
2759         amdgpu_dm_irq_resume_late(adev);
2760
2761         amdgpu_dm_smu_write_watermarks_table(adev);
2762
2763         return 0;
2764 }
2765
2766 /**
2767  * DOC: DM Lifecycle
2768  *
2769  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2770  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2771  * the base driver's device list to be initialized and torn down accordingly.
2772  *
2773  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2774  */
2775
2776 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2777         .name = "dm",
2778         .early_init = dm_early_init,
2779         .late_init = dm_late_init,
2780         .sw_init = dm_sw_init,
2781         .sw_fini = dm_sw_fini,
2782         .early_fini = amdgpu_dm_early_fini,
2783         .hw_init = dm_hw_init,
2784         .hw_fini = dm_hw_fini,
2785         .suspend = dm_suspend,
2786         .resume = dm_resume,
2787         .is_idle = dm_is_idle,
2788         .wait_for_idle = dm_wait_for_idle,
2789         .check_soft_reset = dm_check_soft_reset,
2790         .soft_reset = dm_soft_reset,
2791         .set_clockgating_state = dm_set_clockgating_state,
2792         .set_powergating_state = dm_set_powergating_state,
2793 };
2794
2795 const struct amdgpu_ip_block_version dm_ip_block =
2796 {
2797         .type = AMD_IP_BLOCK_TYPE_DCE,
2798         .major = 1,
2799         .minor = 0,
2800         .rev = 0,
2801         .funcs = &amdgpu_dm_funcs,
2802 };
2803
2804
2805 /**
2806  * DOC: atomic
2807  *
2808  * *WIP*
2809  */
2810
2811 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2812         .fb_create = amdgpu_display_user_framebuffer_create,
2813         .get_format_info = amd_get_format_info,
2814         .atomic_check = amdgpu_dm_atomic_check,
2815         .atomic_commit = drm_atomic_helper_commit,
2816 };
2817
2818 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2819         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2820         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2821 };
2822
2823 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2824 {
2825         struct amdgpu_dm_backlight_caps *caps;
2826         struct amdgpu_display_manager *dm;
2827         struct drm_connector *conn_base;
2828         struct amdgpu_device *adev;
2829         struct dc_link *link = NULL;
2830         struct drm_luminance_range_info *luminance_range;
2831         int i;
2832
2833         if (!aconnector || !aconnector->dc_link)
2834                 return;
2835
2836         link = aconnector->dc_link;
2837         if (link->connector_signal != SIGNAL_TYPE_EDP)
2838                 return;
2839
2840         conn_base = &aconnector->base;
2841         adev = drm_to_adev(conn_base->dev);
2842         dm = &adev->dm;
2843         for (i = 0; i < dm->num_of_edps; i++) {
2844                 if (link == dm->backlight_link[i])
2845                         break;
2846         }
2847         if (i >= dm->num_of_edps)
2848                 return;
2849         caps = &dm->backlight_caps[i];
2850         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2851         caps->aux_support = false;
2852
2853         if (caps->ext_caps->bits.oled == 1 /*||
2854             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2855             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2856                 caps->aux_support = true;
2857
2858         if (amdgpu_backlight == 0)
2859                 caps->aux_support = false;
2860         else if (amdgpu_backlight == 1)
2861                 caps->aux_support = true;
2862
2863         luminance_range = &conn_base->display_info.luminance_range;
2864         caps->aux_min_input_signal = luminance_range->min_luminance;
2865         caps->aux_max_input_signal = luminance_range->max_luminance;
2866 }
2867
2868 void amdgpu_dm_update_connector_after_detect(
2869                 struct amdgpu_dm_connector *aconnector)
2870 {
2871         struct drm_connector *connector = &aconnector->base;
2872         struct drm_device *dev = connector->dev;
2873         struct dc_sink *sink;
2874
2875         /* MST handled by drm_mst framework */
2876         if (aconnector->mst_mgr.mst_state == true)
2877                 return;
2878
2879         sink = aconnector->dc_link->local_sink;
2880         if (sink)
2881                 dc_sink_retain(sink);
2882
2883         /*
2884          * Edid mgmt connector gets first update only in mode_valid hook and then
2885          * the connector sink is set to either fake or physical sink depends on link status.
2886          * Skip if already done during boot.
2887          */
2888         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2889                         && aconnector->dc_em_sink) {
2890
2891                 /*
2892                  * For S3 resume with headless use eml_sink to fake stream
2893                  * because on resume connector->sink is set to NULL
2894                  */
2895                 mutex_lock(&dev->mode_config.mutex);
2896
2897                 if (sink) {
2898                         if (aconnector->dc_sink) {
2899                                 amdgpu_dm_update_freesync_caps(connector, NULL);
2900                                 /*
2901                                  * retain and release below are used to
2902                                  * bump up refcount for sink because the link doesn't point
2903                                  * to it anymore after disconnect, so on next crtc to connector
2904                                  * reshuffle by UMD we will get into unwanted dc_sink release
2905                                  */
2906                                 dc_sink_release(aconnector->dc_sink);
2907                         }
2908                         aconnector->dc_sink = sink;
2909                         dc_sink_retain(aconnector->dc_sink);
2910                         amdgpu_dm_update_freesync_caps(connector,
2911                                         aconnector->edid);
2912                 } else {
2913                         amdgpu_dm_update_freesync_caps(connector, NULL);
2914                         if (!aconnector->dc_sink) {
2915                                 aconnector->dc_sink = aconnector->dc_em_sink;
2916                                 dc_sink_retain(aconnector->dc_sink);
2917                         }
2918                 }
2919
2920                 mutex_unlock(&dev->mode_config.mutex);
2921
2922                 if (sink)
2923                         dc_sink_release(sink);
2924                 return;
2925         }
2926
2927         /*
2928          * TODO: temporary guard to look for proper fix
2929          * if this sink is MST sink, we should not do anything
2930          */
2931         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2932                 dc_sink_release(sink);
2933                 return;
2934         }
2935
2936         if (aconnector->dc_sink == sink) {
2937                 /*
2938                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
2939                  * Do nothing!!
2940                  */
2941                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2942                                 aconnector->connector_id);
2943                 if (sink)
2944                         dc_sink_release(sink);
2945                 return;
2946         }
2947
2948         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2949                 aconnector->connector_id, aconnector->dc_sink, sink);
2950
2951         mutex_lock(&dev->mode_config.mutex);
2952
2953         /*
2954          * 1. Update status of the drm connector
2955          * 2. Send an event and let userspace tell us what to do
2956          */
2957         if (sink) {
2958                 /*
2959                  * TODO: check if we still need the S3 mode update workaround.
2960                  * If yes, put it here.
2961                  */
2962                 if (aconnector->dc_sink) {
2963                         amdgpu_dm_update_freesync_caps(connector, NULL);
2964                         dc_sink_release(aconnector->dc_sink);
2965                 }
2966
2967                 aconnector->dc_sink = sink;
2968                 dc_sink_retain(aconnector->dc_sink);
2969                 if (sink->dc_edid.length == 0) {
2970                         aconnector->edid = NULL;
2971                         if (aconnector->dc_link->aux_mode) {
2972                                 drm_dp_cec_unset_edid(
2973                                         &aconnector->dm_dp_aux.aux);
2974                         }
2975                 } else {
2976                         aconnector->edid =
2977                                 (struct edid *)sink->dc_edid.raw_edid;
2978
2979                         if (aconnector->dc_link->aux_mode)
2980                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2981                                                     aconnector->edid);
2982                 }
2983
2984                 drm_connector_update_edid_property(connector, aconnector->edid);
2985                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2986                 update_connector_ext_caps(aconnector);
2987         } else {
2988                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2989                 amdgpu_dm_update_freesync_caps(connector, NULL);
2990                 drm_connector_update_edid_property(connector, NULL);
2991                 aconnector->num_modes = 0;
2992                 dc_sink_release(aconnector->dc_sink);
2993                 aconnector->dc_sink = NULL;
2994                 aconnector->edid = NULL;
2995 #ifdef CONFIG_DRM_AMD_DC_HDCP
2996                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2997                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2998                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2999 #endif
3000         }
3001
3002         mutex_unlock(&dev->mode_config.mutex);
3003
3004         update_subconnector_property(aconnector);
3005
3006         if (sink)
3007                 dc_sink_release(sink);
3008 }
3009
3010 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3011 {
3012         struct drm_connector *connector = &aconnector->base;
3013         struct drm_device *dev = connector->dev;
3014         enum dc_connection_type new_connection_type = dc_connection_none;
3015         struct amdgpu_device *adev = drm_to_adev(dev);
3016 #ifdef CONFIG_DRM_AMD_DC_HDCP
3017         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3018 #endif
3019         bool ret = false;
3020
3021         if (adev->dm.disable_hpd_irq)
3022                 return;
3023
3024         /*
3025          * In case of failure or MST no need to update connector status or notify the OS
3026          * since (for MST case) MST does this in its own context.
3027          */
3028         mutex_lock(&aconnector->hpd_lock);
3029
3030 #ifdef CONFIG_DRM_AMD_DC_HDCP
3031         if (adev->dm.hdcp_workqueue) {
3032                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3033                 dm_con_state->update_hdcp = true;
3034         }
3035 #endif
3036         if (aconnector->fake_enable)
3037                 aconnector->fake_enable = false;
3038
3039         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3040                 DRM_ERROR("KMS: Failed to detect connector\n");
3041
3042         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3043                 emulated_link_detect(aconnector->dc_link);
3044
3045                 drm_modeset_lock_all(dev);
3046                 dm_restore_drm_connector_state(dev, connector);
3047                 drm_modeset_unlock_all(dev);
3048
3049                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3050                         drm_kms_helper_connector_hotplug_event(connector);
3051         } else {
3052                 mutex_lock(&adev->dm.dc_lock);
3053                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3054                 mutex_unlock(&adev->dm.dc_lock);
3055                 if (ret) {
3056                         amdgpu_dm_update_connector_after_detect(aconnector);
3057
3058                         drm_modeset_lock_all(dev);
3059                         dm_restore_drm_connector_state(dev, connector);
3060                         drm_modeset_unlock_all(dev);
3061
3062                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3063                                 drm_kms_helper_connector_hotplug_event(connector);
3064                 }
3065         }
3066         mutex_unlock(&aconnector->hpd_lock);
3067
3068 }
3069
3070 static void handle_hpd_irq(void *param)
3071 {
3072         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3073
3074         handle_hpd_irq_helper(aconnector);
3075
3076 }
3077
3078 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3079 {
3080         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3081         uint8_t dret;
3082         bool new_irq_handled = false;
3083         int dpcd_addr;
3084         int dpcd_bytes_to_read;
3085
3086         const int max_process_count = 30;
3087         int process_count = 0;
3088
3089         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3090
3091         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3092                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3093                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3094                 dpcd_addr = DP_SINK_COUNT;
3095         } else {
3096                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3097                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3098                 dpcd_addr = DP_SINK_COUNT_ESI;
3099         }
3100
3101         dret = drm_dp_dpcd_read(
3102                 &aconnector->dm_dp_aux.aux,
3103                 dpcd_addr,
3104                 esi,
3105                 dpcd_bytes_to_read);
3106
3107         while (dret == dpcd_bytes_to_read &&
3108                 process_count < max_process_count) {
3109                 uint8_t retry;
3110                 dret = 0;
3111
3112                 process_count++;
3113
3114                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3115                 /* handle HPD short pulse irq */
3116                 if (aconnector->mst_mgr.mst_state)
3117                         drm_dp_mst_hpd_irq(
3118                                 &aconnector->mst_mgr,
3119                                 esi,
3120                                 &new_irq_handled);
3121
3122                 if (new_irq_handled) {
3123                         /* ACK at DPCD to notify down stream */
3124                         const int ack_dpcd_bytes_to_write =
3125                                 dpcd_bytes_to_read - 1;
3126
3127                         for (retry = 0; retry < 3; retry++) {
3128                                 uint8_t wret;
3129
3130                                 wret = drm_dp_dpcd_write(
3131                                         &aconnector->dm_dp_aux.aux,
3132                                         dpcd_addr + 1,
3133                                         &esi[1],
3134                                         ack_dpcd_bytes_to_write);
3135                                 if (wret == ack_dpcd_bytes_to_write)
3136                                         break;
3137                         }
3138
3139                         /* check if there is new irq to be handled */
3140                         dret = drm_dp_dpcd_read(
3141                                 &aconnector->dm_dp_aux.aux,
3142                                 dpcd_addr,
3143                                 esi,
3144                                 dpcd_bytes_to_read);
3145
3146                         new_irq_handled = false;
3147                 } else {
3148                         break;
3149                 }
3150         }
3151
3152         if (process_count == max_process_count)
3153                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3154 }
3155
3156 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3157                                                         union hpd_irq_data hpd_irq_data)
3158 {
3159         struct hpd_rx_irq_offload_work *offload_work =
3160                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3161
3162         if (!offload_work) {
3163                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3164                 return;
3165         }
3166
3167         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3168         offload_work->data = hpd_irq_data;
3169         offload_work->offload_wq = offload_wq;
3170
3171         queue_work(offload_wq->wq, &offload_work->work);
3172         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3173 }
3174
3175 static void handle_hpd_rx_irq(void *param)
3176 {
3177         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3178         struct drm_connector *connector = &aconnector->base;
3179         struct drm_device *dev = connector->dev;
3180         struct dc_link *dc_link = aconnector->dc_link;
3181         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3182         bool result = false;
3183         enum dc_connection_type new_connection_type = dc_connection_none;
3184         struct amdgpu_device *adev = drm_to_adev(dev);
3185         union hpd_irq_data hpd_irq_data;
3186         bool link_loss = false;
3187         bool has_left_work = false;
3188         int idx = aconnector->base.index;
3189         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3190
3191         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3192
3193         if (adev->dm.disable_hpd_irq)
3194                 return;
3195
3196         /*
3197          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3198          * conflict, after implement i2c helper, this mutex should be
3199          * retired.
3200          */
3201         mutex_lock(&aconnector->hpd_lock);
3202
3203         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3204                                                 &link_loss, true, &has_left_work);
3205
3206         if (!has_left_work)
3207                 goto out;
3208
3209         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3210                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3211                 goto out;
3212         }
3213
3214         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3215                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3216                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3217                         dm_handle_mst_sideband_msg(aconnector);
3218                         goto out;
3219                 }
3220
3221                 if (link_loss) {
3222                         bool skip = false;
3223
3224                         spin_lock(&offload_wq->offload_lock);
3225                         skip = offload_wq->is_handling_link_loss;
3226
3227                         if (!skip)
3228                                 offload_wq->is_handling_link_loss = true;
3229
3230                         spin_unlock(&offload_wq->offload_lock);
3231
3232                         if (!skip)
3233                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3234
3235                         goto out;
3236                 }
3237         }
3238
3239 out:
3240         if (result && !is_mst_root_connector) {
3241                 /* Downstream Port status changed. */
3242                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3243                         DRM_ERROR("KMS: Failed to detect connector\n");
3244
3245                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3246                         emulated_link_detect(dc_link);
3247
3248                         if (aconnector->fake_enable)
3249                                 aconnector->fake_enable = false;
3250
3251                         amdgpu_dm_update_connector_after_detect(aconnector);
3252
3253
3254                         drm_modeset_lock_all(dev);
3255                         dm_restore_drm_connector_state(dev, connector);
3256                         drm_modeset_unlock_all(dev);
3257
3258                         drm_kms_helper_connector_hotplug_event(connector);
3259                 } else {
3260                         bool ret = false;
3261
3262                         mutex_lock(&adev->dm.dc_lock);
3263                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3264                         mutex_unlock(&adev->dm.dc_lock);
3265
3266                         if (ret) {
3267                                 if (aconnector->fake_enable)
3268                                         aconnector->fake_enable = false;
3269
3270                                 amdgpu_dm_update_connector_after_detect(aconnector);
3271
3272                                 drm_modeset_lock_all(dev);
3273                                 dm_restore_drm_connector_state(dev, connector);
3274                                 drm_modeset_unlock_all(dev);
3275
3276                                 drm_kms_helper_connector_hotplug_event(connector);
3277                         }
3278                 }
3279         }
3280 #ifdef CONFIG_DRM_AMD_DC_HDCP
3281         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3282                 if (adev->dm.hdcp_workqueue)
3283                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3284         }
3285 #endif
3286
3287         if (dc_link->type != dc_connection_mst_branch)
3288                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3289
3290         mutex_unlock(&aconnector->hpd_lock);
3291 }
3292
3293 static void register_hpd_handlers(struct amdgpu_device *adev)
3294 {
3295         struct drm_device *dev = adev_to_drm(adev);
3296         struct drm_connector *connector;
3297         struct amdgpu_dm_connector *aconnector;
3298         const struct dc_link *dc_link;
3299         struct dc_interrupt_params int_params = {0};
3300
3301         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3302         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3303
3304         list_for_each_entry(connector,
3305                         &dev->mode_config.connector_list, head) {
3306
3307                 aconnector = to_amdgpu_dm_connector(connector);
3308                 dc_link = aconnector->dc_link;
3309
3310                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3311                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3312                         int_params.irq_source = dc_link->irq_source_hpd;
3313
3314                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3315                                         handle_hpd_irq,
3316                                         (void *) aconnector);
3317                 }
3318
3319                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3320
3321                         /* Also register for DP short pulse (hpd_rx). */
3322                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3323                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3324
3325                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3326                                         handle_hpd_rx_irq,
3327                                         (void *) aconnector);
3328
3329                         if (adev->dm.hpd_rx_offload_wq)
3330                                 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3331                                         aconnector;
3332                 }
3333         }
3334 }
3335
3336 #if defined(CONFIG_DRM_AMD_DC_SI)
3337 /* Register IRQ sources and initialize IRQ callbacks */
3338 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3339 {
3340         struct dc *dc = adev->dm.dc;
3341         struct common_irq_params *c_irq_params;
3342         struct dc_interrupt_params int_params = {0};
3343         int r;
3344         int i;
3345         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3346
3347         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3348         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3349
3350         /*
3351          * Actions of amdgpu_irq_add_id():
3352          * 1. Register a set() function with base driver.
3353          *    Base driver will call set() function to enable/disable an
3354          *    interrupt in DC hardware.
3355          * 2. Register amdgpu_dm_irq_handler().
3356          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3357          *    coming from DC hardware.
3358          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3359          *    for acknowledging and handling. */
3360
3361         /* Use VBLANK interrupt */
3362         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3363                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3364                 if (r) {
3365                         DRM_ERROR("Failed to add crtc irq id!\n");
3366                         return r;
3367                 }
3368
3369                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3370                 int_params.irq_source =
3371                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3372
3373                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3374
3375                 c_irq_params->adev = adev;
3376                 c_irq_params->irq_src = int_params.irq_source;
3377
3378                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3379                                 dm_crtc_high_irq, c_irq_params);
3380         }
3381
3382         /* Use GRPH_PFLIP interrupt */
3383         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3384                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3385                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3386                 if (r) {
3387                         DRM_ERROR("Failed to add page flip irq id!\n");
3388                         return r;
3389                 }
3390
3391                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3392                 int_params.irq_source =
3393                         dc_interrupt_to_irq_source(dc, i, 0);
3394
3395                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3396
3397                 c_irq_params->adev = adev;
3398                 c_irq_params->irq_src = int_params.irq_source;
3399
3400                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3401                                 dm_pflip_high_irq, c_irq_params);
3402
3403         }
3404
3405         /* HPD */
3406         r = amdgpu_irq_add_id(adev, client_id,
3407                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3408         if (r) {
3409                 DRM_ERROR("Failed to add hpd irq id!\n");
3410                 return r;
3411         }
3412
3413         register_hpd_handlers(adev);
3414
3415         return 0;
3416 }
3417 #endif
3418
3419 /* Register IRQ sources and initialize IRQ callbacks */
3420 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3421 {
3422         struct dc *dc = adev->dm.dc;
3423         struct common_irq_params *c_irq_params;
3424         struct dc_interrupt_params int_params = {0};
3425         int r;
3426         int i;
3427         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3428
3429         if (adev->family >= AMDGPU_FAMILY_AI)
3430                 client_id = SOC15_IH_CLIENTID_DCE;
3431
3432         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3433         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3434
3435         /*
3436          * Actions of amdgpu_irq_add_id():
3437          * 1. Register a set() function with base driver.
3438          *    Base driver will call set() function to enable/disable an
3439          *    interrupt in DC hardware.
3440          * 2. Register amdgpu_dm_irq_handler().
3441          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3442          *    coming from DC hardware.
3443          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3444          *    for acknowledging and handling. */
3445
3446         /* Use VBLANK interrupt */
3447         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3448                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3449                 if (r) {
3450                         DRM_ERROR("Failed to add crtc irq id!\n");
3451                         return r;
3452                 }
3453
3454                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3455                 int_params.irq_source =
3456                         dc_interrupt_to_irq_source(dc, i, 0);
3457
3458                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3459
3460                 c_irq_params->adev = adev;
3461                 c_irq_params->irq_src = int_params.irq_source;
3462
3463                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3464                                 dm_crtc_high_irq, c_irq_params);
3465         }
3466
3467         /* Use VUPDATE interrupt */
3468         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3469                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3470                 if (r) {
3471                         DRM_ERROR("Failed to add vupdate irq id!\n");
3472                         return r;
3473                 }
3474
3475                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3476                 int_params.irq_source =
3477                         dc_interrupt_to_irq_source(dc, i, 0);
3478
3479                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3480
3481                 c_irq_params->adev = adev;
3482                 c_irq_params->irq_src = int_params.irq_source;
3483
3484                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3485                                 dm_vupdate_high_irq, c_irq_params);
3486         }
3487
3488         /* Use GRPH_PFLIP interrupt */
3489         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3490                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3491                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3492                 if (r) {
3493                         DRM_ERROR("Failed to add page flip irq id!\n");
3494                         return r;
3495                 }
3496
3497                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3498                 int_params.irq_source =
3499                         dc_interrupt_to_irq_source(dc, i, 0);
3500
3501                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3502
3503                 c_irq_params->adev = adev;
3504                 c_irq_params->irq_src = int_params.irq_source;
3505
3506                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3507                                 dm_pflip_high_irq, c_irq_params);
3508
3509         }
3510
3511         /* HPD */
3512         r = amdgpu_irq_add_id(adev, client_id,
3513                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3514         if (r) {
3515                 DRM_ERROR("Failed to add hpd irq id!\n");
3516                 return r;
3517         }
3518
3519         register_hpd_handlers(adev);
3520
3521         return 0;
3522 }
3523
3524 /* Register IRQ sources and initialize IRQ callbacks */
3525 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3526 {
3527         struct dc *dc = adev->dm.dc;
3528         struct common_irq_params *c_irq_params;
3529         struct dc_interrupt_params int_params = {0};
3530         int r;
3531         int i;
3532 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3533         static const unsigned int vrtl_int_srcid[] = {
3534                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3535                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3536                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3537                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3538                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3539                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3540         };
3541 #endif
3542
3543         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3544         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3545
3546         /*
3547          * Actions of amdgpu_irq_add_id():
3548          * 1. Register a set() function with base driver.
3549          *    Base driver will call set() function to enable/disable an
3550          *    interrupt in DC hardware.
3551          * 2. Register amdgpu_dm_irq_handler().
3552          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3553          *    coming from DC hardware.
3554          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3555          *    for acknowledging and handling.
3556          */
3557
3558         /* Use VSTARTUP interrupt */
3559         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3560                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3561                         i++) {
3562                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3563
3564                 if (r) {
3565                         DRM_ERROR("Failed to add crtc irq id!\n");
3566                         return r;
3567                 }
3568
3569                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3570                 int_params.irq_source =
3571                         dc_interrupt_to_irq_source(dc, i, 0);
3572
3573                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3574
3575                 c_irq_params->adev = adev;
3576                 c_irq_params->irq_src = int_params.irq_source;
3577
3578                 amdgpu_dm_irq_register_interrupt(
3579                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3580         }
3581
3582         /* Use otg vertical line interrupt */
3583 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3584         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3585                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3586                                 vrtl_int_srcid[i], &adev->vline0_irq);
3587
3588                 if (r) {
3589                         DRM_ERROR("Failed to add vline0 irq id!\n");
3590                         return r;
3591                 }
3592
3593                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3594                 int_params.irq_source =
3595                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3596
3597                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3598                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3599                         break;
3600                 }
3601
3602                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3603                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3604
3605                 c_irq_params->adev = adev;
3606                 c_irq_params->irq_src = int_params.irq_source;
3607
3608                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3609                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3610         }
3611 #endif
3612
3613         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3614          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3615          * to trigger at end of each vblank, regardless of state of the lock,
3616          * matching DCE behaviour.
3617          */
3618         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3619              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3620              i++) {
3621                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3622
3623                 if (r) {
3624                         DRM_ERROR("Failed to add vupdate irq id!\n");
3625                         return r;
3626                 }
3627
3628                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3629                 int_params.irq_source =
3630                         dc_interrupt_to_irq_source(dc, i, 0);
3631
3632                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3633
3634                 c_irq_params->adev = adev;
3635                 c_irq_params->irq_src = int_params.irq_source;
3636
3637                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3638                                 dm_vupdate_high_irq, c_irq_params);
3639         }
3640
3641         /* Use GRPH_PFLIP interrupt */
3642         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3643                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3644                         i++) {
3645                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3646                 if (r) {
3647                         DRM_ERROR("Failed to add page flip irq id!\n");
3648                         return r;
3649                 }
3650
3651                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3652                 int_params.irq_source =
3653                         dc_interrupt_to_irq_source(dc, i, 0);
3654
3655                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3656
3657                 c_irq_params->adev = adev;
3658                 c_irq_params->irq_src = int_params.irq_source;
3659
3660                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3661                                 dm_pflip_high_irq, c_irq_params);
3662
3663         }
3664
3665         /* HPD */
3666         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3667                         &adev->hpd_irq);
3668         if (r) {
3669                 DRM_ERROR("Failed to add hpd irq id!\n");
3670                 return r;
3671         }
3672
3673         register_hpd_handlers(adev);
3674
3675         return 0;
3676 }
3677 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3678 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3679 {
3680         struct dc *dc = adev->dm.dc;
3681         struct common_irq_params *c_irq_params;
3682         struct dc_interrupt_params int_params = {0};
3683         int r, i;
3684
3685         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3686         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3687
3688         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3689                         &adev->dmub_outbox_irq);
3690         if (r) {
3691                 DRM_ERROR("Failed to add outbox irq id!\n");
3692                 return r;
3693         }
3694
3695         if (dc->ctx->dmub_srv) {
3696                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3697                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3698                 int_params.irq_source =
3699                 dc_interrupt_to_irq_source(dc, i, 0);
3700
3701                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3702
3703                 c_irq_params->adev = adev;
3704                 c_irq_params->irq_src = int_params.irq_source;
3705
3706                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3707                                 dm_dmub_outbox1_low_irq, c_irq_params);
3708         }
3709
3710         return 0;
3711 }
3712
3713 /*
3714  * Acquires the lock for the atomic state object and returns
3715  * the new atomic state.
3716  *
3717  * This should only be called during atomic check.
3718  */
3719 int dm_atomic_get_state(struct drm_atomic_state *state,
3720                         struct dm_atomic_state **dm_state)
3721 {
3722         struct drm_device *dev = state->dev;
3723         struct amdgpu_device *adev = drm_to_adev(dev);
3724         struct amdgpu_display_manager *dm = &adev->dm;
3725         struct drm_private_state *priv_state;
3726
3727         if (*dm_state)
3728                 return 0;
3729
3730         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3731         if (IS_ERR(priv_state))
3732                 return PTR_ERR(priv_state);
3733
3734         *dm_state = to_dm_atomic_state(priv_state);
3735
3736         return 0;
3737 }
3738
3739 static struct dm_atomic_state *
3740 dm_atomic_get_new_state(struct drm_atomic_state *state)
3741 {
3742         struct drm_device *dev = state->dev;
3743         struct amdgpu_device *adev = drm_to_adev(dev);
3744         struct amdgpu_display_manager *dm = &adev->dm;
3745         struct drm_private_obj *obj;
3746         struct drm_private_state *new_obj_state;
3747         int i;
3748
3749         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3750                 if (obj->funcs == dm->atomic_obj.funcs)
3751                         return to_dm_atomic_state(new_obj_state);
3752         }
3753
3754         return NULL;
3755 }
3756
3757 static struct drm_private_state *
3758 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3759 {
3760         struct dm_atomic_state *old_state, *new_state;
3761
3762         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3763         if (!new_state)
3764                 return NULL;
3765
3766         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3767
3768         old_state = to_dm_atomic_state(obj->state);
3769
3770         if (old_state && old_state->context)
3771                 new_state->context = dc_copy_state(old_state->context);
3772
3773         if (!new_state->context) {
3774                 kfree(new_state);
3775                 return NULL;
3776         }
3777
3778         return &new_state->base;
3779 }
3780
3781 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3782                                     struct drm_private_state *state)
3783 {
3784         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3785
3786         if (dm_state && dm_state->context)
3787                 dc_release_state(dm_state->context);
3788
3789         kfree(dm_state);
3790 }
3791
3792 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3793         .atomic_duplicate_state = dm_atomic_duplicate_state,
3794         .atomic_destroy_state = dm_atomic_destroy_state,
3795 };
3796
3797 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3798 {
3799         struct dm_atomic_state *state;
3800         int r;
3801
3802         adev->mode_info.mode_config_initialized = true;
3803
3804         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3805         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3806
3807         adev_to_drm(adev)->mode_config.max_width = 16384;
3808         adev_to_drm(adev)->mode_config.max_height = 16384;
3809
3810         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3811         if (adev->asic_type == CHIP_HAWAII)
3812                 /* disable prefer shadow for now due to hibernation issues */
3813                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3814         else
3815                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3816         /* indicates support for immediate flip */
3817         adev_to_drm(adev)->mode_config.async_page_flip = true;
3818
3819         state = kzalloc(sizeof(*state), GFP_KERNEL);
3820         if (!state)
3821                 return -ENOMEM;
3822
3823         state->context = dc_create_state(adev->dm.dc);
3824         if (!state->context) {
3825                 kfree(state);
3826                 return -ENOMEM;
3827         }
3828
3829         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3830
3831         drm_atomic_private_obj_init(adev_to_drm(adev),
3832                                     &adev->dm.atomic_obj,
3833                                     &state->base,
3834                                     &dm_atomic_state_funcs);
3835
3836         r = amdgpu_display_modeset_create_props(adev);
3837         if (r) {
3838                 dc_release_state(state->context);
3839                 kfree(state);
3840                 return r;
3841         }
3842
3843         r = amdgpu_dm_audio_init(adev);
3844         if (r) {
3845                 dc_release_state(state->context);
3846                 kfree(state);
3847                 return r;
3848         }
3849
3850         return 0;
3851 }
3852
3853 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3854 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3855 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3856
3857 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3858                                             int bl_idx)
3859 {
3860 #if defined(CONFIG_ACPI)
3861         struct amdgpu_dm_backlight_caps caps;
3862
3863         memset(&caps, 0, sizeof(caps));
3864
3865         if (dm->backlight_caps[bl_idx].caps_valid)
3866                 return;
3867
3868         amdgpu_acpi_get_backlight_caps(&caps);
3869         if (caps.caps_valid) {
3870                 dm->backlight_caps[bl_idx].caps_valid = true;
3871                 if (caps.aux_support)
3872                         return;
3873                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3874                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3875         } else {
3876                 dm->backlight_caps[bl_idx].min_input_signal =
3877                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3878                 dm->backlight_caps[bl_idx].max_input_signal =
3879                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3880         }
3881 #else
3882         if (dm->backlight_caps[bl_idx].aux_support)
3883                 return;
3884
3885         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3886         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3887 #endif
3888 }
3889
3890 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3891                                 unsigned *min, unsigned *max)
3892 {
3893         if (!caps)
3894                 return 0;
3895
3896         if (caps->aux_support) {
3897                 // Firmware limits are in nits, DC API wants millinits.
3898                 *max = 1000 * caps->aux_max_input_signal;
3899                 *min = 1000 * caps->aux_min_input_signal;
3900         } else {
3901                 // Firmware limits are 8-bit, PWM control is 16-bit.
3902                 *max = 0x101 * caps->max_input_signal;
3903                 *min = 0x101 * caps->min_input_signal;
3904         }
3905         return 1;
3906 }
3907
3908 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3909                                         uint32_t brightness)
3910 {
3911         unsigned min, max;
3912
3913         if (!get_brightness_range(caps, &min, &max))
3914                 return brightness;
3915
3916         // Rescale 0..255 to min..max
3917         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3918                                        AMDGPU_MAX_BL_LEVEL);
3919 }
3920
3921 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3922                                       uint32_t brightness)
3923 {
3924         unsigned min, max;
3925
3926         if (!get_brightness_range(caps, &min, &max))
3927                 return brightness;
3928
3929         if (brightness < min)
3930                 return 0;
3931         // Rescale min..max to 0..255
3932         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3933                                  max - min);
3934 }
3935
3936 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
3937                                          int bl_idx,
3938                                          u32 user_brightness)
3939 {
3940         struct amdgpu_dm_backlight_caps caps;
3941         struct dc_link *link;
3942         u32 brightness;
3943         bool rc;
3944
3945         amdgpu_dm_update_backlight_caps(dm, bl_idx);
3946         caps = dm->backlight_caps[bl_idx];
3947
3948         dm->brightness[bl_idx] = user_brightness;
3949         /* update scratch register */
3950         if (bl_idx == 0)
3951                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
3952         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
3953         link = (struct dc_link *)dm->backlight_link[bl_idx];
3954
3955         /* Change brightness based on AUX property */
3956         if (caps.aux_support) {
3957                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3958                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3959                 if (!rc)
3960                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
3961         } else {
3962                 rc = dc_link_set_backlight_level(link, brightness, 0);
3963                 if (!rc)
3964                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
3965         }
3966
3967         if (rc)
3968                 dm->actual_brightness[bl_idx] = user_brightness;
3969 }
3970
3971 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3972 {
3973         struct amdgpu_display_manager *dm = bl_get_data(bd);
3974         int i;
3975
3976         for (i = 0; i < dm->num_of_edps; i++) {
3977                 if (bd == dm->backlight_dev[i])
3978                         break;
3979         }
3980         if (i >= AMDGPU_DM_MAX_NUM_EDP)
3981                 i = 0;
3982         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
3983
3984         return 0;
3985 }
3986
3987 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
3988                                          int bl_idx)
3989 {
3990         struct amdgpu_dm_backlight_caps caps;
3991         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
3992
3993         amdgpu_dm_update_backlight_caps(dm, bl_idx);
3994         caps = dm->backlight_caps[bl_idx];
3995
3996         if (caps.aux_support) {
3997                 u32 avg, peak;
3998                 bool rc;
3999
4000                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4001                 if (!rc)
4002                         return dm->brightness[bl_idx];
4003                 return convert_brightness_to_user(&caps, avg);
4004         } else {
4005                 int ret = dc_link_get_backlight_level(link);
4006
4007                 if (ret == DC_ERROR_UNEXPECTED)
4008                         return dm->brightness[bl_idx];
4009                 return convert_brightness_to_user(&caps, ret);
4010         }
4011 }
4012
4013 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4014 {
4015         struct amdgpu_display_manager *dm = bl_get_data(bd);
4016         int i;
4017
4018         for (i = 0; i < dm->num_of_edps; i++) {
4019                 if (bd == dm->backlight_dev[i])
4020                         break;
4021         }
4022         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4023                 i = 0;
4024         return amdgpu_dm_backlight_get_level(dm, i);
4025 }
4026
4027 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4028         .options = BL_CORE_SUSPENDRESUME,
4029         .get_brightness = amdgpu_dm_backlight_get_brightness,
4030         .update_status  = amdgpu_dm_backlight_update_status,
4031 };
4032
4033 static void
4034 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4035 {
4036         char bl_name[16];
4037         struct backlight_properties props = { 0 };
4038
4039         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4040         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4041
4042         if (!acpi_video_backlight_use_native()) {
4043                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4044                 /* Try registering an ACPI video backlight device instead. */
4045                 acpi_video_register_backlight();
4046                 return;
4047         }
4048
4049         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4050         props.brightness = AMDGPU_MAX_BL_LEVEL;
4051         props.type = BACKLIGHT_RAW;
4052
4053         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4054                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4055
4056         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4057                                                                        adev_to_drm(dm->adev)->dev,
4058                                                                        dm,
4059                                                                        &amdgpu_dm_backlight_ops,
4060                                                                        &props);
4061
4062         if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4063                 DRM_ERROR("DM: Backlight registration failed!\n");
4064         else
4065                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4066 }
4067
4068 static int initialize_plane(struct amdgpu_display_manager *dm,
4069                             struct amdgpu_mode_info *mode_info, int plane_id,
4070                             enum drm_plane_type plane_type,
4071                             const struct dc_plane_cap *plane_cap)
4072 {
4073         struct drm_plane *plane;
4074         unsigned long possible_crtcs;
4075         int ret = 0;
4076
4077         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4078         if (!plane) {
4079                 DRM_ERROR("KMS: Failed to allocate plane\n");
4080                 return -ENOMEM;
4081         }
4082         plane->type = plane_type;
4083
4084         /*
4085          * HACK: IGT tests expect that the primary plane for a CRTC
4086          * can only have one possible CRTC. Only expose support for
4087          * any CRTC if they're not going to be used as a primary plane
4088          * for a CRTC - like overlay or underlay planes.
4089          */
4090         possible_crtcs = 1 << plane_id;
4091         if (plane_id >= dm->dc->caps.max_streams)
4092                 possible_crtcs = 0xff;
4093
4094         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4095
4096         if (ret) {
4097                 DRM_ERROR("KMS: Failed to initialize plane\n");
4098                 kfree(plane);
4099                 return ret;
4100         }
4101
4102         if (mode_info)
4103                 mode_info->planes[plane_id] = plane;
4104
4105         return ret;
4106 }
4107
4108
4109 static void register_backlight_device(struct amdgpu_display_manager *dm,
4110                                       struct dc_link *link)
4111 {
4112         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4113             link->type != dc_connection_none) {
4114                 /*
4115                  * Event if registration failed, we should continue with
4116                  * DM initialization because not having a backlight control
4117                  * is better then a black screen.
4118                  */
4119                 if (!dm->backlight_dev[dm->num_of_edps])
4120                         amdgpu_dm_register_backlight_device(dm);
4121
4122                 if (dm->backlight_dev[dm->num_of_edps]) {
4123                         dm->backlight_link[dm->num_of_edps] = link;
4124                         dm->num_of_edps++;
4125                 }
4126         }
4127 }
4128
4129 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4130
4131 /*
4132  * In this architecture, the association
4133  * connector -> encoder -> crtc
4134  * id not really requried. The crtc and connector will hold the
4135  * display_index as an abstraction to use with DAL component
4136  *
4137  * Returns 0 on success
4138  */
4139 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4140 {
4141         struct amdgpu_display_manager *dm = &adev->dm;
4142         int32_t i;
4143         struct amdgpu_dm_connector *aconnector = NULL;
4144         struct amdgpu_encoder *aencoder = NULL;
4145         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4146         uint32_t link_cnt;
4147         int32_t primary_planes;
4148         enum dc_connection_type new_connection_type = dc_connection_none;
4149         const struct dc_plane_cap *plane;
4150         bool psr_feature_enabled = false;
4151
4152         dm->display_indexes_num = dm->dc->caps.max_streams;
4153         /* Update the actual used number of crtc */
4154         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4155
4156         link_cnt = dm->dc->caps.max_links;
4157         if (amdgpu_dm_mode_config_init(dm->adev)) {
4158                 DRM_ERROR("DM: Failed to initialize mode config\n");
4159                 return -EINVAL;
4160         }
4161
4162         /* There is one primary plane per CRTC */
4163         primary_planes = dm->dc->caps.max_streams;
4164         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4165
4166         /*
4167          * Initialize primary planes, implicit planes for legacy IOCTLS.
4168          * Order is reversed to match iteration order in atomic check.
4169          */
4170         for (i = (primary_planes - 1); i >= 0; i--) {
4171                 plane = &dm->dc->caps.planes[i];
4172
4173                 if (initialize_plane(dm, mode_info, i,
4174                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4175                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4176                         goto fail;
4177                 }
4178         }
4179
4180         /*
4181          * Initialize overlay planes, index starting after primary planes.
4182          * These planes have a higher DRM index than the primary planes since
4183          * they should be considered as having a higher z-order.
4184          * Order is reversed to match iteration order in atomic check.
4185          *
4186          * Only support DCN for now, and only expose one so we don't encourage
4187          * userspace to use up all the pipes.
4188          */
4189         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4190                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4191
4192                 /* Do not create overlay if MPO disabled */
4193                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4194                         break;
4195
4196                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4197                         continue;
4198
4199                 if (!plane->blends_with_above || !plane->blends_with_below)
4200                         continue;
4201
4202                 if (!plane->pixel_format_support.argb8888)
4203                         continue;
4204
4205                 if (initialize_plane(dm, NULL, primary_planes + i,
4206                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4207                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4208                         goto fail;
4209                 }
4210
4211                 /* Only create one overlay plane. */
4212                 break;
4213         }
4214
4215         for (i = 0; i < dm->dc->caps.max_streams; i++)
4216                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4217                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4218                         goto fail;
4219                 }
4220
4221         /* Use Outbox interrupt */
4222         switch (adev->ip_versions[DCE_HWIP][0]) {
4223         case IP_VERSION(3, 0, 0):
4224         case IP_VERSION(3, 1, 2):
4225         case IP_VERSION(3, 1, 3):
4226         case IP_VERSION(3, 1, 4):
4227         case IP_VERSION(3, 1, 5):
4228         case IP_VERSION(3, 1, 6):
4229         case IP_VERSION(3, 2, 0):
4230         case IP_VERSION(3, 2, 1):
4231         case IP_VERSION(2, 1, 0):
4232                 if (register_outbox_irq_handlers(dm->adev)) {
4233                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4234                         goto fail;
4235                 }
4236                 break;
4237         default:
4238                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4239                               adev->ip_versions[DCE_HWIP][0]);
4240         }
4241
4242         /* Determine whether to enable PSR support by default. */
4243         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4244                 switch (adev->ip_versions[DCE_HWIP][0]) {
4245                 case IP_VERSION(3, 1, 2):
4246                 case IP_VERSION(3, 1, 3):
4247                 case IP_VERSION(3, 1, 4):
4248                 case IP_VERSION(3, 1, 5):
4249                 case IP_VERSION(3, 1, 6):
4250                 case IP_VERSION(3, 2, 0):
4251                 case IP_VERSION(3, 2, 1):
4252                         psr_feature_enabled = true;
4253                         break;
4254                 default:
4255                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4256                         break;
4257                 }
4258         }
4259
4260         /* loops over all connectors on the board */
4261         for (i = 0; i < link_cnt; i++) {
4262                 struct dc_link *link = NULL;
4263
4264                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4265                         DRM_ERROR(
4266                                 "KMS: Cannot support more than %d display indexes\n",
4267                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4268                         continue;
4269                 }
4270
4271                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4272                 if (!aconnector)
4273                         goto fail;
4274
4275                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4276                 if (!aencoder)
4277                         goto fail;
4278
4279                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4280                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4281                         goto fail;
4282                 }
4283
4284                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4285                         DRM_ERROR("KMS: Failed to initialize connector\n");
4286                         goto fail;
4287                 }
4288
4289                 link = dc_get_link_at_index(dm->dc, i);
4290
4291                 if (!dc_link_detect_sink(link, &new_connection_type))
4292                         DRM_ERROR("KMS: Failed to detect connector\n");
4293
4294                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4295                         emulated_link_detect(link);
4296                         amdgpu_dm_update_connector_after_detect(aconnector);
4297                 } else {
4298                         bool ret = false;
4299
4300                         mutex_lock(&dm->dc_lock);
4301                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4302                         mutex_unlock(&dm->dc_lock);
4303
4304                         if (ret) {
4305                                 amdgpu_dm_update_connector_after_detect(aconnector);
4306                                 register_backlight_device(dm, link);
4307
4308                                 if (dm->num_of_edps)
4309                                         update_connector_ext_caps(aconnector);
4310
4311                                 if (psr_feature_enabled)
4312                                         amdgpu_dm_set_psr_caps(link);
4313
4314                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4315                                  * PSR is also supported.
4316                                  */
4317                                 if (link->psr_settings.psr_feature_enabled)
4318                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4319                         }
4320                 }
4321                 amdgpu_set_panel_orientation(&aconnector->base);
4322         }
4323
4324         /* Software is initialized. Now we can register interrupt handlers. */
4325         switch (adev->asic_type) {
4326 #if defined(CONFIG_DRM_AMD_DC_SI)
4327         case CHIP_TAHITI:
4328         case CHIP_PITCAIRN:
4329         case CHIP_VERDE:
4330         case CHIP_OLAND:
4331                 if (dce60_register_irq_handlers(dm->adev)) {
4332                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4333                         goto fail;
4334                 }
4335                 break;
4336 #endif
4337         case CHIP_BONAIRE:
4338         case CHIP_HAWAII:
4339         case CHIP_KAVERI:
4340         case CHIP_KABINI:
4341         case CHIP_MULLINS:
4342         case CHIP_TONGA:
4343         case CHIP_FIJI:
4344         case CHIP_CARRIZO:
4345         case CHIP_STONEY:
4346         case CHIP_POLARIS11:
4347         case CHIP_POLARIS10:
4348         case CHIP_POLARIS12:
4349         case CHIP_VEGAM:
4350         case CHIP_VEGA10:
4351         case CHIP_VEGA12:
4352         case CHIP_VEGA20:
4353                 if (dce110_register_irq_handlers(dm->adev)) {
4354                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4355                         goto fail;
4356                 }
4357                 break;
4358         default:
4359                 switch (adev->ip_versions[DCE_HWIP][0]) {
4360                 case IP_VERSION(1, 0, 0):
4361                 case IP_VERSION(1, 0, 1):
4362                 case IP_VERSION(2, 0, 2):
4363                 case IP_VERSION(2, 0, 3):
4364                 case IP_VERSION(2, 0, 0):
4365                 case IP_VERSION(2, 1, 0):
4366                 case IP_VERSION(3, 0, 0):
4367                 case IP_VERSION(3, 0, 2):
4368                 case IP_VERSION(3, 0, 3):
4369                 case IP_VERSION(3, 0, 1):
4370                 case IP_VERSION(3, 1, 2):
4371                 case IP_VERSION(3, 1, 3):
4372                 case IP_VERSION(3, 1, 4):
4373                 case IP_VERSION(3, 1, 5):
4374                 case IP_VERSION(3, 1, 6):
4375                 case IP_VERSION(3, 2, 0):
4376                 case IP_VERSION(3, 2, 1):
4377                         if (dcn10_register_irq_handlers(dm->adev)) {
4378                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4379                                 goto fail;
4380                         }
4381                         break;
4382                 default:
4383                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4384                                         adev->ip_versions[DCE_HWIP][0]);
4385                         goto fail;
4386                 }
4387                 break;
4388         }
4389
4390         return 0;
4391 fail:
4392         kfree(aencoder);
4393         kfree(aconnector);
4394
4395         return -EINVAL;
4396 }
4397
4398 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4399 {
4400         drm_atomic_private_obj_fini(&dm->atomic_obj);
4401         return;
4402 }
4403
4404 /******************************************************************************
4405  * amdgpu_display_funcs functions
4406  *****************************************************************************/
4407
4408 /*
4409  * dm_bandwidth_update - program display watermarks
4410  *
4411  * @adev: amdgpu_device pointer
4412  *
4413  * Calculate and program the display watermarks and line buffer allocation.
4414  */
4415 static void dm_bandwidth_update(struct amdgpu_device *adev)
4416 {
4417         /* TODO: implement later */
4418 }
4419
4420 static const struct amdgpu_display_funcs dm_display_funcs = {
4421         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4422         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4423         .backlight_set_level = NULL, /* never called for DC */
4424         .backlight_get_level = NULL, /* never called for DC */
4425         .hpd_sense = NULL,/* called unconditionally */
4426         .hpd_set_polarity = NULL, /* called unconditionally */
4427         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4428         .page_flip_get_scanoutpos =
4429                 dm_crtc_get_scanoutpos,/* called unconditionally */
4430         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4431         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4432 };
4433
4434 #if defined(CONFIG_DEBUG_KERNEL_DC)
4435
4436 static ssize_t s3_debug_store(struct device *device,
4437                               struct device_attribute *attr,
4438                               const char *buf,
4439                               size_t count)
4440 {
4441         int ret;
4442         int s3_state;
4443         struct drm_device *drm_dev = dev_get_drvdata(device);
4444         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4445
4446         ret = kstrtoint(buf, 0, &s3_state);
4447
4448         if (ret == 0) {
4449                 if (s3_state) {
4450                         dm_resume(adev);
4451                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4452                 } else
4453                         dm_suspend(adev);
4454         }
4455
4456         return ret == 0 ? count : 0;
4457 }
4458
4459 DEVICE_ATTR_WO(s3_debug);
4460
4461 #endif
4462
4463 static int dm_early_init(void *handle)
4464 {
4465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4466
4467         switch (adev->asic_type) {
4468 #if defined(CONFIG_DRM_AMD_DC_SI)
4469         case CHIP_TAHITI:
4470         case CHIP_PITCAIRN:
4471         case CHIP_VERDE:
4472                 adev->mode_info.num_crtc = 6;
4473                 adev->mode_info.num_hpd = 6;
4474                 adev->mode_info.num_dig = 6;
4475                 break;
4476         case CHIP_OLAND:
4477                 adev->mode_info.num_crtc = 2;
4478                 adev->mode_info.num_hpd = 2;
4479                 adev->mode_info.num_dig = 2;
4480                 break;
4481 #endif
4482         case CHIP_BONAIRE:
4483         case CHIP_HAWAII:
4484                 adev->mode_info.num_crtc = 6;
4485                 adev->mode_info.num_hpd = 6;
4486                 adev->mode_info.num_dig = 6;
4487                 break;
4488         case CHIP_KAVERI:
4489                 adev->mode_info.num_crtc = 4;
4490                 adev->mode_info.num_hpd = 6;
4491                 adev->mode_info.num_dig = 7;
4492                 break;
4493         case CHIP_KABINI:
4494         case CHIP_MULLINS:
4495                 adev->mode_info.num_crtc = 2;
4496                 adev->mode_info.num_hpd = 6;
4497                 adev->mode_info.num_dig = 6;
4498                 break;
4499         case CHIP_FIJI:
4500         case CHIP_TONGA:
4501                 adev->mode_info.num_crtc = 6;
4502                 adev->mode_info.num_hpd = 6;
4503                 adev->mode_info.num_dig = 7;
4504                 break;
4505         case CHIP_CARRIZO:
4506                 adev->mode_info.num_crtc = 3;
4507                 adev->mode_info.num_hpd = 6;
4508                 adev->mode_info.num_dig = 9;
4509                 break;
4510         case CHIP_STONEY:
4511                 adev->mode_info.num_crtc = 2;
4512                 adev->mode_info.num_hpd = 6;
4513                 adev->mode_info.num_dig = 9;
4514                 break;
4515         case CHIP_POLARIS11:
4516         case CHIP_POLARIS12:
4517                 adev->mode_info.num_crtc = 5;
4518                 adev->mode_info.num_hpd = 5;
4519                 adev->mode_info.num_dig = 5;
4520                 break;
4521         case CHIP_POLARIS10:
4522         case CHIP_VEGAM:
4523                 adev->mode_info.num_crtc = 6;
4524                 adev->mode_info.num_hpd = 6;
4525                 adev->mode_info.num_dig = 6;
4526                 break;
4527         case CHIP_VEGA10:
4528         case CHIP_VEGA12:
4529         case CHIP_VEGA20:
4530                 adev->mode_info.num_crtc = 6;
4531                 adev->mode_info.num_hpd = 6;
4532                 adev->mode_info.num_dig = 6;
4533                 break;
4534         default:
4535
4536                 switch (adev->ip_versions[DCE_HWIP][0]) {
4537                 case IP_VERSION(2, 0, 2):
4538                 case IP_VERSION(3, 0, 0):
4539                         adev->mode_info.num_crtc = 6;
4540                         adev->mode_info.num_hpd = 6;
4541                         adev->mode_info.num_dig = 6;
4542                         break;
4543                 case IP_VERSION(2, 0, 0):
4544                 case IP_VERSION(3, 0, 2):
4545                         adev->mode_info.num_crtc = 5;
4546                         adev->mode_info.num_hpd = 5;
4547                         adev->mode_info.num_dig = 5;
4548                         break;
4549                 case IP_VERSION(2, 0, 3):
4550                 case IP_VERSION(3, 0, 3):
4551                         adev->mode_info.num_crtc = 2;
4552                         adev->mode_info.num_hpd = 2;
4553                         adev->mode_info.num_dig = 2;
4554                         break;
4555                 case IP_VERSION(1, 0, 0):
4556                 case IP_VERSION(1, 0, 1):
4557                 case IP_VERSION(3, 0, 1):
4558                 case IP_VERSION(2, 1, 0):
4559                 case IP_VERSION(3, 1, 2):
4560                 case IP_VERSION(3, 1, 3):
4561                 case IP_VERSION(3, 1, 4):
4562                 case IP_VERSION(3, 1, 5):
4563                 case IP_VERSION(3, 1, 6):
4564                 case IP_VERSION(3, 2, 0):
4565                 case IP_VERSION(3, 2, 1):
4566                         adev->mode_info.num_crtc = 4;
4567                         adev->mode_info.num_hpd = 4;
4568                         adev->mode_info.num_dig = 4;
4569                         break;
4570                 default:
4571                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4572                                         adev->ip_versions[DCE_HWIP][0]);
4573                         return -EINVAL;
4574                 }
4575                 break;
4576         }
4577
4578         amdgpu_dm_set_irq_funcs(adev);
4579
4580         if (adev->mode_info.funcs == NULL)
4581                 adev->mode_info.funcs = &dm_display_funcs;
4582
4583         /*
4584          * Note: Do NOT change adev->audio_endpt_rreg and
4585          * adev->audio_endpt_wreg because they are initialised in
4586          * amdgpu_device_init()
4587          */
4588 #if defined(CONFIG_DEBUG_KERNEL_DC)
4589         device_create_file(
4590                 adev_to_drm(adev)->dev,
4591                 &dev_attr_s3_debug);
4592 #endif
4593
4594         return 0;
4595 }
4596
4597 static bool modereset_required(struct drm_crtc_state *crtc_state)
4598 {
4599         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4600 }
4601
4602 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4603 {
4604         drm_encoder_cleanup(encoder);
4605         kfree(encoder);
4606 }
4607
4608 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4609         .destroy = amdgpu_dm_encoder_destroy,
4610 };
4611
4612 static int
4613 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4614                             const enum surface_pixel_format format,
4615                             enum dc_color_space *color_space)
4616 {
4617         bool full_range;
4618
4619         *color_space = COLOR_SPACE_SRGB;
4620
4621         /* DRM color properties only affect non-RGB formats. */
4622         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4623                 return 0;
4624
4625         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4626
4627         switch (plane_state->color_encoding) {
4628         case DRM_COLOR_YCBCR_BT601:
4629                 if (full_range)
4630                         *color_space = COLOR_SPACE_YCBCR601;
4631                 else
4632                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4633                 break;
4634
4635         case DRM_COLOR_YCBCR_BT709:
4636                 if (full_range)
4637                         *color_space = COLOR_SPACE_YCBCR709;
4638                 else
4639                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4640                 break;
4641
4642         case DRM_COLOR_YCBCR_BT2020:
4643                 if (full_range)
4644                         *color_space = COLOR_SPACE_2020_YCBCR;
4645                 else
4646                         return -EINVAL;
4647                 break;
4648
4649         default:
4650                 return -EINVAL;
4651         }
4652
4653         return 0;
4654 }
4655
4656 static int
4657 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4658                             const struct drm_plane_state *plane_state,
4659                             const uint64_t tiling_flags,
4660                             struct dc_plane_info *plane_info,
4661                             struct dc_plane_address *address,
4662                             bool tmz_surface,
4663                             bool force_disable_dcc)
4664 {
4665         const struct drm_framebuffer *fb = plane_state->fb;
4666         const struct amdgpu_framebuffer *afb =
4667                 to_amdgpu_framebuffer(plane_state->fb);
4668         int ret;
4669
4670         memset(plane_info, 0, sizeof(*plane_info));
4671
4672         switch (fb->format->format) {
4673         case DRM_FORMAT_C8:
4674                 plane_info->format =
4675                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4676                 break;
4677         case DRM_FORMAT_RGB565:
4678                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4679                 break;
4680         case DRM_FORMAT_XRGB8888:
4681         case DRM_FORMAT_ARGB8888:
4682                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4683                 break;
4684         case DRM_FORMAT_XRGB2101010:
4685         case DRM_FORMAT_ARGB2101010:
4686                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4687                 break;
4688         case DRM_FORMAT_XBGR2101010:
4689         case DRM_FORMAT_ABGR2101010:
4690                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4691                 break;
4692         case DRM_FORMAT_XBGR8888:
4693         case DRM_FORMAT_ABGR8888:
4694                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4695                 break;
4696         case DRM_FORMAT_NV21:
4697                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4698                 break;
4699         case DRM_FORMAT_NV12:
4700                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4701                 break;
4702         case DRM_FORMAT_P010:
4703                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4704                 break;
4705         case DRM_FORMAT_XRGB16161616F:
4706         case DRM_FORMAT_ARGB16161616F:
4707                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4708                 break;
4709         case DRM_FORMAT_XBGR16161616F:
4710         case DRM_FORMAT_ABGR16161616F:
4711                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4712                 break;
4713         case DRM_FORMAT_XRGB16161616:
4714         case DRM_FORMAT_ARGB16161616:
4715                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4716                 break;
4717         case DRM_FORMAT_XBGR16161616:
4718         case DRM_FORMAT_ABGR16161616:
4719                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4720                 break;
4721         default:
4722                 DRM_ERROR(
4723                         "Unsupported screen format %p4cc\n",
4724                         &fb->format->format);
4725                 return -EINVAL;
4726         }
4727
4728         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4729         case DRM_MODE_ROTATE_0:
4730                 plane_info->rotation = ROTATION_ANGLE_0;
4731                 break;
4732         case DRM_MODE_ROTATE_90:
4733                 plane_info->rotation = ROTATION_ANGLE_90;
4734                 break;
4735         case DRM_MODE_ROTATE_180:
4736                 plane_info->rotation = ROTATION_ANGLE_180;
4737                 break;
4738         case DRM_MODE_ROTATE_270:
4739                 plane_info->rotation = ROTATION_ANGLE_270;
4740                 break;
4741         default:
4742                 plane_info->rotation = ROTATION_ANGLE_0;
4743                 break;
4744         }
4745
4746
4747         plane_info->visible = true;
4748         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4749
4750         plane_info->layer_index = plane_state->normalized_zpos;
4751
4752         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4753                                           &plane_info->color_space);
4754         if (ret)
4755                 return ret;
4756
4757         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4758                                            plane_info->rotation, tiling_flags,
4759                                            &plane_info->tiling_info,
4760                                            &plane_info->plane_size,
4761                                            &plane_info->dcc, address,
4762                                            tmz_surface, force_disable_dcc);
4763         if (ret)
4764                 return ret;
4765
4766         fill_blending_from_plane_state(
4767                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4768                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4769
4770         return 0;
4771 }
4772
4773 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4774                                     struct dc_plane_state *dc_plane_state,
4775                                     struct drm_plane_state *plane_state,
4776                                     struct drm_crtc_state *crtc_state)
4777 {
4778         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4779         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4780         struct dc_scaling_info scaling_info;
4781         struct dc_plane_info plane_info;
4782         int ret;
4783         bool force_disable_dcc = false;
4784
4785         ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4786         if (ret)
4787                 return ret;
4788
4789         dc_plane_state->src_rect = scaling_info.src_rect;
4790         dc_plane_state->dst_rect = scaling_info.dst_rect;
4791         dc_plane_state->clip_rect = scaling_info.clip_rect;
4792         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4793
4794         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4795         ret = fill_dc_plane_info_and_addr(adev, plane_state,
4796                                           afb->tiling_flags,
4797                                           &plane_info,
4798                                           &dc_plane_state->address,
4799                                           afb->tmz_surface,
4800                                           force_disable_dcc);
4801         if (ret)
4802                 return ret;
4803
4804         dc_plane_state->format = plane_info.format;
4805         dc_plane_state->color_space = plane_info.color_space;
4806         dc_plane_state->format = plane_info.format;
4807         dc_plane_state->plane_size = plane_info.plane_size;
4808         dc_plane_state->rotation = plane_info.rotation;
4809         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4810         dc_plane_state->stereo_format = plane_info.stereo_format;
4811         dc_plane_state->tiling_info = plane_info.tiling_info;
4812         dc_plane_state->visible = plane_info.visible;
4813         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4814         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4815         dc_plane_state->global_alpha = plane_info.global_alpha;
4816         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4817         dc_plane_state->dcc = plane_info.dcc;
4818         dc_plane_state->layer_index = plane_info.layer_index;
4819         dc_plane_state->flip_int_enabled = true;
4820
4821         /*
4822          * Always set input transfer function, since plane state is refreshed
4823          * every time.
4824          */
4825         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4826         if (ret)
4827                 return ret;
4828
4829         return 0;
4830 }
4831
4832 /**
4833  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4834  *
4835  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4836  *         remote fb
4837  * @old_plane_state: Old state of @plane
4838  * @new_plane_state: New state of @plane
4839  * @crtc_state: New state of CRTC connected to the @plane
4840  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4841  *
4842  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4843  * (referred to as "damage clips" in DRM nomenclature) that require updating on
4844  * the eDP remote buffer. The responsibility of specifying the dirty regions is
4845  * amdgpu_dm's.
4846  *
4847  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4848  * plane with regions that require flushing to the eDP remote buffer. In
4849  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4850  * implicitly provide damage clips without any client support via the plane
4851  * bounds.
4852  *
4853  * Today, amdgpu_dm only supports the MPO and cursor usecase.
4854  *
4855  * TODO: Also enable for FB_DAMAGE_CLIPS
4856  */
4857 static void fill_dc_dirty_rects(struct drm_plane *plane,
4858                                 struct drm_plane_state *old_plane_state,
4859                                 struct drm_plane_state *new_plane_state,
4860                                 struct drm_crtc_state *crtc_state,
4861                                 struct dc_flip_addrs *flip_addrs)
4862 {
4863         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4864         struct rect *dirty_rects = flip_addrs->dirty_rects;
4865         uint32_t num_clips;
4866         bool bb_changed;
4867         bool fb_changed;
4868         uint32_t i = 0;
4869
4870         flip_addrs->dirty_rect_count = 0;
4871
4872         /*
4873          * Cursor plane has it's own dirty rect update interface. See
4874          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
4875          */
4876         if (plane->type == DRM_PLANE_TYPE_CURSOR)
4877                 return;
4878
4879         /*
4880          * Today, we only consider MPO use-case for PSR SU. If MPO not
4881          * requested, and there is a plane update, do FFU.
4882          */
4883         if (!dm_crtc_state->mpo_requested) {
4884                 dirty_rects[0].x = 0;
4885                 dirty_rects[0].y = 0;
4886                 dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
4887                 dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
4888                 flip_addrs->dirty_rect_count = 1;
4889                 DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4890                                  new_plane_state->plane->base.id,
4891                                  dm_crtc_state->base.mode.crtc_hdisplay,
4892                                  dm_crtc_state->base.mode.crtc_vdisplay);
4893                 return;
4894         }
4895
4896         /*
4897          * MPO is requested. Add entire plane bounding box to dirty rects if
4898          * flipped to or damaged.
4899          *
4900          * If plane is moved or resized, also add old bounding box to dirty
4901          * rects.
4902          */
4903         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
4904         fb_changed = old_plane_state->fb->base.id !=
4905                      new_plane_state->fb->base.id;
4906         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
4907                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
4908                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
4909                       old_plane_state->crtc_h != new_plane_state->crtc_h);
4910
4911         DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
4912                          new_plane_state->plane->base.id,
4913                          bb_changed, fb_changed, num_clips);
4914
4915         if (num_clips || fb_changed || bb_changed) {
4916                 dirty_rects[i].x = new_plane_state->crtc_x;
4917                 dirty_rects[i].y = new_plane_state->crtc_y;
4918                 dirty_rects[i].width = new_plane_state->crtc_w;
4919                 dirty_rects[i].height = new_plane_state->crtc_h;
4920                 DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
4921                                  new_plane_state->plane->base.id,
4922                                  dirty_rects[i].x, dirty_rects[i].y,
4923                                  dirty_rects[i].width, dirty_rects[i].height);
4924                 i += 1;
4925         }
4926
4927         /* Add old plane bounding-box if plane is moved or resized */
4928         if (bb_changed) {
4929                 dirty_rects[i].x = old_plane_state->crtc_x;
4930                 dirty_rects[i].y = old_plane_state->crtc_y;
4931                 dirty_rects[i].width = old_plane_state->crtc_w;
4932                 dirty_rects[i].height = old_plane_state->crtc_h;
4933                 DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
4934                                 old_plane_state->plane->base.id,
4935                                 dirty_rects[i].x, dirty_rects[i].y,
4936                                 dirty_rects[i].width, dirty_rects[i].height);
4937                 i += 1;
4938         }
4939
4940         flip_addrs->dirty_rect_count = i;
4941 }
4942
4943 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4944                                            const struct dm_connector_state *dm_state,
4945                                            struct dc_stream_state *stream)
4946 {
4947         enum amdgpu_rmx_type rmx_type;
4948
4949         struct rect src = { 0 }; /* viewport in composition space*/
4950         struct rect dst = { 0 }; /* stream addressable area */
4951
4952         /* no mode. nothing to be done */
4953         if (!mode)
4954                 return;
4955
4956         /* Full screen scaling by default */
4957         src.width = mode->hdisplay;
4958         src.height = mode->vdisplay;
4959         dst.width = stream->timing.h_addressable;
4960         dst.height = stream->timing.v_addressable;
4961
4962         if (dm_state) {
4963                 rmx_type = dm_state->scaling;
4964                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4965                         if (src.width * dst.height <
4966                                         src.height * dst.width) {
4967                                 /* height needs less upscaling/more downscaling */
4968                                 dst.width = src.width *
4969                                                 dst.height / src.height;
4970                         } else {
4971                                 /* width needs less upscaling/more downscaling */
4972                                 dst.height = src.height *
4973                                                 dst.width / src.width;
4974                         }
4975                 } else if (rmx_type == RMX_CENTER) {
4976                         dst = src;
4977                 }
4978
4979                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4980                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
4981
4982                 if (dm_state->underscan_enable) {
4983                         dst.x += dm_state->underscan_hborder / 2;
4984                         dst.y += dm_state->underscan_vborder / 2;
4985                         dst.width -= dm_state->underscan_hborder;
4986                         dst.height -= dm_state->underscan_vborder;
4987                 }
4988         }
4989
4990         stream->src = src;
4991         stream->dst = dst;
4992
4993         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
4994                       dst.x, dst.y, dst.width, dst.height);
4995
4996 }
4997
4998 static enum dc_color_depth
4999 convert_color_depth_from_display_info(const struct drm_connector *connector,
5000                                       bool is_y420, int requested_bpc)
5001 {
5002         uint8_t bpc;
5003
5004         if (is_y420) {
5005                 bpc = 8;
5006
5007                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5008                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5009                         bpc = 16;
5010                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5011                         bpc = 12;
5012                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5013                         bpc = 10;
5014         } else {
5015                 bpc = (uint8_t)connector->display_info.bpc;
5016                 /* Assume 8 bpc by default if no bpc is specified. */
5017                 bpc = bpc ? bpc : 8;
5018         }
5019
5020         if (requested_bpc > 0) {
5021                 /*
5022                  * Cap display bpc based on the user requested value.
5023                  *
5024                  * The value for state->max_bpc may not correctly updated
5025                  * depending on when the connector gets added to the state
5026                  * or if this was called outside of atomic check, so it
5027                  * can't be used directly.
5028                  */
5029                 bpc = min_t(u8, bpc, requested_bpc);
5030
5031                 /* Round down to the nearest even number. */
5032                 bpc = bpc - (bpc & 1);
5033         }
5034
5035         switch (bpc) {
5036         case 0:
5037                 /*
5038                  * Temporary Work around, DRM doesn't parse color depth for
5039                  * EDID revision before 1.4
5040                  * TODO: Fix edid parsing
5041                  */
5042                 return COLOR_DEPTH_888;
5043         case 6:
5044                 return COLOR_DEPTH_666;
5045         case 8:
5046                 return COLOR_DEPTH_888;
5047         case 10:
5048                 return COLOR_DEPTH_101010;
5049         case 12:
5050                 return COLOR_DEPTH_121212;
5051         case 14:
5052                 return COLOR_DEPTH_141414;
5053         case 16:
5054                 return COLOR_DEPTH_161616;
5055         default:
5056                 return COLOR_DEPTH_UNDEFINED;
5057         }
5058 }
5059
5060 static enum dc_aspect_ratio
5061 get_aspect_ratio(const struct drm_display_mode *mode_in)
5062 {
5063         /* 1-1 mapping, since both enums follow the HDMI spec. */
5064         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5065 }
5066
5067 static enum dc_color_space
5068 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5069 {
5070         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5071
5072         switch (dc_crtc_timing->pixel_encoding) {
5073         case PIXEL_ENCODING_YCBCR422:
5074         case PIXEL_ENCODING_YCBCR444:
5075         case PIXEL_ENCODING_YCBCR420:
5076         {
5077                 /*
5078                  * 27030khz is the separation point between HDTV and SDTV
5079                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5080                  * respectively
5081                  */
5082                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5083                         if (dc_crtc_timing->flags.Y_ONLY)
5084                                 color_space =
5085                                         COLOR_SPACE_YCBCR709_LIMITED;
5086                         else
5087                                 color_space = COLOR_SPACE_YCBCR709;
5088                 } else {
5089                         if (dc_crtc_timing->flags.Y_ONLY)
5090                                 color_space =
5091                                         COLOR_SPACE_YCBCR601_LIMITED;
5092                         else
5093                                 color_space = COLOR_SPACE_YCBCR601;
5094                 }
5095
5096         }
5097         break;
5098         case PIXEL_ENCODING_RGB:
5099                 color_space = COLOR_SPACE_SRGB;
5100                 break;
5101
5102         default:
5103                 WARN_ON(1);
5104                 break;
5105         }
5106
5107         return color_space;
5108 }
5109
5110 static bool adjust_colour_depth_from_display_info(
5111         struct dc_crtc_timing *timing_out,
5112         const struct drm_display_info *info)
5113 {
5114         enum dc_color_depth depth = timing_out->display_color_depth;
5115         int normalized_clk;
5116         do {
5117                 normalized_clk = timing_out->pix_clk_100hz / 10;
5118                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5119                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5120                         normalized_clk /= 2;
5121                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5122                 switch (depth) {
5123                 case COLOR_DEPTH_888:
5124                         break;
5125                 case COLOR_DEPTH_101010:
5126                         normalized_clk = (normalized_clk * 30) / 24;
5127                         break;
5128                 case COLOR_DEPTH_121212:
5129                         normalized_clk = (normalized_clk * 36) / 24;
5130                         break;
5131                 case COLOR_DEPTH_161616:
5132                         normalized_clk = (normalized_clk * 48) / 24;
5133                         break;
5134                 default:
5135                         /* The above depths are the only ones valid for HDMI. */
5136                         return false;
5137                 }
5138                 if (normalized_clk <= info->max_tmds_clock) {
5139                         timing_out->display_color_depth = depth;
5140                         return true;
5141                 }
5142         } while (--depth > COLOR_DEPTH_666);
5143         return false;
5144 }
5145
5146 static void fill_stream_properties_from_drm_display_mode(
5147         struct dc_stream_state *stream,
5148         const struct drm_display_mode *mode_in,
5149         const struct drm_connector *connector,
5150         const struct drm_connector_state *connector_state,
5151         const struct dc_stream_state *old_stream,
5152         int requested_bpc)
5153 {
5154         struct dc_crtc_timing *timing_out = &stream->timing;
5155         const struct drm_display_info *info = &connector->display_info;
5156         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5157         struct hdmi_vendor_infoframe hv_frame;
5158         struct hdmi_avi_infoframe avi_frame;
5159
5160         memset(&hv_frame, 0, sizeof(hv_frame));
5161         memset(&avi_frame, 0, sizeof(avi_frame));
5162
5163         timing_out->h_border_left = 0;
5164         timing_out->h_border_right = 0;
5165         timing_out->v_border_top = 0;
5166         timing_out->v_border_bottom = 0;
5167         /* TODO: un-hardcode */
5168         if (drm_mode_is_420_only(info, mode_in)
5169                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5170                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5171         else if (drm_mode_is_420_also(info, mode_in)
5172                         && aconnector->force_yuv420_output)
5173                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5174         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5175                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5176                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5177         else
5178                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5179
5180         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5181         timing_out->display_color_depth = convert_color_depth_from_display_info(
5182                 connector,
5183                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5184                 requested_bpc);
5185         timing_out->scan_type = SCANNING_TYPE_NODATA;
5186         timing_out->hdmi_vic = 0;
5187
5188         if (old_stream) {
5189                 timing_out->vic = old_stream->timing.vic;
5190                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5191                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5192         } else {
5193                 timing_out->vic = drm_match_cea_mode(mode_in);
5194                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5195                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5196                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5197                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5198         }
5199
5200         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5201                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5202                 timing_out->vic = avi_frame.video_code;
5203                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5204                 timing_out->hdmi_vic = hv_frame.vic;
5205         }
5206
5207         if (is_freesync_video_mode(mode_in, aconnector)) {
5208                 timing_out->h_addressable = mode_in->hdisplay;
5209                 timing_out->h_total = mode_in->htotal;
5210                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5211                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5212                 timing_out->v_total = mode_in->vtotal;
5213                 timing_out->v_addressable = mode_in->vdisplay;
5214                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5215                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5216                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5217         } else {
5218                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5219                 timing_out->h_total = mode_in->crtc_htotal;
5220                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5221                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5222                 timing_out->v_total = mode_in->crtc_vtotal;
5223                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5224                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5225                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5226                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5227         }
5228
5229         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5230
5231         stream->output_color_space = get_output_color_space(timing_out);
5232
5233         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5234         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5235         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5236                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5237                     drm_mode_is_420_also(info, mode_in) &&
5238                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5239                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5240                         adjust_colour_depth_from_display_info(timing_out, info);
5241                 }
5242         }
5243 }
5244
5245 static void fill_audio_info(struct audio_info *audio_info,
5246                             const struct drm_connector *drm_connector,
5247                             const struct dc_sink *dc_sink)
5248 {
5249         int i = 0;
5250         int cea_revision = 0;
5251         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5252
5253         audio_info->manufacture_id = edid_caps->manufacturer_id;
5254         audio_info->product_id = edid_caps->product_id;
5255
5256         cea_revision = drm_connector->display_info.cea_rev;
5257
5258         strscpy(audio_info->display_name,
5259                 edid_caps->display_name,
5260                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5261
5262         if (cea_revision >= 3) {
5263                 audio_info->mode_count = edid_caps->audio_mode_count;
5264
5265                 for (i = 0; i < audio_info->mode_count; ++i) {
5266                         audio_info->modes[i].format_code =
5267                                         (enum audio_format_code)
5268                                         (edid_caps->audio_modes[i].format_code);
5269                         audio_info->modes[i].channel_count =
5270                                         edid_caps->audio_modes[i].channel_count;
5271                         audio_info->modes[i].sample_rates.all =
5272                                         edid_caps->audio_modes[i].sample_rate;
5273                         audio_info->modes[i].sample_size =
5274                                         edid_caps->audio_modes[i].sample_size;
5275                 }
5276         }
5277
5278         audio_info->flags.all = edid_caps->speaker_flags;
5279
5280         /* TODO: We only check for the progressive mode, check for interlace mode too */
5281         if (drm_connector->latency_present[0]) {
5282                 audio_info->video_latency = drm_connector->video_latency[0];
5283                 audio_info->audio_latency = drm_connector->audio_latency[0];
5284         }
5285
5286         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5287
5288 }
5289
5290 static void
5291 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5292                                       struct drm_display_mode *dst_mode)
5293 {
5294         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5295         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5296         dst_mode->crtc_clock = src_mode->crtc_clock;
5297         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5298         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5299         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5300         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5301         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5302         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5303         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5304         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5305         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5306         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5307         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5308 }
5309
5310 static void
5311 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5312                                         const struct drm_display_mode *native_mode,
5313                                         bool scale_enabled)
5314 {
5315         if (scale_enabled) {
5316                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5317         } else if (native_mode->clock == drm_mode->clock &&
5318                         native_mode->htotal == drm_mode->htotal &&
5319                         native_mode->vtotal == drm_mode->vtotal) {
5320                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5321         } else {
5322                 /* no scaling nor amdgpu inserted, no need to patch */
5323         }
5324 }
5325
5326 static struct dc_sink *
5327 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5328 {
5329         struct dc_sink_init_data sink_init_data = { 0 };
5330         struct dc_sink *sink = NULL;
5331         sink_init_data.link = aconnector->dc_link;
5332         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5333
5334         sink = dc_sink_create(&sink_init_data);
5335         if (!sink) {
5336                 DRM_ERROR("Failed to create sink!\n");
5337                 return NULL;
5338         }
5339         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5340
5341         return sink;
5342 }
5343
5344 static void set_multisync_trigger_params(
5345                 struct dc_stream_state *stream)
5346 {
5347         struct dc_stream_state *master = NULL;
5348
5349         if (stream->triggered_crtc_reset.enabled) {
5350                 master = stream->triggered_crtc_reset.event_source;
5351                 stream->triggered_crtc_reset.event =
5352                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5353                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5354                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5355         }
5356 }
5357
5358 static void set_master_stream(struct dc_stream_state *stream_set[],
5359                               int stream_count)
5360 {
5361         int j, highest_rfr = 0, master_stream = 0;
5362
5363         for (j = 0;  j < stream_count; j++) {
5364                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5365                         int refresh_rate = 0;
5366
5367                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5368                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5369                         if (refresh_rate > highest_rfr) {
5370                                 highest_rfr = refresh_rate;
5371                                 master_stream = j;
5372                         }
5373                 }
5374         }
5375         for (j = 0;  j < stream_count; j++) {
5376                 if (stream_set[j])
5377                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5378         }
5379 }
5380
5381 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5382 {
5383         int i = 0;
5384         struct dc_stream_state *stream;
5385
5386         if (context->stream_count < 2)
5387                 return;
5388         for (i = 0; i < context->stream_count ; i++) {
5389                 if (!context->streams[i])
5390                         continue;
5391                 /*
5392                  * TODO: add a function to read AMD VSDB bits and set
5393                  * crtc_sync_master.multi_sync_enabled flag
5394                  * For now it's set to false
5395                  */
5396         }
5397
5398         set_master_stream(context->streams, context->stream_count);
5399
5400         for (i = 0; i < context->stream_count ; i++) {
5401                 stream = context->streams[i];
5402
5403                 if (!stream)
5404                         continue;
5405
5406                 set_multisync_trigger_params(stream);
5407         }
5408 }
5409
5410 /**
5411  * DOC: FreeSync Video
5412  *
5413  * When a userspace application wants to play a video, the content follows a
5414  * standard format definition that usually specifies the FPS for that format.
5415  * The below list illustrates some video format and the expected FPS,
5416  * respectively:
5417  *
5418  * - TV/NTSC (23.976 FPS)
5419  * - Cinema (24 FPS)
5420  * - TV/PAL (25 FPS)
5421  * - TV/NTSC (29.97 FPS)
5422  * - TV/NTSC (30 FPS)
5423  * - Cinema HFR (48 FPS)
5424  * - TV/PAL (50 FPS)
5425  * - Commonly used (60 FPS)
5426  * - Multiples of 24 (48,72,96 FPS)
5427  *
5428  * The list of standards video format is not huge and can be added to the
5429  * connector modeset list beforehand. With that, userspace can leverage
5430  * FreeSync to extends the front porch in order to attain the target refresh
5431  * rate. Such a switch will happen seamlessly, without screen blanking or
5432  * reprogramming of the output in any other way. If the userspace requests a
5433  * modesetting change compatible with FreeSync modes that only differ in the
5434  * refresh rate, DC will skip the full update and avoid blink during the
5435  * transition. For example, the video player can change the modesetting from
5436  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5437  * causing any display blink. This same concept can be applied to a mode
5438  * setting change.
5439  */
5440 static struct drm_display_mode *
5441 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5442                 bool use_probed_modes)
5443 {
5444         struct drm_display_mode *m, *m_pref = NULL;
5445         u16 current_refresh, highest_refresh;
5446         struct list_head *list_head = use_probed_modes ?
5447                 &aconnector->base.probed_modes :
5448                 &aconnector->base.modes;
5449
5450         if (aconnector->freesync_vid_base.clock != 0)
5451                 return &aconnector->freesync_vid_base;
5452
5453         /* Find the preferred mode */
5454         list_for_each_entry (m, list_head, head) {
5455                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5456                         m_pref = m;
5457                         break;
5458                 }
5459         }
5460
5461         if (!m_pref) {
5462                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5463                 m_pref = list_first_entry_or_null(
5464                                 &aconnector->base.modes, struct drm_display_mode, head);
5465                 if (!m_pref) {
5466                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5467                         return NULL;
5468                 }
5469         }
5470
5471         highest_refresh = drm_mode_vrefresh(m_pref);
5472
5473         /*
5474          * Find the mode with highest refresh rate with same resolution.
5475          * For some monitors, preferred mode is not the mode with highest
5476          * supported refresh rate.
5477          */
5478         list_for_each_entry (m, list_head, head) {
5479                 current_refresh  = drm_mode_vrefresh(m);
5480
5481                 if (m->hdisplay == m_pref->hdisplay &&
5482                     m->vdisplay == m_pref->vdisplay &&
5483                     highest_refresh < current_refresh) {
5484                         highest_refresh = current_refresh;
5485                         m_pref = m;
5486                 }
5487         }
5488
5489         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5490         return m_pref;
5491 }
5492
5493 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5494                 struct amdgpu_dm_connector *aconnector)
5495 {
5496         struct drm_display_mode *high_mode;
5497         int timing_diff;
5498
5499         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5500         if (!high_mode || !mode)
5501                 return false;
5502
5503         timing_diff = high_mode->vtotal - mode->vtotal;
5504
5505         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5506             high_mode->hdisplay != mode->hdisplay ||
5507             high_mode->vdisplay != mode->vdisplay ||
5508             high_mode->hsync_start != mode->hsync_start ||
5509             high_mode->hsync_end != mode->hsync_end ||
5510             high_mode->htotal != mode->htotal ||
5511             high_mode->hskew != mode->hskew ||
5512             high_mode->vscan != mode->vscan ||
5513             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5514             high_mode->vsync_end - mode->vsync_end != timing_diff)
5515                 return false;
5516         else
5517                 return true;
5518 }
5519
5520 #if defined(CONFIG_DRM_AMD_DC_DCN)
5521 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5522                             struct dc_sink *sink, struct dc_stream_state *stream,
5523                             struct dsc_dec_dpcd_caps *dsc_caps)
5524 {
5525         stream->timing.flags.DSC = 0;
5526         dsc_caps->is_dsc_supported = false;
5527
5528         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5529             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5530                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5531                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5532                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5533                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5534                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5535                                 dsc_caps);
5536         }
5537 }
5538
5539
5540 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5541                                     struct dc_sink *sink, struct dc_stream_state *stream,
5542                                     struct dsc_dec_dpcd_caps *dsc_caps,
5543                                     uint32_t max_dsc_target_bpp_limit_override)
5544 {
5545         const struct dc_link_settings *verified_link_cap = NULL;
5546         uint32_t link_bw_in_kbps;
5547         uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
5548         struct dc *dc = sink->ctx->dc;
5549         struct dc_dsc_bw_range bw_range = {0};
5550         struct dc_dsc_config dsc_cfg = {0};
5551
5552         verified_link_cap = dc_link_get_link_cap(stream->link);
5553         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5554         edp_min_bpp_x16 = 8 * 16;
5555         edp_max_bpp_x16 = 8 * 16;
5556
5557         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5558                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5559
5560         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5561                 edp_min_bpp_x16 = edp_max_bpp_x16;
5562
5563         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5564                                 dc->debug.dsc_min_slice_height_override,
5565                                 edp_min_bpp_x16, edp_max_bpp_x16,
5566                                 dsc_caps,
5567                                 &stream->timing,
5568                                 &bw_range)) {
5569
5570                 if (bw_range.max_kbps < link_bw_in_kbps) {
5571                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5572                                         dsc_caps,
5573                                         dc->debug.dsc_min_slice_height_override,
5574                                         max_dsc_target_bpp_limit_override,
5575                                         0,
5576                                         &stream->timing,
5577                                         &dsc_cfg)) {
5578                                 stream->timing.dsc_cfg = dsc_cfg;
5579                                 stream->timing.flags.DSC = 1;
5580                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5581                         }
5582                         return;
5583                 }
5584         }
5585
5586         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5587                                 dsc_caps,
5588                                 dc->debug.dsc_min_slice_height_override,
5589                                 max_dsc_target_bpp_limit_override,
5590                                 link_bw_in_kbps,
5591                                 &stream->timing,
5592                                 &dsc_cfg)) {
5593                 stream->timing.dsc_cfg = dsc_cfg;
5594                 stream->timing.flags.DSC = 1;
5595         }
5596 }
5597
5598
5599 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5600                                         struct dc_sink *sink, struct dc_stream_state *stream,
5601                                         struct dsc_dec_dpcd_caps *dsc_caps)
5602 {
5603         struct drm_connector *drm_connector = &aconnector->base;
5604         uint32_t link_bandwidth_kbps;
5605         struct dc *dc = sink->ctx->dc;
5606         uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
5607         uint32_t dsc_max_supported_bw_in_kbps;
5608         uint32_t max_dsc_target_bpp_limit_override =
5609                 drm_connector->display_info.max_dsc_bpp;
5610
5611         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5612                                                         dc_link_get_link_cap(aconnector->dc_link));
5613
5614         /* Set DSC policy according to dsc_clock_en */
5615         dc_dsc_policy_set_enable_dsc_when_not_needed(
5616                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5617
5618         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5619             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5620             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5621
5622                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5623
5624         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5625                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5626                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5627                                                 dsc_caps,
5628                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5629                                                 max_dsc_target_bpp_limit_override,
5630                                                 link_bandwidth_kbps,
5631                                                 &stream->timing,
5632                                                 &stream->timing.dsc_cfg)) {
5633                                 stream->timing.flags.DSC = 1;
5634                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5635                         }
5636                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5637                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5638                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5639                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5640
5641                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5642                                         max_supported_bw_in_kbps > 0 &&
5643                                         dsc_max_supported_bw_in_kbps > 0)
5644                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5645                                                 dsc_caps,
5646                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5647                                                 max_dsc_target_bpp_limit_override,
5648                                                 dsc_max_supported_bw_in_kbps,
5649                                                 &stream->timing,
5650                                                 &stream->timing.dsc_cfg)) {
5651                                         stream->timing.flags.DSC = 1;
5652                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5653                                                                          __func__, drm_connector->name);
5654                                 }
5655                 }
5656         }
5657
5658         /* Overwrite the stream flag if DSC is enabled through debugfs */
5659         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5660                 stream->timing.flags.DSC = 1;
5661
5662         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5663                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5664
5665         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5666                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5667
5668         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5669                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5670 }
5671 #endif /* CONFIG_DRM_AMD_DC_DCN */
5672
5673 static struct dc_stream_state *
5674 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5675                        const struct drm_display_mode *drm_mode,
5676                        const struct dm_connector_state *dm_state,
5677                        const struct dc_stream_state *old_stream,
5678                        int requested_bpc)
5679 {
5680         struct drm_display_mode *preferred_mode = NULL;
5681         struct drm_connector *drm_connector;
5682         const struct drm_connector_state *con_state =
5683                 dm_state ? &dm_state->base : NULL;
5684         struct dc_stream_state *stream = NULL;
5685         struct drm_display_mode mode = *drm_mode;
5686         struct drm_display_mode saved_mode;
5687         struct drm_display_mode *freesync_mode = NULL;
5688         bool native_mode_found = false;
5689         bool recalculate_timing = false;
5690         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5691         int mode_refresh;
5692         int preferred_refresh = 0;
5693         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5694 #if defined(CONFIG_DRM_AMD_DC_DCN)
5695         struct dsc_dec_dpcd_caps dsc_caps;
5696 #endif
5697
5698         struct dc_sink *sink = NULL;
5699
5700         memset(&saved_mode, 0, sizeof(saved_mode));
5701
5702         if (aconnector == NULL) {
5703                 DRM_ERROR("aconnector is NULL!\n");
5704                 return stream;
5705         }
5706
5707         drm_connector = &aconnector->base;
5708
5709         if (!aconnector->dc_sink) {
5710                 sink = create_fake_sink(aconnector);
5711                 if (!sink)
5712                         return stream;
5713         } else {
5714                 sink = aconnector->dc_sink;
5715                 dc_sink_retain(sink);
5716         }
5717
5718         stream = dc_create_stream_for_sink(sink);
5719
5720         if (stream == NULL) {
5721                 DRM_ERROR("Failed to create stream for sink!\n");
5722                 goto finish;
5723         }
5724
5725         stream->dm_stream_context = aconnector;
5726
5727         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5728                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5729
5730         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5731                 /* Search for preferred mode */
5732                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5733                         native_mode_found = true;
5734                         break;
5735                 }
5736         }
5737         if (!native_mode_found)
5738                 preferred_mode = list_first_entry_or_null(
5739                                 &aconnector->base.modes,
5740                                 struct drm_display_mode,
5741                                 head);
5742
5743         mode_refresh = drm_mode_vrefresh(&mode);
5744
5745         if (preferred_mode == NULL) {
5746                 /*
5747                  * This may not be an error, the use case is when we have no
5748                  * usermode calls to reset and set mode upon hotplug. In this
5749                  * case, we call set mode ourselves to restore the previous mode
5750                  * and the modelist may not be filled in in time.
5751                  */
5752                 DRM_DEBUG_DRIVER("No preferred mode found\n");
5753         } else {
5754                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
5755                 if (recalculate_timing) {
5756                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5757                         drm_mode_copy(&saved_mode, &mode);
5758                         drm_mode_copy(&mode, freesync_mode);
5759                 } else {
5760                         decide_crtc_timing_for_drm_display_mode(
5761                                         &mode, preferred_mode, scale);
5762
5763                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
5764                 }
5765         }
5766
5767         if (recalculate_timing)
5768                 drm_mode_set_crtcinfo(&saved_mode, 0);
5769         else if (!dm_state)
5770                 drm_mode_set_crtcinfo(&mode, 0);
5771
5772         /*
5773         * If scaling is enabled and refresh rate didn't change
5774         * we copy the vic and polarities of the old timings
5775         */
5776         if (!scale || mode_refresh != preferred_refresh)
5777                 fill_stream_properties_from_drm_display_mode(
5778                         stream, &mode, &aconnector->base, con_state, NULL,
5779                         requested_bpc);
5780         else
5781                 fill_stream_properties_from_drm_display_mode(
5782                         stream, &mode, &aconnector->base, con_state, old_stream,
5783                         requested_bpc);
5784
5785 #if defined(CONFIG_DRM_AMD_DC_DCN)
5786         /* SST DSC determination policy */
5787         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5788         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5789                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
5790 #endif
5791
5792         update_stream_scaling_settings(&mode, dm_state, stream);
5793
5794         fill_audio_info(
5795                 &stream->audio_info,
5796                 drm_connector,
5797                 sink);
5798
5799         update_stream_signal(stream, sink);
5800
5801         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5802                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5803
5804         if (stream->link->psr_settings.psr_feature_enabled) {
5805                 //
5806                 // should decide stream support vsc sdp colorimetry capability
5807                 // before building vsc info packet
5808                 //
5809                 stream->use_vsc_sdp_for_colorimetry = false;
5810                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5811                         stream->use_vsc_sdp_for_colorimetry =
5812                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5813                 } else {
5814                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5815                                 stream->use_vsc_sdp_for_colorimetry = true;
5816                 }
5817                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
5818                         tf = TRANSFER_FUNC_GAMMA_22;
5819                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
5820                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5821
5822         }
5823 finish:
5824         dc_sink_release(sink);
5825
5826         return stream;
5827 }
5828
5829 static enum drm_connector_status
5830 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5831 {
5832         bool connected;
5833         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5834
5835         /*
5836          * Notes:
5837          * 1. This interface is NOT called in context of HPD irq.
5838          * 2. This interface *is called* in context of user-mode ioctl. Which
5839          * makes it a bad place for *any* MST-related activity.
5840          */
5841
5842         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5843             !aconnector->fake_enable)
5844                 connected = (aconnector->dc_sink != NULL);
5845         else
5846                 connected = (aconnector->base.force == DRM_FORCE_ON ||
5847                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
5848
5849         update_subconnector_property(aconnector);
5850
5851         return (connected ? connector_status_connected :
5852                         connector_status_disconnected);
5853 }
5854
5855 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5856                                             struct drm_connector_state *connector_state,
5857                                             struct drm_property *property,
5858                                             uint64_t val)
5859 {
5860         struct drm_device *dev = connector->dev;
5861         struct amdgpu_device *adev = drm_to_adev(dev);
5862         struct dm_connector_state *dm_old_state =
5863                 to_dm_connector_state(connector->state);
5864         struct dm_connector_state *dm_new_state =
5865                 to_dm_connector_state(connector_state);
5866
5867         int ret = -EINVAL;
5868
5869         if (property == dev->mode_config.scaling_mode_property) {
5870                 enum amdgpu_rmx_type rmx_type;
5871
5872                 switch (val) {
5873                 case DRM_MODE_SCALE_CENTER:
5874                         rmx_type = RMX_CENTER;
5875                         break;
5876                 case DRM_MODE_SCALE_ASPECT:
5877                         rmx_type = RMX_ASPECT;
5878                         break;
5879                 case DRM_MODE_SCALE_FULLSCREEN:
5880                         rmx_type = RMX_FULL;
5881                         break;
5882                 case DRM_MODE_SCALE_NONE:
5883                 default:
5884                         rmx_type = RMX_OFF;
5885                         break;
5886                 }
5887
5888                 if (dm_old_state->scaling == rmx_type)
5889                         return 0;
5890
5891                 dm_new_state->scaling = rmx_type;
5892                 ret = 0;
5893         } else if (property == adev->mode_info.underscan_hborder_property) {
5894                 dm_new_state->underscan_hborder = val;
5895                 ret = 0;
5896         } else if (property == adev->mode_info.underscan_vborder_property) {
5897                 dm_new_state->underscan_vborder = val;
5898                 ret = 0;
5899         } else if (property == adev->mode_info.underscan_property) {
5900                 dm_new_state->underscan_enable = val;
5901                 ret = 0;
5902         } else if (property == adev->mode_info.abm_level_property) {
5903                 dm_new_state->abm_level = val;
5904                 ret = 0;
5905         }
5906
5907         return ret;
5908 }
5909
5910 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5911                                             const struct drm_connector_state *state,
5912                                             struct drm_property *property,
5913                                             uint64_t *val)
5914 {
5915         struct drm_device *dev = connector->dev;
5916         struct amdgpu_device *adev = drm_to_adev(dev);
5917         struct dm_connector_state *dm_state =
5918                 to_dm_connector_state(state);
5919         int ret = -EINVAL;
5920
5921         if (property == dev->mode_config.scaling_mode_property) {
5922                 switch (dm_state->scaling) {
5923                 case RMX_CENTER:
5924                         *val = DRM_MODE_SCALE_CENTER;
5925                         break;
5926                 case RMX_ASPECT:
5927                         *val = DRM_MODE_SCALE_ASPECT;
5928                         break;
5929                 case RMX_FULL:
5930                         *val = DRM_MODE_SCALE_FULLSCREEN;
5931                         break;
5932                 case RMX_OFF:
5933                 default:
5934                         *val = DRM_MODE_SCALE_NONE;
5935                         break;
5936                 }
5937                 ret = 0;
5938         } else if (property == adev->mode_info.underscan_hborder_property) {
5939                 *val = dm_state->underscan_hborder;
5940                 ret = 0;
5941         } else if (property == adev->mode_info.underscan_vborder_property) {
5942                 *val = dm_state->underscan_vborder;
5943                 ret = 0;
5944         } else if (property == adev->mode_info.underscan_property) {
5945                 *val = dm_state->underscan_enable;
5946                 ret = 0;
5947         } else if (property == adev->mode_info.abm_level_property) {
5948                 *val = dm_state->abm_level;
5949                 ret = 0;
5950         }
5951
5952         return ret;
5953 }
5954
5955 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5956 {
5957         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5958
5959         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5960 }
5961
5962 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5963 {
5964         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5965         const struct dc_link *link = aconnector->dc_link;
5966         struct amdgpu_device *adev = drm_to_adev(connector->dev);
5967         struct amdgpu_display_manager *dm = &adev->dm;
5968         int i;
5969
5970         /*
5971          * Call only if mst_mgr was initialized before since it's not done
5972          * for all connector types.
5973          */
5974         if (aconnector->mst_mgr.dev)
5975                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5976
5977 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5978         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5979         for (i = 0; i < dm->num_of_edps; i++) {
5980                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
5981                         backlight_device_unregister(dm->backlight_dev[i]);
5982                         dm->backlight_dev[i] = NULL;
5983                 }
5984         }
5985 #endif
5986
5987         if (aconnector->dc_em_sink)
5988                 dc_sink_release(aconnector->dc_em_sink);
5989         aconnector->dc_em_sink = NULL;
5990         if (aconnector->dc_sink)
5991                 dc_sink_release(aconnector->dc_sink);
5992         aconnector->dc_sink = NULL;
5993
5994         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
5995         drm_connector_unregister(connector);
5996         drm_connector_cleanup(connector);
5997         if (aconnector->i2c) {
5998                 i2c_del_adapter(&aconnector->i2c->base);
5999                 kfree(aconnector->i2c);
6000         }
6001         kfree(aconnector->dm_dp_aux.aux.name);
6002
6003         kfree(connector);
6004 }
6005
6006 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6007 {
6008         struct dm_connector_state *state =
6009                 to_dm_connector_state(connector->state);
6010
6011         if (connector->state)
6012                 __drm_atomic_helper_connector_destroy_state(connector->state);
6013
6014         kfree(state);
6015
6016         state = kzalloc(sizeof(*state), GFP_KERNEL);
6017
6018         if (state) {
6019                 state->scaling = RMX_OFF;
6020                 state->underscan_enable = false;
6021                 state->underscan_hborder = 0;
6022                 state->underscan_vborder = 0;
6023                 state->base.max_requested_bpc = 8;
6024                 state->vcpi_slots = 0;
6025                 state->pbn = 0;
6026
6027                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6028                         state->abm_level = amdgpu_dm_abm_level;
6029
6030                 __drm_atomic_helper_connector_reset(connector, &state->base);
6031         }
6032 }
6033
6034 struct drm_connector_state *
6035 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6036 {
6037         struct dm_connector_state *state =
6038                 to_dm_connector_state(connector->state);
6039
6040         struct dm_connector_state *new_state =
6041                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6042
6043         if (!new_state)
6044                 return NULL;
6045
6046         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6047
6048         new_state->freesync_capable = state->freesync_capable;
6049         new_state->abm_level = state->abm_level;
6050         new_state->scaling = state->scaling;
6051         new_state->underscan_enable = state->underscan_enable;
6052         new_state->underscan_hborder = state->underscan_hborder;
6053         new_state->underscan_vborder = state->underscan_vborder;
6054         new_state->vcpi_slots = state->vcpi_slots;
6055         new_state->pbn = state->pbn;
6056         return &new_state->base;
6057 }
6058
6059 static int
6060 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6061 {
6062         struct amdgpu_dm_connector *amdgpu_dm_connector =
6063                 to_amdgpu_dm_connector(connector);
6064         int r;
6065
6066         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6067             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6068                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6069                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6070                 if (r)
6071                         return r;
6072         }
6073
6074 #if defined(CONFIG_DEBUG_FS)
6075         connector_debugfs_init(amdgpu_dm_connector);
6076 #endif
6077
6078         return 0;
6079 }
6080
6081 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6082         .reset = amdgpu_dm_connector_funcs_reset,
6083         .detect = amdgpu_dm_connector_detect,
6084         .fill_modes = drm_helper_probe_single_connector_modes,
6085         .destroy = amdgpu_dm_connector_destroy,
6086         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6087         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6088         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6089         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6090         .late_register = amdgpu_dm_connector_late_register,
6091         .early_unregister = amdgpu_dm_connector_unregister
6092 };
6093
6094 static int get_modes(struct drm_connector *connector)
6095 {
6096         return amdgpu_dm_connector_get_modes(connector);
6097 }
6098
6099 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6100 {
6101         struct dc_sink_init_data init_params = {
6102                         .link = aconnector->dc_link,
6103                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6104         };
6105         struct edid *edid;
6106
6107         if (!aconnector->base.edid_blob_ptr) {
6108                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6109                                 aconnector->base.name);
6110
6111                 aconnector->base.force = DRM_FORCE_OFF;
6112                 return;
6113         }
6114
6115         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6116
6117         aconnector->edid = edid;
6118
6119         aconnector->dc_em_sink = dc_link_add_remote_sink(
6120                 aconnector->dc_link,
6121                 (uint8_t *)edid,
6122                 (edid->extensions + 1) * EDID_LENGTH,
6123                 &init_params);
6124
6125         if (aconnector->base.force == DRM_FORCE_ON) {
6126                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6127                 aconnector->dc_link->local_sink :
6128                 aconnector->dc_em_sink;
6129                 dc_sink_retain(aconnector->dc_sink);
6130         }
6131 }
6132
6133 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6134 {
6135         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6136
6137         /*
6138          * In case of headless boot with force on for DP managed connector
6139          * Those settings have to be != 0 to get initial modeset
6140          */
6141         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6142                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6143                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6144         }
6145
6146         create_eml_sink(aconnector);
6147 }
6148
6149 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6150                                                 struct dc_stream_state *stream)
6151 {
6152         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6153         struct dc_plane_state *dc_plane_state = NULL;
6154         struct dc_state *dc_state = NULL;
6155
6156         if (!stream)
6157                 goto cleanup;
6158
6159         dc_plane_state = dc_create_plane_state(dc);
6160         if (!dc_plane_state)
6161                 goto cleanup;
6162
6163         dc_state = dc_create_state(dc);
6164         if (!dc_state)
6165                 goto cleanup;
6166
6167         /* populate stream to plane */
6168         dc_plane_state->src_rect.height  = stream->src.height;
6169         dc_plane_state->src_rect.width   = stream->src.width;
6170         dc_plane_state->dst_rect.height  = stream->src.height;
6171         dc_plane_state->dst_rect.width   = stream->src.width;
6172         dc_plane_state->clip_rect.height = stream->src.height;
6173         dc_plane_state->clip_rect.width  = stream->src.width;
6174         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6175         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6176         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6177         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6178         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6179         dc_plane_state->tiling_info.gfx9.swizzle =  DC_SW_UNKNOWN;
6180         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6181         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6182         dc_plane_state->rotation = ROTATION_ANGLE_0;
6183         dc_plane_state->is_tiling_rotated = false;
6184         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6185
6186         dc_result = dc_validate_stream(dc, stream);
6187         if (dc_result == DC_OK)
6188                 dc_result = dc_validate_plane(dc, dc_plane_state);
6189
6190         if (dc_result == DC_OK)
6191                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6192
6193         if (dc_result == DC_OK && !dc_add_plane_to_context(
6194                                                 dc,
6195                                                 stream,
6196                                                 dc_plane_state,
6197                                                 dc_state))
6198                 dc_result = DC_FAIL_ATTACH_SURFACES;
6199
6200         if (dc_result == DC_OK)
6201                 dc_result = dc_validate_global_state(dc, dc_state, true);
6202
6203 cleanup:
6204         if (dc_state)
6205                 dc_release_state(dc_state);
6206
6207         if (dc_plane_state)
6208                 dc_plane_state_release(dc_plane_state);
6209
6210         return dc_result;
6211 }
6212
6213 struct dc_stream_state *
6214 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6215                                 const struct drm_display_mode *drm_mode,
6216                                 const struct dm_connector_state *dm_state,
6217                                 const struct dc_stream_state *old_stream)
6218 {
6219         struct drm_connector *connector = &aconnector->base;
6220         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6221         struct dc_stream_state *stream;
6222         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6223         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6224         enum dc_status dc_result = DC_OK;
6225
6226         do {
6227                 stream = create_stream_for_sink(aconnector, drm_mode,
6228                                                 dm_state, old_stream,
6229                                                 requested_bpc);
6230                 if (stream == NULL) {
6231                         DRM_ERROR("Failed to create stream for sink!\n");
6232                         break;
6233                 }
6234
6235                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6236                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6237                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6238
6239                 if (dc_result == DC_OK)
6240                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6241
6242                 if (dc_result != DC_OK) {
6243                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6244                                       drm_mode->hdisplay,
6245                                       drm_mode->vdisplay,
6246                                       drm_mode->clock,
6247                                       dc_result,
6248                                       dc_status_to_str(dc_result));
6249
6250                         dc_stream_release(stream);
6251                         stream = NULL;
6252                         requested_bpc -= 2; /* lower bpc to retry validation */
6253                 }
6254
6255         } while (stream == NULL && requested_bpc >= 6);
6256
6257         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6258                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6259
6260                 aconnector->force_yuv420_output = true;
6261                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6262                                                 dm_state, old_stream);
6263                 aconnector->force_yuv420_output = false;
6264         }
6265
6266         return stream;
6267 }
6268
6269 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6270                                    struct drm_display_mode *mode)
6271 {
6272         int result = MODE_ERROR;
6273         struct dc_sink *dc_sink;
6274         /* TODO: Unhardcode stream count */
6275         struct dc_stream_state *stream;
6276         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6277
6278         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6279                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6280                 return result;
6281
6282         /*
6283          * Only run this the first time mode_valid is called to initilialize
6284          * EDID mgmt
6285          */
6286         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6287                 !aconnector->dc_em_sink)
6288                 handle_edid_mgmt(aconnector);
6289
6290         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6291
6292         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6293                                 aconnector->base.force != DRM_FORCE_ON) {
6294                 DRM_ERROR("dc_sink is NULL!\n");
6295                 goto fail;
6296         }
6297
6298         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6299         if (stream) {
6300                 dc_stream_release(stream);
6301                 result = MODE_OK;
6302         }
6303
6304 fail:
6305         /* TODO: error handling*/
6306         return result;
6307 }
6308
6309 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6310                                 struct dc_info_packet *out)
6311 {
6312         struct hdmi_drm_infoframe frame;
6313         unsigned char buf[30]; /* 26 + 4 */
6314         ssize_t len;
6315         int ret, i;
6316
6317         memset(out, 0, sizeof(*out));
6318
6319         if (!state->hdr_output_metadata)
6320                 return 0;
6321
6322         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6323         if (ret)
6324                 return ret;
6325
6326         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6327         if (len < 0)
6328                 return (int)len;
6329
6330         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6331         if (len != 30)
6332                 return -EINVAL;
6333
6334         /* Prepare the infopacket for DC. */
6335         switch (state->connector->connector_type) {
6336         case DRM_MODE_CONNECTOR_HDMIA:
6337                 out->hb0 = 0x87; /* type */
6338                 out->hb1 = 0x01; /* version */
6339                 out->hb2 = 0x1A; /* length */
6340                 out->sb[0] = buf[3]; /* checksum */
6341                 i = 1;
6342                 break;
6343
6344         case DRM_MODE_CONNECTOR_DisplayPort:
6345         case DRM_MODE_CONNECTOR_eDP:
6346                 out->hb0 = 0x00; /* sdp id, zero */
6347                 out->hb1 = 0x87; /* type */
6348                 out->hb2 = 0x1D; /* payload len - 1 */
6349                 out->hb3 = (0x13 << 2); /* sdp version */
6350                 out->sb[0] = 0x01; /* version */
6351                 out->sb[1] = 0x1A; /* length */
6352                 i = 2;
6353                 break;
6354
6355         default:
6356                 return -EINVAL;
6357         }
6358
6359         memcpy(&out->sb[i], &buf[4], 26);
6360         out->valid = true;
6361
6362         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6363                        sizeof(out->sb), false);
6364
6365         return 0;
6366 }
6367
6368 static int
6369 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6370                                  struct drm_atomic_state *state)
6371 {
6372         struct drm_connector_state *new_con_state =
6373                 drm_atomic_get_new_connector_state(state, conn);
6374         struct drm_connector_state *old_con_state =
6375                 drm_atomic_get_old_connector_state(state, conn);
6376         struct drm_crtc *crtc = new_con_state->crtc;
6377         struct drm_crtc_state *new_crtc_state;
6378         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6379         int ret;
6380
6381         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6382
6383         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6384                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6385                 if (ret < 0)
6386                         return ret;
6387         }
6388
6389         if (!crtc)
6390                 return 0;
6391
6392         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6393                 struct dc_info_packet hdr_infopacket;
6394
6395                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6396                 if (ret)
6397                         return ret;
6398
6399                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6400                 if (IS_ERR(new_crtc_state))
6401                         return PTR_ERR(new_crtc_state);
6402
6403                 /*
6404                  * DC considers the stream backends changed if the
6405                  * static metadata changes. Forcing the modeset also
6406                  * gives a simple way for userspace to switch from
6407                  * 8bpc to 10bpc when setting the metadata to enter
6408                  * or exit HDR.
6409                  *
6410                  * Changing the static metadata after it's been
6411                  * set is permissible, however. So only force a
6412                  * modeset if we're entering or exiting HDR.
6413                  */
6414                 new_crtc_state->mode_changed =
6415                         !old_con_state->hdr_output_metadata ||
6416                         !new_con_state->hdr_output_metadata;
6417         }
6418
6419         return 0;
6420 }
6421
6422 static const struct drm_connector_helper_funcs
6423 amdgpu_dm_connector_helper_funcs = {
6424         /*
6425          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6426          * modes will be filtered by drm_mode_validate_size(), and those modes
6427          * are missing after user start lightdm. So we need to renew modes list.
6428          * in get_modes call back, not just return the modes count
6429          */
6430         .get_modes = get_modes,
6431         .mode_valid = amdgpu_dm_connector_mode_valid,
6432         .atomic_check = amdgpu_dm_connector_atomic_check,
6433 };
6434
6435 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6436 {
6437
6438 }
6439
6440 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6441 {
6442         switch (display_color_depth) {
6443         case COLOR_DEPTH_666:
6444                 return 6;
6445         case COLOR_DEPTH_888:
6446                 return 8;
6447         case COLOR_DEPTH_101010:
6448                 return 10;
6449         case COLOR_DEPTH_121212:
6450                 return 12;
6451         case COLOR_DEPTH_141414:
6452                 return 14;
6453         case COLOR_DEPTH_161616:
6454                 return 16;
6455         default:
6456                 break;
6457         }
6458         return 0;
6459 }
6460
6461 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6462                                           struct drm_crtc_state *crtc_state,
6463                                           struct drm_connector_state *conn_state)
6464 {
6465         struct drm_atomic_state *state = crtc_state->state;
6466         struct drm_connector *connector = conn_state->connector;
6467         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6468         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6469         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6470         struct drm_dp_mst_topology_mgr *mst_mgr;
6471         struct drm_dp_mst_port *mst_port;
6472         struct drm_dp_mst_topology_state *mst_state;
6473         enum dc_color_depth color_depth;
6474         int clock, bpp = 0;
6475         bool is_y420 = false;
6476
6477         if (!aconnector->port || !aconnector->dc_sink)
6478                 return 0;
6479
6480         mst_port = aconnector->port;
6481         mst_mgr = &aconnector->mst_port->mst_mgr;
6482
6483         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6484                 return 0;
6485
6486         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6487         if (IS_ERR(mst_state))
6488                 return PTR_ERR(mst_state);
6489
6490         if (!mst_state->pbn_div)
6491                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
6492
6493         if (!state->duplicated) {
6494                 int max_bpc = conn_state->max_requested_bpc;
6495                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6496                           aconnector->force_yuv420_output;
6497                 color_depth = convert_color_depth_from_display_info(connector,
6498                                                                     is_y420,
6499                                                                     max_bpc);
6500                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6501                 clock = adjusted_mode->clock;
6502                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6503         }
6504
6505         dm_new_connector_state->vcpi_slots =
6506                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6507                                               dm_new_connector_state->pbn);
6508         if (dm_new_connector_state->vcpi_slots < 0) {
6509                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6510                 return dm_new_connector_state->vcpi_slots;
6511         }
6512         return 0;
6513 }
6514
6515 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6516         .disable = dm_encoder_helper_disable,
6517         .atomic_check = dm_encoder_helper_atomic_check
6518 };
6519
6520 #if defined(CONFIG_DRM_AMD_DC_DCN)
6521 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6522                                             struct dc_state *dc_state,
6523                                             struct dsc_mst_fairness_vars *vars)
6524 {
6525         struct dc_stream_state *stream = NULL;
6526         struct drm_connector *connector;
6527         struct drm_connector_state *new_con_state;
6528         struct amdgpu_dm_connector *aconnector;
6529         struct dm_connector_state *dm_conn_state;
6530         int i, j;
6531         int vcpi, pbn_div, pbn, slot_num = 0;
6532
6533         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6534
6535                 aconnector = to_amdgpu_dm_connector(connector);
6536
6537                 if (!aconnector->port)
6538                         continue;
6539
6540                 if (!new_con_state || !new_con_state->crtc)
6541                         continue;
6542
6543                 dm_conn_state = to_dm_connector_state(new_con_state);
6544
6545                 for (j = 0; j < dc_state->stream_count; j++) {
6546                         stream = dc_state->streams[j];
6547                         if (!stream)
6548                                 continue;
6549
6550                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6551                                 break;
6552
6553                         stream = NULL;
6554                 }
6555
6556                 if (!stream)
6557                         continue;
6558
6559                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6560                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6561                 for (j = 0; j < dc_state->stream_count; j++) {
6562                         if (vars[j].aconnector == aconnector) {
6563                                 pbn = vars[j].pbn;
6564                                 break;
6565                         }
6566                 }
6567
6568                 if (j == dc_state->stream_count)
6569                         continue;
6570
6571                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6572
6573                 if (stream->timing.flags.DSC != 1) {
6574                         dm_conn_state->pbn = pbn;
6575                         dm_conn_state->vcpi_slots = slot_num;
6576
6577                         drm_dp_mst_atomic_enable_dsc(state, aconnector->port, dm_conn_state->pbn,
6578                                                      false);
6579                         continue;
6580                 }
6581
6582                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
6583                 if (vcpi < 0)
6584                         return vcpi;
6585
6586                 dm_conn_state->pbn = pbn;
6587                 dm_conn_state->vcpi_slots = vcpi;
6588         }
6589         return 0;
6590 }
6591 #endif
6592
6593 static int to_drm_connector_type(enum signal_type st)
6594 {
6595         switch (st) {
6596         case SIGNAL_TYPE_HDMI_TYPE_A:
6597                 return DRM_MODE_CONNECTOR_HDMIA;
6598         case SIGNAL_TYPE_EDP:
6599                 return DRM_MODE_CONNECTOR_eDP;
6600         case SIGNAL_TYPE_LVDS:
6601                 return DRM_MODE_CONNECTOR_LVDS;
6602         case SIGNAL_TYPE_RGB:
6603                 return DRM_MODE_CONNECTOR_VGA;
6604         case SIGNAL_TYPE_DISPLAY_PORT:
6605         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6606                 return DRM_MODE_CONNECTOR_DisplayPort;
6607         case SIGNAL_TYPE_DVI_DUAL_LINK:
6608         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6609                 return DRM_MODE_CONNECTOR_DVID;
6610         case SIGNAL_TYPE_VIRTUAL:
6611                 return DRM_MODE_CONNECTOR_VIRTUAL;
6612
6613         default:
6614                 return DRM_MODE_CONNECTOR_Unknown;
6615         }
6616 }
6617
6618 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6619 {
6620         struct drm_encoder *encoder;
6621
6622         /* There is only one encoder per connector */
6623         drm_connector_for_each_possible_encoder(connector, encoder)
6624                 return encoder;
6625
6626         return NULL;
6627 }
6628
6629 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6630 {
6631         struct drm_encoder *encoder;
6632         struct amdgpu_encoder *amdgpu_encoder;
6633
6634         encoder = amdgpu_dm_connector_to_encoder(connector);
6635
6636         if (encoder == NULL)
6637                 return;
6638
6639         amdgpu_encoder = to_amdgpu_encoder(encoder);
6640
6641         amdgpu_encoder->native_mode.clock = 0;
6642
6643         if (!list_empty(&connector->probed_modes)) {
6644                 struct drm_display_mode *preferred_mode = NULL;
6645
6646                 list_for_each_entry(preferred_mode,
6647                                     &connector->probed_modes,
6648                                     head) {
6649                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6650                                 amdgpu_encoder->native_mode = *preferred_mode;
6651
6652                         break;
6653                 }
6654
6655         }
6656 }
6657
6658 static struct drm_display_mode *
6659 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6660                              char *name,
6661                              int hdisplay, int vdisplay)
6662 {
6663         struct drm_device *dev = encoder->dev;
6664         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6665         struct drm_display_mode *mode = NULL;
6666         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6667
6668         mode = drm_mode_duplicate(dev, native_mode);
6669
6670         if (mode == NULL)
6671                 return NULL;
6672
6673         mode->hdisplay = hdisplay;
6674         mode->vdisplay = vdisplay;
6675         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6676         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6677
6678         return mode;
6679
6680 }
6681
6682 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6683                                                  struct drm_connector *connector)
6684 {
6685         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6686         struct drm_display_mode *mode = NULL;
6687         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6688         struct amdgpu_dm_connector *amdgpu_dm_connector =
6689                                 to_amdgpu_dm_connector(connector);
6690         int i;
6691         int n;
6692         struct mode_size {
6693                 char name[DRM_DISPLAY_MODE_LEN];
6694                 int w;
6695                 int h;
6696         } common_modes[] = {
6697                 {  "640x480",  640,  480},
6698                 {  "800x600",  800,  600},
6699                 { "1024x768", 1024,  768},
6700                 { "1280x720", 1280,  720},
6701                 { "1280x800", 1280,  800},
6702                 {"1280x1024", 1280, 1024},
6703                 { "1440x900", 1440,  900},
6704                 {"1680x1050", 1680, 1050},
6705                 {"1600x1200", 1600, 1200},
6706                 {"1920x1080", 1920, 1080},
6707                 {"1920x1200", 1920, 1200}
6708         };
6709
6710         n = ARRAY_SIZE(common_modes);
6711
6712         for (i = 0; i < n; i++) {
6713                 struct drm_display_mode *curmode = NULL;
6714                 bool mode_existed = false;
6715
6716                 if (common_modes[i].w > native_mode->hdisplay ||
6717                     common_modes[i].h > native_mode->vdisplay ||
6718                    (common_modes[i].w == native_mode->hdisplay &&
6719                     common_modes[i].h == native_mode->vdisplay))
6720                         continue;
6721
6722                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6723                         if (common_modes[i].w == curmode->hdisplay &&
6724                             common_modes[i].h == curmode->vdisplay) {
6725                                 mode_existed = true;
6726                                 break;
6727                         }
6728                 }
6729
6730                 if (mode_existed)
6731                         continue;
6732
6733                 mode = amdgpu_dm_create_common_mode(encoder,
6734                                 common_modes[i].name, common_modes[i].w,
6735                                 common_modes[i].h);
6736                 if (!mode)
6737                         continue;
6738
6739                 drm_mode_probed_add(connector, mode);
6740                 amdgpu_dm_connector->num_modes++;
6741         }
6742 }
6743
6744 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6745 {
6746         struct drm_encoder *encoder;
6747         struct amdgpu_encoder *amdgpu_encoder;
6748         const struct drm_display_mode *native_mode;
6749
6750         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6751             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6752                 return;
6753
6754         mutex_lock(&connector->dev->mode_config.mutex);
6755         amdgpu_dm_connector_get_modes(connector);
6756         mutex_unlock(&connector->dev->mode_config.mutex);
6757
6758         encoder = amdgpu_dm_connector_to_encoder(connector);
6759         if (!encoder)
6760                 return;
6761
6762         amdgpu_encoder = to_amdgpu_encoder(encoder);
6763
6764         native_mode = &amdgpu_encoder->native_mode;
6765         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6766                 return;
6767
6768         drm_connector_set_panel_orientation_with_quirk(connector,
6769                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6770                                                        native_mode->hdisplay,
6771                                                        native_mode->vdisplay);
6772 }
6773
6774 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6775                                               struct edid *edid)
6776 {
6777         struct amdgpu_dm_connector *amdgpu_dm_connector =
6778                         to_amdgpu_dm_connector(connector);
6779
6780         if (edid) {
6781                 /* empty probed_modes */
6782                 INIT_LIST_HEAD(&connector->probed_modes);
6783                 amdgpu_dm_connector->num_modes =
6784                                 drm_add_edid_modes(connector, edid);
6785
6786                 /* sorting the probed modes before calling function
6787                  * amdgpu_dm_get_native_mode() since EDID can have
6788                  * more than one preferred mode. The modes that are
6789                  * later in the probed mode list could be of higher
6790                  * and preferred resolution. For example, 3840x2160
6791                  * resolution in base EDID preferred timing and 4096x2160
6792                  * preferred resolution in DID extension block later.
6793                  */
6794                 drm_mode_sort(&connector->probed_modes);
6795                 amdgpu_dm_get_native_mode(connector);
6796
6797                 /* Freesync capabilities are reset by calling
6798                  * drm_add_edid_modes() and need to be
6799                  * restored here.
6800                  */
6801                 amdgpu_dm_update_freesync_caps(connector, edid);
6802         } else {
6803                 amdgpu_dm_connector->num_modes = 0;
6804         }
6805 }
6806
6807 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6808                               struct drm_display_mode *mode)
6809 {
6810         struct drm_display_mode *m;
6811
6812         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6813                 if (drm_mode_equal(m, mode))
6814                         return true;
6815         }
6816
6817         return false;
6818 }
6819
6820 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6821 {
6822         const struct drm_display_mode *m;
6823         struct drm_display_mode *new_mode;
6824         uint i;
6825         uint32_t new_modes_count = 0;
6826
6827         /* Standard FPS values
6828          *
6829          * 23.976       - TV/NTSC
6830          * 24           - Cinema
6831          * 25           - TV/PAL
6832          * 29.97        - TV/NTSC
6833          * 30           - TV/NTSC
6834          * 48           - Cinema HFR
6835          * 50           - TV/PAL
6836          * 60           - Commonly used
6837          * 48,72,96,120 - Multiples of 24
6838          */
6839         static const uint32_t common_rates[] = {
6840                 23976, 24000, 25000, 29970, 30000,
6841                 48000, 50000, 60000, 72000, 96000, 120000
6842         };
6843
6844         /*
6845          * Find mode with highest refresh rate with the same resolution
6846          * as the preferred mode. Some monitors report a preferred mode
6847          * with lower resolution than the highest refresh rate supported.
6848          */
6849
6850         m = get_highest_refresh_rate_mode(aconnector, true);
6851         if (!m)
6852                 return 0;
6853
6854         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
6855                 uint64_t target_vtotal, target_vtotal_diff;
6856                 uint64_t num, den;
6857
6858                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
6859                         continue;
6860
6861                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
6862                     common_rates[i] > aconnector->max_vfreq * 1000)
6863                         continue;
6864
6865                 num = (unsigned long long)m->clock * 1000 * 1000;
6866                 den = common_rates[i] * (unsigned long long)m->htotal;
6867                 target_vtotal = div_u64(num, den);
6868                 target_vtotal_diff = target_vtotal - m->vtotal;
6869
6870                 /* Check for illegal modes */
6871                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
6872                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
6873                     m->vtotal + target_vtotal_diff < m->vsync_end)
6874                         continue;
6875
6876                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
6877                 if (!new_mode)
6878                         goto out;
6879
6880                 new_mode->vtotal += (u16)target_vtotal_diff;
6881                 new_mode->vsync_start += (u16)target_vtotal_diff;
6882                 new_mode->vsync_end += (u16)target_vtotal_diff;
6883                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6884                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
6885
6886                 if (!is_duplicate_mode(aconnector, new_mode)) {
6887                         drm_mode_probed_add(&aconnector->base, new_mode);
6888                         new_modes_count += 1;
6889                 } else
6890                         drm_mode_destroy(aconnector->base.dev, new_mode);
6891         }
6892  out:
6893         return new_modes_count;
6894 }
6895
6896 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
6897                                                    struct edid *edid)
6898 {
6899         struct amdgpu_dm_connector *amdgpu_dm_connector =
6900                 to_amdgpu_dm_connector(connector);
6901
6902         if (!edid)
6903                 return;
6904
6905         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
6906                 amdgpu_dm_connector->num_modes +=
6907                         add_fs_modes(amdgpu_dm_connector);
6908 }
6909
6910 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6911 {
6912         struct amdgpu_dm_connector *amdgpu_dm_connector =
6913                         to_amdgpu_dm_connector(connector);
6914         struct drm_encoder *encoder;
6915         struct edid *edid = amdgpu_dm_connector->edid;
6916
6917         encoder = amdgpu_dm_connector_to_encoder(connector);
6918
6919         if (!drm_edid_is_valid(edid)) {
6920                 amdgpu_dm_connector->num_modes =
6921                                 drm_add_modes_noedid(connector, 640, 480);
6922         } else {
6923                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
6924                 amdgpu_dm_connector_add_common_modes(encoder, connector);
6925                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
6926         }
6927         amdgpu_dm_fbc_init(connector);
6928
6929         return amdgpu_dm_connector->num_modes;
6930 }
6931
6932 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
6933                                      struct amdgpu_dm_connector *aconnector,
6934                                      int connector_type,
6935                                      struct dc_link *link,
6936                                      int link_index)
6937 {
6938         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
6939
6940         /*
6941          * Some of the properties below require access to state, like bpc.
6942          * Allocate some default initial connector state with our reset helper.
6943          */
6944         if (aconnector->base.funcs->reset)
6945                 aconnector->base.funcs->reset(&aconnector->base);
6946
6947         aconnector->connector_id = link_index;
6948         aconnector->dc_link = link;
6949         aconnector->base.interlace_allowed = false;
6950         aconnector->base.doublescan_allowed = false;
6951         aconnector->base.stereo_allowed = false;
6952         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
6953         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6954         aconnector->audio_inst = -1;
6955         mutex_init(&aconnector->hpd_lock);
6956
6957         /*
6958          * configure support HPD hot plug connector_>polled default value is 0
6959          * which means HPD hot plug not supported
6960          */
6961         switch (connector_type) {
6962         case DRM_MODE_CONNECTOR_HDMIA:
6963                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6964                 aconnector->base.ycbcr_420_allowed =
6965                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
6966                 break;
6967         case DRM_MODE_CONNECTOR_DisplayPort:
6968                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6969                 link->link_enc = link_enc_cfg_get_link_enc(link);
6970                 ASSERT(link->link_enc);
6971                 if (link->link_enc)
6972                         aconnector->base.ycbcr_420_allowed =
6973                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
6974                 break;
6975         case DRM_MODE_CONNECTOR_DVID:
6976                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6977                 break;
6978         default:
6979                 break;
6980         }
6981
6982         drm_object_attach_property(&aconnector->base.base,
6983                                 dm->ddev->mode_config.scaling_mode_property,
6984                                 DRM_MODE_SCALE_NONE);
6985
6986         drm_object_attach_property(&aconnector->base.base,
6987                                 adev->mode_info.underscan_property,
6988                                 UNDERSCAN_OFF);
6989         drm_object_attach_property(&aconnector->base.base,
6990                                 adev->mode_info.underscan_hborder_property,
6991                                 0);
6992         drm_object_attach_property(&aconnector->base.base,
6993                                 adev->mode_info.underscan_vborder_property,
6994                                 0);
6995
6996         if (!aconnector->mst_port)
6997                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
6998
6999         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7000         aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7001         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7002
7003         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7004             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7005                 drm_object_attach_property(&aconnector->base.base,
7006                                 adev->mode_info.abm_level_property, 0);
7007         }
7008
7009         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7010             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7011             connector_type == DRM_MODE_CONNECTOR_eDP) {
7012                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7013
7014                 if (!aconnector->mst_port)
7015                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7016
7017 #ifdef CONFIG_DRM_AMD_DC_HDCP
7018                 if (adev->dm.hdcp_workqueue)
7019                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7020 #endif
7021         }
7022 }
7023
7024 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7025                               struct i2c_msg *msgs, int num)
7026 {
7027         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7028         struct ddc_service *ddc_service = i2c->ddc_service;
7029         struct i2c_command cmd;
7030         int i;
7031         int result = -EIO;
7032
7033         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7034
7035         if (!cmd.payloads)
7036                 return result;
7037
7038         cmd.number_of_payloads = num;
7039         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7040         cmd.speed = 100;
7041
7042         for (i = 0; i < num; i++) {
7043                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7044                 cmd.payloads[i].address = msgs[i].addr;
7045                 cmd.payloads[i].length = msgs[i].len;
7046                 cmd.payloads[i].data = msgs[i].buf;
7047         }
7048
7049         if (dc_submit_i2c(
7050                         ddc_service->ctx->dc,
7051                         ddc_service->link->link_index,
7052                         &cmd))
7053                 result = num;
7054
7055         kfree(cmd.payloads);
7056         return result;
7057 }
7058
7059 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7060 {
7061         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7062 }
7063
7064 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7065         .master_xfer = amdgpu_dm_i2c_xfer,
7066         .functionality = amdgpu_dm_i2c_func,
7067 };
7068
7069 static struct amdgpu_i2c_adapter *
7070 create_i2c(struct ddc_service *ddc_service,
7071            int link_index,
7072            int *res)
7073 {
7074         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7075         struct amdgpu_i2c_adapter *i2c;
7076
7077         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7078         if (!i2c)
7079                 return NULL;
7080         i2c->base.owner = THIS_MODULE;
7081         i2c->base.class = I2C_CLASS_DDC;
7082         i2c->base.dev.parent = &adev->pdev->dev;
7083         i2c->base.algo = &amdgpu_dm_i2c_algo;
7084         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7085         i2c_set_adapdata(&i2c->base, i2c);
7086         i2c->ddc_service = ddc_service;
7087
7088         return i2c;
7089 }
7090
7091
7092 /*
7093  * Note: this function assumes that dc_link_detect() was called for the
7094  * dc_link which will be represented by this aconnector.
7095  */
7096 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7097                                     struct amdgpu_dm_connector *aconnector,
7098                                     uint32_t link_index,
7099                                     struct amdgpu_encoder *aencoder)
7100 {
7101         int res = 0;
7102         int connector_type;
7103         struct dc *dc = dm->dc;
7104         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7105         struct amdgpu_i2c_adapter *i2c;
7106
7107         link->priv = aconnector;
7108
7109         DRM_DEBUG_DRIVER("%s()\n", __func__);
7110
7111         i2c = create_i2c(link->ddc, link->link_index, &res);
7112         if (!i2c) {
7113                 DRM_ERROR("Failed to create i2c adapter data\n");
7114                 return -ENOMEM;
7115         }
7116
7117         aconnector->i2c = i2c;
7118         res = i2c_add_adapter(&i2c->base);
7119
7120         if (res) {
7121                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7122                 goto out_free;
7123         }
7124
7125         connector_type = to_drm_connector_type(link->connector_signal);
7126
7127         res = drm_connector_init_with_ddc(
7128                         dm->ddev,
7129                         &aconnector->base,
7130                         &amdgpu_dm_connector_funcs,
7131                         connector_type,
7132                         &i2c->base);
7133
7134         if (res) {
7135                 DRM_ERROR("connector_init failed\n");
7136                 aconnector->connector_id = -1;
7137                 goto out_free;
7138         }
7139
7140         drm_connector_helper_add(
7141                         &aconnector->base,
7142                         &amdgpu_dm_connector_helper_funcs);
7143
7144         amdgpu_dm_connector_init_helper(
7145                 dm,
7146                 aconnector,
7147                 connector_type,
7148                 link,
7149                 link_index);
7150
7151         drm_connector_attach_encoder(
7152                 &aconnector->base, &aencoder->base);
7153
7154         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7155                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7156                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7157
7158 out_free:
7159         if (res) {
7160                 kfree(i2c);
7161                 aconnector->i2c = NULL;
7162         }
7163         return res;
7164 }
7165
7166 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7167 {
7168         switch (adev->mode_info.num_crtc) {
7169         case 1:
7170                 return 0x1;
7171         case 2:
7172                 return 0x3;
7173         case 3:
7174                 return 0x7;
7175         case 4:
7176                 return 0xf;
7177         case 5:
7178                 return 0x1f;
7179         case 6:
7180         default:
7181                 return 0x3f;
7182         }
7183 }
7184
7185 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7186                                   struct amdgpu_encoder *aencoder,
7187                                   uint32_t link_index)
7188 {
7189         struct amdgpu_device *adev = drm_to_adev(dev);
7190
7191         int res = drm_encoder_init(dev,
7192                                    &aencoder->base,
7193                                    &amdgpu_dm_encoder_funcs,
7194                                    DRM_MODE_ENCODER_TMDS,
7195                                    NULL);
7196
7197         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7198
7199         if (!res)
7200                 aencoder->encoder_id = link_index;
7201         else
7202                 aencoder->encoder_id = -1;
7203
7204         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7205
7206         return res;
7207 }
7208
7209 static void manage_dm_interrupts(struct amdgpu_device *adev,
7210                                  struct amdgpu_crtc *acrtc,
7211                                  bool enable)
7212 {
7213         /*
7214          * We have no guarantee that the frontend index maps to the same
7215          * backend index - some even map to more than one.
7216          *
7217          * TODO: Use a different interrupt or check DC itself for the mapping.
7218          */
7219         int irq_type =
7220                 amdgpu_display_crtc_idx_to_irq_type(
7221                         adev,
7222                         acrtc->crtc_id);
7223
7224         if (enable) {
7225                 drm_crtc_vblank_on(&acrtc->base);
7226                 amdgpu_irq_get(
7227                         adev,
7228                         &adev->pageflip_irq,
7229                         irq_type);
7230 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7231                 amdgpu_irq_get(
7232                         adev,
7233                         &adev->vline0_irq,
7234                         irq_type);
7235 #endif
7236         } else {
7237 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7238                 amdgpu_irq_put(
7239                         adev,
7240                         &adev->vline0_irq,
7241                         irq_type);
7242 #endif
7243                 amdgpu_irq_put(
7244                         adev,
7245                         &adev->pageflip_irq,
7246                         irq_type);
7247                 drm_crtc_vblank_off(&acrtc->base);
7248         }
7249 }
7250
7251 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7252                                       struct amdgpu_crtc *acrtc)
7253 {
7254         int irq_type =
7255                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7256
7257         /**
7258          * This reads the current state for the IRQ and force reapplies
7259          * the setting to hardware.
7260          */
7261         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7262 }
7263
7264 static bool
7265 is_scaling_state_different(const struct dm_connector_state *dm_state,
7266                            const struct dm_connector_state *old_dm_state)
7267 {
7268         if (dm_state->scaling != old_dm_state->scaling)
7269                 return true;
7270         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7271                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7272                         return true;
7273         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7274                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7275                         return true;
7276         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7277                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7278                 return true;
7279         return false;
7280 }
7281
7282 #ifdef CONFIG_DRM_AMD_DC_HDCP
7283 static bool is_content_protection_different(struct drm_connector_state *state,
7284                                             const struct drm_connector_state *old_state,
7285                                             const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7286 {
7287         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7288         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7289
7290         /* Handle: Type0/1 change */
7291         if (old_state->hdcp_content_type != state->hdcp_content_type &&
7292             state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7293                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7294                 return true;
7295         }
7296
7297         /* CP is being re enabled, ignore this
7298          *
7299          * Handles:     ENABLED -> DESIRED
7300          */
7301         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7302             state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7303                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7304                 return false;
7305         }
7306
7307         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7308          *
7309          * Handles:     UNDESIRED -> ENABLED
7310          */
7311         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7312             state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7313                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7314
7315         /* Stream removed and re-enabled
7316          *
7317          * Can sometimes overlap with the HPD case,
7318          * thus set update_hdcp to false to avoid
7319          * setting HDCP multiple times.
7320          *
7321          * Handles:     DESIRED -> DESIRED (Special case)
7322          */
7323         if (!(old_state->crtc && old_state->crtc->enabled) &&
7324                 state->crtc && state->crtc->enabled &&
7325                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7326                 dm_con_state->update_hdcp = false;
7327                 return true;
7328         }
7329
7330         /* Hot-plug, headless s3, dpms
7331          *
7332          * Only start HDCP if the display is connected/enabled.
7333          * update_hdcp flag will be set to false until the next
7334          * HPD comes in.
7335          *
7336          * Handles:     DESIRED -> DESIRED (Special case)
7337          */
7338         if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7339             connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7340                 dm_con_state->update_hdcp = false;
7341                 return true;
7342         }
7343
7344         /*
7345          * Handles:     UNDESIRED -> UNDESIRED
7346          *              DESIRED -> DESIRED
7347          *              ENABLED -> ENABLED
7348          */
7349         if (old_state->content_protection == state->content_protection)
7350                 return false;
7351
7352         /*
7353          * Handles:     UNDESIRED -> DESIRED
7354          *              DESIRED -> UNDESIRED
7355          *              ENABLED -> UNDESIRED
7356          */
7357         if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7358                 return true;
7359
7360         /*
7361          * Handles:     DESIRED -> ENABLED
7362          */
7363         return false;
7364 }
7365
7366 #endif
7367 static void remove_stream(struct amdgpu_device *adev,
7368                           struct amdgpu_crtc *acrtc,
7369                           struct dc_stream_state *stream)
7370 {
7371         /* this is the update mode case */
7372
7373         acrtc->otg_inst = -1;
7374         acrtc->enabled = false;
7375 }
7376
7377 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7378 {
7379
7380         assert_spin_locked(&acrtc->base.dev->event_lock);
7381         WARN_ON(acrtc->event);
7382
7383         acrtc->event = acrtc->base.state->event;
7384
7385         /* Set the flip status */
7386         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7387
7388         /* Mark this event as consumed */
7389         acrtc->base.state->event = NULL;
7390
7391         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7392                      acrtc->crtc_id);
7393 }
7394
7395 static void update_freesync_state_on_stream(
7396         struct amdgpu_display_manager *dm,
7397         struct dm_crtc_state *new_crtc_state,
7398         struct dc_stream_state *new_stream,
7399         struct dc_plane_state *surface,
7400         u32 flip_timestamp_in_us)
7401 {
7402         struct mod_vrr_params vrr_params;
7403         struct dc_info_packet vrr_infopacket = {0};
7404         struct amdgpu_device *adev = dm->adev;
7405         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7406         unsigned long flags;
7407         bool pack_sdp_v1_3 = false;
7408
7409         if (!new_stream)
7410                 return;
7411
7412         /*
7413          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7414          * For now it's sufficient to just guard against these conditions.
7415          */
7416
7417         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7418                 return;
7419
7420         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7421         vrr_params = acrtc->dm_irq_params.vrr_params;
7422
7423         if (surface) {
7424                 mod_freesync_handle_preflip(
7425                         dm->freesync_module,
7426                         surface,
7427                         new_stream,
7428                         flip_timestamp_in_us,
7429                         &vrr_params);
7430
7431                 if (adev->family < AMDGPU_FAMILY_AI &&
7432                     amdgpu_dm_vrr_active(new_crtc_state)) {
7433                         mod_freesync_handle_v_update(dm->freesync_module,
7434                                                      new_stream, &vrr_params);
7435
7436                         /* Need to call this before the frame ends. */
7437                         dc_stream_adjust_vmin_vmax(dm->dc,
7438                                                    new_crtc_state->stream,
7439                                                    &vrr_params.adjust);
7440                 }
7441         }
7442
7443         mod_freesync_build_vrr_infopacket(
7444                 dm->freesync_module,
7445                 new_stream,
7446                 &vrr_params,
7447                 PACKET_TYPE_VRR,
7448                 TRANSFER_FUNC_UNKNOWN,
7449                 &vrr_infopacket,
7450                 pack_sdp_v1_3);
7451
7452         new_crtc_state->freesync_vrr_info_changed |=
7453                 (memcmp(&new_crtc_state->vrr_infopacket,
7454                         &vrr_infopacket,
7455                         sizeof(vrr_infopacket)) != 0);
7456
7457         acrtc->dm_irq_params.vrr_params = vrr_params;
7458         new_crtc_state->vrr_infopacket = vrr_infopacket;
7459
7460         new_stream->vrr_infopacket = vrr_infopacket;
7461
7462         if (new_crtc_state->freesync_vrr_info_changed)
7463                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7464                               new_crtc_state->base.crtc->base.id,
7465                               (int)new_crtc_state->base.vrr_enabled,
7466                               (int)vrr_params.state);
7467
7468         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7469 }
7470
7471 static void update_stream_irq_parameters(
7472         struct amdgpu_display_manager *dm,
7473         struct dm_crtc_state *new_crtc_state)
7474 {
7475         struct dc_stream_state *new_stream = new_crtc_state->stream;
7476         struct mod_vrr_params vrr_params;
7477         struct mod_freesync_config config = new_crtc_state->freesync_config;
7478         struct amdgpu_device *adev = dm->adev;
7479         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7480         unsigned long flags;
7481
7482         if (!new_stream)
7483                 return;
7484
7485         /*
7486          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7487          * For now it's sufficient to just guard against these conditions.
7488          */
7489         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7490                 return;
7491
7492         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7493         vrr_params = acrtc->dm_irq_params.vrr_params;
7494
7495         if (new_crtc_state->vrr_supported &&
7496             config.min_refresh_in_uhz &&
7497             config.max_refresh_in_uhz) {
7498                 /*
7499                  * if freesync compatible mode was set, config.state will be set
7500                  * in atomic check
7501                  */
7502                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7503                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7504                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7505                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7506                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7507                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7508                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7509                 } else {
7510                         config.state = new_crtc_state->base.vrr_enabled ?
7511                                                      VRR_STATE_ACTIVE_VARIABLE :
7512                                                      VRR_STATE_INACTIVE;
7513                 }
7514         } else {
7515                 config.state = VRR_STATE_UNSUPPORTED;
7516         }
7517
7518         mod_freesync_build_vrr_params(dm->freesync_module,
7519                                       new_stream,
7520                                       &config, &vrr_params);
7521
7522         new_crtc_state->freesync_config = config;
7523         /* Copy state for access from DM IRQ handler */
7524         acrtc->dm_irq_params.freesync_config = config;
7525         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7526         acrtc->dm_irq_params.vrr_params = vrr_params;
7527         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7528 }
7529
7530 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7531                                             struct dm_crtc_state *new_state)
7532 {
7533         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7534         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7535
7536         if (!old_vrr_active && new_vrr_active) {
7537                 /* Transition VRR inactive -> active:
7538                  * While VRR is active, we must not disable vblank irq, as a
7539                  * reenable after disable would compute bogus vblank/pflip
7540                  * timestamps if it likely happened inside display front-porch.
7541                  *
7542                  * We also need vupdate irq for the actual core vblank handling
7543                  * at end of vblank.
7544                  */
7545                 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
7546                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7547                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7548                                  __func__, new_state->base.crtc->base.id);
7549         } else if (old_vrr_active && !new_vrr_active) {
7550                 /* Transition VRR active -> inactive:
7551                  * Allow vblank irq disable again for fixed refresh rate.
7552                  */
7553                 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
7554                 drm_crtc_vblank_put(new_state->base.crtc);
7555                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7556                                  __func__, new_state->base.crtc->base.id);
7557         }
7558 }
7559
7560 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7561 {
7562         struct drm_plane *plane;
7563         struct drm_plane_state *old_plane_state;
7564         int i;
7565
7566         /*
7567          * TODO: Make this per-stream so we don't issue redundant updates for
7568          * commits with multiple streams.
7569          */
7570         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7571                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7572                         handle_cursor_update(plane, old_plane_state);
7573 }
7574
7575 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7576                                     struct dc_state *dc_state,
7577                                     struct drm_device *dev,
7578                                     struct amdgpu_display_manager *dm,
7579                                     struct drm_crtc *pcrtc,
7580                                     bool wait_for_vblank)
7581 {
7582         uint32_t i;
7583         uint64_t timestamp_ns;
7584         struct drm_plane *plane;
7585         struct drm_plane_state *old_plane_state, *new_plane_state;
7586         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7587         struct drm_crtc_state *new_pcrtc_state =
7588                         drm_atomic_get_new_crtc_state(state, pcrtc);
7589         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7590         struct dm_crtc_state *dm_old_crtc_state =
7591                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7592         int planes_count = 0, vpos, hpos;
7593         unsigned long flags;
7594         uint32_t target_vblank, last_flip_vblank;
7595         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7596         bool cursor_update = false;
7597         bool pflip_present = false;
7598         struct {
7599                 struct dc_surface_update surface_updates[MAX_SURFACES];
7600                 struct dc_plane_info plane_infos[MAX_SURFACES];
7601                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7602                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7603                 struct dc_stream_update stream_update;
7604         } *bundle;
7605
7606         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7607
7608         if (!bundle) {
7609                 dm_error("Failed to allocate update bundle\n");
7610                 goto cleanup;
7611         }
7612
7613         /*
7614          * Disable the cursor first if we're disabling all the planes.
7615          * It'll remain on the screen after the planes are re-enabled
7616          * if we don't.
7617          */
7618         if (acrtc_state->active_planes == 0)
7619                 amdgpu_dm_commit_cursors(state);
7620
7621         /* update planes when needed */
7622         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7623                 struct drm_crtc *crtc = new_plane_state->crtc;
7624                 struct drm_crtc_state *new_crtc_state;
7625                 struct drm_framebuffer *fb = new_plane_state->fb;
7626                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7627                 bool plane_needs_flip;
7628                 struct dc_plane_state *dc_plane;
7629                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7630
7631                 /* Cursor plane is handled after stream updates */
7632                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7633                         if ((fb && crtc == pcrtc) ||
7634                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7635                                 cursor_update = true;
7636
7637                         continue;
7638                 }
7639
7640                 if (!fb || !crtc || pcrtc != crtc)
7641                         continue;
7642
7643                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7644                 if (!new_crtc_state->active)
7645                         continue;
7646
7647                 dc_plane = dm_new_plane_state->dc_state;
7648
7649                 bundle->surface_updates[planes_count].surface = dc_plane;
7650                 if (new_pcrtc_state->color_mgmt_changed) {
7651                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7652                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7653                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7654                 }
7655
7656                 fill_dc_scaling_info(dm->adev, new_plane_state,
7657                                      &bundle->scaling_infos[planes_count]);
7658
7659                 bundle->surface_updates[planes_count].scaling_info =
7660                         &bundle->scaling_infos[planes_count];
7661
7662                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7663
7664                 pflip_present = pflip_present || plane_needs_flip;
7665
7666                 if (!plane_needs_flip) {
7667                         planes_count += 1;
7668                         continue;
7669                 }
7670
7671                 fill_dc_plane_info_and_addr(
7672                         dm->adev, new_plane_state,
7673                         afb->tiling_flags,
7674                         &bundle->plane_infos[planes_count],
7675                         &bundle->flip_addrs[planes_count].address,
7676                         afb->tmz_surface, false);
7677
7678                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
7679                                  new_plane_state->plane->index,
7680                                  bundle->plane_infos[planes_count].dcc.enable);
7681
7682                 bundle->surface_updates[planes_count].plane_info =
7683                         &bundle->plane_infos[planes_count];
7684
7685                 fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
7686                                     new_crtc_state,
7687                                     &bundle->flip_addrs[planes_count]);
7688
7689                 /*
7690                  * Only allow immediate flips for fast updates that don't
7691                  * change FB pitch, DCC state, rotation or mirroing.
7692                  */
7693                 bundle->flip_addrs[planes_count].flip_immediate =
7694                         crtc->state->async_flip &&
7695                         acrtc_state->update_type == UPDATE_TYPE_FAST;
7696
7697                 timestamp_ns = ktime_get_ns();
7698                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7699                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7700                 bundle->surface_updates[planes_count].surface = dc_plane;
7701
7702                 if (!bundle->surface_updates[planes_count].surface) {
7703                         DRM_ERROR("No surface for CRTC: id=%d\n",
7704                                         acrtc_attach->crtc_id);
7705                         continue;
7706                 }
7707
7708                 if (plane == pcrtc->primary)
7709                         update_freesync_state_on_stream(
7710                                 dm,
7711                                 acrtc_state,
7712                                 acrtc_state->stream,
7713                                 dc_plane,
7714                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7715
7716                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
7717                                  __func__,
7718                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7719                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7720
7721                 planes_count += 1;
7722
7723         }
7724
7725         if (pflip_present) {
7726                 if (!vrr_active) {
7727                         /* Use old throttling in non-vrr fixed refresh rate mode
7728                          * to keep flip scheduling based on target vblank counts
7729                          * working in a backwards compatible way, e.g., for
7730                          * clients using the GLX_OML_sync_control extension or
7731                          * DRI3/Present extension with defined target_msc.
7732                          */
7733                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7734                 }
7735                 else {
7736                         /* For variable refresh rate mode only:
7737                          * Get vblank of last completed flip to avoid > 1 vrr
7738                          * flips per video frame by use of throttling, but allow
7739                          * flip programming anywhere in the possibly large
7740                          * variable vrr vblank interval for fine-grained flip
7741                          * timing control and more opportunity to avoid stutter
7742                          * on late submission of flips.
7743                          */
7744                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7745                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7746                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7747                 }
7748
7749                 target_vblank = last_flip_vblank + wait_for_vblank;
7750
7751                 /*
7752                  * Wait until we're out of the vertical blank period before the one
7753                  * targeted by the flip
7754                  */
7755                 while ((acrtc_attach->enabled &&
7756                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7757                                                             0, &vpos, &hpos, NULL,
7758                                                             NULL, &pcrtc->hwmode)
7759                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7760                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7761                         (int)(target_vblank -
7762                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7763                         usleep_range(1000, 1100);
7764                 }
7765
7766                 /**
7767                  * Prepare the flip event for the pageflip interrupt to handle.
7768                  *
7769                  * This only works in the case where we've already turned on the
7770                  * appropriate hardware blocks (eg. HUBP) so in the transition case
7771                  * from 0 -> n planes we have to skip a hardware generated event
7772                  * and rely on sending it from software.
7773                  */
7774                 if (acrtc_attach->base.state->event &&
7775                     acrtc_state->active_planes > 0) {
7776                         drm_crtc_vblank_get(pcrtc);
7777
7778                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7779
7780                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7781                         prepare_flip_isr(acrtc_attach);
7782
7783                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7784                 }
7785
7786                 if (acrtc_state->stream) {
7787                         if (acrtc_state->freesync_vrr_info_changed)
7788                                 bundle->stream_update.vrr_infopacket =
7789                                         &acrtc_state->stream->vrr_infopacket;
7790                 }
7791         } else if (cursor_update && acrtc_state->active_planes > 0 &&
7792                    acrtc_attach->base.state->event) {
7793                 drm_crtc_vblank_get(pcrtc);
7794
7795                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7796
7797                 acrtc_attach->event = acrtc_attach->base.state->event;
7798                 acrtc_attach->base.state->event = NULL;
7799
7800                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7801         }
7802
7803         /* Update the planes if changed or disable if we don't have any. */
7804         if ((planes_count || acrtc_state->active_planes == 0) &&
7805                 acrtc_state->stream) {
7806                 /*
7807                  * If PSR or idle optimizations are enabled then flush out
7808                  * any pending work before hardware programming.
7809                  */
7810                 if (dm->vblank_control_workqueue)
7811                         flush_workqueue(dm->vblank_control_workqueue);
7812
7813                 bundle->stream_update.stream = acrtc_state->stream;
7814                 if (new_pcrtc_state->mode_changed) {
7815                         bundle->stream_update.src = acrtc_state->stream->src;
7816                         bundle->stream_update.dst = acrtc_state->stream->dst;
7817                 }
7818
7819                 if (new_pcrtc_state->color_mgmt_changed) {
7820                         /*
7821                          * TODO: This isn't fully correct since we've actually
7822                          * already modified the stream in place.
7823                          */
7824                         bundle->stream_update.gamut_remap =
7825                                 &acrtc_state->stream->gamut_remap_matrix;
7826                         bundle->stream_update.output_csc_transform =
7827                                 &acrtc_state->stream->csc_color_matrix;
7828                         bundle->stream_update.out_transfer_func =
7829                                 acrtc_state->stream->out_transfer_func;
7830                 }
7831
7832                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
7833                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7834                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
7835
7836                 /*
7837                  * If FreeSync state on the stream has changed then we need to
7838                  * re-adjust the min/max bounds now that DC doesn't handle this
7839                  * as part of commit.
7840                  */
7841                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
7842                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7843                         dc_stream_adjust_vmin_vmax(
7844                                 dm->dc, acrtc_state->stream,
7845                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
7846                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7847                 }
7848                 mutex_lock(&dm->dc_lock);
7849                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7850                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
7851                         amdgpu_dm_psr_disable(acrtc_state->stream);
7852
7853                 dc_commit_updates_for_stream(dm->dc,
7854                                                      bundle->surface_updates,
7855                                                      planes_count,
7856                                                      acrtc_state->stream,
7857                                                      &bundle->stream_update,
7858                                                      dc_state);
7859
7860                 /**
7861                  * Enable or disable the interrupts on the backend.
7862                  *
7863                  * Most pipes are put into power gating when unused.
7864                  *
7865                  * When power gating is enabled on a pipe we lose the
7866                  * interrupt enablement state when power gating is disabled.
7867                  *
7868                  * So we need to update the IRQ control state in hardware
7869                  * whenever the pipe turns on (since it could be previously
7870                  * power gated) or off (since some pipes can't be power gated
7871                  * on some ASICs).
7872                  */
7873                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
7874                         dm_update_pflip_irq_state(drm_to_adev(dev),
7875                                                   acrtc_attach);
7876
7877                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7878                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
7879                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7880                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
7881
7882                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
7883                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
7884                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
7885                         struct amdgpu_dm_connector *aconn =
7886                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
7887
7888                         if (aconn->psr_skip_count > 0)
7889                                 aconn->psr_skip_count--;
7890
7891                         /* Allow PSR when skip count is 0. */
7892                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7893
7894                         /*
7895                          * If sink supports PSR SU, there is no need to rely on
7896                          * a vblank event disable request to enable PSR. PSR SU
7897                          * can be enabled immediately once OS demonstrates an
7898                          * adequate number of fast atomic commits to notify KMD
7899                          * of update events. See `vblank_control_worker()`.
7900                          */
7901                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
7902                             acrtc_attach->dm_irq_params.allow_psr_entry &&
7903 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
7904                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
7905 #endif
7906                             !acrtc_state->stream->link->psr_settings.psr_allow_active)
7907                                 amdgpu_dm_psr_enable(acrtc_state->stream);
7908                 } else {
7909                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
7910                 }
7911
7912                 mutex_unlock(&dm->dc_lock);
7913         }
7914
7915         /*
7916          * Update cursor state *after* programming all the planes.
7917          * This avoids redundant programming in the case where we're going
7918          * to be disabling a single plane - those pipes are being disabled.
7919          */
7920         if (acrtc_state->active_planes)
7921                 amdgpu_dm_commit_cursors(state);
7922
7923 cleanup:
7924         kfree(bundle);
7925 }
7926
7927 static void amdgpu_dm_commit_audio(struct drm_device *dev,
7928                                    struct drm_atomic_state *state)
7929 {
7930         struct amdgpu_device *adev = drm_to_adev(dev);
7931         struct amdgpu_dm_connector *aconnector;
7932         struct drm_connector *connector;
7933         struct drm_connector_state *old_con_state, *new_con_state;
7934         struct drm_crtc_state *new_crtc_state;
7935         struct dm_crtc_state *new_dm_crtc_state;
7936         const struct dc_stream_status *status;
7937         int i, inst;
7938
7939         /* Notify device removals. */
7940         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7941                 if (old_con_state->crtc != new_con_state->crtc) {
7942                         /* CRTC changes require notification. */
7943                         goto notify;
7944                 }
7945
7946                 if (!new_con_state->crtc)
7947                         continue;
7948
7949                 new_crtc_state = drm_atomic_get_new_crtc_state(
7950                         state, new_con_state->crtc);
7951
7952                 if (!new_crtc_state)
7953                         continue;
7954
7955                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7956                         continue;
7957
7958         notify:
7959                 aconnector = to_amdgpu_dm_connector(connector);
7960
7961                 mutex_lock(&adev->dm.audio_lock);
7962                 inst = aconnector->audio_inst;
7963                 aconnector->audio_inst = -1;
7964                 mutex_unlock(&adev->dm.audio_lock);
7965
7966                 amdgpu_dm_audio_eld_notify(adev, inst);
7967         }
7968
7969         /* Notify audio device additions. */
7970         for_each_new_connector_in_state(state, connector, new_con_state, i) {
7971                 if (!new_con_state->crtc)
7972                         continue;
7973
7974                 new_crtc_state = drm_atomic_get_new_crtc_state(
7975                         state, new_con_state->crtc);
7976
7977                 if (!new_crtc_state)
7978                         continue;
7979
7980                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7981                         continue;
7982
7983                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7984                 if (!new_dm_crtc_state->stream)
7985                         continue;
7986
7987                 status = dc_stream_get_status(new_dm_crtc_state->stream);
7988                 if (!status)
7989                         continue;
7990
7991                 aconnector = to_amdgpu_dm_connector(connector);
7992
7993                 mutex_lock(&adev->dm.audio_lock);
7994                 inst = status->audio_inst;
7995                 aconnector->audio_inst = inst;
7996                 mutex_unlock(&adev->dm.audio_lock);
7997
7998                 amdgpu_dm_audio_eld_notify(adev, inst);
7999         }
8000 }
8001
8002 /*
8003  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8004  * @crtc_state: the DRM CRTC state
8005  * @stream_state: the DC stream state.
8006  *
8007  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8008  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8009  */
8010 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8011                                                 struct dc_stream_state *stream_state)
8012 {
8013         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8014 }
8015
8016 /**
8017  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8018  * @state: The atomic state to commit
8019  *
8020  * This will tell DC to commit the constructed DC state from atomic_check,
8021  * programming the hardware. Any failures here implies a hardware failure, since
8022  * atomic check should have filtered anything non-kosher.
8023  */
8024 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8025 {
8026         struct drm_device *dev = state->dev;
8027         struct amdgpu_device *adev = drm_to_adev(dev);
8028         struct amdgpu_display_manager *dm = &adev->dm;
8029         struct dm_atomic_state *dm_state;
8030         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8031         uint32_t i, j;
8032         struct drm_crtc *crtc;
8033         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8034         unsigned long flags;
8035         bool wait_for_vblank = true;
8036         struct drm_connector *connector;
8037         struct drm_connector_state *old_con_state, *new_con_state;
8038         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8039         int crtc_disable_count = 0;
8040         bool mode_set_reset_required = false;
8041         int r;
8042
8043         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8044
8045         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8046         if (unlikely(r))
8047                 DRM_ERROR("Waiting for fences timed out!");
8048
8049         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8050         drm_dp_mst_atomic_wait_for_dependencies(state);
8051
8052         dm_state = dm_atomic_get_new_state(state);
8053         if (dm_state && dm_state->context) {
8054                 dc_state = dm_state->context;
8055         } else {
8056                 /* No state changes, retain current state. */
8057                 dc_state_temp = dc_create_state(dm->dc);
8058                 ASSERT(dc_state_temp);
8059                 dc_state = dc_state_temp;
8060                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8061         }
8062
8063         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8064                                        new_crtc_state, i) {
8065                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8066
8067                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8068
8069                 if (old_crtc_state->active &&
8070                     (!new_crtc_state->active ||
8071                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8072                         manage_dm_interrupts(adev, acrtc, false);
8073                         dc_stream_release(dm_old_crtc_state->stream);
8074                 }
8075         }
8076
8077         drm_atomic_helper_calc_timestamping_constants(state);
8078
8079         /* update changed items */
8080         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8081                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8082
8083                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8084                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8085
8086                 drm_dbg_state(state->dev,
8087                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8088                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8089                         "connectors_changed:%d\n",
8090                         acrtc->crtc_id,
8091                         new_crtc_state->enable,
8092                         new_crtc_state->active,
8093                         new_crtc_state->planes_changed,
8094                         new_crtc_state->mode_changed,
8095                         new_crtc_state->active_changed,
8096                         new_crtc_state->connectors_changed);
8097
8098                 /* Disable cursor if disabling crtc */
8099                 if (old_crtc_state->active && !new_crtc_state->active) {
8100                         struct dc_cursor_position position;
8101
8102                         memset(&position, 0, sizeof(position));
8103                         mutex_lock(&dm->dc_lock);
8104                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8105                         mutex_unlock(&dm->dc_lock);
8106                 }
8107
8108                 /* Copy all transient state flags into dc state */
8109                 if (dm_new_crtc_state->stream) {
8110                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8111                                                             dm_new_crtc_state->stream);
8112                 }
8113
8114                 /* handles headless hotplug case, updating new_state and
8115                  * aconnector as needed
8116                  */
8117
8118                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8119
8120                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8121
8122                         if (!dm_new_crtc_state->stream) {
8123                                 /*
8124                                  * this could happen because of issues with
8125                                  * userspace notifications delivery.
8126                                  * In this case userspace tries to set mode on
8127                                  * display which is disconnected in fact.
8128                                  * dc_sink is NULL in this case on aconnector.
8129                                  * We expect reset mode will come soon.
8130                                  *
8131                                  * This can also happen when unplug is done
8132                                  * during resume sequence ended
8133                                  *
8134                                  * In this case, we want to pretend we still
8135                                  * have a sink to keep the pipe running so that
8136                                  * hw state is consistent with the sw state
8137                                  */
8138                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8139                                                 __func__, acrtc->base.base.id);
8140                                 continue;
8141                         }
8142
8143                         if (dm_old_crtc_state->stream)
8144                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8145
8146                         pm_runtime_get_noresume(dev->dev);
8147
8148                         acrtc->enabled = true;
8149                         acrtc->hw_mode = new_crtc_state->mode;
8150                         crtc->hwmode = new_crtc_state->mode;
8151                         mode_set_reset_required = true;
8152                 } else if (modereset_required(new_crtc_state)) {
8153                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8154                         /* i.e. reset mode */
8155                         if (dm_old_crtc_state->stream)
8156                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8157
8158                         mode_set_reset_required = true;
8159                 }
8160         } /* for_each_crtc_in_state() */
8161
8162         if (dc_state) {
8163                 /* if there mode set or reset, disable eDP PSR */
8164                 if (mode_set_reset_required) {
8165                         if (dm->vblank_control_workqueue)
8166                                 flush_workqueue(dm->vblank_control_workqueue);
8167
8168                         amdgpu_dm_psr_disable_all(dm);
8169                 }
8170
8171                 dm_enable_per_frame_crtc_master_sync(dc_state);
8172                 mutex_lock(&dm->dc_lock);
8173                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8174
8175                 /* Allow idle optimization when vblank count is 0 for display off */
8176                 if (dm->active_vblank_irq_count == 0)
8177                         dc_allow_idle_optimizations(dm->dc, true);
8178                 mutex_unlock(&dm->dc_lock);
8179         }
8180
8181         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8182                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8183
8184                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8185
8186                 if (dm_new_crtc_state->stream != NULL) {
8187                         const struct dc_stream_status *status =
8188                                         dc_stream_get_status(dm_new_crtc_state->stream);
8189
8190                         if (!status)
8191                                 status = dc_stream_get_status_from_state(dc_state,
8192                                                                          dm_new_crtc_state->stream);
8193                         if (!status)
8194                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8195                         else
8196                                 acrtc->otg_inst = status->primary_otg_inst;
8197                 }
8198         }
8199 #ifdef CONFIG_DRM_AMD_DC_HDCP
8200         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8201                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8202                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8203                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8204
8205                 new_crtc_state = NULL;
8206
8207                 if (acrtc)
8208                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8209
8210                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8211
8212                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8213                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8214                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8215                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8216                         dm_new_con_state->update_hdcp = true;
8217                         continue;
8218                 }
8219
8220                 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8221                         hdcp_update_display(
8222                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8223                                 new_con_state->hdcp_content_type,
8224                                 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8225         }
8226 #endif
8227
8228         /* Handle connector state changes */
8229         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8230                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8231                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8232                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8233                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8234                 struct dc_stream_update stream_update;
8235                 struct dc_info_packet hdr_packet;
8236                 struct dc_stream_status *status = NULL;
8237                 bool abm_changed, hdr_changed, scaling_changed;
8238
8239                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8240                 memset(&stream_update, 0, sizeof(stream_update));
8241
8242                 if (acrtc) {
8243                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8244                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8245                 }
8246
8247                 /* Skip any modesets/resets */
8248                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8249                         continue;
8250
8251                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8252                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8253
8254                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8255                                                              dm_old_con_state);
8256
8257                 abm_changed = dm_new_crtc_state->abm_level !=
8258                               dm_old_crtc_state->abm_level;
8259
8260                 hdr_changed =
8261                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8262
8263                 if (!scaling_changed && !abm_changed && !hdr_changed)
8264                         continue;
8265
8266                 stream_update.stream = dm_new_crtc_state->stream;
8267                 if (scaling_changed) {
8268                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8269                                         dm_new_con_state, dm_new_crtc_state->stream);
8270
8271                         stream_update.src = dm_new_crtc_state->stream->src;
8272                         stream_update.dst = dm_new_crtc_state->stream->dst;
8273                 }
8274
8275                 if (abm_changed) {
8276                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8277
8278                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8279                 }
8280
8281                 if (hdr_changed) {
8282                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8283                         stream_update.hdr_static_metadata = &hdr_packet;
8284                 }
8285
8286                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8287
8288                 if (WARN_ON(!status))
8289                         continue;
8290
8291                 WARN_ON(!status->plane_count);
8292
8293                 /*
8294                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8295                  * Here we create an empty update on each plane.
8296                  * To fix this, DC should permit updating only stream properties.
8297                  */
8298                 for (j = 0; j < status->plane_count; j++)
8299                         dummy_updates[j].surface = status->plane_states[0];
8300
8301
8302                 mutex_lock(&dm->dc_lock);
8303                 dc_commit_updates_for_stream(dm->dc,
8304                                                      dummy_updates,
8305                                                      status->plane_count,
8306                                                      dm_new_crtc_state->stream,
8307                                                      &stream_update,
8308                                                      dc_state);
8309                 mutex_unlock(&dm->dc_lock);
8310         }
8311
8312         /**
8313          * Enable interrupts for CRTCs that are newly enabled or went through
8314          * a modeset. It was intentionally deferred until after the front end
8315          * state was modified to wait until the OTG was on and so the IRQ
8316          * handlers didn't access stale or invalid state.
8317          */
8318         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8319                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8320 #ifdef CONFIG_DEBUG_FS
8321                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8322 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8323                 struct crc_rd_work *crc_rd_wrk;
8324 #endif
8325 #endif
8326                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8327                 if (old_crtc_state->active && !new_crtc_state->active)
8328                         crtc_disable_count++;
8329
8330                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8331                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8332
8333                 /* For freesync config update on crtc state and params for irq */
8334                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8335
8336 #ifdef CONFIG_DEBUG_FS
8337 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8338                 crc_rd_wrk = dm->crc_rd_wrk;
8339 #endif
8340                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8341                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8342                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8343 #endif
8344
8345                 if (new_crtc_state->active &&
8346                     (!old_crtc_state->active ||
8347                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8348                         dc_stream_retain(dm_new_crtc_state->stream);
8349                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8350                         manage_dm_interrupts(adev, acrtc, true);
8351                 }
8352                 /* Handle vrr on->off / off->on transitions */
8353                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8354
8355 #ifdef CONFIG_DEBUG_FS
8356                 if (new_crtc_state->active &&
8357                     (!old_crtc_state->active ||
8358                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8359                         /**
8360                          * Frontend may have changed so reapply the CRC capture
8361                          * settings for the stream.
8362                          */
8363                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8364 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8365                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8366                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8367                                         acrtc->dm_irq_params.window_param.update_win = true;
8368                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8369                                         spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
8370                                         crc_rd_wrk->crtc = crtc;
8371                                         spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
8372                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8373                                 }
8374 #endif
8375                                 if (amdgpu_dm_crtc_configure_crc_source(
8376                                         crtc, dm_new_crtc_state, cur_crc_src))
8377                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8378                         }
8379                 }
8380 #endif
8381         }
8382
8383         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8384                 if (new_crtc_state->async_flip)
8385                         wait_for_vblank = false;
8386
8387         /* update planes when needed per crtc*/
8388         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8389                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8390
8391                 if (dm_new_crtc_state->stream)
8392                         amdgpu_dm_commit_planes(state, dc_state, dev,
8393                                                 dm, crtc, wait_for_vblank);
8394         }
8395
8396         /* Update audio instances for each connector. */
8397         amdgpu_dm_commit_audio(dev, state);
8398
8399         /* restore the backlight level */
8400         for (i = 0; i < dm->num_of_edps; i++) {
8401                 if (dm->backlight_dev[i] &&
8402                     (dm->actual_brightness[i] != dm->brightness[i]))
8403                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8404         }
8405
8406         /*
8407          * send vblank event on all events not handled in flip and
8408          * mark consumed event for drm_atomic_helper_commit_hw_done
8409          */
8410         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8411         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8412
8413                 if (new_crtc_state->event)
8414                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8415
8416                 new_crtc_state->event = NULL;
8417         }
8418         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8419
8420         /* Signal HW programming completion */
8421         drm_atomic_helper_commit_hw_done(state);
8422
8423         if (wait_for_vblank)
8424                 drm_atomic_helper_wait_for_flip_done(dev, state);
8425
8426         drm_atomic_helper_cleanup_planes(dev, state);
8427
8428         /* return the stolen vga memory back to VRAM */
8429         if (!adev->mman.keep_stolen_vga_memory)
8430                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8431         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8432
8433         /*
8434          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8435          * so we can put the GPU into runtime suspend if we're not driving any
8436          * displays anymore
8437          */
8438         for (i = 0; i < crtc_disable_count; i++)
8439                 pm_runtime_put_autosuspend(dev->dev);
8440         pm_runtime_mark_last_busy(dev->dev);
8441
8442         if (dc_state_temp)
8443                 dc_release_state(dc_state_temp);
8444 }
8445
8446 static int dm_force_atomic_commit(struct drm_connector *connector)
8447 {
8448         int ret = 0;
8449         struct drm_device *ddev = connector->dev;
8450         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8451         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8452         struct drm_plane *plane = disconnected_acrtc->base.primary;
8453         struct drm_connector_state *conn_state;
8454         struct drm_crtc_state *crtc_state;
8455         struct drm_plane_state *plane_state;
8456
8457         if (!state)
8458                 return -ENOMEM;
8459
8460         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8461
8462         /* Construct an atomic state to restore previous display setting */
8463
8464         /*
8465          * Attach connectors to drm_atomic_state
8466          */
8467         conn_state = drm_atomic_get_connector_state(state, connector);
8468
8469         ret = PTR_ERR_OR_ZERO(conn_state);
8470         if (ret)
8471                 goto out;
8472
8473         /* Attach crtc to drm_atomic_state*/
8474         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8475
8476         ret = PTR_ERR_OR_ZERO(crtc_state);
8477         if (ret)
8478                 goto out;
8479
8480         /* force a restore */
8481         crtc_state->mode_changed = true;
8482
8483         /* Attach plane to drm_atomic_state */
8484         plane_state = drm_atomic_get_plane_state(state, plane);
8485
8486         ret = PTR_ERR_OR_ZERO(plane_state);
8487         if (ret)
8488                 goto out;
8489
8490         /* Call commit internally with the state we just constructed */
8491         ret = drm_atomic_commit(state);
8492
8493 out:
8494         drm_atomic_state_put(state);
8495         if (ret)
8496                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8497
8498         return ret;
8499 }
8500
8501 /*
8502  * This function handles all cases when set mode does not come upon hotplug.
8503  * This includes when a display is unplugged then plugged back into the
8504  * same port and when running without usermode desktop manager supprot
8505  */
8506 void dm_restore_drm_connector_state(struct drm_device *dev,
8507                                     struct drm_connector *connector)
8508 {
8509         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8510         struct amdgpu_crtc *disconnected_acrtc;
8511         struct dm_crtc_state *acrtc_state;
8512
8513         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8514                 return;
8515
8516         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8517         if (!disconnected_acrtc)
8518                 return;
8519
8520         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8521         if (!acrtc_state->stream)
8522                 return;
8523
8524         /*
8525          * If the previous sink is not released and different from the current,
8526          * we deduce we are in a state where we can not rely on usermode call
8527          * to turn on the display, so we do it here
8528          */
8529         if (acrtc_state->stream->sink != aconnector->dc_sink)
8530                 dm_force_atomic_commit(&aconnector->base);
8531 }
8532
8533 /*
8534  * Grabs all modesetting locks to serialize against any blocking commits,
8535  * Waits for completion of all non blocking commits.
8536  */
8537 static int do_aquire_global_lock(struct drm_device *dev,
8538                                  struct drm_atomic_state *state)
8539 {
8540         struct drm_crtc *crtc;
8541         struct drm_crtc_commit *commit;
8542         long ret;
8543
8544         /*
8545          * Adding all modeset locks to aquire_ctx will
8546          * ensure that when the framework release it the
8547          * extra locks we are locking here will get released to
8548          */
8549         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8550         if (ret)
8551                 return ret;
8552
8553         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8554                 spin_lock(&crtc->commit_lock);
8555                 commit = list_first_entry_or_null(&crtc->commit_list,
8556                                 struct drm_crtc_commit, commit_entry);
8557                 if (commit)
8558                         drm_crtc_commit_get(commit);
8559                 spin_unlock(&crtc->commit_lock);
8560
8561                 if (!commit)
8562                         continue;
8563
8564                 /*
8565                  * Make sure all pending HW programming completed and
8566                  * page flips done
8567                  */
8568                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8569
8570                 if (ret > 0)
8571                         ret = wait_for_completion_interruptible_timeout(
8572                                         &commit->flip_done, 10*HZ);
8573
8574                 if (ret == 0)
8575                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8576                                   "timed out\n", crtc->base.id, crtc->name);
8577
8578                 drm_crtc_commit_put(commit);
8579         }
8580
8581         return ret < 0 ? ret : 0;
8582 }
8583
8584 static void get_freesync_config_for_crtc(
8585         struct dm_crtc_state *new_crtc_state,
8586         struct dm_connector_state *new_con_state)
8587 {
8588         struct mod_freesync_config config = {0};
8589         struct amdgpu_dm_connector *aconnector =
8590                         to_amdgpu_dm_connector(new_con_state->base.connector);
8591         struct drm_display_mode *mode = &new_crtc_state->base.mode;
8592         int vrefresh = drm_mode_vrefresh(mode);
8593         bool fs_vid_mode = false;
8594
8595         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8596                                         vrefresh >= aconnector->min_vfreq &&
8597                                         vrefresh <= aconnector->max_vfreq;
8598
8599         if (new_crtc_state->vrr_supported) {
8600                 new_crtc_state->stream->ignore_msa_timing_param = true;
8601                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
8602
8603                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8604                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
8605                 config.vsif_supported = true;
8606                 config.btr = true;
8607
8608                 if (fs_vid_mode) {
8609                         config.state = VRR_STATE_ACTIVE_FIXED;
8610                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8611                         goto out;
8612                 } else if (new_crtc_state->base.vrr_enabled) {
8613                         config.state = VRR_STATE_ACTIVE_VARIABLE;
8614                 } else {
8615                         config.state = VRR_STATE_INACTIVE;
8616                 }
8617         }
8618 out:
8619         new_crtc_state->freesync_config = config;
8620 }
8621
8622 static void reset_freesync_config_for_crtc(
8623         struct dm_crtc_state *new_crtc_state)
8624 {
8625         new_crtc_state->vrr_supported = false;
8626
8627         memset(&new_crtc_state->vrr_infopacket, 0,
8628                sizeof(new_crtc_state->vrr_infopacket));
8629 }
8630
8631 static bool
8632 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8633                                  struct drm_crtc_state *new_crtc_state)
8634 {
8635         const struct drm_display_mode *old_mode, *new_mode;
8636
8637         if (!old_crtc_state || !new_crtc_state)
8638                 return false;
8639
8640         old_mode = &old_crtc_state->mode;
8641         new_mode = &new_crtc_state->mode;
8642
8643         if (old_mode->clock       == new_mode->clock &&
8644             old_mode->hdisplay    == new_mode->hdisplay &&
8645             old_mode->vdisplay    == new_mode->vdisplay &&
8646             old_mode->htotal      == new_mode->htotal &&
8647             old_mode->vtotal      != new_mode->vtotal &&
8648             old_mode->hsync_start == new_mode->hsync_start &&
8649             old_mode->vsync_start != new_mode->vsync_start &&
8650             old_mode->hsync_end   == new_mode->hsync_end &&
8651             old_mode->vsync_end   != new_mode->vsync_end &&
8652             old_mode->hskew       == new_mode->hskew &&
8653             old_mode->vscan       == new_mode->vscan &&
8654             (old_mode->vsync_end - old_mode->vsync_start) ==
8655             (new_mode->vsync_end - new_mode->vsync_start))
8656                 return true;
8657
8658         return false;
8659 }
8660
8661 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
8662         uint64_t num, den, res;
8663         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8664
8665         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8666
8667         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8668         den = (unsigned long long)new_crtc_state->mode.htotal *
8669               (unsigned long long)new_crtc_state->mode.vtotal;
8670
8671         res = div_u64(num, den);
8672         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8673 }
8674
8675 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8676                          struct drm_atomic_state *state,
8677                          struct drm_crtc *crtc,
8678                          struct drm_crtc_state *old_crtc_state,
8679                          struct drm_crtc_state *new_crtc_state,
8680                          bool enable,
8681                          bool *lock_and_validation_needed)
8682 {
8683         struct dm_atomic_state *dm_state = NULL;
8684         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8685         struct dc_stream_state *new_stream;
8686         int ret = 0;
8687
8688         /*
8689          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8690          * update changed items
8691          */
8692         struct amdgpu_crtc *acrtc = NULL;
8693         struct amdgpu_dm_connector *aconnector = NULL;
8694         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8695         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8696
8697         new_stream = NULL;
8698
8699         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8700         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8701         acrtc = to_amdgpu_crtc(crtc);
8702         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8703
8704         /* TODO This hack should go away */
8705         if (aconnector && enable) {
8706                 /* Make sure fake sink is created in plug-in scenario */
8707                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8708                                                             &aconnector->base);
8709                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8710                                                             &aconnector->base);
8711
8712                 if (IS_ERR(drm_new_conn_state)) {
8713                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8714                         goto fail;
8715                 }
8716
8717                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8718                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
8719
8720                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8721                         goto skip_modeset;
8722
8723                 new_stream = create_validate_stream_for_sink(aconnector,
8724                                                              &new_crtc_state->mode,
8725                                                              dm_new_conn_state,
8726                                                              dm_old_crtc_state->stream);
8727
8728                 /*
8729                  * we can have no stream on ACTION_SET if a display
8730                  * was disconnected during S3, in this case it is not an
8731                  * error, the OS will be updated after detection, and
8732                  * will do the right thing on next atomic commit
8733                  */
8734
8735                 if (!new_stream) {
8736                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8737                                         __func__, acrtc->base.base.id);
8738                         ret = -ENOMEM;
8739                         goto fail;
8740                 }
8741
8742                 /*
8743                  * TODO: Check VSDB bits to decide whether this should
8744                  * be enabled or not.
8745                  */
8746                 new_stream->triggered_crtc_reset.enabled =
8747                         dm->force_timing_sync;
8748
8749                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8750
8751                 ret = fill_hdr_info_packet(drm_new_conn_state,
8752                                            &new_stream->hdr_static_metadata);
8753                 if (ret)
8754                         goto fail;
8755
8756                 /*
8757                  * If we already removed the old stream from the context
8758                  * (and set the new stream to NULL) then we can't reuse
8759                  * the old stream even if the stream and scaling are unchanged.
8760                  * We'll hit the BUG_ON and black screen.
8761                  *
8762                  * TODO: Refactor this function to allow this check to work
8763                  * in all conditions.
8764                  */
8765                 if (dm_new_crtc_state->stream &&
8766                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
8767                         goto skip_modeset;
8768
8769                 if (dm_new_crtc_state->stream &&
8770                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
8771                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
8772                         new_crtc_state->mode_changed = false;
8773                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
8774                                          new_crtc_state->mode_changed);
8775                 }
8776         }
8777
8778         /* mode_changed flag may get updated above, need to check again */
8779         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8780                 goto skip_modeset;
8781
8782         drm_dbg_state(state->dev,
8783                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8784                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8785                 "connectors_changed:%d\n",
8786                 acrtc->crtc_id,
8787                 new_crtc_state->enable,
8788                 new_crtc_state->active,
8789                 new_crtc_state->planes_changed,
8790                 new_crtc_state->mode_changed,
8791                 new_crtc_state->active_changed,
8792                 new_crtc_state->connectors_changed);
8793
8794         /* Remove stream for any changed/disabled CRTC */
8795         if (!enable) {
8796
8797                 if (!dm_old_crtc_state->stream)
8798                         goto skip_modeset;
8799
8800                 if (dm_new_crtc_state->stream &&
8801                     is_timing_unchanged_for_freesync(new_crtc_state,
8802                                                      old_crtc_state)) {
8803                         new_crtc_state->mode_changed = false;
8804                         DRM_DEBUG_DRIVER(
8805                                 "Mode change not required for front porch change, "
8806                                 "setting mode_changed to %d",
8807                                 new_crtc_state->mode_changed);
8808
8809                         set_freesync_fixed_config(dm_new_crtc_state);
8810
8811                         goto skip_modeset;
8812                 } else if (aconnector &&
8813                            is_freesync_video_mode(&new_crtc_state->mode,
8814                                                   aconnector)) {
8815                         struct drm_display_mode *high_mode;
8816
8817                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
8818                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
8819                                 set_freesync_fixed_config(dm_new_crtc_state);
8820                         }
8821                 }
8822
8823                 ret = dm_atomic_get_state(state, &dm_state);
8824                 if (ret)
8825                         goto fail;
8826
8827                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
8828                                 crtc->base.id);
8829
8830                 /* i.e. reset mode */
8831                 if (dc_remove_stream_from_ctx(
8832                                 dm->dc,
8833                                 dm_state->context,
8834                                 dm_old_crtc_state->stream) != DC_OK) {
8835                         ret = -EINVAL;
8836                         goto fail;
8837                 }
8838
8839                 dc_stream_release(dm_old_crtc_state->stream);
8840                 dm_new_crtc_state->stream = NULL;
8841
8842                 reset_freesync_config_for_crtc(dm_new_crtc_state);
8843
8844                 *lock_and_validation_needed = true;
8845
8846         } else {/* Add stream for any updated/enabled CRTC */
8847                 /*
8848                  * Quick fix to prevent NULL pointer on new_stream when
8849                  * added MST connectors not found in existing crtc_state in the chained mode
8850                  * TODO: need to dig out the root cause of that
8851                  */
8852                 if (!aconnector)
8853                         goto skip_modeset;
8854
8855                 if (modereset_required(new_crtc_state))
8856                         goto skip_modeset;
8857
8858                 if (modeset_required(new_crtc_state, new_stream,
8859                                      dm_old_crtc_state->stream)) {
8860
8861                         WARN_ON(dm_new_crtc_state->stream);
8862
8863                         ret = dm_atomic_get_state(state, &dm_state);
8864                         if (ret)
8865                                 goto fail;
8866
8867                         dm_new_crtc_state->stream = new_stream;
8868
8869                         dc_stream_retain(new_stream);
8870
8871                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
8872                                          crtc->base.id);
8873
8874                         if (dc_add_stream_to_ctx(
8875                                         dm->dc,
8876                                         dm_state->context,
8877                                         dm_new_crtc_state->stream) != DC_OK) {
8878                                 ret = -EINVAL;
8879                                 goto fail;
8880                         }
8881
8882                         *lock_and_validation_needed = true;
8883                 }
8884         }
8885
8886 skip_modeset:
8887         /* Release extra reference */
8888         if (new_stream)
8889                  dc_stream_release(new_stream);
8890
8891         /*
8892          * We want to do dc stream updates that do not require a
8893          * full modeset below.
8894          */
8895         if (!(enable && aconnector && new_crtc_state->active))
8896                 return 0;
8897         /*
8898          * Given above conditions, the dc state cannot be NULL because:
8899          * 1. We're in the process of enabling CRTCs (just been added
8900          *    to the dc context, or already is on the context)
8901          * 2. Has a valid connector attached, and
8902          * 3. Is currently active and enabled.
8903          * => The dc stream state currently exists.
8904          */
8905         BUG_ON(dm_new_crtc_state->stream == NULL);
8906
8907         /* Scaling or underscan settings */
8908         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
8909                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
8910                 update_stream_scaling_settings(
8911                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
8912
8913         /* ABM settings */
8914         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8915
8916         /*
8917          * Color management settings. We also update color properties
8918          * when a modeset is needed, to ensure it gets reprogrammed.
8919          */
8920         if (dm_new_crtc_state->base.color_mgmt_changed ||
8921             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
8922                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
8923                 if (ret)
8924                         goto fail;
8925         }
8926
8927         /* Update Freesync settings. */
8928         get_freesync_config_for_crtc(dm_new_crtc_state,
8929                                      dm_new_conn_state);
8930
8931         return ret;
8932
8933 fail:
8934         if (new_stream)
8935                 dc_stream_release(new_stream);
8936         return ret;
8937 }
8938
8939 static bool should_reset_plane(struct drm_atomic_state *state,
8940                                struct drm_plane *plane,
8941                                struct drm_plane_state *old_plane_state,
8942                                struct drm_plane_state *new_plane_state)
8943 {
8944         struct drm_plane *other;
8945         struct drm_plane_state *old_other_state, *new_other_state;
8946         struct drm_crtc_state *new_crtc_state;
8947         int i;
8948
8949         /*
8950          * TODO: Remove this hack once the checks below are sufficient
8951          * enough to determine when we need to reset all the planes on
8952          * the stream.
8953          */
8954         if (state->allow_modeset)
8955                 return true;
8956
8957         /* Exit early if we know that we're adding or removing the plane. */
8958         if (old_plane_state->crtc != new_plane_state->crtc)
8959                 return true;
8960
8961         /* old crtc == new_crtc == NULL, plane not in context. */
8962         if (!new_plane_state->crtc)
8963                 return false;
8964
8965         new_crtc_state =
8966                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
8967
8968         if (!new_crtc_state)
8969                 return true;
8970
8971         /* CRTC Degamma changes currently require us to recreate planes. */
8972         if (new_crtc_state->color_mgmt_changed)
8973                 return true;
8974
8975         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
8976                 return true;
8977
8978         /*
8979          * If there are any new primary or overlay planes being added or
8980          * removed then the z-order can potentially change. To ensure
8981          * correct z-order and pipe acquisition the current DC architecture
8982          * requires us to remove and recreate all existing planes.
8983          *
8984          * TODO: Come up with a more elegant solution for this.
8985          */
8986         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
8987                 struct amdgpu_framebuffer *old_afb, *new_afb;
8988                 if (other->type == DRM_PLANE_TYPE_CURSOR)
8989                         continue;
8990
8991                 if (old_other_state->crtc != new_plane_state->crtc &&
8992                     new_other_state->crtc != new_plane_state->crtc)
8993                         continue;
8994
8995                 if (old_other_state->crtc != new_other_state->crtc)
8996                         return true;
8997
8998                 /* Src/dst size and scaling updates. */
8999                 if (old_other_state->src_w != new_other_state->src_w ||
9000                     old_other_state->src_h != new_other_state->src_h ||
9001                     old_other_state->crtc_w != new_other_state->crtc_w ||
9002                     old_other_state->crtc_h != new_other_state->crtc_h)
9003                         return true;
9004
9005                 /* Rotation / mirroring updates. */
9006                 if (old_other_state->rotation != new_other_state->rotation)
9007                         return true;
9008
9009                 /* Blending updates. */
9010                 if (old_other_state->pixel_blend_mode !=
9011                     new_other_state->pixel_blend_mode)
9012                         return true;
9013
9014                 /* Alpha updates. */
9015                 if (old_other_state->alpha != new_other_state->alpha)
9016                         return true;
9017
9018                 /* Colorspace changes. */
9019                 if (old_other_state->color_range != new_other_state->color_range ||
9020                     old_other_state->color_encoding != new_other_state->color_encoding)
9021                         return true;
9022
9023                 /* Framebuffer checks fall at the end. */
9024                 if (!old_other_state->fb || !new_other_state->fb)
9025                         continue;
9026
9027                 /* Pixel format changes can require bandwidth updates. */
9028                 if (old_other_state->fb->format != new_other_state->fb->format)
9029                         return true;
9030
9031                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9032                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9033
9034                 /* Tiling and DCC changes also require bandwidth updates. */
9035                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9036                     old_afb->base.modifier != new_afb->base.modifier)
9037                         return true;
9038         }
9039
9040         return false;
9041 }
9042
9043 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9044                               struct drm_plane_state *new_plane_state,
9045                               struct drm_framebuffer *fb)
9046 {
9047         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9048         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9049         unsigned int pitch;
9050         bool linear;
9051
9052         if (fb->width > new_acrtc->max_cursor_width ||
9053             fb->height > new_acrtc->max_cursor_height) {
9054                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9055                                  new_plane_state->fb->width,
9056                                  new_plane_state->fb->height);
9057                 return -EINVAL;
9058         }
9059         if (new_plane_state->src_w != fb->width << 16 ||
9060             new_plane_state->src_h != fb->height << 16) {
9061                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9062                 return -EINVAL;
9063         }
9064
9065         /* Pitch in pixels */
9066         pitch = fb->pitches[0] / fb->format->cpp[0];
9067
9068         if (fb->width != pitch) {
9069                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9070                                  fb->width, pitch);
9071                 return -EINVAL;
9072         }
9073
9074         switch (pitch) {
9075         case 64:
9076         case 128:
9077         case 256:
9078                 /* FB pitch is supported by cursor plane */
9079                 break;
9080         default:
9081                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9082                 return -EINVAL;
9083         }
9084
9085         /* Core DRM takes care of checking FB modifiers, so we only need to
9086          * check tiling flags when the FB doesn't have a modifier. */
9087         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9088                 if (adev->family < AMDGPU_FAMILY_AI) {
9089                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9090                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9091                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9092                 } else {
9093                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9094                 }
9095                 if (!linear) {
9096                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9097                         return -EINVAL;
9098                 }
9099         }
9100
9101         return 0;
9102 }
9103
9104 static int dm_update_plane_state(struct dc *dc,
9105                                  struct drm_atomic_state *state,
9106                                  struct drm_plane *plane,
9107                                  struct drm_plane_state *old_plane_state,
9108                                  struct drm_plane_state *new_plane_state,
9109                                  bool enable,
9110                                  bool *lock_and_validation_needed)
9111 {
9112
9113         struct dm_atomic_state *dm_state = NULL;
9114         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9115         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9116         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9117         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9118         struct amdgpu_crtc *new_acrtc;
9119         bool needs_reset;
9120         int ret = 0;
9121
9122
9123         new_plane_crtc = new_plane_state->crtc;
9124         old_plane_crtc = old_plane_state->crtc;
9125         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9126         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9127
9128         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9129                 if (!enable || !new_plane_crtc ||
9130                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9131                         return 0;
9132
9133                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9134
9135                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9136                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9137                         return -EINVAL;
9138                 }
9139
9140                 if (new_plane_state->fb) {
9141                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9142                                                  new_plane_state->fb);
9143                         if (ret)
9144                                 return ret;
9145                 }
9146
9147                 return 0;
9148         }
9149
9150         needs_reset = should_reset_plane(state, plane, old_plane_state,
9151                                          new_plane_state);
9152
9153         /* Remove any changed/removed planes */
9154         if (!enable) {
9155                 if (!needs_reset)
9156                         return 0;
9157
9158                 if (!old_plane_crtc)
9159                         return 0;
9160
9161                 old_crtc_state = drm_atomic_get_old_crtc_state(
9162                                 state, old_plane_crtc);
9163                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9164
9165                 if (!dm_old_crtc_state->stream)
9166                         return 0;
9167
9168                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9169                                 plane->base.id, old_plane_crtc->base.id);
9170
9171                 ret = dm_atomic_get_state(state, &dm_state);
9172                 if (ret)
9173                         return ret;
9174
9175                 if (!dc_remove_plane_from_context(
9176                                 dc,
9177                                 dm_old_crtc_state->stream,
9178                                 dm_old_plane_state->dc_state,
9179                                 dm_state->context)) {
9180
9181                         return -EINVAL;
9182                 }
9183
9184
9185                 dc_plane_state_release(dm_old_plane_state->dc_state);
9186                 dm_new_plane_state->dc_state = NULL;
9187
9188                 *lock_and_validation_needed = true;
9189
9190         } else { /* Add new planes */
9191                 struct dc_plane_state *dc_new_plane_state;
9192
9193                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9194                         return 0;
9195
9196                 if (!new_plane_crtc)
9197                         return 0;
9198
9199                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9200                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9201
9202                 if (!dm_new_crtc_state->stream)
9203                         return 0;
9204
9205                 if (!needs_reset)
9206                         return 0;
9207
9208                 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9209                 if (ret)
9210                         return ret;
9211
9212                 WARN_ON(dm_new_plane_state->dc_state);
9213
9214                 dc_new_plane_state = dc_create_plane_state(dc);
9215                 if (!dc_new_plane_state)
9216                         return -ENOMEM;
9217
9218                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9219                                  plane->base.id, new_plane_crtc->base.id);
9220
9221                 ret = fill_dc_plane_attributes(
9222                         drm_to_adev(new_plane_crtc->dev),
9223                         dc_new_plane_state,
9224                         new_plane_state,
9225                         new_crtc_state);
9226                 if (ret) {
9227                         dc_plane_state_release(dc_new_plane_state);
9228                         return ret;
9229                 }
9230
9231                 ret = dm_atomic_get_state(state, &dm_state);
9232                 if (ret) {
9233                         dc_plane_state_release(dc_new_plane_state);
9234                         return ret;
9235                 }
9236
9237                 /*
9238                  * Any atomic check errors that occur after this will
9239                  * not need a release. The plane state will be attached
9240                  * to the stream, and therefore part of the atomic
9241                  * state. It'll be released when the atomic state is
9242                  * cleaned.
9243                  */
9244                 if (!dc_add_plane_to_context(
9245                                 dc,
9246                                 dm_new_crtc_state->stream,
9247                                 dc_new_plane_state,
9248                                 dm_state->context)) {
9249
9250                         dc_plane_state_release(dc_new_plane_state);
9251                         return -EINVAL;
9252                 }
9253
9254                 dm_new_plane_state->dc_state = dc_new_plane_state;
9255
9256                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9257
9258                 /* Tell DC to do a full surface update every time there
9259                  * is a plane change. Inefficient, but works for now.
9260                  */
9261                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9262
9263                 *lock_and_validation_needed = true;
9264         }
9265
9266
9267         return ret;
9268 }
9269
9270 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9271                                        int *src_w, int *src_h)
9272 {
9273         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9274         case DRM_MODE_ROTATE_90:
9275         case DRM_MODE_ROTATE_270:
9276                 *src_w = plane_state->src_h >> 16;
9277                 *src_h = plane_state->src_w >> 16;
9278                 break;
9279         case DRM_MODE_ROTATE_0:
9280         case DRM_MODE_ROTATE_180:
9281         default:
9282                 *src_w = plane_state->src_w >> 16;
9283                 *src_h = plane_state->src_h >> 16;
9284                 break;
9285         }
9286 }
9287
9288 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9289                                 struct drm_crtc *crtc,
9290                                 struct drm_crtc_state *new_crtc_state)
9291 {
9292         struct drm_plane *cursor = crtc->cursor, *underlying;
9293         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9294         int i;
9295         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9296         int cursor_src_w, cursor_src_h;
9297         int underlying_src_w, underlying_src_h;
9298
9299         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9300          * cursor per pipe but it's going to inherit the scaling and
9301          * positioning from the underlying pipe. Check the cursor plane's
9302          * blending properties match the underlying planes'. */
9303
9304         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9305         if (!new_cursor_state || !new_cursor_state->fb) {
9306                 return 0;
9307         }
9308
9309         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9310         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9311         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9312
9313         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9314                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9315                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9316                         continue;
9317
9318                 /* Ignore disabled planes */
9319                 if (!new_underlying_state->fb)
9320                         continue;
9321
9322                 dm_get_oriented_plane_size(new_underlying_state,
9323                                            &underlying_src_w, &underlying_src_h);
9324                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9325                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9326
9327                 if (cursor_scale_w != underlying_scale_w ||
9328                     cursor_scale_h != underlying_scale_h) {
9329                         drm_dbg_atomic(crtc->dev,
9330                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9331                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9332                         return -EINVAL;
9333                 }
9334
9335                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9336                 if (new_underlying_state->crtc_x <= 0 &&
9337                     new_underlying_state->crtc_y <= 0 &&
9338                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9339                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9340                         break;
9341         }
9342
9343         return 0;
9344 }
9345
9346 #if defined(CONFIG_DRM_AMD_DC_DCN)
9347 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9348 {
9349         struct drm_connector *connector;
9350         struct drm_connector_state *conn_state, *old_conn_state;
9351         struct amdgpu_dm_connector *aconnector = NULL;
9352         int i;
9353         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9354                 if (!conn_state->crtc)
9355                         conn_state = old_conn_state;
9356
9357                 if (conn_state->crtc != crtc)
9358                         continue;
9359
9360                 aconnector = to_amdgpu_dm_connector(connector);
9361                 if (!aconnector->port || !aconnector->mst_port)
9362                         aconnector = NULL;
9363                 else
9364                         break;
9365         }
9366
9367         if (!aconnector)
9368                 return 0;
9369
9370         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9371 }
9372 #endif
9373
9374 /**
9375  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9376  *
9377  * @dev: The DRM device
9378  * @state: The atomic state to commit
9379  *
9380  * Validate that the given atomic state is programmable by DC into hardware.
9381  * This involves constructing a &struct dc_state reflecting the new hardware
9382  * state we wish to commit, then querying DC to see if it is programmable. It's
9383  * important not to modify the existing DC state. Otherwise, atomic_check
9384  * may unexpectedly commit hardware changes.
9385  *
9386  * When validating the DC state, it's important that the right locks are
9387  * acquired. For full updates case which removes/adds/updates streams on one
9388  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9389  * that any such full update commit will wait for completion of any outstanding
9390  * flip using DRMs synchronization events.
9391  *
9392  * Note that DM adds the affected connectors for all CRTCs in state, when that
9393  * might not seem necessary. This is because DC stream creation requires the
9394  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9395  * be possible but non-trivial - a possible TODO item.
9396  *
9397  * Return: -Error code if validation failed.
9398  */
9399 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9400                                   struct drm_atomic_state *state)
9401 {
9402         struct amdgpu_device *adev = drm_to_adev(dev);
9403         struct dm_atomic_state *dm_state = NULL;
9404         struct dc *dc = adev->dm.dc;
9405         struct drm_connector *connector;
9406         struct drm_connector_state *old_con_state, *new_con_state;
9407         struct drm_crtc *crtc;
9408         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9409         struct drm_plane *plane;
9410         struct drm_plane_state *old_plane_state, *new_plane_state;
9411         enum dc_status status;
9412         int ret, i;
9413         bool lock_and_validation_needed = false;
9414         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9415 #if defined(CONFIG_DRM_AMD_DC_DCN)
9416         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9417 #endif
9418
9419         trace_amdgpu_dm_atomic_check_begin(state);
9420
9421         ret = drm_atomic_helper_check_modeset(dev, state);
9422         if (ret) {
9423                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9424                 goto fail;
9425         }
9426
9427         /* Check connector changes */
9428         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9429                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9430                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9431
9432                 /* Skip connectors that are disabled or part of modeset already. */
9433                 if (!new_con_state->crtc)
9434                         continue;
9435
9436                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9437                 if (IS_ERR(new_crtc_state)) {
9438                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9439                         ret = PTR_ERR(new_crtc_state);
9440                         goto fail;
9441                 }
9442
9443                 if (dm_old_con_state->abm_level !=
9444                     dm_new_con_state->abm_level)
9445                         new_crtc_state->connectors_changed = true;
9446         }
9447
9448 #if defined(CONFIG_DRM_AMD_DC_DCN)
9449         if (dc_resource_is_dsc_encoding_supported(dc)) {
9450                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9451                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9452                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9453                                 if (ret) {
9454                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9455                                         goto fail;
9456                                 }
9457                         }
9458                 }
9459         }
9460 #endif
9461         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9462                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9463
9464                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9465                     !new_crtc_state->color_mgmt_changed &&
9466                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9467                         dm_old_crtc_state->dsc_force_changed == false)
9468                         continue;
9469
9470                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9471                 if (ret) {
9472                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9473                         goto fail;
9474                 }
9475
9476                 if (!new_crtc_state->enable)
9477                         continue;
9478
9479                 ret = drm_atomic_add_affected_connectors(state, crtc);
9480                 if (ret) {
9481                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9482                         goto fail;
9483                 }
9484
9485                 ret = drm_atomic_add_affected_planes(state, crtc);
9486                 if (ret) {
9487                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9488                         goto fail;
9489                 }
9490
9491                 if (dm_old_crtc_state->dsc_force_changed)
9492                         new_crtc_state->mode_changed = true;
9493         }
9494
9495         /*
9496          * Add all primary and overlay planes on the CRTC to the state
9497          * whenever a plane is enabled to maintain correct z-ordering
9498          * and to enable fast surface updates.
9499          */
9500         drm_for_each_crtc(crtc, dev) {
9501                 bool modified = false;
9502
9503                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9504                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9505                                 continue;
9506
9507                         if (new_plane_state->crtc == crtc ||
9508                             old_plane_state->crtc == crtc) {
9509                                 modified = true;
9510                                 break;
9511                         }
9512                 }
9513
9514                 if (!modified)
9515                         continue;
9516
9517                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9518                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9519                                 continue;
9520
9521                         new_plane_state =
9522                                 drm_atomic_get_plane_state(state, plane);
9523
9524                         if (IS_ERR(new_plane_state)) {
9525                                 ret = PTR_ERR(new_plane_state);
9526                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9527                                 goto fail;
9528                         }
9529                 }
9530         }
9531
9532         /*
9533          * DC consults the zpos (layer_index in DC terminology) to determine the
9534          * hw plane on which to enable the hw cursor (see
9535          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9536          * atomic state, so call drm helper to normalize zpos.
9537          */
9538         drm_atomic_normalize_zpos(dev, state);
9539
9540         /* Remove exiting planes if they are modified */
9541         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9542                 ret = dm_update_plane_state(dc, state, plane,
9543                                             old_plane_state,
9544                                             new_plane_state,
9545                                             false,
9546                                             &lock_and_validation_needed);
9547                 if (ret) {
9548                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9549                         goto fail;
9550                 }
9551         }
9552
9553         /* Disable all crtcs which require disable */
9554         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9555                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9556                                            old_crtc_state,
9557                                            new_crtc_state,
9558                                            false,
9559                                            &lock_and_validation_needed);
9560                 if (ret) {
9561                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
9562                         goto fail;
9563                 }
9564         }
9565
9566         /* Enable all crtcs which require enable */
9567         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9568                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9569                                            old_crtc_state,
9570                                            new_crtc_state,
9571                                            true,
9572                                            &lock_and_validation_needed);
9573                 if (ret) {
9574                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
9575                         goto fail;
9576                 }
9577         }
9578
9579         /* Add new/modified planes */
9580         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9581                 ret = dm_update_plane_state(dc, state, plane,
9582                                             old_plane_state,
9583                                             new_plane_state,
9584                                             true,
9585                                             &lock_and_validation_needed);
9586                 if (ret) {
9587                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9588                         goto fail;
9589                 }
9590         }
9591
9592 #if defined(CONFIG_DRM_AMD_DC_DCN)
9593         if (dc_resource_is_dsc_encoding_supported(dc)) {
9594                 if (!pre_validate_dsc(state, &dm_state, vars)) {
9595                         ret = -EINVAL;
9596                         goto fail;
9597                 }
9598         }
9599 #endif
9600
9601         /* Run this here since we want to validate the streams we created */
9602         ret = drm_atomic_helper_check_planes(dev, state);
9603         if (ret) {
9604                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
9605                 goto fail;
9606         }
9607
9608         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9609                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9610                 if (dm_new_crtc_state->mpo_requested)
9611                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9612         }
9613
9614         /* Check cursor planes scaling */
9615         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9616                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9617                 if (ret) {
9618                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
9619                         goto fail;
9620                 }
9621         }
9622
9623         if (state->legacy_cursor_update) {
9624                 /*
9625                  * This is a fast cursor update coming from the plane update
9626                  * helper, check if it can be done asynchronously for better
9627                  * performance.
9628                  */
9629                 state->async_update =
9630                         !drm_atomic_helper_async_check(dev, state);
9631
9632                 /*
9633                  * Skip the remaining global validation if this is an async
9634                  * update. Cursor updates can be done without affecting
9635                  * state or bandwidth calcs and this avoids the performance
9636                  * penalty of locking the private state object and
9637                  * allocating a new dc_state.
9638                  */
9639                 if (state->async_update)
9640                         return 0;
9641         }
9642
9643         /* Check scaling and underscan changes*/
9644         /* TODO Removed scaling changes validation due to inability to commit
9645          * new stream into context w\o causing full reset. Need to
9646          * decide how to handle.
9647          */
9648         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9649                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9650                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9651                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9652
9653                 /* Skip any modesets/resets */
9654                 if (!acrtc || drm_atomic_crtc_needs_modeset(
9655                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9656                         continue;
9657
9658                 /* Skip any thing not scale or underscan changes */
9659                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9660                         continue;
9661
9662                 lock_and_validation_needed = true;
9663         }
9664
9665         /**
9666          * Streams and planes are reset when there are changes that affect
9667          * bandwidth. Anything that affects bandwidth needs to go through
9668          * DC global validation to ensure that the configuration can be applied
9669          * to hardware.
9670          *
9671          * We have to currently stall out here in atomic_check for outstanding
9672          * commits to finish in this case because our IRQ handlers reference
9673          * DRM state directly - we can end up disabling interrupts too early
9674          * if we don't.
9675          *
9676          * TODO: Remove this stall and drop DM state private objects.
9677          */
9678         if (lock_and_validation_needed) {
9679                 ret = dm_atomic_get_state(state, &dm_state);
9680                 if (ret) {
9681                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
9682                         goto fail;
9683                 }
9684
9685                 ret = do_aquire_global_lock(dev, state);
9686                 if (ret) {
9687                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
9688                         goto fail;
9689                 }
9690
9691 #if defined(CONFIG_DRM_AMD_DC_DCN)
9692                 if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) {
9693                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
9694                         ret = -EINVAL;
9695                         goto fail;
9696                 }
9697
9698                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
9699                 if (ret) {
9700                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
9701                         goto fail;
9702                 }
9703 #endif
9704
9705                 /*
9706                  * Perform validation of MST topology in the state:
9707                  * We need to perform MST atomic check before calling
9708                  * dc_validate_global_state(), or there is a chance
9709                  * to get stuck in an infinite loop and hang eventually.
9710                  */
9711                 ret = drm_dp_mst_atomic_check(state);
9712                 if (ret) {
9713                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
9714                         goto fail;
9715                 }
9716                 status = dc_validate_global_state(dc, dm_state->context, true);
9717                 if (status != DC_OK) {
9718                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
9719                                        dc_status_to_str(status), status);
9720                         ret = -EINVAL;
9721                         goto fail;
9722                 }
9723         } else {
9724                 /*
9725                  * The commit is a fast update. Fast updates shouldn't change
9726                  * the DC context, affect global validation, and can have their
9727                  * commit work done in parallel with other commits not touching
9728                  * the same resource. If we have a new DC context as part of
9729                  * the DM atomic state from validation we need to free it and
9730                  * retain the existing one instead.
9731                  *
9732                  * Furthermore, since the DM atomic state only contains the DC
9733                  * context and can safely be annulled, we can free the state
9734                  * and clear the associated private object now to free
9735                  * some memory and avoid a possible use-after-free later.
9736                  */
9737
9738                 for (i = 0; i < state->num_private_objs; i++) {
9739                         struct drm_private_obj *obj = state->private_objs[i].ptr;
9740
9741                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
9742                                 int j = state->num_private_objs-1;
9743
9744                                 dm_atomic_destroy_state(obj,
9745                                                 state->private_objs[i].state);
9746
9747                                 /* If i is not at the end of the array then the
9748                                  * last element needs to be moved to where i was
9749                                  * before the array can safely be truncated.
9750                                  */
9751                                 if (i != j)
9752                                         state->private_objs[i] =
9753                                                 state->private_objs[j];
9754
9755                                 state->private_objs[j].ptr = NULL;
9756                                 state->private_objs[j].state = NULL;
9757                                 state->private_objs[j].old_state = NULL;
9758                                 state->private_objs[j].new_state = NULL;
9759
9760                                 state->num_private_objs = j;
9761                                 break;
9762                         }
9763                 }
9764         }
9765
9766         /* Store the overall update type for use later in atomic check. */
9767         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
9768                 struct dm_crtc_state *dm_new_crtc_state =
9769                         to_dm_crtc_state(new_crtc_state);
9770
9771                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
9772                                                          UPDATE_TYPE_FULL :
9773                                                          UPDATE_TYPE_FAST;
9774         }
9775
9776         /* Must be success */
9777         WARN_ON(ret);
9778
9779         trace_amdgpu_dm_atomic_check_finish(state, ret);
9780
9781         return ret;
9782
9783 fail:
9784         if (ret == -EDEADLK)
9785                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
9786         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
9787                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
9788         else
9789                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
9790
9791         trace_amdgpu_dm_atomic_check_finish(state, ret);
9792
9793         return ret;
9794 }
9795
9796 static bool is_dp_capable_without_timing_msa(struct dc *dc,
9797                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
9798 {
9799         uint8_t dpcd_data;
9800         bool capable = false;
9801
9802         if (amdgpu_dm_connector->dc_link &&
9803                 dm_helpers_dp_read_dpcd(
9804                                 NULL,
9805                                 amdgpu_dm_connector->dc_link,
9806                                 DP_DOWN_STREAM_PORT_COUNT,
9807                                 &dpcd_data,
9808                                 sizeof(dpcd_data))) {
9809                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
9810         }
9811
9812         return capable;
9813 }
9814
9815 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
9816                 unsigned int offset,
9817                 unsigned int total_length,
9818                 uint8_t *data,
9819                 unsigned int length,
9820                 struct amdgpu_hdmi_vsdb_info *vsdb)
9821 {
9822         bool res;
9823         union dmub_rb_cmd cmd;
9824         struct dmub_cmd_send_edid_cea *input;
9825         struct dmub_cmd_edid_cea_output *output;
9826
9827         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
9828                 return false;
9829
9830         memset(&cmd, 0, sizeof(cmd));
9831
9832         input = &cmd.edid_cea.data.input;
9833
9834         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
9835         cmd.edid_cea.header.sub_type = 0;
9836         cmd.edid_cea.header.payload_bytes =
9837                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
9838         input->offset = offset;
9839         input->length = length;
9840         input->cea_total_length = total_length;
9841         memcpy(input->payload, data, length);
9842
9843         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
9844         if (!res) {
9845                 DRM_ERROR("EDID CEA parser failed\n");
9846                 return false;
9847         }
9848
9849         output = &cmd.edid_cea.data.output;
9850
9851         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
9852                 if (!output->ack.success) {
9853                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
9854                                         output->ack.offset);
9855                 }
9856         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
9857                 if (!output->amd_vsdb.vsdb_found)
9858                         return false;
9859
9860                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
9861                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
9862                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
9863                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
9864         } else {
9865                 DRM_WARN("Unknown EDID CEA parser results\n");
9866                 return false;
9867         }
9868
9869         return true;
9870 }
9871
9872 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
9873                 uint8_t *edid_ext, int len,
9874                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9875 {
9876         int i;
9877
9878         /* send extension block to DMCU for parsing */
9879         for (i = 0; i < len; i += 8) {
9880                 bool res;
9881                 int offset;
9882
9883                 /* send 8 bytes a time */
9884                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
9885                         return false;
9886
9887                 if (i+8 == len) {
9888                         /* EDID block sent completed, expect result */
9889                         int version, min_rate, max_rate;
9890
9891                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
9892                         if (res) {
9893                                 /* amd vsdb found */
9894                                 vsdb_info->freesync_supported = 1;
9895                                 vsdb_info->amd_vsdb_version = version;
9896                                 vsdb_info->min_refresh_rate_hz = min_rate;
9897                                 vsdb_info->max_refresh_rate_hz = max_rate;
9898                                 return true;
9899                         }
9900                         /* not amd vsdb */
9901                         return false;
9902                 }
9903
9904                 /* check for ack*/
9905                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
9906                 if (!res)
9907                         return false;
9908         }
9909
9910         return false;
9911 }
9912
9913 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
9914                 uint8_t *edid_ext, int len,
9915                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9916 {
9917         int i;
9918
9919         /* send extension block to DMCU for parsing */
9920         for (i = 0; i < len; i += 8) {
9921                 /* send 8 bytes a time */
9922                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
9923                         return false;
9924         }
9925
9926         return vsdb_info->freesync_supported;
9927 }
9928
9929 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
9930                 uint8_t *edid_ext, int len,
9931                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9932 {
9933         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
9934
9935         if (adev->dm.dmub_srv)
9936                 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
9937         else
9938                 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
9939 }
9940
9941 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
9942                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
9943 {
9944         uint8_t *edid_ext = NULL;
9945         int i;
9946         bool valid_vsdb_found = false;
9947
9948         /*----- drm_find_cea_extension() -----*/
9949         /* No EDID or EDID extensions */
9950         if (edid == NULL || edid->extensions == 0)
9951                 return -ENODEV;
9952
9953         /* Find CEA extension */
9954         for (i = 0; i < edid->extensions; i++) {
9955                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
9956                 if (edid_ext[0] == CEA_EXT)
9957                         break;
9958         }
9959
9960         if (i == edid->extensions)
9961                 return -ENODEV;
9962
9963         /*----- cea_db_offsets() -----*/
9964         if (edid_ext[0] != CEA_EXT)
9965                 return -ENODEV;
9966
9967         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
9968
9969         return valid_vsdb_found ? i : -ENODEV;
9970 }
9971
9972 /**
9973  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
9974  *
9975  * @connector: Connector to query.
9976  * @edid: EDID from monitor
9977  *
9978  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
9979  * track of some of the display information in the internal data struct used by
9980  * amdgpu_dm. This function checks which type of connector we need to set the
9981  * FreeSync parameters.
9982  */
9983 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
9984                                     struct edid *edid)
9985 {
9986         int i = 0;
9987         struct detailed_timing *timing;
9988         struct detailed_non_pixel *data;
9989         struct detailed_data_monitor_range *range;
9990         struct amdgpu_dm_connector *amdgpu_dm_connector =
9991                         to_amdgpu_dm_connector(connector);
9992         struct dm_connector_state *dm_con_state = NULL;
9993         struct dc_sink *sink;
9994
9995         struct drm_device *dev = connector->dev;
9996         struct amdgpu_device *adev = drm_to_adev(dev);
9997         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
9998         bool freesync_capable = false;
9999
10000         if (!connector->state) {
10001                 DRM_ERROR("%s - Connector has no state", __func__);
10002                 goto update;
10003         }
10004
10005         sink = amdgpu_dm_connector->dc_sink ?
10006                 amdgpu_dm_connector->dc_sink :
10007                 amdgpu_dm_connector->dc_em_sink;
10008
10009         if (!edid || !sink) {
10010                 dm_con_state = to_dm_connector_state(connector->state);
10011
10012                 amdgpu_dm_connector->min_vfreq = 0;
10013                 amdgpu_dm_connector->max_vfreq = 0;
10014                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10015                 connector->display_info.monitor_range.min_vfreq = 0;
10016                 connector->display_info.monitor_range.max_vfreq = 0;
10017                 freesync_capable = false;
10018
10019                 goto update;
10020         }
10021
10022         dm_con_state = to_dm_connector_state(connector->state);
10023
10024         if (!adev->dm.freesync_module)
10025                 goto update;
10026
10027         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10028                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10029                 bool edid_check_required = false;
10030
10031                 if (edid) {
10032                         edid_check_required = is_dp_capable_without_timing_msa(
10033                                                 adev->dm.dc,
10034                                                 amdgpu_dm_connector);
10035                 }
10036
10037                 if (edid_check_required == true && (edid->version > 1 ||
10038                    (edid->version == 1 && edid->revision > 1))) {
10039                         for (i = 0; i < 4; i++) {
10040
10041                                 timing  = &edid->detailed_timings[i];
10042                                 data    = &timing->data.other_data;
10043                                 range   = &data->data.range;
10044                                 /*
10045                                  * Check if monitor has continuous frequency mode
10046                                  */
10047                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10048                                         continue;
10049                                 /*
10050                                  * Check for flag range limits only. If flag == 1 then
10051                                  * no additional timing information provided.
10052                                  * Default GTF, GTF Secondary curve and CVT are not
10053                                  * supported
10054                                  */
10055                                 if (range->flags != 1)
10056                                         continue;
10057
10058                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10059                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10060                                 amdgpu_dm_connector->pixel_clock_mhz =
10061                                         range->pixel_clock_mhz * 10;
10062
10063                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10064                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10065
10066                                 break;
10067                         }
10068
10069                         if (amdgpu_dm_connector->max_vfreq -
10070                             amdgpu_dm_connector->min_vfreq > 10) {
10071
10072                                 freesync_capable = true;
10073                         }
10074                 }
10075         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10076                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10077                 if (i >= 0 && vsdb_info.freesync_supported) {
10078                         timing  = &edid->detailed_timings[i];
10079                         data    = &timing->data.other_data;
10080
10081                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10082                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10083                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10084                                 freesync_capable = true;
10085
10086                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10087                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10088                 }
10089         }
10090
10091 update:
10092         if (dm_con_state)
10093                 dm_con_state->freesync_capable = freesync_capable;
10094
10095         if (connector->vrr_capable_property)
10096                 drm_connector_set_vrr_capable_property(connector,
10097                                                        freesync_capable);
10098 }
10099
10100 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10101 {
10102         struct amdgpu_device *adev = drm_to_adev(dev);
10103         struct dc *dc = adev->dm.dc;
10104         int i;
10105
10106         mutex_lock(&adev->dm.dc_lock);
10107         if (dc->current_state) {
10108                 for (i = 0; i < dc->current_state->stream_count; ++i)
10109                         dc->current_state->streams[i]
10110                                 ->triggered_crtc_reset.enabled =
10111                                 adev->dm.force_timing_sync;
10112
10113                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10114                 dc_trigger_sync(dc, dc->current_state);
10115         }
10116         mutex_unlock(&adev->dm.dc_lock);
10117 }
10118
10119 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10120                        uint32_t value, const char *func_name)
10121 {
10122 #ifdef DM_CHECK_ADDR_0
10123         if (address == 0) {
10124                 DC_ERR("invalid register write. address = 0");
10125                 return;
10126         }
10127 #endif
10128         cgs_write_register(ctx->cgs_device, address, value);
10129         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10130 }
10131
10132 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10133                           const char *func_name)
10134 {
10135         uint32_t value;
10136 #ifdef DM_CHECK_ADDR_0
10137         if (address == 0) {
10138                 DC_ERR("invalid register read; address = 0\n");
10139                 return 0;
10140         }
10141 #endif
10142
10143         if (ctx->dmub_srv &&
10144             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10145             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10146                 ASSERT(false);
10147                 return 0;
10148         }
10149
10150         value = cgs_read_register(ctx->cgs_device, address);
10151
10152         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10153
10154         return value;
10155 }
10156
10157 static int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux,
10158                                                 struct dc_context *ctx,
10159                                                 uint8_t status_type,
10160                                                 uint32_t *operation_result)
10161 {
10162         struct amdgpu_device *adev = ctx->driver_context;
10163         int return_status = -1;
10164         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10165
10166         if (is_cmd_aux) {
10167                 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
10168                         return_status = p_notify->aux_reply.length;
10169                         *operation_result = p_notify->result;
10170                 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT) {
10171                         *operation_result = AUX_RET_ERROR_TIMEOUT;
10172                 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_FAIL) {
10173                         *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10174                 } else {
10175                         *operation_result = AUX_RET_ERROR_UNKNOWN;
10176                 }
10177         } else {
10178                 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
10179                         return_status = 0;
10180                         *operation_result = p_notify->sc_status;
10181                 } else {
10182                         *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10183                 }
10184         }
10185
10186         return return_status;
10187 }
10188
10189 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context *ctx,
10190         unsigned int link_index, void *cmd_payload, void *operation_result)
10191 {
10192         struct amdgpu_device *adev = ctx->driver_context;
10193         int ret = 0;
10194
10195         if (is_cmd_aux) {
10196                 dc_process_dmub_aux_transfer_async(ctx->dc,
10197                         link_index, (struct aux_payload *)cmd_payload);
10198         } else if (dc_process_dmub_set_config_async(ctx->dc, link_index,
10199                                         (struct set_config_cmd_payload *)cmd_payload,
10200                                         adev->dm.dmub_notify)) {
10201                 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10202                                         ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
10203                                         (uint32_t *)operation_result);
10204         }
10205
10206         ret = wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ);
10207         if (ret == 0) {
10208                 DRM_ERROR("wait_for_completion_timeout timeout!");
10209                 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10210                                 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT,
10211                                 (uint32_t *)operation_result);
10212         }
10213
10214         if (is_cmd_aux) {
10215                 if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) {
10216                         struct aux_payload *payload = (struct aux_payload *)cmd_payload;
10217
10218                         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10219                         if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
10220                             payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK) {
10221                                 memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
10222                                        adev->dm.dmub_notify->aux_reply.length);
10223                         }
10224                 }
10225         }
10226
10227         return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10228                         ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
10229                         (uint32_t *)operation_result);
10230 }
10231
10232 /*
10233  * Check whether seamless boot is supported.
10234  *
10235  * So far we only support seamless boot on CHIP_VANGOGH.
10236  * If everything goes well, we may consider expanding
10237  * seamless boot to other ASICs.
10238  */
10239 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10240 {
10241         switch (adev->asic_type) {
10242         case CHIP_VANGOGH:
10243                 if (!adev->mman.keep_stolen_vga_memory)
10244                         return true;
10245                 break;
10246         default:
10247                 break;
10248         }
10249
10250         return false;
10251 }