drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "clearstate_gfx10.h"
  47 #include "v10_structs.h"
  48 #include "gfx_v10_0.h"
  49 #include "nbio_v2_3.h"
  50
  51 /**
  52  * Navi10 has two graphic rings to share each graphic pipe.
  53  * 1. Primary ring
  54  * 2. Async ring
  55  */
  56 #define GFX10_NUM_GFX_RINGS_NV1X        1
  57 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  66 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  67 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  68 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  69
  70 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  71 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  72
  73 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  75 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  77 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  79 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  81 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  83 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  85 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  87 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  89 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  91 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  93 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  95 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  97 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  98 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 100
 101 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 102 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 103 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 104 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 105 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 106 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 107 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 108 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 109 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 110 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 111 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 112 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 113 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 114 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 115 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 116 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 117 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 118 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 120 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 121
 122 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 123 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 124 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 125 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 126 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 127 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 128 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 129 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 130 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 131 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 132 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 133 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 134
 135 #define mmCPG_PSP_DEBUG                         0x5c10
 136 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 137 #define mmCPC_PSP_DEBUG                         0x5c11
 138 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 139 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 140 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 141
 142 //CC_GC_SA_UNIT_DISABLE
 143 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 144 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 145 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 146 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 147 //GC_USER_SA_UNIT_DISABLE
 148 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 149 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 150 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 151 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 152 //PA_SC_ENHANCE_3
 153 #define mmPA_SC_ENHANCE_3                       0x1085
 154 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 155 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 156 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 157
 158 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 159 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 160
 161 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 162 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 163 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 164 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 165
 166 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 167 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 168
 169 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 170 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 171 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 172 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 173 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 174 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 175
 176 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 177 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 178 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 179 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 180 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 181 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 182 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 183 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 184 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 185 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 186 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 187
 188 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 189 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 190 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 191 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 192 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 193 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 194
 195 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 196 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 197 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 198 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 199 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 200 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 201
 202 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 203 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 204 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 205 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 206 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 207 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 208
 209 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 210 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 211 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 212 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 213 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 214 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 215
 216 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 217 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 218 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 219 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 220 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 221 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 222
 223 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 224 {
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 265 };
 266
 267 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 268 {
 269         /* Pending on emulation bring up */
 270 };
 271
 272 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 273 {
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1326 };
1327
1328 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1329 {
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1368 };
1369
1370 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1371 {
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1412 };
1413
1414 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1415 {
1416         static void *scratch_reg0;
1417         static void *scratch_reg1;
1418         static void *spare_int;
1419         uint32_t i = 0;
1420         uint32_t retries = 50000;
1421
1422         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1423         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1424         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1425
1426         if (amdgpu_sriov_runtime(adev)) {
1427                 pr_err("shouldn't call rlcg write register during runtime\n");
1428                 return;
1429         }
1430
1431         writel(v, scratch_reg0);
1432         writel(offset | 0x80000000, scratch_reg1);
1433         writel(1, spare_int);
1434         for (i = 0; i < retries; i++) {
1435                 u32 tmp;
1436
1437                 tmp = readl(scratch_reg1);
1438                 if (!(tmp & 0x80000000))
1439                         break;
1440
1441                 udelay(10);
1442         }
1443
1444         if (i >= retries)
1445                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1446 }
1447
1448 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1449 {
1450         /* Pending on emulation bring up */
1451 };
1452
1453 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1454 {
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2075 };
2076
2077 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2078 {
2079         /* Pending on emulation bring up */
2080 };
2081
2082 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2083 {
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3136 };
3137
3138 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3139 {
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3182 };
3183
3184 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3185 {
3186         /* Pending on emulation bring up */
3187 };
3188
3189 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3190 {
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3232
3233         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3235 };
3236
3237 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3238 {
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3262
3263         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3265 };
3266
3267 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3268 {
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3304 };
3305
3306 #define DEFAULT_SH_MEM_CONFIG \
3307         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3308          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3309          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3310          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3311
3312
3313 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3314 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3315 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3316 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3317 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3318                                  struct amdgpu_cu_info *cu_info);
3319 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3320 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3321                                    u32 sh_num, u32 instance);
3322 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3323
3324 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3325 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3326 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3327 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3328 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3329 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3330 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3331 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3332 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3333 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3334
3335 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3336 {
3337         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3338         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3339                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3340         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3341         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3342         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3343         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3344         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3345         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3346 }
3347
3348 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3349                                  struct amdgpu_ring *ring)
3350 {
3351         struct amdgpu_device *adev = kiq_ring->adev;
3352         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3353         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3354         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3355
3356         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3357         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3358         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3359                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3360                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3361                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3362                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3363                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3364                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3365                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3366                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3367                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3368         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3369         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3370         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3371         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3372         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3373 }
3374
3375 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3376                                    struct amdgpu_ring *ring,
3377                                    enum amdgpu_unmap_queues_action action,
3378                                    u64 gpu_addr, u64 seq)
3379 {
3380         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3381
3382         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3383         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3384                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3385                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3386                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3387                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3388         amdgpu_ring_write(kiq_ring,
3389                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3390
3391         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3392                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3393                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3394                 amdgpu_ring_write(kiq_ring, seq);
3395         } else {
3396                 amdgpu_ring_write(kiq_ring, 0);
3397                 amdgpu_ring_write(kiq_ring, 0);
3398                 amdgpu_ring_write(kiq_ring, 0);
3399         }
3400 }
3401
3402 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3403                                    struct amdgpu_ring *ring,
3404                                    u64 addr,
3405                                    u64 seq)
3406 {
3407         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3408
3409         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3410         amdgpu_ring_write(kiq_ring,
3411                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3412                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3413                           PACKET3_QUERY_STATUS_COMMAND(2));
3414         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3415                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3416                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3417         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3418         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3419         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3420         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3421 }
3422
3423 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3424                                 uint16_t pasid, uint32_t flush_type,
3425                                 bool all_hub)
3426 {
3427         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3428         amdgpu_ring_write(kiq_ring,
3429                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3430                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3431                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3432                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3433 }
3434
3435 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3436         .kiq_set_resources = gfx10_kiq_set_resources,
3437         .kiq_map_queues = gfx10_kiq_map_queues,
3438         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3439         .kiq_query_status = gfx10_kiq_query_status,
3440         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3441         .set_resources_size = 8,
3442         .map_queues_size = 7,
3443         .unmap_queues_size = 6,
3444         .query_status_size = 7,
3445         .invalidate_tlbs_size = 2,
3446 };
3447
3448 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3449 {
3450         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3451 }
3452
3453 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3454 {
3455         switch (adev->asic_type) {
3456         case CHIP_NAVI10:
3457                 soc15_program_register_sequence(adev,
3458                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3459                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3460                 break;
3461         case CHIP_NAVI14:
3462                 soc15_program_register_sequence(adev,
3463                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3464                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3465                 break;
3466         case CHIP_NAVI12:
3467                 soc15_program_register_sequence(adev,
3468                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3469                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3470                 break;
3471         default:
3472                 break;
3473         }
3474 }
3475
3476 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3477 {
3478         switch (adev->asic_type) {
3479         case CHIP_NAVI10:
3480                 soc15_program_register_sequence(adev,
3481                                                 golden_settings_gc_10_1,
3482                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3483                 soc15_program_register_sequence(adev,
3484                                                 golden_settings_gc_10_0_nv10,
3485                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3486                 break;
3487         case CHIP_NAVI14:
3488                 soc15_program_register_sequence(adev,
3489                                                 golden_settings_gc_10_1_1,
3490                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3491                 soc15_program_register_sequence(adev,
3492                                                 golden_settings_gc_10_1_nv14,
3493                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3494                 break;
3495         case CHIP_NAVI12:
3496                 soc15_program_register_sequence(adev,
3497                                                 golden_settings_gc_10_1_2,
3498                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3499                 soc15_program_register_sequence(adev,
3500                                                 golden_settings_gc_10_1_2_nv12,
3501                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3502                 break;
3503         case CHIP_SIENNA_CICHLID:
3504                 soc15_program_register_sequence(adev,
3505                                                 golden_settings_gc_10_3,
3506                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3507                 soc15_program_register_sequence(adev,
3508                                                 golden_settings_gc_10_3_sienna_cichlid,
3509                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3510                 break;
3511         case CHIP_NAVY_FLOUNDER:
3512                 soc15_program_register_sequence(adev,
3513                                                 golden_settings_gc_10_3_2,
3514                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3515                 break;
3516         case CHIP_VANGOGH:
3517                 soc15_program_register_sequence(adev,
3518                                                 golden_settings_gc_10_3_vangogh,
3519                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3520                 break;
3521         case CHIP_DIMGREY_CAVEFISH:
3522                 soc15_program_register_sequence(adev,
3523                                                 golden_settings_gc_10_3_4,
3524                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3525                 break;
3526         default:
3527                 break;
3528         }
3529         gfx_v10_0_init_spm_golden_registers(adev);
3530 }
3531
3532 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3533 {
3534         adev->gfx.scratch.num_reg = 8;
3535         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3536         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3537 }
3538
3539 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3540                                        bool wc, uint32_t reg, uint32_t val)
3541 {
3542         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3543         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3544                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3545         amdgpu_ring_write(ring, reg);
3546         amdgpu_ring_write(ring, 0);
3547         amdgpu_ring_write(ring, val);
3548 }
3549
3550 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3551                                   int mem_space, int opt, uint32_t addr0,
3552                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3553                                   uint32_t inv)
3554 {
3555         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3556         amdgpu_ring_write(ring,
3557                           /* memory (1) or register (0) */
3558                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3559                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3560                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3561                            WAIT_REG_MEM_ENGINE(eng_sel)));
3562
3563         if (mem_space)
3564                 BUG_ON(addr0 & 0x3); /* Dword align */
3565         amdgpu_ring_write(ring, addr0);
3566         amdgpu_ring_write(ring, addr1);
3567         amdgpu_ring_write(ring, ref);
3568         amdgpu_ring_write(ring, mask);
3569         amdgpu_ring_write(ring, inv); /* poll interval */
3570 }
3571
3572 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3573 {
3574         struct amdgpu_device *adev = ring->adev;
3575         uint32_t scratch;
3576         uint32_t tmp = 0;
3577         unsigned i;
3578         int r;
3579
3580         r = amdgpu_gfx_scratch_get(adev, &scratch);
3581         if (r) {
3582                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3583                 return r;
3584         }
3585
3586         WREG32(scratch, 0xCAFEDEAD);
3587
3588         r = amdgpu_ring_alloc(ring, 3);
3589         if (r) {
3590                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3591                           ring->idx, r);
3592                 amdgpu_gfx_scratch_free(adev, scratch);
3593                 return r;
3594         }
3595
3596         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3597         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3598         amdgpu_ring_write(ring, 0xDEADBEEF);
3599         amdgpu_ring_commit(ring);
3600
3601         for (i = 0; i < adev->usec_timeout; i++) {
3602                 tmp = RREG32(scratch);
3603                 if (tmp == 0xDEADBEEF)
3604                         break;
3605                 if (amdgpu_emu_mode == 1)
3606                         msleep(1);
3607                 else
3608                         udelay(1);
3609         }
3610
3611         if (i >= adev->usec_timeout)
3612                 r = -ETIMEDOUT;
3613
3614         amdgpu_gfx_scratch_free(adev, scratch);
3615
3616         return r;
3617 }
3618
3619 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3620 {
3621         struct amdgpu_device *adev = ring->adev;
3622         struct amdgpu_ib ib;
3623         struct dma_fence *f = NULL;
3624         unsigned index;
3625         uint64_t gpu_addr;
3626         uint32_t tmp;
3627         long r;
3628
3629         r = amdgpu_device_wb_get(adev, &index);
3630         if (r)
3631                 return r;
3632
3633         gpu_addr = adev->wb.gpu_addr + (index * 4);
3634         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3635         memset(&ib, 0, sizeof(ib));
3636         r = amdgpu_ib_get(adev, NULL, 16,
3637                                         AMDGPU_IB_POOL_DIRECT, &ib);
3638         if (r)
3639                 goto err1;
3640
3641         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3642         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3643         ib.ptr[2] = lower_32_bits(gpu_addr);
3644         ib.ptr[3] = upper_32_bits(gpu_addr);
3645         ib.ptr[4] = 0xDEADBEEF;
3646         ib.length_dw = 5;
3647
3648         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3649         if (r)
3650                 goto err2;
3651
3652         r = dma_fence_wait_timeout(f, false, timeout);
3653         if (r == 0) {
3654                 r = -ETIMEDOUT;
3655                 goto err2;
3656         } else if (r < 0) {
3657                 goto err2;
3658         }
3659
3660         tmp = adev->wb.wb[index];
3661         if (tmp == 0xDEADBEEF)
3662                 r = 0;
3663         else
3664                 r = -EINVAL;
3665 err2:
3666         amdgpu_ib_free(adev, &ib, NULL);
3667         dma_fence_put(f);
3668 err1:
3669         amdgpu_device_wb_free(adev, index);
3670         return r;
3671 }
3672
3673 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3674 {
3675         release_firmware(adev->gfx.pfp_fw);
3676         adev->gfx.pfp_fw = NULL;
3677         release_firmware(adev->gfx.me_fw);
3678         adev->gfx.me_fw = NULL;
3679         release_firmware(adev->gfx.ce_fw);
3680         adev->gfx.ce_fw = NULL;
3681         release_firmware(adev->gfx.rlc_fw);
3682         adev->gfx.rlc_fw = NULL;
3683         release_firmware(adev->gfx.mec_fw);
3684         adev->gfx.mec_fw = NULL;
3685         release_firmware(adev->gfx.mec2_fw);
3686         adev->gfx.mec2_fw = NULL;
3687
3688         kfree(adev->gfx.rlc.register_list_format);
3689 }
3690
3691 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3692 {
3693         adev->gfx.cp_fw_write_wait = false;
3694
3695         switch (adev->asic_type) {
3696         case CHIP_NAVI10:
3697         case CHIP_NAVI12:
3698         case CHIP_NAVI14:
3699                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3700                     (adev->gfx.me_feature_version >= 27) &&
3701                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3702                     (adev->gfx.pfp_feature_version >= 27) &&
3703                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3704                     (adev->gfx.mec_feature_version >= 27))
3705                         adev->gfx.cp_fw_write_wait = true;
3706                 break;
3707         case CHIP_SIENNA_CICHLID:
3708         case CHIP_NAVY_FLOUNDER:
3709         case CHIP_VANGOGH:
3710         case CHIP_DIMGREY_CAVEFISH:
3711                 adev->gfx.cp_fw_write_wait = true;
3712                 break;
3713         default:
3714                 break;
3715         }
3716
3717         if (!adev->gfx.cp_fw_write_wait)
3718                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3719 }
3720
3721
3722 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3723 {
3724         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3725
3726         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3727         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3728         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3729         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3730         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3731         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3732         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3733         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3734         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3735         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3736         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3737         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3738         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3739         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3740                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3741 }
3742
3743 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3744 {
3745         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3746
3747         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3748         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3749         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3750         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3751         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3752 }
3753
3754 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3755 {
3756         bool ret = false;
3757
3758         switch (adev->pdev->revision) {
3759         case 0xc2:
3760         case 0xc3:
3761                 ret = true;
3762                 break;
3763         default:
3764                 ret = false;
3765                 break;
3766         }
3767
3768         return ret ;
3769 }
3770
3771 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3772 {
3773         switch (adev->asic_type) {
3774         case CHIP_NAVI10:
3775                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3776                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3777                 break;
3778         case CHIP_VANGOGH:
3779                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3780                 break;
3781         default:
3782                 break;
3783         }
3784 }
3785
3786 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3787 {
3788         const char *chip_name;
3789         char fw_name[40];
3790         char wks[10];
3791         int err;
3792         struct amdgpu_firmware_info *info = NULL;
3793         const struct common_firmware_header *header = NULL;
3794         const struct gfx_firmware_header_v1_0 *cp_hdr;
3795         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3796         unsigned int *tmp = NULL;
3797         unsigned int i = 0;
3798         uint16_t version_major;
3799         uint16_t version_minor;
3800
3801         DRM_DEBUG("\n");
3802
3803         memset(wks, 0, sizeof(wks));
3804         switch (adev->asic_type) {
3805         case CHIP_NAVI10:
3806                 chip_name = "navi10";
3807                 break;
3808         case CHIP_NAVI14:
3809                 chip_name = "navi14";
3810                 if (!(adev->pdev->device == 0x7340 &&
3811                       adev->pdev->revision != 0x00))
3812                         snprintf(wks, sizeof(wks), "_wks");
3813                 break;
3814         case CHIP_NAVI12:
3815                 chip_name = "navi12";
3816                 break;
3817         case CHIP_SIENNA_CICHLID:
3818                 chip_name = "sienna_cichlid";
3819                 break;
3820         case CHIP_NAVY_FLOUNDER:
3821                 chip_name = "navy_flounder";
3822                 break;
3823         case CHIP_VANGOGH:
3824                 chip_name = "vangogh";
3825                 break;
3826         case CHIP_DIMGREY_CAVEFISH:
3827                 chip_name = "dimgrey_cavefish";
3828                 break;
3829         default:
3830                 BUG();
3831         }
3832
3833         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3834         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3835         if (err)
3836                 goto out;
3837         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3838         if (err)
3839                 goto out;
3840         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3841         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3842         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3843
3844         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3845         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3846         if (err)
3847                 goto out;
3848         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3849         if (err)
3850                 goto out;
3851         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3852         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3853         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3854
3855         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3856         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3857         if (err)
3858                 goto out;
3859         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3860         if (err)
3861                 goto out;
3862         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3863         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3864         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3865
3866         if (!amdgpu_sriov_vf(adev)) {
3867                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3868                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3869                 if (err)
3870                         goto out;
3871                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3872                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3873                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3874                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3875
3876                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3877                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3878                 adev->gfx.rlc.save_and_restore_offset =
3879                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3880                 adev->gfx.rlc.clear_state_descriptor_offset =
3881                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3882                 adev->gfx.rlc.avail_scratch_ram_locations =
3883                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3884                 adev->gfx.rlc.reg_restore_list_size =
3885                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3886                 adev->gfx.rlc.reg_list_format_start =
3887                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3888                 adev->gfx.rlc.reg_list_format_separate_start =
3889                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3890                 adev->gfx.rlc.starting_offsets_start =
3891                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3892                 adev->gfx.rlc.reg_list_format_size_bytes =
3893                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3894                 adev->gfx.rlc.reg_list_size_bytes =
3895                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3896                 adev->gfx.rlc.register_list_format =
3897                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3898                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3899                 if (!adev->gfx.rlc.register_list_format) {
3900                         err = -ENOMEM;
3901                         goto out;
3902                 }
3903
3904                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3905                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3906                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3907                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3908
3909                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3910
3911                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3912                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3913                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3914                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3915
3916                 if (version_major == 2) {
3917                         if (version_minor >= 1)
3918                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3919                         if (version_minor == 2)
3920                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3921                 }
3922         }
3923
3924         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3925         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3926         if (err)
3927                 goto out;
3928         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3929         if (err)
3930                 goto out;
3931         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3932         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3933         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3934
3935         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3936         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3937         if (!err) {
3938                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3939                 if (err)
3940                         goto out;
3941                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3942                 adev->gfx.mec2_fw->data;
3943                 adev->gfx.mec2_fw_version =
3944                 le32_to_cpu(cp_hdr->header.ucode_version);
3945                 adev->gfx.mec2_feature_version =
3946                 le32_to_cpu(cp_hdr->ucode_feature_version);
3947         } else {
3948                 err = 0;
3949                 adev->gfx.mec2_fw = NULL;
3950         }
3951
3952         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3953                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3954                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3955                 info->fw = adev->gfx.pfp_fw;
3956                 header = (const struct common_firmware_header *)info->fw->data;
3957                 adev->firmware.fw_size +=
3958                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3959
3960                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3961                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3962                 info->fw = adev->gfx.me_fw;
3963                 header = (const struct common_firmware_header *)info->fw->data;
3964                 adev->firmware.fw_size +=
3965                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3966
3967                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3968                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3969                 info->fw = adev->gfx.ce_fw;
3970                 header = (const struct common_firmware_header *)info->fw->data;
3971                 adev->firmware.fw_size +=
3972                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3973
3974                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3975                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3976                 info->fw = adev->gfx.rlc_fw;
3977                 if (info->fw) {
3978                         header = (const struct common_firmware_header *)info->fw->data;
3979                         adev->firmware.fw_size +=
3980                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3981                 }
3982                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3983                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3984                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3985                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3986                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3987                         info->fw = adev->gfx.rlc_fw;
3988                         adev->firmware.fw_size +=
3989                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3990
3991                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3992                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3993                         info->fw = adev->gfx.rlc_fw;
3994                         adev->firmware.fw_size +=
3995                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3996
3997                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3998                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3999                         info->fw = adev->gfx.rlc_fw;
4000                         adev->firmware.fw_size +=
4001                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4002
4003                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4004                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4005                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4006                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4007                                 info->fw = adev->gfx.rlc_fw;
4008                                 adev->firmware.fw_size +=
4009                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4010
4011                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4012                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4013                                 info->fw = adev->gfx.rlc_fw;
4014                                 adev->firmware.fw_size +=
4015                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4016                         }
4017                 }
4018
4019                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4020                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4021                 info->fw = adev->gfx.mec_fw;
4022                 header = (const struct common_firmware_header *)info->fw->data;
4023                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4024                 adev->firmware.fw_size +=
4025                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4026                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4027
4028                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4029                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4030                 info->fw = adev->gfx.mec_fw;
4031                 adev->firmware.fw_size +=
4032                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4033
4034                 if (adev->gfx.mec2_fw) {
4035                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4036                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4037                         info->fw = adev->gfx.mec2_fw;
4038                         header = (const struct common_firmware_header *)info->fw->data;
4039                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4040                         adev->firmware.fw_size +=
4041                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4042                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4043                                       PAGE_SIZE);
4044                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4045                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4046                         info->fw = adev->gfx.mec2_fw;
4047                         adev->firmware.fw_size +=
4048                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4049                                       PAGE_SIZE);
4050                 }
4051         }
4052
4053         gfx_v10_0_check_fw_write_wait(adev);
4054 out:
4055         if (err) {
4056                 dev_err(adev->dev,
4057                         "gfx10: Failed to load firmware \"%s\"\n",
4058                         fw_name);
4059                 release_firmware(adev->gfx.pfp_fw);
4060                 adev->gfx.pfp_fw = NULL;
4061                 release_firmware(adev->gfx.me_fw);
4062                 adev->gfx.me_fw = NULL;
4063                 release_firmware(adev->gfx.ce_fw);
4064                 adev->gfx.ce_fw = NULL;
4065                 release_firmware(adev->gfx.rlc_fw);
4066                 adev->gfx.rlc_fw = NULL;
4067                 release_firmware(adev->gfx.mec_fw);
4068                 adev->gfx.mec_fw = NULL;
4069                 release_firmware(adev->gfx.mec2_fw);
4070                 adev->gfx.mec2_fw = NULL;
4071         }
4072
4073         gfx_v10_0_check_gfxoff_flag(adev);
4074
4075         return err;
4076 }
4077
4078 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4079 {
4080         u32 count = 0;
4081         const struct cs_section_def *sect = NULL;
4082         const struct cs_extent_def *ext = NULL;
4083
4084         /* begin clear state */
4085         count += 2;
4086         /* context control state */
4087         count += 3;
4088
4089         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4090                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4091                         if (sect->id == SECT_CONTEXT)
4092                                 count += 2 + ext->reg_count;
4093                         else
4094                                 return 0;
4095                 }
4096         }
4097
4098         /* set PA_SC_TILE_STEERING_OVERRIDE */
4099         count += 3;
4100         /* end clear state */
4101         count += 2;
4102         /* clear state */
4103         count += 2;
4104
4105         return count;
4106 }
4107
4108 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4109                                     volatile u32 *buffer)
4110 {
4111         u32 count = 0, i;
4112         const struct cs_section_def *sect = NULL;
4113         const struct cs_extent_def *ext = NULL;
4114         int ctx_reg_offset;
4115
4116         if (adev->gfx.rlc.cs_data == NULL)
4117                 return;
4118         if (buffer == NULL)
4119                 return;
4120
4121         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4122         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4123
4124         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4125         buffer[count++] = cpu_to_le32(0x80000000);
4126         buffer[count++] = cpu_to_le32(0x80000000);
4127
4128         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4129                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4130                         if (sect->id == SECT_CONTEXT) {
4131                                 buffer[count++] =
4132                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4133                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4134                                                 PACKET3_SET_CONTEXT_REG_START);
4135                                 for (i = 0; i < ext->reg_count; i++)
4136                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4137                         } else {
4138                                 return;
4139                         }
4140                 }
4141         }
4142
4143         ctx_reg_offset =
4144                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4145         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4146         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4147         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4148
4149         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4150         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4151
4152         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4153         buffer[count++] = cpu_to_le32(0);
4154 }
4155
4156 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4157 {
4158         /* clear state block */
4159         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4160                         &adev->gfx.rlc.clear_state_gpu_addr,
4161                         (void **)&adev->gfx.rlc.cs_ptr);
4162
4163         /* jump table block */
4164         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4165                         &adev->gfx.rlc.cp_table_gpu_addr,
4166                         (void **)&adev->gfx.rlc.cp_table_ptr);
4167 }
4168
4169 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4170 {
4171         const struct cs_section_def *cs_data;
4172         int r;
4173
4174         adev->gfx.rlc.cs_data = gfx10_cs_data;
4175
4176         cs_data = adev->gfx.rlc.cs_data;
4177
4178         if (cs_data) {
4179                 /* init clear state block */
4180                 r = amdgpu_gfx_rlc_init_csb(adev);
4181                 if (r)
4182                         return r;
4183         }
4184
4185         /* init spm vmid with 0xf */
4186         if (adev->gfx.rlc.funcs->update_spm_vmid)
4187                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4188
4189         return 0;
4190 }
4191
4192 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4193 {
4194         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4195         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4196 }
4197
4198 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4199 {
4200         int r;
4201
4202         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4203
4204         amdgpu_gfx_graphics_queue_acquire(adev);
4205
4206         r = gfx_v10_0_init_microcode(adev);
4207         if (r)
4208                 DRM_ERROR("Failed to load gfx firmware!\n");
4209
4210         return r;
4211 }
4212
4213 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4214 {
4215         int r;
4216         u32 *hpd;
4217         const __le32 *fw_data = NULL;
4218         unsigned fw_size;
4219         u32 *fw = NULL;
4220         size_t mec_hpd_size;
4221
4222         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4223
4224         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4225
4226         /* take ownership of the relevant compute queues */
4227         amdgpu_gfx_compute_queue_acquire(adev);
4228         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4229
4230         if (mec_hpd_size) {
4231                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4232                                               AMDGPU_GEM_DOMAIN_GTT,
4233                                               &adev->gfx.mec.hpd_eop_obj,
4234                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4235                                               (void **)&hpd);
4236                 if (r) {
4237                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4238                         gfx_v10_0_mec_fini(adev);
4239                         return r;
4240                 }
4241
4242                 memset(hpd, 0, mec_hpd_size);
4243
4244                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4245                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4246         }
4247
4248         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4249                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4250
4251                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4252                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4253                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4254
4255                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4256                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4257                                               &adev->gfx.mec.mec_fw_obj,
4258                                               &adev->gfx.mec.mec_fw_gpu_addr,
4259                                               (void **)&fw);
4260                 if (r) {
4261                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4262                         gfx_v10_0_mec_fini(adev);
4263                         return r;
4264                 }
4265
4266                 memcpy(fw, fw_data, fw_size);
4267
4268                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4269                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4270         }
4271
4272         return 0;
4273 }
4274
4275 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4276 {
4277         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4278                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4279                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4280         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4281 }
4282
4283 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4284                            uint32_t thread, uint32_t regno,
4285                            uint32_t num, uint32_t *out)
4286 {
4287         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4288                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4289                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4290                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4291                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4292         while (num--)
4293                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4294 }
4295
4296 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4297 {
4298         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4299          * field when performing a select_se_sh so it should be
4300          * zero here */
4301         WARN_ON(simd != 0);
4302
4303         /* type 2 wave data */
4304         dst[(*no_fields)++] = 2;
4305         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4306         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4307         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4308         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4309         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4310         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4311         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4312         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4313         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4314         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4315         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4316         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4317         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4318         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4319         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4320 }
4321
4322 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4323                                      uint32_t wave, uint32_t start,
4324                                      uint32_t size, uint32_t *dst)
4325 {
4326         WARN_ON(simd != 0);
4327
4328         wave_read_regs(
4329                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4330                 dst);
4331 }
4332
4333 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4334                                       uint32_t wave, uint32_t thread,
4335                                       uint32_t start, uint32_t size,
4336                                       uint32_t *dst)
4337 {
4338         wave_read_regs(
4339                 adev, wave, thread,
4340                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4341 }
4342
4343 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4344                                        u32 me, u32 pipe, u32 q, u32 vm)
4345 {
4346         nv_grbm_select(adev, me, pipe, q, vm);
4347 }
4348
4349 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4350                                           bool enable)
4351 {
4352         uint32_t data, def;
4353
4354         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4355
4356         if (enable)
4357                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4358         else
4359                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4360
4361         if (data != def)
4362                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4363 }
4364
4365 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4366         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4367         .select_se_sh = &gfx_v10_0_select_se_sh,
4368         .read_wave_data = &gfx_v10_0_read_wave_data,
4369         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4370         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4371         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4372         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4373         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4374 };
4375
4376 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4377 {
4378         u32 gb_addr_config;
4379
4380         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4381
4382         switch (adev->asic_type) {
4383         case CHIP_NAVI10:
4384         case CHIP_NAVI14:
4385         case CHIP_NAVI12:
4386                 adev->gfx.config.max_hw_contexts = 8;
4387                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4388                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4389                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4390                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4391                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4392                 break;
4393         case CHIP_SIENNA_CICHLID:
4394         case CHIP_NAVY_FLOUNDER:
4395         case CHIP_VANGOGH:
4396         case CHIP_DIMGREY_CAVEFISH:
4397                 adev->gfx.config.max_hw_contexts = 8;
4398                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4399                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4400                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4401                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4402                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4403                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4404                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4405                 break;
4406         default:
4407                 BUG();
4408                 break;
4409         }
4410
4411         adev->gfx.config.gb_addr_config = gb_addr_config;
4412
4413         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4414                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4415                                       GB_ADDR_CONFIG, NUM_PIPES);
4416
4417         adev->gfx.config.max_tile_pipes =
4418                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4419
4420         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4421                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4422                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4423         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4424                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4425                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4426         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4427                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4428                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4429         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4430                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4431                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4432 }
4433
4434 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4435                                    int me, int pipe, int queue)
4436 {
4437         int r;
4438         struct amdgpu_ring *ring;
4439         unsigned int irq_type;
4440
4441         ring = &adev->gfx.gfx_ring[ring_id];
4442
4443         ring->me = me;
4444         ring->pipe = pipe;
4445         ring->queue = queue;
4446
4447         ring->ring_obj = NULL;
4448         ring->use_doorbell = true;
4449
4450         if (!ring_id)
4451                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4452         else
4453                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4454         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4455
4456         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4457         r = amdgpu_ring_init(adev, ring, 1024,
4458                              &adev->gfx.eop_irq, irq_type,
4459                              AMDGPU_RING_PRIO_DEFAULT);
4460         if (r)
4461                 return r;
4462         return 0;
4463 }
4464
4465 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4466                                        int mec, int pipe, int queue)
4467 {
4468         int r;
4469         unsigned irq_type;
4470         struct amdgpu_ring *ring;
4471         unsigned int hw_prio;
4472
4473         ring = &adev->gfx.compute_ring[ring_id];
4474
4475         /* mec0 is me1 */
4476         ring->me = mec + 1;
4477         ring->pipe = pipe;
4478         ring->queue = queue;
4479
4480         ring->ring_obj = NULL;
4481         ring->use_doorbell = true;
4482         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4483         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4484                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4485         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4486
4487         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4488                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4489                 + ring->pipe;
4490         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
4491                                                             ring->queue) ?
4492                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4493         /* type-2 packets are deprecated on MEC, use type-3 instead */
4494         r = amdgpu_ring_init(adev, ring, 1024,
4495                              &adev->gfx.eop_irq, irq_type, hw_prio);
4496         if (r)
4497                 return r;
4498
4499         return 0;
4500 }
4501
4502 static int gfx_v10_0_sw_init(void *handle)
4503 {
4504         int i, j, k, r, ring_id = 0;
4505         struct amdgpu_kiq *kiq;
4506         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4507
4508         switch (adev->asic_type) {
4509         case CHIP_NAVI10:
4510         case CHIP_NAVI14:
4511         case CHIP_NAVI12:
4512                 adev->gfx.me.num_me = 1;
4513                 adev->gfx.me.num_pipe_per_me = 1;
4514                 adev->gfx.me.num_queue_per_pipe = 1;
4515                 adev->gfx.mec.num_mec = 2;
4516                 adev->gfx.mec.num_pipe_per_mec = 4;
4517                 adev->gfx.mec.num_queue_per_pipe = 8;
4518                 break;
4519         case CHIP_SIENNA_CICHLID:
4520         case CHIP_NAVY_FLOUNDER:
4521         case CHIP_VANGOGH:
4522         case CHIP_DIMGREY_CAVEFISH:
4523                 adev->gfx.me.num_me = 1;
4524                 adev->gfx.me.num_pipe_per_me = 1;
4525                 adev->gfx.me.num_queue_per_pipe = 1;
4526                 adev->gfx.mec.num_mec = 2;
4527                 adev->gfx.mec.num_pipe_per_mec = 4;
4528                 adev->gfx.mec.num_queue_per_pipe = 4;
4529                 break;
4530         default:
4531                 adev->gfx.me.num_me = 1;
4532                 adev->gfx.me.num_pipe_per_me = 1;
4533                 adev->gfx.me.num_queue_per_pipe = 1;
4534                 adev->gfx.mec.num_mec = 1;
4535                 adev->gfx.mec.num_pipe_per_mec = 4;
4536                 adev->gfx.mec.num_queue_per_pipe = 8;
4537                 break;
4538         }
4539
4540         /* KIQ event */
4541         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4542                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4543                               &adev->gfx.kiq.irq);
4544         if (r)
4545                 return r;
4546
4547         /* EOP Event */
4548         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4549                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4550                               &adev->gfx.eop_irq);
4551         if (r)
4552                 return r;
4553
4554         /* Privileged reg */
4555         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4556                               &adev->gfx.priv_reg_irq);
4557         if (r)
4558                 return r;
4559
4560         /* Privileged inst */
4561         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4562                               &adev->gfx.priv_inst_irq);
4563         if (r)
4564                 return r;
4565
4566         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4567
4568         gfx_v10_0_scratch_init(adev);
4569
4570         r = gfx_v10_0_me_init(adev);
4571         if (r)
4572                 return r;
4573
4574         r = gfx_v10_0_rlc_init(adev);
4575         if (r) {
4576                 DRM_ERROR("Failed to init rlc BOs!\n");
4577                 return r;
4578         }
4579
4580         r = gfx_v10_0_mec_init(adev);
4581         if (r) {
4582                 DRM_ERROR("Failed to init MEC BOs!\n");
4583                 return r;
4584         }
4585
4586         /* set up the gfx ring */
4587         for (i = 0; i < adev->gfx.me.num_me; i++) {
4588                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4589                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4590                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4591                                         continue;
4592
4593                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4594                                                             i, k, j);
4595                                 if (r)
4596                                         return r;
4597                                 ring_id++;
4598                         }
4599                 }
4600         }
4601
4602         ring_id = 0;
4603         /* set up the compute queues - allocate horizontally across pipes */
4604         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4605                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4606                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4607                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4608                                                                      j))
4609                                         continue;
4610
4611                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4612                                                                 i, k, j);
4613                                 if (r)
4614                                         return r;
4615
4616                                 ring_id++;
4617                         }
4618                 }
4619         }
4620
4621         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4622         if (r) {
4623                 DRM_ERROR("Failed to init KIQ BOs!\n");
4624                 return r;
4625         }
4626
4627         kiq = &adev->gfx.kiq;
4628         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4629         if (r)
4630                 return r;
4631
4632         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4633         if (r)
4634                 return r;
4635
4636         /* allocate visible FB for rlc auto-loading fw */
4637         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4638                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4639                 if (r)
4640                         return r;
4641         }
4642
4643         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4644
4645         gfx_v10_0_gpu_early_init(adev);
4646
4647         return 0;
4648 }
4649
4650 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4651 {
4652         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4653                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4654                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4655 }
4656
4657 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4658 {
4659         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4660                               &adev->gfx.ce.ce_fw_gpu_addr,
4661                               (void **)&adev->gfx.ce.ce_fw_ptr);
4662 }
4663
4664 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4665 {
4666         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4667                               &adev->gfx.me.me_fw_gpu_addr,
4668                               (void **)&adev->gfx.me.me_fw_ptr);
4669 }
4670
4671 static int gfx_v10_0_sw_fini(void *handle)
4672 {
4673         int i;
4674         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4675
4676         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4677                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4678         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4679                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4680
4681         amdgpu_gfx_mqd_sw_fini(adev);
4682         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4683         amdgpu_gfx_kiq_fini(adev);
4684
4685         gfx_v10_0_pfp_fini(adev);
4686         gfx_v10_0_ce_fini(adev);
4687         gfx_v10_0_me_fini(adev);
4688         gfx_v10_0_rlc_fini(adev);
4689         gfx_v10_0_mec_fini(adev);
4690
4691         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4692                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4693
4694         gfx_v10_0_free_microcode(adev);
4695
4696         return 0;
4697 }
4698
4699 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4700                                    u32 sh_num, u32 instance)
4701 {
4702         u32 data;
4703
4704         if (instance == 0xffffffff)
4705                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4706                                      INSTANCE_BROADCAST_WRITES, 1);
4707         else
4708                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4709                                      instance);
4710
4711         if (se_num == 0xffffffff)
4712                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4713                                      1);
4714         else
4715                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4716
4717         if (sh_num == 0xffffffff)
4718                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4719                                      1);
4720         else
4721                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4722
4723         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4724 }
4725
4726 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4727 {
4728         u32 data, mask;
4729
4730         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4731         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4732
4733         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4734         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4735
4736         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4737                                          adev->gfx.config.max_sh_per_se);
4738
4739         return (~data) & mask;
4740 }
4741
4742 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4743 {
4744         int i, j;
4745         u32 data;
4746         u32 active_rbs = 0;
4747         u32 bitmap;
4748         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4749                                         adev->gfx.config.max_sh_per_se;
4750
4751         mutex_lock(&adev->grbm_idx_mutex);
4752         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4753                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4754                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4755                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4756                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4757                                 continue;
4758                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4759                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4760                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4761                                                rb_bitmap_width_per_sh);
4762                 }
4763         }
4764         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4765         mutex_unlock(&adev->grbm_idx_mutex);
4766
4767         adev->gfx.config.backend_enable_mask = active_rbs;
4768         adev->gfx.config.num_rbs = hweight32(active_rbs);
4769 }
4770
4771 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4772 {
4773         uint32_t num_sc;
4774         uint32_t enabled_rb_per_sh;
4775         uint32_t active_rb_bitmap;
4776         uint32_t num_rb_per_sc;
4777         uint32_t num_packer_per_sc;
4778         uint32_t pa_sc_tile_steering_override;
4779
4780         /* for ASICs that integrates GFX v10.3
4781          * pa_sc_tile_steering_override should be set to 0 */
4782         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4783                 return 0;
4784
4785         /* init num_sc */
4786         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4787                         adev->gfx.config.num_sc_per_sh;
4788         /* init num_rb_per_sc */
4789         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4790         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4791         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4792         /* init num_packer_per_sc */
4793         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4794
4795         pa_sc_tile_steering_override = 0;
4796         pa_sc_tile_steering_override |=
4797                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4798                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4799         pa_sc_tile_steering_override |=
4800                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4801                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4802         pa_sc_tile_steering_override |=
4803                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4804                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4805
4806         return pa_sc_tile_steering_override;
4807 }
4808
4809 #define DEFAULT_SH_MEM_BASES    (0x6000)
4810
4811 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4812 {
4813         int i;
4814         uint32_t sh_mem_bases;
4815
4816         /*
4817          * Configure apertures:
4818          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4819          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4820          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4821          */
4822         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4823
4824         mutex_lock(&adev->srbm_mutex);
4825         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4826                 nv_grbm_select(adev, 0, 0, 0, i);
4827                 /* CP and shaders */
4828                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4829                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4830         }
4831         nv_grbm_select(adev, 0, 0, 0, 0);
4832         mutex_unlock(&adev->srbm_mutex);
4833
4834         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4835            acccess. These should be enabled by FW for target VMIDs. */
4836         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4837                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4838                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4839                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4840                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4841         }
4842 }
4843
4844 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4845 {
4846         int vmid;
4847
4848         /*
4849          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4850          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4851          * the driver can enable them for graphics. VMID0 should maintain
4852          * access so that HWS firmware can save/restore entries.
4853          */
4854         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4855                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4856                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4857                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4858                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4859         }
4860 }
4861
4862
4863 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4864 {
4865         int i, j, k;
4866         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4867         u32 tmp, wgp_active_bitmap = 0;
4868         u32 gcrd_targets_disable_tcp = 0;
4869         u32 utcl_invreq_disable = 0;
4870         /*
4871          * GCRD_TARGETS_DISABLE field contains
4872          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4873          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4874          */
4875         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4876                 2 * max_wgp_per_sh + /* TCP */
4877                 max_wgp_per_sh + /* SQC */
4878                 4); /* GL1C */
4879         /*
4880          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4881          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4882          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4883          */
4884         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4885                 2 * max_wgp_per_sh + /* TCP */
4886                 2 * max_wgp_per_sh + /* SQC */
4887                 4 + /* RMI */
4888                 1); /* SQG */
4889
4890         if (adev->asic_type == CHIP_NAVI10 ||
4891             adev->asic_type == CHIP_NAVI14 ||
4892             adev->asic_type == CHIP_NAVI12) {
4893                 mutex_lock(&adev->grbm_idx_mutex);
4894                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4895                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4896                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4897                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4898                                 /*
4899                                  * Set corresponding TCP bits for the inactive WGPs in
4900                                  * GCRD_SA_TARGETS_DISABLE
4901                                  */
4902                                 gcrd_targets_disable_tcp = 0;
4903                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4904                                 utcl_invreq_disable = 0;
4905
4906                                 for (k = 0; k < max_wgp_per_sh; k++) {
4907                                         if (!(wgp_active_bitmap & (1 << k))) {
4908                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4909                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4910                                                         (3 << (2 * (max_wgp_per_sh + k)));
4911                                         }
4912                                 }
4913
4914                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4915                                 /* only override TCP & SQC bits */
4916                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4917                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4918                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4919
4920                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4921                                 /* only override TCP bits */
4922                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4923                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4924                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4925                         }
4926                 }
4927
4928                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4929                 mutex_unlock(&adev->grbm_idx_mutex);
4930         }
4931 }
4932
4933 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4934 {
4935         /* TCCs are global (not instanced). */
4936         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4937                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4938
4939         adev->gfx.config.tcc_disabled_mask =
4940                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4941                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4942 }
4943
4944 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4945 {
4946         u32 tmp;
4947         int i;
4948
4949         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4950
4951         gfx_v10_0_setup_rb(adev);
4952         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4953         gfx_v10_0_get_tcc_info(adev);
4954         adev->gfx.config.pa_sc_tile_steering_override =
4955                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4956
4957         /* XXX SH_MEM regs */
4958         /* where to put LDS, scratch, GPUVM in FSA64 space */
4959         mutex_lock(&adev->srbm_mutex);
4960         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4961                 nv_grbm_select(adev, 0, 0, 0, i);
4962                 /* CP and shaders */
4963                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4964                 if (i != 0) {
4965                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4966                                 (adev->gmc.private_aperture_start >> 48));
4967                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4968                                 (adev->gmc.shared_aperture_start >> 48));
4969                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4970                 }
4971         }
4972         nv_grbm_select(adev, 0, 0, 0, 0);
4973
4974         mutex_unlock(&adev->srbm_mutex);
4975
4976         gfx_v10_0_init_compute_vmid(adev);
4977         gfx_v10_0_init_gds_vmid(adev);
4978
4979 }
4980
4981 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4982                                                bool enable)
4983 {
4984         u32 tmp;
4985
4986         if (amdgpu_sriov_vf(adev))
4987                 return;
4988
4989         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4990
4991         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4992                             enable ? 1 : 0);
4993         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4994                             enable ? 1 : 0);
4995         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4996                             enable ? 1 : 0);
4997         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4998                             enable ? 1 : 0);
4999
5000         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5001 }
5002
5003 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5004 {
5005         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5006
5007         /* csib */
5008         if (adev->asic_type == CHIP_NAVI12) {
5009                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5010                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5011                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5012                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5013                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5014         } else {
5015                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5016                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5017                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5018                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5019                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5020         }
5021         return 0;
5022 }
5023
5024 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5025 {
5026         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5027
5028         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5029         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5030 }
5031
5032 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5033 {
5034         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5035         udelay(50);
5036         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5037         udelay(50);
5038 }
5039
5040 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5041                                              bool enable)
5042 {
5043         uint32_t rlc_pg_cntl;
5044
5045         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5046
5047         if (!enable) {
5048                 /* RLC_PG_CNTL[23] = 0 (default)
5049                  * RLC will wait for handshake acks with SMU
5050                  * GFXOFF will be enabled
5051                  * RLC_PG_CNTL[23] = 1
5052                  * RLC will not issue any message to SMU
5053                  * hence no handshake between SMU & RLC
5054                  * GFXOFF will be disabled
5055                  */
5056                 rlc_pg_cntl |= 0x800000;
5057         } else
5058                 rlc_pg_cntl &= ~0x800000;
5059         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5060 }
5061
5062 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5063 {
5064         /* TODO: enable rlc & smu handshake until smu
5065          * and gfxoff feature works as expected */
5066         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5067                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5068
5069         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5070         udelay(50);
5071 }
5072
5073 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5074 {
5075         uint32_t tmp;
5076
5077         /* enable Save Restore Machine */
5078         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5079         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5080         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5081         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5082 }
5083
5084 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5085 {
5086         const struct rlc_firmware_header_v2_0 *hdr;
5087         const __le32 *fw_data;
5088         unsigned i, fw_size;
5089
5090         if (!adev->gfx.rlc_fw)
5091                 return -EINVAL;
5092
5093         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5094         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5095
5096         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5097                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5098         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5099
5100         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5101                      RLCG_UCODE_LOADING_START_ADDRESS);
5102
5103         for (i = 0; i < fw_size; i++)
5104                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5105                              le32_to_cpup(fw_data++));
5106
5107         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5108
5109         return 0;
5110 }
5111
5112 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5113 {
5114         int r;
5115
5116         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5117
5118                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5119                 if (r)
5120                         return r;
5121
5122                 gfx_v10_0_init_csb(adev);
5123
5124                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5125                         gfx_v10_0_rlc_enable_srm(adev);
5126         } else {
5127                 if (amdgpu_sriov_vf(adev)) {
5128                         gfx_v10_0_init_csb(adev);
5129                         return 0;
5130                 }
5131
5132                 adev->gfx.rlc.funcs->stop(adev);
5133
5134                 /* disable CG */
5135                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5136
5137                 /* disable PG */
5138                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5139
5140                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5141                         /* legacy rlc firmware loading */
5142                         r = gfx_v10_0_rlc_load_microcode(adev);
5143                         if (r)
5144                                 return r;
5145                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5146                         /* rlc backdoor autoload firmware */
5147                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5148                         if (r)
5149                                 return r;
5150                 }
5151
5152                 gfx_v10_0_init_csb(adev);
5153
5154                 adev->gfx.rlc.funcs->start(adev);
5155
5156                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5157                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5158                         if (r)
5159                                 return r;
5160                 }
5161         }
5162         return 0;
5163 }
5164
5165 static struct {
5166         FIRMWARE_ID     id;
5167         unsigned int    offset;
5168         unsigned int    size;
5169 } rlc_autoload_info[FIRMWARE_ID_MAX];
5170
5171 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5172 {
5173         int ret;
5174         RLC_TABLE_OF_CONTENT *rlc_toc;
5175
5176         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5177                                         AMDGPU_GEM_DOMAIN_GTT,
5178                                         &adev->gfx.rlc.rlc_toc_bo,
5179                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5180                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5181         if (ret) {
5182                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5183                 return ret;
5184         }
5185
5186         /* Copy toc from psp sos fw to rlc toc buffer */
5187         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5188
5189         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5190         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5191                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5192                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5193                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5194                         /* Offset needs 4KB alignment */
5195                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5196                 }
5197
5198                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5199                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5200                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5201
5202                 rlc_toc++;
5203         }
5204
5205         return 0;
5206 }
5207
5208 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5209 {
5210         uint32_t total_size = 0;
5211         FIRMWARE_ID id;
5212         int ret;
5213
5214         ret = gfx_v10_0_parse_rlc_toc(adev);
5215         if (ret) {
5216                 dev_err(adev->dev, "failed to parse rlc toc\n");
5217                 return 0;
5218         }
5219
5220         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5221                 total_size += rlc_autoload_info[id].size;
5222
5223         /* In case the offset in rlc toc ucode is aligned */
5224         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5225                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5226                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5227
5228         return total_size;
5229 }
5230
5231 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5232 {
5233         int r;
5234         uint32_t total_size;
5235
5236         total_size = gfx_v10_0_calc_toc_total_size(adev);
5237
5238         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5239                                       AMDGPU_GEM_DOMAIN_GTT,
5240                                       &adev->gfx.rlc.rlc_autoload_bo,
5241                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5242                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5243         if (r) {
5244                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5245                 return r;
5246         }
5247
5248         return 0;
5249 }
5250
5251 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5252 {
5253         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5254                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5255                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5256         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5257                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5258                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5259 }
5260
5261 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5262                                                        FIRMWARE_ID id,
5263                                                        const void *fw_data,
5264                                                        uint32_t fw_size)
5265 {
5266         uint32_t toc_offset;
5267         uint32_t toc_fw_size;
5268         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5269
5270         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5271                 return;
5272
5273         toc_offset = rlc_autoload_info[id].offset;
5274         toc_fw_size = rlc_autoload_info[id].size;
5275
5276         if (fw_size == 0)
5277                 fw_size = toc_fw_size;
5278
5279         if (fw_size > toc_fw_size)
5280                 fw_size = toc_fw_size;
5281
5282         memcpy(ptr + toc_offset, fw_data, fw_size);
5283
5284         if (fw_size < toc_fw_size)
5285                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5286 }
5287
5288 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5289 {
5290         void *data;
5291         uint32_t size;
5292
5293         data = adev->gfx.rlc.rlc_toc_buf;
5294         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5295
5296         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5297                                                    FIRMWARE_ID_RLC_TOC,
5298                                                    data, size);
5299 }
5300
5301 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5302 {
5303         const __le32 *fw_data;
5304         uint32_t fw_size;
5305         const struct gfx_firmware_header_v1_0 *cp_hdr;
5306         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5307
5308         /* pfp ucode */
5309         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5310                 adev->gfx.pfp_fw->data;
5311         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5312                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5313         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5314         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5315                                                    FIRMWARE_ID_CP_PFP,
5316                                                    fw_data, fw_size);
5317
5318         /* ce ucode */
5319         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5320                 adev->gfx.ce_fw->data;
5321         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5322                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5323         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5324         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5325                                                    FIRMWARE_ID_CP_CE,
5326                                                    fw_data, fw_size);
5327
5328         /* me ucode */
5329         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5330                 adev->gfx.me_fw->data;
5331         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5332                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5333         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5334         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5335                                                    FIRMWARE_ID_CP_ME,
5336                                                    fw_data, fw_size);
5337
5338         /* rlc ucode */
5339         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5340                 adev->gfx.rlc_fw->data;
5341         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5342                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5343         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5344         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5345                                                    FIRMWARE_ID_RLC_G_UCODE,
5346                                                    fw_data, fw_size);
5347
5348         /* mec1 ucode */
5349         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5350                 adev->gfx.mec_fw->data;
5351         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5352                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5353         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5354                 cp_hdr->jt_size * 4;
5355         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5356                                                    FIRMWARE_ID_CP_MEC,
5357                                                    fw_data, fw_size);
5358         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5359 }
5360
5361 /* Temporarily put sdma part here */
5362 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5363 {
5364         const __le32 *fw_data;
5365         uint32_t fw_size;
5366         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5367         int i;
5368
5369         for (i = 0; i < adev->sdma.num_instances; i++) {
5370                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5371                         adev->sdma.instance[i].fw->data;
5372                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5373                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5374                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5375
5376                 if (i == 0) {
5377                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5378                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5379                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5380                                 FIRMWARE_ID_SDMA0_JT,
5381                                 (uint32_t *)fw_data +
5382                                 sdma_hdr->jt_offset,
5383                                 sdma_hdr->jt_size * 4);
5384                 } else if (i == 1) {
5385                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5386                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5387                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5388                                 FIRMWARE_ID_SDMA1_JT,
5389                                 (uint32_t *)fw_data +
5390                                 sdma_hdr->jt_offset,
5391                                 sdma_hdr->jt_size * 4);
5392                 }
5393         }
5394 }
5395
5396 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5397 {
5398         uint32_t rlc_g_offset, rlc_g_size, tmp;
5399         uint64_t gpu_addr;
5400
5401         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5402         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5403         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5404
5405         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5406         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5407         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5408
5409         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5410         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5411         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5412
5413         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5414         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5415                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5416                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5417                 return -EINVAL;
5418         }
5419
5420         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5421         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5422                 DRM_ERROR("RLC ROM should halt itself\n");
5423                 return -EINVAL;
5424         }
5425
5426         return 0;
5427 }
5428
5429 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5430 {
5431         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5432         uint32_t tmp;
5433         int i;
5434         uint64_t addr;
5435
5436         /* Trigger an invalidation of the L1 instruction caches */
5437         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5438         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5439         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5440
5441         /* Wait for invalidation complete */
5442         for (i = 0; i < usec_timeout; i++) {
5443                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5444                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5445                         INVALIDATE_CACHE_COMPLETE))
5446                         break;
5447                 udelay(1);
5448         }
5449
5450         if (i >= usec_timeout) {
5451                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5452                 return -EINVAL;
5453         }
5454
5455         /* Program me ucode address into intruction cache address register */
5456         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5457                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5458         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5459                         lower_32_bits(addr) & 0xFFFFF000);
5460         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5461                         upper_32_bits(addr));
5462
5463         return 0;
5464 }
5465
5466 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5467 {
5468         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5469         uint32_t tmp;
5470         int i;
5471         uint64_t addr;
5472
5473         /* Trigger an invalidation of the L1 instruction caches */
5474         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5475         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5476         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5477
5478         /* Wait for invalidation complete */
5479         for (i = 0; i < usec_timeout; i++) {
5480                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5481                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5482                         INVALIDATE_CACHE_COMPLETE))
5483                         break;
5484                 udelay(1);
5485         }
5486
5487         if (i >= usec_timeout) {
5488                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5489                 return -EINVAL;
5490         }
5491
5492         /* Program ce ucode address into intruction cache address register */
5493         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5494                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5495         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5496                         lower_32_bits(addr) & 0xFFFFF000);
5497         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5498                         upper_32_bits(addr));
5499
5500         return 0;
5501 }
5502
5503 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5504 {
5505         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5506         uint32_t tmp;
5507         int i;
5508         uint64_t addr;
5509
5510         /* Trigger an invalidation of the L1 instruction caches */
5511         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5512         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5513         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5514
5515         /* Wait for invalidation complete */
5516         for (i = 0; i < usec_timeout; i++) {
5517                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5518                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5519                         INVALIDATE_CACHE_COMPLETE))
5520                         break;
5521                 udelay(1);
5522         }
5523
5524         if (i >= usec_timeout) {
5525                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5526                 return -EINVAL;
5527         }
5528
5529         /* Program pfp ucode address into intruction cache address register */
5530         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5531                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5532         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5533                         lower_32_bits(addr) & 0xFFFFF000);
5534         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5535                         upper_32_bits(addr));
5536
5537         return 0;
5538 }
5539
5540 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5541 {
5542         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5543         uint32_t tmp;
5544         int i;
5545         uint64_t addr;
5546
5547         /* Trigger an invalidation of the L1 instruction caches */
5548         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5549         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5550         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5551
5552         /* Wait for invalidation complete */
5553         for (i = 0; i < usec_timeout; i++) {
5554                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5555                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5556                         INVALIDATE_CACHE_COMPLETE))
5557                         break;
5558                 udelay(1);
5559         }
5560
5561         if (i >= usec_timeout) {
5562                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5563                 return -EINVAL;
5564         }
5565
5566         /* Program mec1 ucode address into intruction cache address register */
5567         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5568                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5569         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5570                         lower_32_bits(addr) & 0xFFFFF000);
5571         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5572                         upper_32_bits(addr));
5573
5574         return 0;
5575 }
5576
5577 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5578 {
5579         uint32_t cp_status;
5580         uint32_t bootload_status;
5581         int i, r;
5582
5583         for (i = 0; i < adev->usec_timeout; i++) {
5584                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5585                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5586                 if ((cp_status == 0) &&
5587                     (REG_GET_FIELD(bootload_status,
5588                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5589                         break;
5590                 }
5591                 udelay(1);
5592         }
5593
5594         if (i >= adev->usec_timeout) {
5595                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5596                 return -ETIMEDOUT;
5597         }
5598
5599         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5600                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5601                 if (r)
5602                         return r;
5603
5604                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5605                 if (r)
5606                         return r;
5607
5608                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5609                 if (r)
5610                         return r;
5611
5612                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5613                 if (r)
5614                         return r;
5615         }
5616
5617         return 0;
5618 }
5619
5620 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5621 {
5622         int i;
5623         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5624
5625         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5626         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5627         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5628
5629         if (adev->asic_type == CHIP_NAVI12) {
5630                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5631         } else {
5632                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5633         }
5634
5635         for (i = 0; i < adev->usec_timeout; i++) {
5636                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5637                         break;
5638                 udelay(1);
5639         }
5640
5641         if (i >= adev->usec_timeout)
5642                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5643
5644         return 0;
5645 }
5646
5647 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5648 {
5649         int r;
5650         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5651         const __le32 *fw_data;
5652         unsigned i, fw_size;
5653         uint32_t tmp;
5654         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5655
5656         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5657                 adev->gfx.pfp_fw->data;
5658
5659         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5660
5661         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5662                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5663         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5664
5665         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5666                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5667                                       &adev->gfx.pfp.pfp_fw_obj,
5668                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5669                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5670         if (r) {
5671                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5672                 gfx_v10_0_pfp_fini(adev);
5673                 return r;
5674         }
5675
5676         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5677
5678         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5679         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5680
5681         /* Trigger an invalidation of the L1 instruction caches */
5682         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5683         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5684         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5685
5686         /* Wait for invalidation complete */
5687         for (i = 0; i < usec_timeout; i++) {
5688                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5689                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5690                         INVALIDATE_CACHE_COMPLETE))
5691                         break;
5692                 udelay(1);
5693         }
5694
5695         if (i >= usec_timeout) {
5696                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5697                 return -EINVAL;
5698         }
5699
5700         if (amdgpu_emu_mode == 1)
5701                 adev->hdp.funcs->flush_hdp(adev, NULL);
5702
5703         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5704         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5705         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5706         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5707         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5708         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5709         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5710                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5711         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5712                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5713
5714         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5715
5716         for (i = 0; i < pfp_hdr->jt_size; i++)
5717                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5718                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5719
5720         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5721
5722         return 0;
5723 }
5724
5725 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5726 {
5727         int r;
5728         const struct gfx_firmware_header_v1_0 *ce_hdr;
5729         const __le32 *fw_data;
5730         unsigned i, fw_size;
5731         uint32_t tmp;
5732         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5733
5734         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5735                 adev->gfx.ce_fw->data;
5736
5737         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5738
5739         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5740                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5741         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5742
5743         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5744                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5745                                       &adev->gfx.ce.ce_fw_obj,
5746                                       &adev->gfx.ce.ce_fw_gpu_addr,
5747                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5748         if (r) {
5749                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5750                 gfx_v10_0_ce_fini(adev);
5751                 return r;
5752         }
5753
5754         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5755
5756         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5757         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5758
5759         /* Trigger an invalidation of the L1 instruction caches */
5760         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5761         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5762         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5763
5764         /* Wait for invalidation complete */
5765         for (i = 0; i < usec_timeout; i++) {
5766                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5767                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5768                         INVALIDATE_CACHE_COMPLETE))
5769                         break;
5770                 udelay(1);
5771         }
5772
5773         if (i >= usec_timeout) {
5774                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5775                 return -EINVAL;
5776         }
5777
5778         if (amdgpu_emu_mode == 1)
5779                 adev->hdp.funcs->flush_hdp(adev, NULL);
5780
5781         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5782         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5783         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5784         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5785         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5786         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5787                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5788         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5789                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5790
5791         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5792
5793         for (i = 0; i < ce_hdr->jt_size; i++)
5794                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5795                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5796
5797         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5798
5799         return 0;
5800 }
5801
5802 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5803 {
5804         int r;
5805         const struct gfx_firmware_header_v1_0 *me_hdr;
5806         const __le32 *fw_data;
5807         unsigned i, fw_size;
5808         uint32_t tmp;
5809         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5810
5811         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5812                 adev->gfx.me_fw->data;
5813
5814         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5815
5816         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5817                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5818         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5819
5820         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5821                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5822                                       &adev->gfx.me.me_fw_obj,
5823                                       &adev->gfx.me.me_fw_gpu_addr,
5824                                       (void **)&adev->gfx.me.me_fw_ptr);
5825         if (r) {
5826                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5827                 gfx_v10_0_me_fini(adev);
5828                 return r;
5829         }
5830
5831         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5832
5833         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5834         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5835
5836         /* Trigger an invalidation of the L1 instruction caches */
5837         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5838         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5839         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5840
5841         /* Wait for invalidation complete */
5842         for (i = 0; i < usec_timeout; i++) {
5843                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5844                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5845                         INVALIDATE_CACHE_COMPLETE))
5846                         break;
5847                 udelay(1);
5848         }
5849
5850         if (i >= usec_timeout) {
5851                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5852                 return -EINVAL;
5853         }
5854
5855         if (amdgpu_emu_mode == 1)
5856                 adev->hdp.funcs->flush_hdp(adev, NULL);
5857
5858         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5859         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5860         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5861         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5862         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5863         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5864                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5865         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5866                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5867
5868         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5869
5870         for (i = 0; i < me_hdr->jt_size; i++)
5871                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5872                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5873
5874         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5875
5876         return 0;
5877 }
5878
5879 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5880 {
5881         int r;
5882
5883         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5884                 return -EINVAL;
5885
5886         gfx_v10_0_cp_gfx_enable(adev, false);
5887
5888         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5889         if (r) {
5890                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5891                 return r;
5892         }
5893
5894         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5895         if (r) {
5896                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5897                 return r;
5898         }
5899
5900         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5901         if (r) {
5902                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5903                 return r;
5904         }
5905
5906         return 0;
5907 }
5908
5909 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5910 {
5911         struct amdgpu_ring *ring;
5912         const struct cs_section_def *sect = NULL;
5913         const struct cs_extent_def *ext = NULL;
5914         int r, i;
5915         int ctx_reg_offset;
5916
5917         /* init the CP */
5918         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5919                      adev->gfx.config.max_hw_contexts - 1);
5920         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5921
5922         gfx_v10_0_cp_gfx_enable(adev, true);
5923
5924         ring = &adev->gfx.gfx_ring[0];
5925         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5926         if (r) {
5927                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5928                 return r;
5929         }
5930
5931         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5932         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5933
5934         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5935         amdgpu_ring_write(ring, 0x80000000);
5936         amdgpu_ring_write(ring, 0x80000000);
5937
5938         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5939                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5940                         if (sect->id == SECT_CONTEXT) {
5941                                 amdgpu_ring_write(ring,
5942                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5943                                                           ext->reg_count));
5944                                 amdgpu_ring_write(ring, ext->reg_index -
5945                                                   PACKET3_SET_CONTEXT_REG_START);
5946                                 for (i = 0; i < ext->reg_count; i++)
5947                                         amdgpu_ring_write(ring, ext->extent[i]);
5948                         }
5949                 }
5950         }
5951
5952         ctx_reg_offset =
5953                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5954         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5955         amdgpu_ring_write(ring, ctx_reg_offset);
5956         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5957
5958         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5959         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5960
5961         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5962         amdgpu_ring_write(ring, 0);
5963
5964         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5965         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5966         amdgpu_ring_write(ring, 0x8000);
5967         amdgpu_ring_write(ring, 0x8000);
5968
5969         amdgpu_ring_commit(ring);
5970
5971         /* submit cs packet to copy state 0 to next available state */
5972         if (adev->gfx.num_gfx_rings > 1) {
5973                 /* maximum supported gfx ring is 2 */
5974                 ring = &adev->gfx.gfx_ring[1];
5975                 r = amdgpu_ring_alloc(ring, 2);
5976                 if (r) {
5977                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5978                         return r;
5979                 }
5980
5981                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5982                 amdgpu_ring_write(ring, 0);
5983
5984                 amdgpu_ring_commit(ring);
5985         }
5986         return 0;
5987 }
5988
5989 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5990                                          CP_PIPE_ID pipe)
5991 {
5992         u32 tmp;
5993
5994         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5995         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5996
5997         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5998 }
5999
6000 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6001                                           struct amdgpu_ring *ring)
6002 {
6003         u32 tmp;
6004
6005         if (!amdgpu_async_gfx_ring) {
6006                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6007                 if (ring->use_doorbell) {
6008                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6009                                                 DOORBELL_OFFSET, ring->doorbell_index);
6010                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6011                                                 DOORBELL_EN, 1);
6012                 } else {
6013                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6014                                                 DOORBELL_EN, 0);
6015                 }
6016                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6017         }
6018         switch (adev->asic_type) {
6019         case CHIP_SIENNA_CICHLID:
6020         case CHIP_NAVY_FLOUNDER:
6021         case CHIP_VANGOGH:
6022         case CHIP_DIMGREY_CAVEFISH:
6023                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6024                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6025                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6026
6027                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6028                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6029                 break;
6030         default:
6031                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6032                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6033                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6034
6035                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6036                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6037                 break;
6038         }
6039 }
6040
6041 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6042 {
6043         struct amdgpu_ring *ring;
6044         u32 tmp;
6045         u32 rb_bufsz;
6046         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6047         u32 i;
6048
6049         /* Set the write pointer delay */
6050         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6051
6052         /* set the RB to use vmid 0 */
6053         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6054
6055         /* Init gfx ring 0 for pipe 0 */
6056         mutex_lock(&adev->srbm_mutex);
6057         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6058
6059         /* Set ring buffer size */
6060         ring = &adev->gfx.gfx_ring[0];
6061         rb_bufsz = order_base_2(ring->ring_size / 8);
6062         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6063         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6064 #ifdef __BIG_ENDIAN
6065         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6066 #endif
6067         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6068
6069         /* Initialize the ring buffer's write pointers */
6070         ring->wptr = 0;
6071         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6072         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6073
6074         /* set the wb address wether it's enabled or not */
6075         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6076         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6077         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6078                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6079
6080         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6081         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6082                      lower_32_bits(wptr_gpu_addr));
6083         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6084                      upper_32_bits(wptr_gpu_addr));
6085
6086         mdelay(1);
6087         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6088
6089         rb_addr = ring->gpu_addr >> 8;
6090         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6091         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6092
6093         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6094
6095         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6096         mutex_unlock(&adev->srbm_mutex);
6097
6098         /* Init gfx ring 1 for pipe 1 */
6099         if (adev->gfx.num_gfx_rings > 1) {
6100                 mutex_lock(&adev->srbm_mutex);
6101                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6102                 /* maximum supported gfx ring is 2 */
6103                 ring = &adev->gfx.gfx_ring[1];
6104                 rb_bufsz = order_base_2(ring->ring_size / 8);
6105                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6106                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6107                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6108                 /* Initialize the ring buffer's write pointers */
6109                 ring->wptr = 0;
6110                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6111                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6112                 /* Set the wb address wether it's enabled or not */
6113                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6114                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6115                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6116                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6117                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6118                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6119                              lower_32_bits(wptr_gpu_addr));
6120                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6121                              upper_32_bits(wptr_gpu_addr));
6122
6123                 mdelay(1);
6124                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6125
6126                 rb_addr = ring->gpu_addr >> 8;
6127                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6128                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6129                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6130
6131                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6132                 mutex_unlock(&adev->srbm_mutex);
6133         }
6134         /* Switch to pipe 0 */
6135         mutex_lock(&adev->srbm_mutex);
6136         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6137         mutex_unlock(&adev->srbm_mutex);
6138
6139         /* start the ring */
6140         gfx_v10_0_cp_gfx_start(adev);
6141
6142         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6143                 ring = &adev->gfx.gfx_ring[i];
6144                 ring->sched.ready = true;
6145         }
6146
6147         return 0;
6148 }
6149
6150 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6151 {
6152         if (enable) {
6153                 switch (adev->asic_type) {
6154                 case CHIP_SIENNA_CICHLID:
6155                 case CHIP_NAVY_FLOUNDER:
6156                 case CHIP_VANGOGH:
6157                 case CHIP_DIMGREY_CAVEFISH:
6158                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6159                         break;
6160                 default:
6161                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6162                         break;
6163                 }
6164         } else {
6165                 switch (adev->asic_type) {
6166                 case CHIP_SIENNA_CICHLID:
6167                 case CHIP_NAVY_FLOUNDER:
6168                 case CHIP_VANGOGH:
6169                 case CHIP_DIMGREY_CAVEFISH:
6170                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6171                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6172                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6173                         break;
6174                 default:
6175                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6176                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6177                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6178                         break;
6179                 }
6180                 adev->gfx.kiq.ring.sched.ready = false;
6181         }
6182         udelay(50);
6183 }
6184
6185 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6186 {
6187         const struct gfx_firmware_header_v1_0 *mec_hdr;
6188         const __le32 *fw_data;
6189         unsigned i;
6190         u32 tmp;
6191         u32 usec_timeout = 50000; /* Wait for 50 ms */
6192
6193         if (!adev->gfx.mec_fw)
6194                 return -EINVAL;
6195
6196         gfx_v10_0_cp_compute_enable(adev, false);
6197
6198         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6199         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6200
6201         fw_data = (const __le32 *)
6202                 (adev->gfx.mec_fw->data +
6203                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6204
6205         /* Trigger an invalidation of the L1 instruction caches */
6206         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6207         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6208         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6209
6210         /* Wait for invalidation complete */
6211         for (i = 0; i < usec_timeout; i++) {
6212                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6213                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6214                                        INVALIDATE_CACHE_COMPLETE))
6215                         break;
6216                 udelay(1);
6217         }
6218
6219         if (i >= usec_timeout) {
6220                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6221                 return -EINVAL;
6222         }
6223
6224         if (amdgpu_emu_mode == 1)
6225                 adev->hdp.funcs->flush_hdp(adev, NULL);
6226
6227         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6228         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6229         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6230         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6231         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6232
6233         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6234                      0xFFFFF000);
6235         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6236                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6237
6238         /* MEC1 */
6239         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6240
6241         for (i = 0; i < mec_hdr->jt_size; i++)
6242                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6243                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6244
6245         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6246
6247         /*
6248          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6249          * different microcode than MEC1.
6250          */
6251
6252         return 0;
6253 }
6254
6255 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6256 {
6257         uint32_t tmp;
6258         struct amdgpu_device *adev = ring->adev;
6259
6260         /* tell RLC which is KIQ queue */
6261         switch (adev->asic_type) {
6262         case CHIP_SIENNA_CICHLID:
6263         case CHIP_NAVY_FLOUNDER:
6264         case CHIP_VANGOGH:
6265         case CHIP_DIMGREY_CAVEFISH:
6266                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6267                 tmp &= 0xffffff00;
6268                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6269                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6270                 tmp |= 0x80;
6271                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6272                 break;
6273         default:
6274                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6275                 tmp &= 0xffffff00;
6276                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6277                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6278                 tmp |= 0x80;
6279                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6280                 break;
6281         }
6282 }
6283
6284 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6285 {
6286         struct amdgpu_device *adev = ring->adev;
6287         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6288         uint64_t hqd_gpu_addr, wb_gpu_addr;
6289         uint32_t tmp;
6290         uint32_t rb_bufsz;
6291
6292         /* set up gfx hqd wptr */
6293         mqd->cp_gfx_hqd_wptr = 0;
6294         mqd->cp_gfx_hqd_wptr_hi = 0;
6295
6296         /* set the pointer to the MQD */
6297         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6298         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6299
6300         /* set up mqd control */
6301         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6302         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6303         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6304         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6305         mqd->cp_gfx_mqd_control = tmp;
6306
6307         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6308         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6309         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6310         mqd->cp_gfx_hqd_vmid = 0;
6311
6312         /* set up default queue priority level
6313          * 0x0 = low priority, 0x1 = high priority */
6314         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6315         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6316         mqd->cp_gfx_hqd_queue_priority = tmp;
6317
6318         /* set up time quantum */
6319         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6320         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6321         mqd->cp_gfx_hqd_quantum = tmp;
6322
6323         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6324         hqd_gpu_addr = ring->gpu_addr >> 8;
6325         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6326         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6327
6328         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6329         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6330         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6331         mqd->cp_gfx_hqd_rptr_addr_hi =
6332                 upper_32_bits(wb_gpu_addr) & 0xffff;
6333
6334         /* set up rb_wptr_poll addr */
6335         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6336         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6337         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6338
6339         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6340         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6341         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6342         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6343         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6344 #ifdef __BIG_ENDIAN
6345         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6346 #endif
6347         mqd->cp_gfx_hqd_cntl = tmp;
6348
6349         /* set up cp_doorbell_control */
6350         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6351         if (ring->use_doorbell) {
6352                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6353                                     DOORBELL_OFFSET, ring->doorbell_index);
6354                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6355                                     DOORBELL_EN, 1);
6356         } else
6357                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6358                                     DOORBELL_EN, 0);
6359         mqd->cp_rb_doorbell_control = tmp;
6360
6361         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6362          *otherwise the range of the second ring will override the first ring */
6363         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6364                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6365
6366         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6367         ring->wptr = 0;
6368         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6369
6370         /* active the queue */
6371         mqd->cp_gfx_hqd_active = 1;
6372
6373         return 0;
6374 }
6375
6376 #ifdef BRING_UP_DEBUG
6377 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6378 {
6379         struct amdgpu_device *adev = ring->adev;
6380         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6381
6382         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6383         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6384         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6385
6386         /* set GFX_MQD_BASE */
6387         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6388         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6389
6390         /* set GFX_MQD_CONTROL */
6391         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6392
6393         /* set GFX_HQD_VMID to 0 */
6394         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6395
6396         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6397                         mqd->cp_gfx_hqd_queue_priority);
6398         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6399
6400         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6401         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6402         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6403
6404         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6405         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6406         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6407
6408         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6409         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6410
6411         /* set RB_WPTR_POLL_ADDR */
6412         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6413         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6414
6415         /* set RB_DOORBELL_CONTROL */
6416         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6417
6418         /* active the queue */
6419         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6420
6421         return 0;
6422 }
6423 #endif
6424
6425 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6426 {
6427         struct amdgpu_device *adev = ring->adev;
6428         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6429         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6430
6431         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6432                 memset((void *)mqd, 0, sizeof(*mqd));
6433                 mutex_lock(&adev->srbm_mutex);
6434                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6435                 gfx_v10_0_gfx_mqd_init(ring);
6436 #ifdef BRING_UP_DEBUG
6437                 gfx_v10_0_gfx_queue_init_register(ring);
6438 #endif
6439                 nv_grbm_select(adev, 0, 0, 0, 0);
6440                 mutex_unlock(&adev->srbm_mutex);
6441                 if (adev->gfx.me.mqd_backup[mqd_idx])
6442                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6443         } else if (amdgpu_in_reset(adev)) {
6444                 /* reset mqd with the backup copy */
6445                 if (adev->gfx.me.mqd_backup[mqd_idx])
6446                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6447                 /* reset the ring */
6448                 ring->wptr = 0;
6449                 adev->wb.wb[ring->wptr_offs] = 0;
6450                 amdgpu_ring_clear_ring(ring);
6451 #ifdef BRING_UP_DEBUG
6452                 mutex_lock(&adev->srbm_mutex);
6453                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6454                 gfx_v10_0_gfx_queue_init_register(ring);
6455                 nv_grbm_select(adev, 0, 0, 0, 0);
6456                 mutex_unlock(&adev->srbm_mutex);
6457 #endif
6458         } else {
6459                 amdgpu_ring_clear_ring(ring);
6460         }
6461
6462         return 0;
6463 }
6464
6465 #ifndef BRING_UP_DEBUG
6466 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6467 {
6468         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6469         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6470         int r, i;
6471
6472         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6473                 return -EINVAL;
6474
6475         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6476                                         adev->gfx.num_gfx_rings);
6477         if (r) {
6478                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6479                 return r;
6480         }
6481
6482         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6483                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6484
6485         return amdgpu_ring_test_helper(kiq_ring);
6486 }
6487 #endif
6488
6489 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6490 {
6491         int r, i;
6492         struct amdgpu_ring *ring;
6493
6494         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6495                 ring = &adev->gfx.gfx_ring[i];
6496
6497                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6498                 if (unlikely(r != 0))
6499                         goto done;
6500
6501                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6502                 if (!r) {
6503                         r = gfx_v10_0_gfx_init_queue(ring);
6504                         amdgpu_bo_kunmap(ring->mqd_obj);
6505                         ring->mqd_ptr = NULL;
6506                 }
6507                 amdgpu_bo_unreserve(ring->mqd_obj);
6508                 if (r)
6509                         goto done;
6510         }
6511 #ifndef BRING_UP_DEBUG
6512         r = gfx_v10_0_kiq_enable_kgq(adev);
6513         if (r)
6514                 goto done;
6515 #endif
6516         r = gfx_v10_0_cp_gfx_start(adev);
6517         if (r)
6518                 goto done;
6519
6520         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6521                 ring = &adev->gfx.gfx_ring[i];
6522                 ring->sched.ready = true;
6523         }
6524 done:
6525         return r;
6526 }
6527
6528 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6529 {
6530         struct amdgpu_device *adev = ring->adev;
6531
6532         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6533                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
6534                                                               ring->queue)) {
6535                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6536                         mqd->cp_hqd_queue_priority =
6537                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6538                 }
6539         }
6540 }
6541
6542 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6543 {
6544         struct amdgpu_device *adev = ring->adev;
6545         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6546         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6547         uint32_t tmp;
6548
6549         mqd->header = 0xC0310800;
6550         mqd->compute_pipelinestat_enable = 0x00000001;
6551         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6552         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6553         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6554         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6555         mqd->compute_misc_reserved = 0x00000003;
6556
6557         eop_base_addr = ring->eop_gpu_addr >> 8;
6558         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6559         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6560
6561         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6562         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6563         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6564                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6565
6566         mqd->cp_hqd_eop_control = tmp;
6567
6568         /* enable doorbell? */
6569         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6570
6571         if (ring->use_doorbell) {
6572                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6573                                     DOORBELL_OFFSET, ring->doorbell_index);
6574                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6575                                     DOORBELL_EN, 1);
6576                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6577                                     DOORBELL_SOURCE, 0);
6578                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6579                                     DOORBELL_HIT, 0);
6580         } else {
6581                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6582                                     DOORBELL_EN, 0);
6583         }
6584
6585         mqd->cp_hqd_pq_doorbell_control = tmp;
6586
6587         /* disable the queue if it's active */
6588         ring->wptr = 0;
6589         mqd->cp_hqd_dequeue_request = 0;
6590         mqd->cp_hqd_pq_rptr = 0;
6591         mqd->cp_hqd_pq_wptr_lo = 0;
6592         mqd->cp_hqd_pq_wptr_hi = 0;
6593
6594         /* set the pointer to the MQD */
6595         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6596         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6597
6598         /* set MQD vmid to 0 */
6599         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6600         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6601         mqd->cp_mqd_control = tmp;
6602
6603         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6604         hqd_gpu_addr = ring->gpu_addr >> 8;
6605         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6606         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6607
6608         /* set up the HQD, this is similar to CP_RB0_CNTL */
6609         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6610         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6611                             (order_base_2(ring->ring_size / 4) - 1));
6612         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6613                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6614 #ifdef __BIG_ENDIAN
6615         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6616 #endif
6617         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6618         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6619         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6620         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6621         mqd->cp_hqd_pq_control = tmp;
6622
6623         /* set the wb address whether it's enabled or not */
6624         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6625         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6626         mqd->cp_hqd_pq_rptr_report_addr_hi =
6627                 upper_32_bits(wb_gpu_addr) & 0xffff;
6628
6629         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6630         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6631         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6632         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6633
6634         tmp = 0;
6635         /* enable the doorbell if requested */
6636         if (ring->use_doorbell) {
6637                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6638                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6639                                 DOORBELL_OFFSET, ring->doorbell_index);
6640
6641                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6642                                     DOORBELL_EN, 1);
6643                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6644                                     DOORBELL_SOURCE, 0);
6645                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6646                                     DOORBELL_HIT, 0);
6647         }
6648
6649         mqd->cp_hqd_pq_doorbell_control = tmp;
6650
6651         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6652         ring->wptr = 0;
6653         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6654
6655         /* set the vmid for the queue */
6656         mqd->cp_hqd_vmid = 0;
6657
6658         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6659         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6660         mqd->cp_hqd_persistent_state = tmp;
6661
6662         /* set MIN_IB_AVAIL_SIZE */
6663         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6664         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6665         mqd->cp_hqd_ib_control = tmp;
6666
6667         /* set static priority for a compute queue/ring */
6668         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6669
6670         /* map_queues packet doesn't need activate the queue,
6671          * so only kiq need set this field.
6672          */
6673         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6674                 mqd->cp_hqd_active = 1;
6675
6676         return 0;
6677 }
6678
6679 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6680 {
6681         struct amdgpu_device *adev = ring->adev;
6682         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6683         int j;
6684
6685         /* inactivate the queue */
6686         if (amdgpu_sriov_vf(adev))
6687                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6688
6689         /* disable wptr polling */
6690         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6691
6692         /* write the EOP addr */
6693         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6694                mqd->cp_hqd_eop_base_addr_lo);
6695         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6696                mqd->cp_hqd_eop_base_addr_hi);
6697
6698         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6699         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6700                mqd->cp_hqd_eop_control);
6701
6702         /* enable doorbell? */
6703         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6704                mqd->cp_hqd_pq_doorbell_control);
6705
6706         /* disable the queue if it's active */
6707         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6708                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6709                 for (j = 0; j < adev->usec_timeout; j++) {
6710                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6711                                 break;
6712                         udelay(1);
6713                 }
6714                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6715                        mqd->cp_hqd_dequeue_request);
6716                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6717                        mqd->cp_hqd_pq_rptr);
6718                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6719                        mqd->cp_hqd_pq_wptr_lo);
6720                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6721                        mqd->cp_hqd_pq_wptr_hi);
6722         }
6723
6724         /* set the pointer to the MQD */
6725         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6726                mqd->cp_mqd_base_addr_lo);
6727         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6728                mqd->cp_mqd_base_addr_hi);
6729
6730         /* set MQD vmid to 0 */
6731         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6732                mqd->cp_mqd_control);
6733
6734         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6735         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6736                mqd->cp_hqd_pq_base_lo);
6737         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6738                mqd->cp_hqd_pq_base_hi);
6739
6740         /* set up the HQD, this is similar to CP_RB0_CNTL */
6741         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6742                mqd->cp_hqd_pq_control);
6743
6744         /* set the wb address whether it's enabled or not */
6745         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6746                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6747         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6748                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6749
6750         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6751         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6752                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6753         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6754                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6755
6756         /* enable the doorbell if requested */
6757         if (ring->use_doorbell) {
6758                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6759                         (adev->doorbell_index.kiq * 2) << 2);
6760                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6761                         (adev->doorbell_index.userqueue_end * 2) << 2);
6762         }
6763
6764         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6765                mqd->cp_hqd_pq_doorbell_control);
6766
6767         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6768         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6769                mqd->cp_hqd_pq_wptr_lo);
6770         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6771                mqd->cp_hqd_pq_wptr_hi);
6772
6773         /* set the vmid for the queue */
6774         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6775
6776         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6777                mqd->cp_hqd_persistent_state);
6778
6779         /* activate the queue */
6780         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6781                mqd->cp_hqd_active);
6782
6783         if (ring->use_doorbell)
6784                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6785
6786         return 0;
6787 }
6788
6789 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6790 {
6791         struct amdgpu_device *adev = ring->adev;
6792         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6793         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6794
6795         gfx_v10_0_kiq_setting(ring);
6796
6797         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6798                 /* reset MQD to a clean status */
6799                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6800                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6801
6802                 /* reset ring buffer */
6803                 ring->wptr = 0;
6804                 amdgpu_ring_clear_ring(ring);
6805
6806                 mutex_lock(&adev->srbm_mutex);
6807                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6808                 gfx_v10_0_kiq_init_register(ring);
6809                 nv_grbm_select(adev, 0, 0, 0, 0);
6810                 mutex_unlock(&adev->srbm_mutex);
6811         } else {
6812                 memset((void *)mqd, 0, sizeof(*mqd));
6813                 mutex_lock(&adev->srbm_mutex);
6814                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6815                 gfx_v10_0_compute_mqd_init(ring);
6816                 gfx_v10_0_kiq_init_register(ring);
6817                 nv_grbm_select(adev, 0, 0, 0, 0);
6818                 mutex_unlock(&adev->srbm_mutex);
6819
6820                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6821                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6822         }
6823
6824         return 0;
6825 }
6826
6827 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6828 {
6829         struct amdgpu_device *adev = ring->adev;
6830         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6831         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6832
6833         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6834                 memset((void *)mqd, 0, sizeof(*mqd));
6835                 mutex_lock(&adev->srbm_mutex);
6836                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6837                 gfx_v10_0_compute_mqd_init(ring);
6838                 nv_grbm_select(adev, 0, 0, 0, 0);
6839                 mutex_unlock(&adev->srbm_mutex);
6840
6841                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6842                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6843         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6844                 /* reset MQD to a clean status */
6845                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6846                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6847
6848                 /* reset ring buffer */
6849                 ring->wptr = 0;
6850                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6851                 amdgpu_ring_clear_ring(ring);
6852         } else {
6853                 amdgpu_ring_clear_ring(ring);
6854         }
6855
6856         return 0;
6857 }
6858
6859 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6860 {
6861         struct amdgpu_ring *ring;
6862         int r;
6863
6864         ring = &adev->gfx.kiq.ring;
6865
6866         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6867         if (unlikely(r != 0))
6868                 return r;
6869
6870         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6871         if (unlikely(r != 0))
6872                 return r;
6873
6874         gfx_v10_0_kiq_init_queue(ring);
6875         amdgpu_bo_kunmap(ring->mqd_obj);
6876         ring->mqd_ptr = NULL;
6877         amdgpu_bo_unreserve(ring->mqd_obj);
6878         ring->sched.ready = true;
6879         return 0;
6880 }
6881
6882 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6883 {
6884         struct amdgpu_ring *ring = NULL;
6885         int r = 0, i;
6886
6887         gfx_v10_0_cp_compute_enable(adev, true);
6888
6889         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6890                 ring = &adev->gfx.compute_ring[i];
6891
6892                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6893                 if (unlikely(r != 0))
6894                         goto done;
6895                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6896                 if (!r) {
6897                         r = gfx_v10_0_kcq_init_queue(ring);
6898                         amdgpu_bo_kunmap(ring->mqd_obj);
6899                         ring->mqd_ptr = NULL;
6900                 }
6901                 amdgpu_bo_unreserve(ring->mqd_obj);
6902                 if (r)
6903                         goto done;
6904         }
6905
6906         r = amdgpu_gfx_enable_kcq(adev);
6907 done:
6908         return r;
6909 }
6910
6911 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6912 {
6913         int r, i;
6914         struct amdgpu_ring *ring;
6915
6916         if (!(adev->flags & AMD_IS_APU))
6917                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6918
6919         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6920                 /* legacy firmware loading */
6921                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6922                 if (r)
6923                         return r;
6924
6925                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6926                 if (r)
6927                         return r;
6928         }
6929
6930         r = gfx_v10_0_kiq_resume(adev);
6931         if (r)
6932                 return r;
6933
6934         r = gfx_v10_0_kcq_resume(adev);
6935         if (r)
6936                 return r;
6937
6938         if (!amdgpu_async_gfx_ring) {
6939                 r = gfx_v10_0_cp_gfx_resume(adev);
6940                 if (r)
6941                         return r;
6942         } else {
6943                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6944                 if (r)
6945                         return r;
6946         }
6947
6948         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6949                 ring = &adev->gfx.gfx_ring[i];
6950                 r = amdgpu_ring_test_helper(ring);
6951                 if (r)
6952                         return r;
6953         }
6954
6955         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6956                 ring = &adev->gfx.compute_ring[i];
6957                 r = amdgpu_ring_test_helper(ring);
6958                 if (r)
6959                         return r;
6960         }
6961
6962         return 0;
6963 }
6964
6965 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6966 {
6967         gfx_v10_0_cp_gfx_enable(adev, enable);
6968         gfx_v10_0_cp_compute_enable(adev, enable);
6969 }
6970
6971 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6972 {
6973         uint32_t data, pattern = 0xDEADBEEF;
6974
6975         /* check if mmVGT_ESGS_RING_SIZE_UMD
6976          * has been remapped to mmVGT_ESGS_RING_SIZE */
6977         switch (adev->asic_type) {
6978         case CHIP_SIENNA_CICHLID:
6979         case CHIP_NAVY_FLOUNDER:
6980         case CHIP_DIMGREY_CAVEFISH:
6981                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6982                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6983                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6984
6985                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6986                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6987                         return true;
6988                 } else {
6989                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6990                         return false;
6991                 }
6992                 break;
6993         case CHIP_VANGOGH:
6994                 return true;
6995         default:
6996                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6997                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6998                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6999
7000                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7001                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7002                         return true;
7003                 } else {
7004                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7005                         return false;
7006                 }
7007                 break;
7008         }
7009 }
7010
7011 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7012 {
7013         uint32_t data;
7014
7015         /* initialize cam_index to 0
7016          * index will auto-inc after each data writting */
7017         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7018
7019         switch (adev->asic_type) {
7020         case CHIP_SIENNA_CICHLID:
7021         case CHIP_NAVY_FLOUNDER:
7022         case CHIP_VANGOGH:
7023         case CHIP_DIMGREY_CAVEFISH:
7024                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7025                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7026                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7027                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7028                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7029                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7030                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7031
7032                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7033                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7034                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7035                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7036                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7037                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7038                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7039
7040                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7041                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7042                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7043                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7044                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7045                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7046                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7047
7048                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7049                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7050                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7051                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7052                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7053                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7054                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7055
7056                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7057                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7058                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7059                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7060                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7061                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7062                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7063
7064                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7065                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7066                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7067                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7068                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7069                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7070                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7071
7072                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7073                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7074                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7075                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7076                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7077                 break;
7078         default:
7079                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7080                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7081                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7082                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7083                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7084                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7085                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7086
7087                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7088                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7089                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7090                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7091                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7092                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7093                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7094
7095                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7096                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7097                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7098                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7099                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7100                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7101                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7102
7103                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7104                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7105                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7106                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7107                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7108                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7109                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7110
7111                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7112                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7113                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7114                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7115                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7116                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7117                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7118
7119                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7120                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7121                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7122                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7123                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7124                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7125                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7126
7127                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7128                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7129                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7130                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7131                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7132                 break;
7133         }
7134
7135         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7136         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7137 }
7138
7139 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7140 {
7141         uint32_t data;
7142         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7143         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7144         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7145
7146         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7147         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7148         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7149 }
7150
7151 static int gfx_v10_0_hw_init(void *handle)
7152 {
7153         int r;
7154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7155
7156         if (!amdgpu_emu_mode)
7157                 gfx_v10_0_init_golden_registers(adev);
7158
7159         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7160                 /**
7161                  * For gfx 10, rlc firmware loading relies on smu firmware is
7162                  * loaded firstly, so in direct type, it has to load smc ucode
7163                  * here before rlc.
7164                  */
7165                 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
7166                         r = smu_load_microcode(&adev->smu);
7167                         if (r)
7168                                 return r;
7169
7170                         r = smu_check_fw_status(&adev->smu);
7171                         if (r) {
7172                                 pr_err("SMC firmware status is not correct\n");
7173                                 return r;
7174                         }
7175                 }
7176                 gfx_v10_0_disable_gpa_mode(adev);
7177         }
7178
7179         /* if GRBM CAM not remapped, set up the remapping */
7180         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7181                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7182
7183         gfx_v10_0_constants_init(adev);
7184
7185         r = gfx_v10_0_rlc_resume(adev);
7186         if (r)
7187                 return r;
7188
7189         /*
7190          * init golden registers and rlc resume may override some registers,
7191          * reconfig them here
7192          */
7193         gfx_v10_0_tcp_harvest(adev);
7194
7195         r = gfx_v10_0_cp_resume(adev);
7196         if (r)
7197                 return r;
7198
7199         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7200                 gfx_v10_3_program_pbb_mode(adev);
7201
7202         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7203                 gfx_v10_3_set_power_brake_sequence(adev);
7204
7205         return r;
7206 }
7207
7208 #ifndef BRING_UP_DEBUG
7209 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7210 {
7211         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7212         struct amdgpu_ring *kiq_ring = &kiq->ring;
7213         int i;
7214
7215         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7216                 return -EINVAL;
7217
7218         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7219                                         adev->gfx.num_gfx_rings))
7220                 return -ENOMEM;
7221
7222         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7223                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7224                                            PREEMPT_QUEUES, 0, 0);
7225
7226         return amdgpu_ring_test_helper(kiq_ring);
7227 }
7228 #endif
7229
7230 static int gfx_v10_0_hw_fini(void *handle)
7231 {
7232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7233         int r;
7234         uint32_t tmp;
7235
7236         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7237         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7238
7239         if (!adev->in_pci_err_recovery) {
7240 #ifndef BRING_UP_DEBUG
7241                 if (amdgpu_async_gfx_ring) {
7242                         r = gfx_v10_0_kiq_disable_kgq(adev);
7243                         if (r)
7244                                 DRM_ERROR("KGQ disable failed\n");
7245                 }
7246 #endif
7247                 if (amdgpu_gfx_disable_kcq(adev))
7248                         DRM_ERROR("KCQ disable failed\n");
7249         }
7250
7251         if (amdgpu_sriov_vf(adev)) {
7252                 gfx_v10_0_cp_gfx_enable(adev, false);
7253                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7254                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7255                 tmp &= 0xffffff00;
7256                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7257
7258                 return 0;
7259         }
7260         gfx_v10_0_cp_enable(adev, false);
7261         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7262
7263         return 0;
7264 }
7265
7266 static int gfx_v10_0_suspend(void *handle)
7267 {
7268         return gfx_v10_0_hw_fini(handle);
7269 }
7270
7271 static int gfx_v10_0_resume(void *handle)
7272 {
7273         return gfx_v10_0_hw_init(handle);
7274 }
7275
7276 static bool gfx_v10_0_is_idle(void *handle)
7277 {
7278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7279
7280         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7281                                 GRBM_STATUS, GUI_ACTIVE))
7282                 return false;
7283         else
7284                 return true;
7285 }
7286
7287 static int gfx_v10_0_wait_for_idle(void *handle)
7288 {
7289         unsigned i;
7290         u32 tmp;
7291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7292
7293         for (i = 0; i < adev->usec_timeout; i++) {
7294                 /* read MC_STATUS */
7295                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7296                         GRBM_STATUS__GUI_ACTIVE_MASK;
7297
7298                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7299                         return 0;
7300                 udelay(1);
7301         }
7302         return -ETIMEDOUT;
7303 }
7304
7305 static int gfx_v10_0_soft_reset(void *handle)
7306 {
7307         u32 grbm_soft_reset = 0;
7308         u32 tmp;
7309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7310
7311         /* GRBM_STATUS */
7312         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7313         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7314                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7315                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7316                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7317                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7318                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7319                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7320                                                 1);
7321                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7322                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7323                                                 1);
7324         }
7325
7326         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7327                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7328                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7329                                                 1);
7330         }
7331
7332         /* GRBM_STATUS2 */
7333         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7334         switch (adev->asic_type) {
7335         case CHIP_SIENNA_CICHLID:
7336         case CHIP_NAVY_FLOUNDER:
7337         case CHIP_VANGOGH:
7338         case CHIP_DIMGREY_CAVEFISH:
7339                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7340                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7341                                                         GRBM_SOFT_RESET,
7342                                                         SOFT_RESET_RLC,
7343                                                         1);
7344                 break;
7345         default:
7346                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7347                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7348                                                         GRBM_SOFT_RESET,
7349                                                         SOFT_RESET_RLC,
7350                                                         1);
7351                 break;
7352         }
7353
7354         if (grbm_soft_reset) {
7355                 /* stop the rlc */
7356                 gfx_v10_0_rlc_stop(adev);
7357
7358                 /* Disable GFX parsing/prefetching */
7359                 gfx_v10_0_cp_gfx_enable(adev, false);
7360
7361                 /* Disable MEC parsing/prefetching */
7362                 gfx_v10_0_cp_compute_enable(adev, false);
7363
7364                 if (grbm_soft_reset) {
7365                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7366                         tmp |= grbm_soft_reset;
7367                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7368                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7369                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7370
7371                         udelay(50);
7372
7373                         tmp &= ~grbm_soft_reset;
7374                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7375                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7376                 }
7377
7378                 /* Wait a little for things to settle down */
7379                 udelay(50);
7380         }
7381         return 0;
7382 }
7383
7384 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7385 {
7386         uint64_t clock;
7387
7388         amdgpu_gfx_off_ctrl(adev, false);
7389         mutex_lock(&adev->gfx.gpu_clock_mutex);
7390         switch (adev->asic_type) {
7391         case CHIP_VANGOGH:
7392                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7393                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7394                 break;
7395         default:
7396                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7397                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7398                 break;
7399         }
7400         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7401         amdgpu_gfx_off_ctrl(adev, true);
7402         return clock;
7403 }
7404
7405 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7406                                            uint32_t vmid,
7407                                            uint32_t gds_base, uint32_t gds_size,
7408                                            uint32_t gws_base, uint32_t gws_size,
7409                                            uint32_t oa_base, uint32_t oa_size)
7410 {
7411         struct amdgpu_device *adev = ring->adev;
7412
7413         /* GDS Base */
7414         gfx_v10_0_write_data_to_reg(ring, 0, false,
7415                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7416                                     gds_base);
7417
7418         /* GDS Size */
7419         gfx_v10_0_write_data_to_reg(ring, 0, false,
7420                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7421                                     gds_size);
7422
7423         /* GWS */
7424         gfx_v10_0_write_data_to_reg(ring, 0, false,
7425                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7426                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7427
7428         /* OA */
7429         gfx_v10_0_write_data_to_reg(ring, 0, false,
7430                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7431                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7432 }
7433
7434 static int gfx_v10_0_early_init(void *handle)
7435 {
7436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7437
7438         switch (adev->asic_type) {
7439         case CHIP_NAVI10:
7440         case CHIP_NAVI14:
7441         case CHIP_NAVI12:
7442                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7443                 break;
7444         case CHIP_SIENNA_CICHLID:
7445         case CHIP_NAVY_FLOUNDER:
7446         case CHIP_VANGOGH:
7447         case CHIP_DIMGREY_CAVEFISH:
7448                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7449                 break;
7450         default:
7451                 break;
7452         }
7453
7454         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7455                                           AMDGPU_MAX_COMPUTE_RINGS);
7456
7457         gfx_v10_0_set_kiq_pm4_funcs(adev);
7458         gfx_v10_0_set_ring_funcs(adev);
7459         gfx_v10_0_set_irq_funcs(adev);
7460         gfx_v10_0_set_gds_init(adev);
7461         gfx_v10_0_set_rlc_funcs(adev);
7462
7463         return 0;
7464 }
7465
7466 static int gfx_v10_0_late_init(void *handle)
7467 {
7468         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7469         int r;
7470
7471         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7472         if (r)
7473                 return r;
7474
7475         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7476         if (r)
7477                 return r;
7478
7479         return 0;
7480 }
7481
7482 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7483 {
7484         uint32_t rlc_cntl;
7485
7486         /* if RLC is not enabled, do nothing */
7487         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7488         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7489 }
7490
7491 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7492 {
7493         uint32_t data;
7494         unsigned i;
7495
7496         data = RLC_SAFE_MODE__CMD_MASK;
7497         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7498
7499         switch (adev->asic_type) {
7500         case CHIP_SIENNA_CICHLID:
7501         case CHIP_NAVY_FLOUNDER:
7502         case CHIP_VANGOGH:
7503         case CHIP_DIMGREY_CAVEFISH:
7504                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7505
7506                 /* wait for RLC_SAFE_MODE */
7507                 for (i = 0; i < adev->usec_timeout; i++) {
7508                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7509                                            RLC_SAFE_MODE, CMD))
7510                                 break;
7511                         udelay(1);
7512                 }
7513                 break;
7514         default:
7515                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7516
7517                 /* wait for RLC_SAFE_MODE */
7518                 for (i = 0; i < adev->usec_timeout; i++) {
7519                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7520                                            RLC_SAFE_MODE, CMD))
7521                                 break;
7522                         udelay(1);
7523                 }
7524                 break;
7525         }
7526 }
7527
7528 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7529 {
7530         uint32_t data;
7531
7532         data = RLC_SAFE_MODE__CMD_MASK;
7533         switch (adev->asic_type) {
7534         case CHIP_SIENNA_CICHLID:
7535         case CHIP_NAVY_FLOUNDER:
7536         case CHIP_VANGOGH:
7537         case CHIP_DIMGREY_CAVEFISH:
7538                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7539                 break;
7540         default:
7541                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7542                 break;
7543         }
7544 }
7545
7546 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7547                                                       bool enable)
7548 {
7549         uint32_t data, def;
7550
7551         /* It is disabled by HW by default */
7552         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7553                 /* 0 - Disable some blocks' MGCG */
7554                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7555                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7556                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7557                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7558
7559                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7560                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7561                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7562                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7563                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7564                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7565                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7566
7567                 if (def != data)
7568                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7569
7570                 /* MGLS is a global flag to control all MGLS in GFX */
7571                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7572                         /* 2 - RLC memory Light sleep */
7573                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7574                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7575                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7576                                 if (def != data)
7577                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7578                         }
7579                         /* 3 - CP memory Light sleep */
7580                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7581                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7582                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7583                                 if (def != data)
7584                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7585                         }
7586                 }
7587         } else {
7588                 /* 1 - MGCG_OVERRIDE */
7589                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7590                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7591                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7592                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7593                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7594                 if (def != data)
7595                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7596
7597                 /* 2 - disable MGLS in CP */
7598                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7599                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7600                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7601                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7602                 }
7603
7604                 /* 3 - disable MGLS in RLC */
7605                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7606                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7607                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7608                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7609                 }
7610
7611         }
7612 }
7613
7614 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7615                                            bool enable)
7616 {
7617         uint32_t data, def;
7618
7619         /* Enable 3D CGCG/CGLS */
7620         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7621                 /* write cmd to clear cgcg/cgls ov */
7622                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7623                 /* unset CGCG override */
7624                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7625                 /* update CGCG and CGLS override bits */
7626                 if (def != data)
7627                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7628                 /* enable 3Dcgcg FSM(0x0000363f) */
7629                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7630                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7631                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7632                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7633                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7634                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7635                 if (def != data)
7636                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7637
7638                 /* set IDLE_POLL_COUNT(0x00900100) */
7639                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7640                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7641                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7642                 if (def != data)
7643                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7644         } else {
7645                 /* Disable CGCG/CGLS */
7646                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7647                 /* disable cgcg, cgls should be disabled */
7648                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7649                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7650                 /* disable cgcg and cgls in FSM */
7651                 if (def != data)
7652                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7653         }
7654 }
7655
7656 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7657                                                       bool enable)
7658 {
7659         uint32_t def, data;
7660
7661         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7662                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7663                 /* unset CGCG override */
7664                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7665                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7666                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7667                 else
7668                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7669                 /* update CGCG and CGLS override bits */
7670                 if (def != data)
7671                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7672
7673                 /* enable cgcg FSM(0x0000363F) */
7674                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7675                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7676                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7677                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7678                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7679                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7680                 if (def != data)
7681                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7682
7683                 /* set IDLE_POLL_COUNT(0x00900100) */
7684                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7685                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7686                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7687                 if (def != data)
7688                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7689         } else {
7690                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7691                 /* reset CGCG/CGLS bits */
7692                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7693                 /* disable cgcg and cgls in FSM */
7694                 if (def != data)
7695                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7696         }
7697 }
7698
7699 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7700                                                       bool enable)
7701 {
7702         uint32_t def, data;
7703
7704         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7705                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7706                 /* unset FGCG override */
7707                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7708                 /* update FGCG override bits */
7709                 if (def != data)
7710                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7711
7712                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7713                 /* unset RLC SRAM CLK GATER override */
7714                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7715                 /* update RLC SRAM CLK GATER override bits */
7716                 if (def != data)
7717                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7718         } else {
7719                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7720                 /* reset FGCG bits */
7721                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7722                 /* disable FGCG*/
7723                 if (def != data)
7724                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7725
7726                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7727                 /* reset RLC SRAM CLK GATER bits */
7728                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7729                 /* disable RLC SRAM CLK*/
7730                 if (def != data)
7731                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7732         }
7733 }
7734
7735 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7736                                             bool enable)
7737 {
7738         amdgpu_gfx_rlc_enter_safe_mode(adev);
7739
7740         if (enable) {
7741                 /* enable FGCG firstly*/
7742                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7743                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7744                  * ===  MGCG + MGLS ===
7745                  */
7746                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7747                 /* ===  CGCG /CGLS for GFX 3D Only === */
7748                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7749                 /* ===  CGCG + CGLS === */
7750                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7751         } else {
7752                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7753                  * ===  CGCG + CGLS ===
7754                  */
7755                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7756                 /* ===  CGCG /CGLS for GFX 3D Only === */
7757                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7758                 /* ===  MGCG + MGLS === */
7759                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7760                 /* disable fgcg at last*/
7761                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7762         }
7763
7764         if (adev->cg_flags &
7765             (AMD_CG_SUPPORT_GFX_MGCG |
7766              AMD_CG_SUPPORT_GFX_CGLS |
7767              AMD_CG_SUPPORT_GFX_CGCG |
7768              AMD_CG_SUPPORT_GFX_3D_CGCG |
7769              AMD_CG_SUPPORT_GFX_3D_CGLS))
7770                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7771
7772         amdgpu_gfx_rlc_exit_safe_mode(adev);
7773
7774         return 0;
7775 }
7776
7777 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7778 {
7779         u32 reg, data;
7780
7781         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7782         if (amdgpu_sriov_is_pp_one_vf(adev))
7783                 data = RREG32_NO_KIQ(reg);
7784         else
7785                 data = RREG32(reg);
7786
7787         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7788         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7789
7790         if (amdgpu_sriov_is_pp_one_vf(adev))
7791                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7792         else
7793                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7794 }
7795
7796 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7797                                         uint32_t offset,
7798                                         struct soc15_reg_rlcg *entries, int arr_size)
7799 {
7800         int i;
7801         uint32_t reg;
7802
7803         if (!entries)
7804                 return false;
7805
7806         for (i = 0; i < arr_size; i++) {
7807                 const struct soc15_reg_rlcg *entry;
7808
7809                 entry = &entries[i];
7810                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7811                 if (offset == reg)
7812                         return true;
7813         }
7814
7815         return false;
7816 }
7817
7818 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7819 {
7820         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7821 }
7822
7823 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7824 {
7825         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7826
7827         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7828                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7829         else
7830                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7831
7832         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7833 }
7834
7835 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7836 {
7837         amdgpu_gfx_rlc_enter_safe_mode(adev);
7838
7839         gfx_v10_cntl_power_gating(adev, enable);
7840
7841         amdgpu_gfx_rlc_exit_safe_mode(adev);
7842 }
7843
7844 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7845         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7846         .set_safe_mode = gfx_v10_0_set_safe_mode,
7847         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7848         .init = gfx_v10_0_rlc_init,
7849         .get_csb_size = gfx_v10_0_get_csb_size,
7850         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7851         .resume = gfx_v10_0_rlc_resume,
7852         .stop = gfx_v10_0_rlc_stop,
7853         .reset = gfx_v10_0_rlc_reset,
7854         .start = gfx_v10_0_rlc_start,
7855         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7856 };
7857
7858 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7859         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7860         .set_safe_mode = gfx_v10_0_set_safe_mode,
7861         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7862         .init = gfx_v10_0_rlc_init,
7863         .get_csb_size = gfx_v10_0_get_csb_size,
7864         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7865         .resume = gfx_v10_0_rlc_resume,
7866         .stop = gfx_v10_0_rlc_stop,
7867         .reset = gfx_v10_0_rlc_reset,
7868         .start = gfx_v10_0_rlc_start,
7869         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7870         .rlcg_wreg = gfx_v10_rlcg_wreg,
7871         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7872 };
7873
7874 static int gfx_v10_0_set_powergating_state(void *handle,
7875                                           enum amd_powergating_state state)
7876 {
7877         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7878         bool enable = (state == AMD_PG_STATE_GATE);
7879
7880         if (amdgpu_sriov_vf(adev))
7881                 return 0;
7882
7883         switch (adev->asic_type) {
7884         case CHIP_NAVI10:
7885         case CHIP_NAVI14:
7886         case CHIP_NAVI12:
7887         case CHIP_SIENNA_CICHLID:
7888         case CHIP_NAVY_FLOUNDER:
7889         case CHIP_DIMGREY_CAVEFISH:
7890                 amdgpu_gfx_off_ctrl(adev, enable);
7891                 break;
7892         case CHIP_VANGOGH:
7893                 gfx_v10_cntl_pg(adev, enable);
7894                 break;
7895         default:
7896                 break;
7897         }
7898         return 0;
7899 }
7900
7901 static int gfx_v10_0_set_clockgating_state(void *handle,
7902                                           enum amd_clockgating_state state)
7903 {
7904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7905
7906         if (amdgpu_sriov_vf(adev))
7907                 return 0;
7908
7909         switch (adev->asic_type) {
7910         case CHIP_NAVI10:
7911         case CHIP_NAVI14:
7912         case CHIP_NAVI12:
7913         case CHIP_SIENNA_CICHLID:
7914         case CHIP_NAVY_FLOUNDER:
7915         case CHIP_VANGOGH:
7916         case CHIP_DIMGREY_CAVEFISH:
7917                 gfx_v10_0_update_gfx_clock_gating(adev,
7918                                                  state == AMD_CG_STATE_GATE);
7919                 break;
7920         default:
7921                 break;
7922         }
7923         return 0;
7924 }
7925
7926 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7927 {
7928         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7929         int data;
7930
7931         /* AMD_CG_SUPPORT_GFX_FGCG */
7932         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7933         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
7934                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
7935
7936         /* AMD_CG_SUPPORT_GFX_MGCG */
7937         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7938         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7939                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7940
7941         /* AMD_CG_SUPPORT_GFX_CGCG */
7942         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7943         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7944                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7945
7946         /* AMD_CG_SUPPORT_GFX_CGLS */
7947         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7948                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7949
7950         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7951         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7952         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7953                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7954
7955         /* AMD_CG_SUPPORT_GFX_CP_LS */
7956         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7957         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7958                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7959
7960         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7961         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7962         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7963                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7964
7965         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7966         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7967                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7968 }
7969
7970 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7971 {
7972         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7973 }
7974
7975 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7976 {
7977         struct amdgpu_device *adev = ring->adev;
7978         u64 wptr;
7979
7980         /* XXX check if swapping is necessary on BE */
7981         if (ring->use_doorbell) {
7982                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7983         } else {
7984                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7985                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7986         }
7987
7988         return wptr;
7989 }
7990
7991 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7992 {
7993         struct amdgpu_device *adev = ring->adev;
7994
7995         if (ring->use_doorbell) {
7996                 /* XXX check if swapping is necessary on BE */
7997                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7998                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7999         } else {
8000                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8001                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8002         }
8003 }
8004
8005 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8006 {
8007         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8008 }
8009
8010 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8011 {
8012         u64 wptr;
8013
8014         /* XXX check if swapping is necessary on BE */
8015         if (ring->use_doorbell)
8016                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8017         else
8018                 BUG();
8019         return wptr;
8020 }
8021
8022 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8023 {
8024         struct amdgpu_device *adev = ring->adev;
8025
8026         /* XXX check if swapping is necessary on BE */
8027         if (ring->use_doorbell) {
8028                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8029                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8030         } else {
8031                 BUG(); /* only DOORBELL method supported on gfx10 now */
8032         }
8033 }
8034
8035 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8036 {
8037         struct amdgpu_device *adev = ring->adev;
8038         u32 ref_and_mask, reg_mem_engine;
8039         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8040
8041         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8042                 switch (ring->me) {
8043                 case 1:
8044                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8045                         break;
8046                 case 2:
8047                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8048                         break;
8049                 default:
8050                         return;
8051                 }
8052                 reg_mem_engine = 0;
8053         } else {
8054                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8055                 reg_mem_engine = 1; /* pfp */
8056         }
8057
8058         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8059                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8060                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8061                                ref_and_mask, ref_and_mask, 0x20);
8062 }
8063
8064 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8065                                        struct amdgpu_job *job,
8066                                        struct amdgpu_ib *ib,
8067                                        uint32_t flags)
8068 {
8069         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8070         u32 header, control = 0;
8071
8072         if (ib->flags & AMDGPU_IB_FLAG_CE)
8073                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8074         else
8075                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8076
8077         control |= ib->length_dw | (vmid << 24);
8078
8079         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8080                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8081
8082                 if (flags & AMDGPU_IB_PREEMPTED)
8083                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8084
8085                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8086                         gfx_v10_0_ring_emit_de_meta(ring,
8087                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8088         }
8089
8090         amdgpu_ring_write(ring, header);
8091         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8092         amdgpu_ring_write(ring,
8093 #ifdef __BIG_ENDIAN
8094                 (2 << 0) |
8095 #endif
8096                 lower_32_bits(ib->gpu_addr));
8097         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8098         amdgpu_ring_write(ring, control);
8099 }
8100
8101 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8102                                            struct amdgpu_job *job,
8103                                            struct amdgpu_ib *ib,
8104                                            uint32_t flags)
8105 {
8106         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8107         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8108
8109         /* Currently, there is a high possibility to get wave ID mismatch
8110          * between ME and GDS, leading to a hw deadlock, because ME generates
8111          * different wave IDs than the GDS expects. This situation happens
8112          * randomly when at least 5 compute pipes use GDS ordered append.
8113          * The wave IDs generated by ME are also wrong after suspend/resume.
8114          * Those are probably bugs somewhere else in the kernel driver.
8115          *
8116          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8117          * GDS to 0 for this ring (me/pipe).
8118          */
8119         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8120                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8121                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8122                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8123         }
8124
8125         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8126         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8127         amdgpu_ring_write(ring,
8128 #ifdef __BIG_ENDIAN
8129                                 (2 << 0) |
8130 #endif
8131                                 lower_32_bits(ib->gpu_addr));
8132         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8133         amdgpu_ring_write(ring, control);
8134 }
8135
8136 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8137                                      u64 seq, unsigned flags)
8138 {
8139         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8140         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8141
8142         /* RELEASE_MEM - flush caches, send int */
8143         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8144         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8145                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8146                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8147                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8148                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8149                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8150                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8151         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8152                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8153
8154         /*
8155          * the address should be Qword aligned if 64bit write, Dword
8156          * aligned if only send 32bit data low (discard data high)
8157          */
8158         if (write64bit)
8159                 BUG_ON(addr & 0x7);
8160         else
8161                 BUG_ON(addr & 0x3);
8162         amdgpu_ring_write(ring, lower_32_bits(addr));
8163         amdgpu_ring_write(ring, upper_32_bits(addr));
8164         amdgpu_ring_write(ring, lower_32_bits(seq));
8165         amdgpu_ring_write(ring, upper_32_bits(seq));
8166         amdgpu_ring_write(ring, 0);
8167 }
8168
8169 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8170 {
8171         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8172         uint32_t seq = ring->fence_drv.sync_seq;
8173         uint64_t addr = ring->fence_drv.gpu_addr;
8174
8175         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8176                                upper_32_bits(addr), seq, 0xffffffff, 4);
8177 }
8178
8179 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8180                                          unsigned vmid, uint64_t pd_addr)
8181 {
8182         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8183
8184         /* compute doesn't have PFP */
8185         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8186                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8187                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8188                 amdgpu_ring_write(ring, 0x0);
8189         }
8190 }
8191
8192 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8193                                           u64 seq, unsigned int flags)
8194 {
8195         struct amdgpu_device *adev = ring->adev;
8196
8197         /* we only allocate 32bit for each seq wb address */
8198         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8199
8200         /* write fence seq to the "addr" */
8201         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8202         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8203                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8204         amdgpu_ring_write(ring, lower_32_bits(addr));
8205         amdgpu_ring_write(ring, upper_32_bits(addr));
8206         amdgpu_ring_write(ring, lower_32_bits(seq));
8207
8208         if (flags & AMDGPU_FENCE_FLAG_INT) {
8209                 /* set register to trigger INT */
8210                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8211                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8212                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8213                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8214                 amdgpu_ring_write(ring, 0);
8215                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8216         }
8217 }
8218
8219 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8220 {
8221         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8222         amdgpu_ring_write(ring, 0);
8223 }
8224
8225 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8226                                          uint32_t flags)
8227 {
8228         uint32_t dw2 = 0;
8229
8230         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8231                 gfx_v10_0_ring_emit_ce_meta(ring,
8232                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8233
8234         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8235         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8236                 /* set load_global_config & load_global_uconfig */
8237                 dw2 |= 0x8001;
8238                 /* set load_cs_sh_regs */
8239                 dw2 |= 0x01000000;
8240                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8241                 dw2 |= 0x10002;
8242
8243                 /* set load_ce_ram if preamble presented */
8244                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8245                         dw2 |= 0x10000000;
8246         } else {
8247                 /* still load_ce_ram if this is the first time preamble presented
8248                  * although there is no context switch happens.
8249                  */
8250                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8251                         dw2 |= 0x10000000;
8252         }
8253
8254         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8255         amdgpu_ring_write(ring, dw2);
8256         amdgpu_ring_write(ring, 0);
8257 }
8258
8259 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8260 {
8261         unsigned ret;
8262
8263         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8264         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8265         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8266         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8267         ret = ring->wptr & ring->buf_mask;
8268         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8269
8270         return ret;
8271 }
8272
8273 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8274 {
8275         unsigned cur;
8276         BUG_ON(offset > ring->buf_mask);
8277         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8278
8279         cur = (ring->wptr - 1) & ring->buf_mask;
8280         if (likely(cur > offset))
8281                 ring->ring[offset] = cur - offset;
8282         else
8283                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8284 }
8285
8286 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8287 {
8288         int i, r = 0;
8289         struct amdgpu_device *adev = ring->adev;
8290         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8291         struct amdgpu_ring *kiq_ring = &kiq->ring;
8292         unsigned long flags;
8293
8294         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8295                 return -EINVAL;
8296
8297         spin_lock_irqsave(&kiq->ring_lock, flags);
8298
8299         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8300                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8301                 return -ENOMEM;
8302         }
8303
8304         /* assert preemption condition */
8305         amdgpu_ring_set_preempt_cond_exec(ring, false);
8306
8307         /* assert IB preemption, emit the trailing fence */
8308         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8309                                    ring->trail_fence_gpu_addr,
8310                                    ++ring->trail_seq);
8311         amdgpu_ring_commit(kiq_ring);
8312
8313         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8314
8315         /* poll the trailing fence */
8316         for (i = 0; i < adev->usec_timeout; i++) {
8317                 if (ring->trail_seq ==
8318                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8319                         break;
8320                 udelay(1);
8321         }
8322
8323         if (i >= adev->usec_timeout) {
8324                 r = -EINVAL;
8325                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8326         }
8327
8328         /* deassert preemption condition */
8329         amdgpu_ring_set_preempt_cond_exec(ring, true);
8330         return r;
8331 }
8332
8333 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8334 {
8335         struct amdgpu_device *adev = ring->adev;
8336         struct v10_ce_ib_state ce_payload = {0};
8337         uint64_t csa_addr;
8338         int cnt;
8339
8340         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8341         csa_addr = amdgpu_csa_vaddr(ring->adev);
8342
8343         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8344         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8345                                  WRITE_DATA_DST_SEL(8) |
8346                                  WR_CONFIRM) |
8347                                  WRITE_DATA_CACHE_POLICY(0));
8348         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8349                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8350         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8351                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8352
8353         if (resume)
8354                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8355                                            offsetof(struct v10_gfx_meta_data,
8356                                                     ce_payload),
8357                                            sizeof(ce_payload) >> 2);
8358         else
8359                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8360                                            sizeof(ce_payload) >> 2);
8361 }
8362
8363 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8364 {
8365         struct amdgpu_device *adev = ring->adev;
8366         struct v10_de_ib_state de_payload = {0};
8367         uint64_t csa_addr, gds_addr;
8368         int cnt;
8369
8370         csa_addr = amdgpu_csa_vaddr(ring->adev);
8371         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8372                          PAGE_SIZE);
8373         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8374         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8375
8376         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8377         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8378         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8379                                  WRITE_DATA_DST_SEL(8) |
8380                                  WR_CONFIRM) |
8381                                  WRITE_DATA_CACHE_POLICY(0));
8382         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8383                               offsetof(struct v10_gfx_meta_data, de_payload)));
8384         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8385                               offsetof(struct v10_gfx_meta_data, de_payload)));
8386
8387         if (resume)
8388                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8389                                            offsetof(struct v10_gfx_meta_data,
8390                                                     de_payload),
8391                                            sizeof(de_payload) >> 2);
8392         else
8393                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8394                                            sizeof(de_payload) >> 2);
8395 }
8396
8397 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8398                                     bool secure)
8399 {
8400         uint32_t v = secure ? FRAME_TMZ : 0;
8401
8402         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8403         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8404 }
8405
8406 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8407                                      uint32_t reg_val_offs)
8408 {
8409         struct amdgpu_device *adev = ring->adev;
8410
8411         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8412         amdgpu_ring_write(ring, 0 |     /* src: register*/
8413                                 (5 << 8) |      /* dst: memory */
8414                                 (1 << 20));     /* write confirm */
8415         amdgpu_ring_write(ring, reg);
8416         amdgpu_ring_write(ring, 0);
8417         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8418                                 reg_val_offs * 4));
8419         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8420                                 reg_val_offs * 4));
8421 }
8422
8423 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8424                                    uint32_t val)
8425 {
8426         uint32_t cmd = 0;
8427
8428         switch (ring->funcs->type) {
8429         case AMDGPU_RING_TYPE_GFX:
8430                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8431                 break;
8432         case AMDGPU_RING_TYPE_KIQ:
8433                 cmd = (1 << 16); /* no inc addr */
8434                 break;
8435         default:
8436                 cmd = WR_CONFIRM;
8437                 break;
8438         }
8439         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8440         amdgpu_ring_write(ring, cmd);
8441         amdgpu_ring_write(ring, reg);
8442         amdgpu_ring_write(ring, 0);
8443         amdgpu_ring_write(ring, val);
8444 }
8445
8446 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8447                                         uint32_t val, uint32_t mask)
8448 {
8449         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8450 }
8451
8452 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8453                                                    uint32_t reg0, uint32_t reg1,
8454                                                    uint32_t ref, uint32_t mask)
8455 {
8456         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8457         struct amdgpu_device *adev = ring->adev;
8458         bool fw_version_ok = false;
8459
8460         fw_version_ok = adev->gfx.cp_fw_write_wait;
8461
8462         if (fw_version_ok)
8463                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8464                                        ref, mask, 0x20);
8465         else
8466                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8467                                                            ref, mask);
8468 }
8469
8470 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8471                                          unsigned vmid)
8472 {
8473         struct amdgpu_device *adev = ring->adev;
8474         uint32_t value = 0;
8475
8476         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8477         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8478         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8479         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8480         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8481 }
8482
8483 static void
8484 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8485                                       uint32_t me, uint32_t pipe,
8486                                       enum amdgpu_interrupt_state state)
8487 {
8488         uint32_t cp_int_cntl, cp_int_cntl_reg;
8489
8490         if (!me) {
8491                 switch (pipe) {
8492                 case 0:
8493                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8494                         break;
8495                 case 1:
8496                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8497                         break;
8498                 default:
8499                         DRM_DEBUG("invalid pipe %d\n", pipe);
8500                         return;
8501                 }
8502         } else {
8503                 DRM_DEBUG("invalid me %d\n", me);
8504                 return;
8505         }
8506
8507         switch (state) {
8508         case AMDGPU_IRQ_STATE_DISABLE:
8509                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8510                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8511                                             TIME_STAMP_INT_ENABLE, 0);
8512                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8513                 break;
8514         case AMDGPU_IRQ_STATE_ENABLE:
8515                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8516                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8517                                             TIME_STAMP_INT_ENABLE, 1);
8518                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8519                 break;
8520         default:
8521                 break;
8522         }
8523 }
8524
8525 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8526                                                      int me, int pipe,
8527                                                      enum amdgpu_interrupt_state state)
8528 {
8529         u32 mec_int_cntl, mec_int_cntl_reg;
8530
8531         /*
8532          * amdgpu controls only the first MEC. That's why this function only
8533          * handles the setting of interrupts for this specific MEC. All other
8534          * pipes' interrupts are set by amdkfd.
8535          */
8536
8537         if (me == 1) {
8538                 switch (pipe) {
8539                 case 0:
8540                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8541                         break;
8542                 case 1:
8543                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8544                         break;
8545                 case 2:
8546                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8547                         break;
8548                 case 3:
8549                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8550                         break;
8551                 default:
8552                         DRM_DEBUG("invalid pipe %d\n", pipe);
8553                         return;
8554                 }
8555         } else {
8556                 DRM_DEBUG("invalid me %d\n", me);
8557                 return;
8558         }
8559
8560         switch (state) {
8561         case AMDGPU_IRQ_STATE_DISABLE:
8562                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8563                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8564                                              TIME_STAMP_INT_ENABLE, 0);
8565                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8566                 break;
8567         case AMDGPU_IRQ_STATE_ENABLE:
8568                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8569                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8570                                              TIME_STAMP_INT_ENABLE, 1);
8571                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8572                 break;
8573         default:
8574                 break;
8575         }
8576 }
8577
8578 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8579                                             struct amdgpu_irq_src *src,
8580                                             unsigned type,
8581                                             enum amdgpu_interrupt_state state)
8582 {
8583         switch (type) {
8584         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8585                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8586                 break;
8587         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8588                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8589                 break;
8590         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8591                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8592                 break;
8593         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8594                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8595                 break;
8596         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8597                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8598                 break;
8599         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8600                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8601                 break;
8602         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8603                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8604                 break;
8605         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8606                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8607                 break;
8608         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8609                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8610                 break;
8611         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8612                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8613                 break;
8614         default:
8615                 break;
8616         }
8617         return 0;
8618 }
8619
8620 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8621                              struct amdgpu_irq_src *source,
8622                              struct amdgpu_iv_entry *entry)
8623 {
8624         int i;
8625         u8 me_id, pipe_id, queue_id;
8626         struct amdgpu_ring *ring;
8627
8628         DRM_DEBUG("IH: CP EOP\n");
8629         me_id = (entry->ring_id & 0x0c) >> 2;
8630         pipe_id = (entry->ring_id & 0x03) >> 0;
8631         queue_id = (entry->ring_id & 0x70) >> 4;
8632
8633         switch (me_id) {
8634         case 0:
8635                 if (pipe_id == 0)
8636                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8637                 else
8638                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8639                 break;
8640         case 1:
8641         case 2:
8642                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8643                         ring = &adev->gfx.compute_ring[i];
8644                         /* Per-queue interrupt is supported for MEC starting from VI.
8645                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8646                           */
8647                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8648                                 amdgpu_fence_process(ring);
8649                 }
8650                 break;
8651         }
8652         return 0;
8653 }
8654
8655 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8656                                               struct amdgpu_irq_src *source,
8657                                               unsigned type,
8658                                               enum amdgpu_interrupt_state state)
8659 {
8660         switch (state) {
8661         case AMDGPU_IRQ_STATE_DISABLE:
8662         case AMDGPU_IRQ_STATE_ENABLE:
8663                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8664                                PRIV_REG_INT_ENABLE,
8665                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8666                 break;
8667         default:
8668                 break;
8669         }
8670
8671         return 0;
8672 }
8673
8674 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8675                                                struct amdgpu_irq_src *source,
8676                                                unsigned type,
8677                                                enum amdgpu_interrupt_state state)
8678 {
8679         switch (state) {
8680         case AMDGPU_IRQ_STATE_DISABLE:
8681         case AMDGPU_IRQ_STATE_ENABLE:
8682                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8683                                PRIV_INSTR_INT_ENABLE,
8684                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8685                 break;
8686         default:
8687                 break;
8688         }
8689
8690         return 0;
8691 }
8692
8693 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8694                                         struct amdgpu_iv_entry *entry)
8695 {
8696         u8 me_id, pipe_id, queue_id;
8697         struct amdgpu_ring *ring;
8698         int i;
8699
8700         me_id = (entry->ring_id & 0x0c) >> 2;
8701         pipe_id = (entry->ring_id & 0x03) >> 0;
8702         queue_id = (entry->ring_id & 0x70) >> 4;
8703
8704         switch (me_id) {
8705         case 0:
8706                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8707                         ring = &adev->gfx.gfx_ring[i];
8708                         /* we only enabled 1 gfx queue per pipe for now */
8709                         if (ring->me == me_id && ring->pipe == pipe_id)
8710                                 drm_sched_fault(&ring->sched);
8711                 }
8712                 break;
8713         case 1:
8714         case 2:
8715                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8716                         ring = &adev->gfx.compute_ring[i];
8717                         if (ring->me == me_id && ring->pipe == pipe_id &&
8718                             ring->queue == queue_id)
8719                                 drm_sched_fault(&ring->sched);
8720                 }
8721                 break;
8722         default:
8723                 BUG();
8724         }
8725 }
8726
8727 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8728                                   struct amdgpu_irq_src *source,
8729                                   struct amdgpu_iv_entry *entry)
8730 {
8731         DRM_ERROR("Illegal register access in command stream\n");
8732         gfx_v10_0_handle_priv_fault(adev, entry);
8733         return 0;
8734 }
8735
8736 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8737                                    struct amdgpu_irq_src *source,
8738                                    struct amdgpu_iv_entry *entry)
8739 {
8740         DRM_ERROR("Illegal instruction in command stream\n");
8741         gfx_v10_0_handle_priv_fault(adev, entry);
8742         return 0;
8743 }
8744
8745 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8746                                              struct amdgpu_irq_src *src,
8747                                              unsigned int type,
8748                                              enum amdgpu_interrupt_state state)
8749 {
8750         uint32_t tmp, target;
8751         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8752
8753         if (ring->me == 1)
8754                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8755         else
8756                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8757         target += ring->pipe;
8758
8759         switch (type) {
8760         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8761                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8762                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8763                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8764                                             GENERIC2_INT_ENABLE, 0);
8765                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8766
8767                         tmp = RREG32(target);
8768                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8769                                             GENERIC2_INT_ENABLE, 0);
8770                         WREG32(target, tmp);
8771                 } else {
8772                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8773                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8774                                             GENERIC2_INT_ENABLE, 1);
8775                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8776
8777                         tmp = RREG32(target);
8778                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8779                                             GENERIC2_INT_ENABLE, 1);
8780                         WREG32(target, tmp);
8781                 }
8782                 break;
8783         default:
8784                 BUG(); /* kiq only support GENERIC2_INT now */
8785                 break;
8786         }
8787         return 0;
8788 }
8789
8790 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8791                              struct amdgpu_irq_src *source,
8792                              struct amdgpu_iv_entry *entry)
8793 {
8794         u8 me_id, pipe_id, queue_id;
8795         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8796
8797         me_id = (entry->ring_id & 0x0c) >> 2;
8798         pipe_id = (entry->ring_id & 0x03) >> 0;
8799         queue_id = (entry->ring_id & 0x70) >> 4;
8800         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8801                    me_id, pipe_id, queue_id);
8802
8803         amdgpu_fence_process(ring);
8804         return 0;
8805 }
8806
8807 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8808 {
8809         const unsigned int gcr_cntl =
8810                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8811                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8812                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8813                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8814                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8815                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8816                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8817                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8818
8819         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8820         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8821         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8822         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8823         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8824         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8825         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8826         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8827         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8828 }
8829
8830 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8831         .name = "gfx_v10_0",
8832         .early_init = gfx_v10_0_early_init,
8833         .late_init = gfx_v10_0_late_init,
8834         .sw_init = gfx_v10_0_sw_init,
8835         .sw_fini = gfx_v10_0_sw_fini,
8836         .hw_init = gfx_v10_0_hw_init,
8837         .hw_fini = gfx_v10_0_hw_fini,
8838         .suspend = gfx_v10_0_suspend,
8839         .resume = gfx_v10_0_resume,
8840         .is_idle = gfx_v10_0_is_idle,
8841         .wait_for_idle = gfx_v10_0_wait_for_idle,
8842         .soft_reset = gfx_v10_0_soft_reset,
8843         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8844         .set_powergating_state = gfx_v10_0_set_powergating_state,
8845         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8846 };
8847
8848 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8849         .type = AMDGPU_RING_TYPE_GFX,
8850         .align_mask = 0xff,
8851         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8852         .support_64bit_ptrs = true,
8853         .vmhub = AMDGPU_GFXHUB_0,
8854         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8855         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8856         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8857         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8858                 5 + /* COND_EXEC */
8859                 7 + /* PIPELINE_SYNC */
8860                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8861                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8862                 2 + /* VM_FLUSH */
8863                 8 + /* FENCE for VM_FLUSH */
8864                 20 + /* GDS switch */
8865                 4 + /* double SWITCH_BUFFER,
8866                      * the first COND_EXEC jump to the place
8867                      * just prior to this double SWITCH_BUFFER
8868                      */
8869                 5 + /* COND_EXEC */
8870                 7 + /* HDP_flush */
8871                 4 + /* VGT_flush */
8872                 14 + /* CE_META */
8873                 31 + /* DE_META */
8874                 3 + /* CNTX_CTRL */
8875                 5 + /* HDP_INVL */
8876                 8 + 8 + /* FENCE x2 */
8877                 2 + /* SWITCH_BUFFER */
8878                 8, /* gfx_v10_0_emit_mem_sync */
8879         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8880         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8881         .emit_fence = gfx_v10_0_ring_emit_fence,
8882         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8883         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8884         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8885         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8886         .test_ring = gfx_v10_0_ring_test_ring,
8887         .test_ib = gfx_v10_0_ring_test_ib,
8888         .insert_nop = amdgpu_ring_insert_nop,
8889         .pad_ib = amdgpu_ring_generic_pad_ib,
8890         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8891         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8892         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8893         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8894         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8895         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8896         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8897         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8898         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8899         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8900         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8901 };
8902
8903 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8904         .type = AMDGPU_RING_TYPE_COMPUTE,
8905         .align_mask = 0xff,
8906         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8907         .support_64bit_ptrs = true,
8908         .vmhub = AMDGPU_GFXHUB_0,
8909         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8910         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8911         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8912         .emit_frame_size =
8913                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8914                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8915                 5 + /* hdp invalidate */
8916                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8917                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8918                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8919                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8920                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8921                 8, /* gfx_v10_0_emit_mem_sync */
8922         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8923         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8924         .emit_fence = gfx_v10_0_ring_emit_fence,
8925         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8926         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8927         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8928         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8929         .test_ring = gfx_v10_0_ring_test_ring,
8930         .test_ib = gfx_v10_0_ring_test_ib,
8931         .insert_nop = amdgpu_ring_insert_nop,
8932         .pad_ib = amdgpu_ring_generic_pad_ib,
8933         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8934         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8935         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8936         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8937 };
8938
8939 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8940         .type = AMDGPU_RING_TYPE_KIQ,
8941         .align_mask = 0xff,
8942         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8943         .support_64bit_ptrs = true,
8944         .vmhub = AMDGPU_GFXHUB_0,
8945         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8946         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8947         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8948         .emit_frame_size =
8949                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8950                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8951                 5 + /*hdp invalidate */
8952                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8953                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8954                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8955                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8956                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8957         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8958         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8959         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8960         .test_ring = gfx_v10_0_ring_test_ring,
8961         .test_ib = gfx_v10_0_ring_test_ib,
8962         .insert_nop = amdgpu_ring_insert_nop,
8963         .pad_ib = amdgpu_ring_generic_pad_ib,
8964         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8965         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8966         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8967         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8968 };
8969
8970 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8971 {
8972         int i;
8973
8974         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8975
8976         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8977                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8978
8979         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8980                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8981 }
8982
8983 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8984         .set = gfx_v10_0_set_eop_interrupt_state,
8985         .process = gfx_v10_0_eop_irq,
8986 };
8987
8988 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8989         .set = gfx_v10_0_set_priv_reg_fault_state,
8990         .process = gfx_v10_0_priv_reg_irq,
8991 };
8992
8993 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8994         .set = gfx_v10_0_set_priv_inst_fault_state,
8995         .process = gfx_v10_0_priv_inst_irq,
8996 };
8997
8998 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8999         .set = gfx_v10_0_kiq_set_interrupt_state,
9000         .process = gfx_v10_0_kiq_irq,
9001 };
9002
9003 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9004 {
9005         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9006         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9007
9008         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9009         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9010
9011         adev->gfx.priv_reg_irq.num_types = 1;
9012         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9013
9014         adev->gfx.priv_inst_irq.num_types = 1;
9015         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9016 }
9017
9018 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9019 {
9020         switch (adev->asic_type) {
9021         case CHIP_NAVI10:
9022         case CHIP_NAVI14:
9023         case CHIP_SIENNA_CICHLID:
9024         case CHIP_NAVY_FLOUNDER:
9025         case CHIP_VANGOGH:
9026         case CHIP_DIMGREY_CAVEFISH:
9027                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9028                 break;
9029         case CHIP_NAVI12:
9030                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9031                 break;
9032         default:
9033                 break;
9034         }
9035 }
9036
9037 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9038 {
9039         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9040                             adev->gfx.config.max_sh_per_se *
9041                             adev->gfx.config.max_shader_engines;
9042
9043         adev->gds.gds_size = 0x10000;
9044         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9045         adev->gds.gws_size = 64;
9046         adev->gds.oa_size = 16;
9047 }
9048
9049 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9050                                                           u32 bitmap)
9051 {
9052         u32 data;
9053
9054         if (!bitmap)
9055                 return;
9056
9057         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9058         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9059
9060         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9061 }
9062
9063 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9064 {
9065         u32 data, wgp_bitmask;
9066         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9067         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9068
9069         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9070         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9071
9072         wgp_bitmask =
9073                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9074
9075         return (~data) & wgp_bitmask;
9076 }
9077
9078 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9079 {
9080         u32 wgp_idx, wgp_active_bitmap;
9081         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9082
9083         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9084         cu_active_bitmap = 0;
9085
9086         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9087                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9088                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9089                 if (wgp_active_bitmap & (1 << wgp_idx))
9090                         cu_active_bitmap |= cu_bitmap_per_wgp;
9091         }
9092
9093         return cu_active_bitmap;
9094 }
9095
9096 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9097                                  struct amdgpu_cu_info *cu_info)
9098 {
9099         int i, j, k, counter, active_cu_number = 0;
9100         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9101         unsigned disable_masks[4 * 2];
9102
9103         if (!adev || !cu_info)
9104                 return -EINVAL;
9105
9106         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9107
9108         mutex_lock(&adev->grbm_idx_mutex);
9109         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9110                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9111                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9112                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9113                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9114                                 continue;
9115                         mask = 1;
9116                         ao_bitmap = 0;
9117                         counter = 0;
9118                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9119                         if (i < 4 && j < 2)
9120                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9121                                         adev, disable_masks[i * 2 + j]);
9122                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9123                         cu_info->bitmap[i][j] = bitmap;
9124
9125                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9126                                 if (bitmap & mask) {
9127                                         if (counter < adev->gfx.config.max_cu_per_sh)
9128                                                 ao_bitmap |= mask;
9129                                         counter++;
9130                                 }
9131                                 mask <<= 1;
9132                         }
9133                         active_cu_number += counter;
9134                         if (i < 2 && j < 2)
9135                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9136                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9137                 }
9138         }
9139         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9140         mutex_unlock(&adev->grbm_idx_mutex);
9141
9142         cu_info->number = active_cu_number;
9143         cu_info->ao_cu_mask = ao_cu_mask;
9144         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9145
9146         return 0;
9147 }
9148
9149 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9150 {
9151         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9152
9153         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9154         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9155         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9156
9157         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9158         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9159         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9160
9161         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9162                                                 adev->gfx.config.max_shader_engines);
9163         disabled_sa = efuse_setting | vbios_setting;
9164         disabled_sa &= max_sa_mask;
9165
9166         return disabled_sa;
9167 }
9168
9169 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9170 {
9171         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9172         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9173
9174         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9175
9176         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9177         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9178         max_shader_engines = adev->gfx.config.max_shader_engines;
9179
9180         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9181                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9182                 disabled_sa_per_se &= max_sa_per_se_mask;
9183                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9184                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9185                         break;
9186                 }
9187         }
9188 }
9189
9190 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9191 {
9192         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9193                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9194                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9195                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9196
9197         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9198         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9199                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9200                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9201                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9202                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9203
9204         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9205                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9206                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9207                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9208
9209         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9210
9211         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9212                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9213 }
9214
9215 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9216 {
9217         .type = AMD_IP_BLOCK_TYPE_GFX,
9218         .major = 10,
9219         .minor = 0,
9220         .rev = 0,
9221         .funcs = &gfx_v10_0_ip_funcs,
9222 };