drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/module.h>
  30 #include <linux/pagemap.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-buf.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_exec.h>
  37 #include <drm/drm_gem_ttm_helper.h>
  38 #include <drm/ttm/ttm_tt.h>
  39
  40 #include "amdgpu.h"
  41 #include "amdgpu_display.h"
  42 #include "amdgpu_dma_buf.h"
  43 #include "amdgpu_hmm.h"
  44 #include "amdgpu_xgmi.h"
  45
  46 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
  47
  48 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
  49 {
  50         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
  51         struct drm_device *ddev = bo->base.dev;
  52         vm_fault_t ret;
  53         int idx;
  54
  55         ret = ttm_bo_vm_reserve(bo, vmf);
  56         if (ret)
  57                 return ret;
  58
  59         if (drm_dev_enter(ddev, &idx)) {
  60                 ret = amdgpu_bo_fault_reserve_notify(bo);
  61                 if (ret) {
  62                         drm_dev_exit(idx);
  63                         goto unlock;
  64                 }
  65
  66                 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
  67                                                TTM_BO_VM_NUM_PREFAULT);
  68
  69                 drm_dev_exit(idx);
  70         } else {
  71                 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
  72         }
  73         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
  74                 return ret;
  75
  76 unlock:
  77         dma_resv_unlock(bo->base.resv);
  78         return ret;
  79 }
  80
  81 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
  82         .fault = amdgpu_gem_fault,
  83         .open = ttm_bo_vm_open,
  84         .close = ttm_bo_vm_close,
  85         .access = ttm_bo_vm_access
  86 };
  87
  88 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  89 {
  90         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  91
  92         if (robj) {
  93                 amdgpu_hmm_unregister(robj);
  94                 amdgpu_bo_unref(&robj);
  95         }
  96 }
  97
  98 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  99                              int alignment, u32 initial_domain,
 100                              u64 flags, enum ttm_bo_type type,
 101                              struct dma_resv *resv,
 102                              struct drm_gem_object **obj, int8_t xcp_id_plus1)
 103 {
 104         struct amdgpu_bo *bo;
 105         struct amdgpu_bo_user *ubo;
 106         struct amdgpu_bo_param bp;
 107         int r;
 108
 109         memset(&bp, 0, sizeof(bp));
 110         *obj = NULL;
 111         flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
 112
 113         bp.size = size;
 114         bp.byte_align = alignment;
 115         bp.type = type;
 116         bp.resv = resv;
 117         bp.preferred_domain = initial_domain;
 118         bp.flags = flags;
 119         bp.domain = initial_domain;
 120         bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 121         bp.xcp_id_plus1 = xcp_id_plus1;
 122
 123         r = amdgpu_bo_create_user(adev, &bp, &ubo);
 124         if (r)
 125                 return r;
 126
 127         bo = &ubo->bo;
 128         *obj = &bo->tbo.base;
 129         (*obj)->funcs = &amdgpu_gem_object_funcs;
 130
 131         return 0;
 132 }
 133
 134 void amdgpu_gem_force_release(struct amdgpu_device *adev)
 135 {
 136         struct drm_device *ddev = adev_to_drm(adev);
 137         struct drm_file *file;
 138
 139         mutex_lock(&ddev->filelist_mutex);
 140
 141         list_for_each_entry(file, &ddev->filelist, lhead) {
 142                 struct drm_gem_object *gobj;
 143                 int handle;
 144
 145                 WARN_ONCE(1, "Still active user space clients!\n");
 146                 spin_lock(&file->table_lock);
 147                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 148                         WARN_ONCE(1, "And also active allocations!\n");
 149                         drm_gem_object_put(gobj);
 150                 }
 151                 idr_destroy(&file->object_idr);
 152                 spin_unlock(&file->table_lock);
 153         }
 154
 155         mutex_unlock(&ddev->filelist_mutex);
 156 }
 157
 158 /*
 159  * Call from drm_gem_handle_create which appear in both new and open ioctl
 160  * case.
 161  */
 162 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
 163                                   struct drm_file *file_priv)
 164 {
 165         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 166         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 167         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 168         struct amdgpu_vm *vm = &fpriv->vm;
 169         struct amdgpu_bo_va *bo_va;
 170         struct mm_struct *mm;
 171         int r;
 172
 173         mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
 174         if (mm && mm != current->mm)
 175                 return -EPERM;
 176
 177         if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
 178             !amdgpu_vm_is_bo_always_valid(vm, abo))
 179                 return -EPERM;
 180
 181         r = amdgpu_bo_reserve(abo, false);
 182         if (r)
 183                 return r;
 184
 185         bo_va = amdgpu_vm_bo_find(vm, abo);
 186         if (!bo_va)
 187                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 188         else
 189                 ++bo_va->ref_count;
 190         amdgpu_bo_unreserve(abo);
 191
 192         /* Validate and add eviction fence to DMABuf imports with dynamic
 193          * attachment in compute VMs. Re-validation will be done by
 194          * amdgpu_vm_validate. Fences are on the reservation shared with the
 195          * export, which is currently required to be validated and fenced
 196          * already by amdgpu_amdkfd_gpuvm_restore_process_bos.
 197          *
 198          * Nested locking below for the case that a GEM object is opened in
 199          * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,
 200          * but not for export, this is a different lock class that cannot lead to
 201          * circular lock dependencies.
 202          */
 203         if (!vm->is_compute_context || !vm->process_info)
 204                 return 0;
 205         if (!obj->import_attach ||
 206             !dma_buf_is_dynamic(obj->import_attach->dmabuf))
 207                 return 0;
 208         mutex_lock_nested(&vm->process_info->lock, 1);
 209         if (!WARN_ON(!vm->process_info->eviction_fence)) {
 210                 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT,
 211                                                         &vm->process_info->eviction_fence->base);
 212                 if (r) {
 213                         struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
 214
 215                         dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);
 216                         if (ti) {
 217                                 dev_warn(adev->dev, "pid %d\n", ti->pid);
 218                                 amdgpu_vm_put_task_info(ti);
 219                         }
 220                 }
 221         }
 222         mutex_unlock(&vm->process_info->lock);
 223
 224         return r;
 225 }
 226
 227 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
 228                                     struct drm_file *file_priv)
 229 {
 230         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 231         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 232         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 233         struct amdgpu_vm *vm = &fpriv->vm;
 234
 235         struct dma_fence *fence = NULL;
 236         struct amdgpu_bo_va *bo_va;
 237         struct drm_exec exec;
 238         long r;
 239
 240         drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
 241         drm_exec_until_all_locked(&exec) {
 242                 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
 243                 drm_exec_retry_on_contention(&exec);
 244                 if (unlikely(r))
 245                         goto out_unlock;
 246
 247                 r = amdgpu_vm_lock_pd(vm, &exec, 0);
 248                 drm_exec_retry_on_contention(&exec);
 249                 if (unlikely(r))
 250                         goto out_unlock;
 251         }
 252
 253         bo_va = amdgpu_vm_bo_find(vm, bo);
 254         if (!bo_va || --bo_va->ref_count)
 255                 goto out_unlock;
 256
 257         amdgpu_vm_bo_del(adev, bo_va);
 258         if (!amdgpu_vm_ready(vm))
 259                 goto out_unlock;
 260
 261         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 262         if (unlikely(r < 0))
 263                 dev_err(adev->dev, "failed to clear page "
 264                         "tables on GEM object close (%ld)\n", r);
 265         if (r || !fence)
 266                 goto out_unlock;
 267
 268         amdgpu_bo_fence(bo, fence, true);
 269         dma_fence_put(fence);
 270
 271 out_unlock:
 272         if (r)
 273                 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
 274         drm_exec_fini(&exec);
 275 }
 276
 277 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 278 {
 279         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 280
 281         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 282                 return -EPERM;
 283         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 284                 return -EPERM;
 285
 286         /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
 287          * for debugger access to invisible VRAM. Should have used MAP_SHARED
 288          * instead. Clearing VM_MAYWRITE prevents the mapping from ever
 289          * becoming writable and makes is_cow_mapping(vm_flags) false.
 290          */
 291         if (is_cow_mapping(vma->vm_flags) &&
 292             !(vma->vm_flags & VM_ACCESS_FLAGS))
 293                 vm_flags_clear(vma, VM_MAYWRITE);
 294
 295         return drm_gem_ttm_mmap(obj, vma);
 296 }
 297
 298 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
 299         .free = amdgpu_gem_object_free,
 300         .open = amdgpu_gem_object_open,
 301         .close = amdgpu_gem_object_close,
 302         .export = amdgpu_gem_prime_export,
 303         .vmap = drm_gem_ttm_vmap,
 304         .vunmap = drm_gem_ttm_vunmap,
 305         .mmap = amdgpu_gem_object_mmap,
 306         .vm_ops = &amdgpu_gem_vm_ops,
 307 };
 308
 309 /*
 310  * GEM ioctls.
 311  */
 312 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 313                             struct drm_file *filp)
 314 {
 315         struct amdgpu_device *adev = drm_to_adev(dev);
 316         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 317         struct amdgpu_vm *vm = &fpriv->vm;
 318         union drm_amdgpu_gem_create *args = data;
 319         uint64_t flags = args->in.domain_flags;
 320         uint64_t size = args->in.bo_size;
 321         struct dma_resv *resv = NULL;
 322         struct drm_gem_object *gobj;
 323         uint32_t handle, initial_domain;
 324         int r;
 325
 326         /* reject DOORBELLs until userspace code to use it is available */
 327         if (args->in.domains & AMDGPU_GEM_DOMAIN_DOORBELL)
 328                 return -EINVAL;
 329
 330         /* reject invalid gem flags */
 331         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 332                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 333                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 334                       AMDGPU_GEM_CREATE_VRAM_CLEARED |
 335                       AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
 336                       AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
 337                       AMDGPU_GEM_CREATE_ENCRYPTED |
 338                       AMDGPU_GEM_CREATE_GFX12_DCC |
 339                       AMDGPU_GEM_CREATE_DISCARDABLE))
 340                 return -EINVAL;
 341
 342         /* reject invalid gem domains */
 343         if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
 344                 return -EINVAL;
 345
 346         if ((flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
 347             ((amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) ||
 348              !(args->in.domains & AMDGPU_GEM_DOMAIN_VRAM)))
 349                 return -EINVAL;
 350
 351         if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
 352                 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
 353                 return -EINVAL;
 354         }
 355
 356         /* create a gem object to contain this object in */
 357         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 358             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 359                 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 360                         /* if gds bo is created from user space, it must be
 361                          * passed to bo list
 362                          */
 363                         DRM_ERROR("GDS bo cannot be per-vm-bo\n");
 364                         return -EINVAL;
 365                 }
 366                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 367         }
 368
 369         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 370                 r = amdgpu_bo_reserve(vm->root.bo, false);
 371                 if (r)
 372                         return r;
 373
 374                 resv = vm->root.bo->tbo.base.resv;
 375         }
 376
 377         initial_domain = (u32)(0xffffffff & args->in.domains);
 378 retry:
 379         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 380                                      initial_domain,
 381                                      flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
 382         if (r && r != -ERESTARTSYS) {
 383                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 384                         flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 385                         goto retry;
 386                 }
 387
 388                 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
 389                         initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
 390                         goto retry;
 391                 }
 392                 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
 393                                 size, initial_domain, args->in.alignment, r);
 394         }
 395
 396         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 397                 if (!r) {
 398                         struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 399
 400                         abo->parent = amdgpu_bo_ref(vm->root.bo);
 401                 }
 402                 amdgpu_bo_unreserve(vm->root.bo);
 403         }
 404         if (r)
 405                 return r;
 406
 407         r = drm_gem_handle_create(filp, gobj, &handle);
 408         /* drop reference from allocate - handle holds it now */
 409         drm_gem_object_put(gobj);
 410         if (r)
 411                 return r;
 412
 413         memset(args, 0, sizeof(*args));
 414         args->out.handle = handle;
 415         return 0;
 416 }
 417
 418 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 419                              struct drm_file *filp)
 420 {
 421         struct ttm_operation_ctx ctx = { true, false };
 422         struct amdgpu_device *adev = drm_to_adev(dev);
 423         struct drm_amdgpu_gem_userptr *args = data;
 424         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 425         struct drm_gem_object *gobj;
 426         struct hmm_range *range;
 427         struct amdgpu_bo *bo;
 428         uint32_t handle;
 429         int r;
 430
 431         args->addr = untagged_addr(args->addr);
 432
 433         if (offset_in_page(args->addr | args->size))
 434                 return -EINVAL;
 435
 436         /* reject unknown flag values */
 437         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 438             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 439             AMDGPU_GEM_USERPTR_REGISTER))
 440                 return -EINVAL;
 441
 442         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 443              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 444
 445                 /* if we want to write to it we must install a MMU notifier */
 446                 return -EACCES;
 447         }
 448
 449         /* create a gem object to contain this object in */
 450         r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
 451                                      0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 452         if (r)
 453                 return r;
 454
 455         bo = gem_to_amdgpu_bo(gobj);
 456         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 457         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 458         r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
 459         if (r)
 460                 goto release_object;
 461
 462         r = amdgpu_hmm_register(bo, args->addr);
 463         if (r)
 464                 goto release_object;
 465
 466         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 467                 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
 468                                                  &range);
 469                 if (r)
 470                         goto release_object;
 471
 472                 r = amdgpu_bo_reserve(bo, true);
 473                 if (r)
 474                         goto user_pages_done;
 475
 476                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 477                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 478                 amdgpu_bo_unreserve(bo);
 479                 if (r)
 480                         goto user_pages_done;
 481         }
 482
 483         r = drm_gem_handle_create(filp, gobj, &handle);
 484         if (r)
 485                 goto user_pages_done;
 486
 487         args->handle = handle;
 488
 489 user_pages_done:
 490         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
 491                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
 492
 493 release_object:
 494         drm_gem_object_put(gobj);
 495
 496         return r;
 497 }
 498
 499 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 500                           struct drm_device *dev,
 501                           uint32_t handle, uint64_t *offset_p)
 502 {
 503         struct drm_gem_object *gobj;
 504         struct amdgpu_bo *robj;
 505
 506         gobj = drm_gem_object_lookup(filp, handle);
 507         if (!gobj)
 508                 return -ENOENT;
 509
 510         robj = gem_to_amdgpu_bo(gobj);
 511         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 512             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 513                 drm_gem_object_put(gobj);
 514                 return -EPERM;
 515         }
 516         *offset_p = amdgpu_bo_mmap_offset(robj);
 517         drm_gem_object_put(gobj);
 518         return 0;
 519 }
 520
 521 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 522                           struct drm_file *filp)
 523 {
 524         union drm_amdgpu_gem_mmap *args = data;
 525         uint32_t handle = args->in.handle;
 526
 527         memset(args, 0, sizeof(*args));
 528         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 529 }
 530
 531 /**
 532  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 533  *
 534  * @timeout_ns: timeout in ns
 535  *
 536  * Calculate the timeout in jiffies from an absolute timeout in ns.
 537  */
 538 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 539 {
 540         unsigned long timeout_jiffies;
 541         ktime_t timeout;
 542
 543         /* clamp timeout if it's to large */
 544         if (((int64_t)timeout_ns) < 0)
 545                 return MAX_SCHEDULE_TIMEOUT;
 546
 547         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 548         if (ktime_to_ns(timeout) < 0)
 549                 return 0;
 550
 551         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 552         /*  clamp timeout to avoid unsigned-> signed overflow */
 553         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
 554                 return MAX_SCHEDULE_TIMEOUT - 1;
 555
 556         return timeout_jiffies;
 557 }
 558
 559 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 560                               struct drm_file *filp)
 561 {
 562         union drm_amdgpu_gem_wait_idle *args = data;
 563         struct drm_gem_object *gobj;
 564         struct amdgpu_bo *robj;
 565         uint32_t handle = args->in.handle;
 566         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 567         int r = 0;
 568         long ret;
 569
 570         gobj = drm_gem_object_lookup(filp, handle);
 571         if (!gobj)
 572                 return -ENOENT;
 573
 574         robj = gem_to_amdgpu_bo(gobj);
 575         ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
 576                                     true, timeout);
 577
 578         /* ret == 0 means not signaled,
 579          * ret > 0 means signaled
 580          * ret < 0 means interrupted before timeout
 581          */
 582         if (ret >= 0) {
 583                 memset(args, 0, sizeof(*args));
 584                 args->out.status = (ret == 0);
 585         } else
 586                 r = ret;
 587
 588         drm_gem_object_put(gobj);
 589         return r;
 590 }
 591
 592 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 593                                 struct drm_file *filp)
 594 {
 595         struct drm_amdgpu_gem_metadata *args = data;
 596         struct drm_gem_object *gobj;
 597         struct amdgpu_bo *robj;
 598         int r = -1;
 599
 600         DRM_DEBUG("%d\n", args->handle);
 601         gobj = drm_gem_object_lookup(filp, args->handle);
 602         if (gobj == NULL)
 603                 return -ENOENT;
 604         robj = gem_to_amdgpu_bo(gobj);
 605
 606         r = amdgpu_bo_reserve(robj, false);
 607         if (unlikely(r != 0))
 608                 goto out;
 609
 610         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 611                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 612                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 613                                            sizeof(args->data.data),
 614                                            &args->data.data_size_bytes,
 615                                            &args->data.flags);
 616         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 617                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 618                         r = -EINVAL;
 619                         goto unreserve;
 620                 }
 621                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 622                 if (!r)
 623                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 624                                                    args->data.data_size_bytes,
 625                                                    args->data.flags);
 626         }
 627
 628 unreserve:
 629         amdgpu_bo_unreserve(robj);
 630 out:
 631         drm_gem_object_put(gobj);
 632         return r;
 633 }
 634
 635 /**
 636  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 637  *
 638  * @adev: amdgpu_device pointer
 639  * @vm: vm to update
 640  * @bo_va: bo_va to update
 641  * @operation: map, unmap or clear
 642  *
 643  * Update the bo_va directly after setting its address. Errors are not
 644  * vital here, so they are not reported back to userspace.
 645  */
 646 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 647                                     struct amdgpu_vm *vm,
 648                                     struct amdgpu_bo_va *bo_va,
 649                                     uint32_t operation)
 650 {
 651         int r;
 652
 653         if (!amdgpu_vm_ready(vm))
 654                 return;
 655
 656         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 657         if (r)
 658                 goto error;
 659
 660         if (operation == AMDGPU_VA_OP_MAP ||
 661             operation == AMDGPU_VA_OP_REPLACE) {
 662                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 663                 if (r)
 664                         goto error;
 665         }
 666
 667         r = amdgpu_vm_update_pdes(adev, vm, false);
 668
 669 error:
 670         if (r && r != -ERESTARTSYS)
 671                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 672 }
 673
 674 /**
 675  * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
 676  *
 677  * @adev: amdgpu_device pointer
 678  * @flags: GEM UAPI flags
 679  *
 680  * Returns the GEM UAPI flags mapped into hardware for the ASIC.
 681  */
 682 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
 683 {
 684         uint64_t pte_flag = 0;
 685
 686         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 687                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 688         if (flags & AMDGPU_VM_PAGE_READABLE)
 689                 pte_flag |= AMDGPU_PTE_READABLE;
 690         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 691                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 692         if (flags & AMDGPU_VM_PAGE_PRT)
 693                 pte_flag |= AMDGPU_PTE_PRT_FLAG(adev);
 694         if (flags & AMDGPU_VM_PAGE_NOALLOC)
 695                 pte_flag |= AMDGPU_PTE_NOALLOC;
 696
 697         if (adev->gmc.gmc_funcs->map_mtype)
 698                 pte_flag |= amdgpu_gmc_map_mtype(adev,
 699                                                  flags & AMDGPU_VM_MTYPE_MASK);
 700
 701         return pte_flag;
 702 }
 703
 704 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 705                           struct drm_file *filp)
 706 {
 707         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 708                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 709                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
 710                 AMDGPU_VM_PAGE_NOALLOC;
 711         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 712                 AMDGPU_VM_PAGE_PRT;
 713
 714         struct drm_amdgpu_gem_va *args = data;
 715         struct drm_gem_object *gobj;
 716         struct amdgpu_device *adev = drm_to_adev(dev);
 717         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 718         struct amdgpu_bo *abo;
 719         struct amdgpu_bo_va *bo_va;
 720         struct drm_exec exec;
 721         uint64_t va_flags;
 722         uint64_t vm_size;
 723         int r = 0;
 724
 725         if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) {
 726                 dev_dbg(dev->dev,
 727                         "va_address 0x%llx is in reserved area 0x%llx\n",
 728                         args->va_address, AMDGPU_VA_RESERVED_BOTTOM);
 729                 return -EINVAL;
 730         }
 731
 732         if (args->va_address >= AMDGPU_GMC_HOLE_START &&
 733             args->va_address < AMDGPU_GMC_HOLE_END) {
 734                 dev_dbg(dev->dev,
 735                         "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
 736                         args->va_address, AMDGPU_GMC_HOLE_START,
 737                         AMDGPU_GMC_HOLE_END);
 738                 return -EINVAL;
 739         }
 740
 741         args->va_address &= AMDGPU_GMC_HOLE_MASK;
 742
 743         vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 744         vm_size -= AMDGPU_VA_RESERVED_TOP;
 745         if (args->va_address + args->map_size > vm_size) {
 746                 dev_dbg(dev->dev,
 747                         "va_address 0x%llx is in top reserved area 0x%llx\n",
 748                         args->va_address + args->map_size, vm_size);
 749                 return -EINVAL;
 750         }
 751
 752         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 753                 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
 754                         args->flags);
 755                 return -EINVAL;
 756         }
 757
 758         switch (args->operation) {
 759         case AMDGPU_VA_OP_MAP:
 760         case AMDGPU_VA_OP_UNMAP:
 761         case AMDGPU_VA_OP_CLEAR:
 762         case AMDGPU_VA_OP_REPLACE:
 763                 break;
 764         default:
 765                 dev_dbg(dev->dev, "unsupported operation %d\n",
 766                         args->operation);
 767                 return -EINVAL;
 768         }
 769
 770         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 771             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 772                 gobj = drm_gem_object_lookup(filp, args->handle);
 773                 if (gobj == NULL)
 774                         return -ENOENT;
 775                 abo = gem_to_amdgpu_bo(gobj);
 776         } else {
 777                 gobj = NULL;
 778                 abo = NULL;
 779         }
 780
 781         drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
 782                       DRM_EXEC_IGNORE_DUPLICATES, 0);
 783         drm_exec_until_all_locked(&exec) {
 784                 if (gobj) {
 785                         r = drm_exec_lock_obj(&exec, gobj);
 786                         drm_exec_retry_on_contention(&exec);
 787                         if (unlikely(r))
 788                                 goto error;
 789                 }
 790
 791                 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
 792                 drm_exec_retry_on_contention(&exec);
 793                 if (unlikely(r))
 794                         goto error;
 795         }
 796
 797         if (abo) {
 798                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 799                 if (!bo_va) {
 800                         r = -ENOENT;
 801                         goto error;
 802                 }
 803         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 804                 bo_va = fpriv->prt_va;
 805         } else {
 806                 bo_va = NULL;
 807         }
 808
 809         switch (args->operation) {
 810         case AMDGPU_VA_OP_MAP:
 811                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 812                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 813                                      args->offset_in_bo, args->map_size,
 814                                      va_flags);
 815                 break;
 816         case AMDGPU_VA_OP_UNMAP:
 817                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 818                 break;
 819
 820         case AMDGPU_VA_OP_CLEAR:
 821                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 822                                                 args->va_address,
 823                                                 args->map_size);
 824                 break;
 825         case AMDGPU_VA_OP_REPLACE:
 826                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 827                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 828                                              args->offset_in_bo, args->map_size,
 829                                              va_flags);
 830                 break;
 831         default:
 832                 break;
 833         }
 834         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm)
 835                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
 836                                         args->operation);
 837
 838 error:
 839         drm_exec_fini(&exec);
 840         drm_gem_object_put(gobj);
 841         return r;
 842 }
 843
 844 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 845                         struct drm_file *filp)
 846 {
 847         struct amdgpu_device *adev = drm_to_adev(dev);
 848         struct drm_amdgpu_gem_op *args = data;
 849         struct drm_gem_object *gobj;
 850         struct amdgpu_vm_bo_base *base;
 851         struct amdgpu_bo *robj;
 852         int r;
 853
 854         gobj = drm_gem_object_lookup(filp, args->handle);
 855         if (!gobj)
 856                 return -ENOENT;
 857
 858         robj = gem_to_amdgpu_bo(gobj);
 859
 860         r = amdgpu_bo_reserve(robj, false);
 861         if (unlikely(r))
 862                 goto out;
 863
 864         switch (args->op) {
 865         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 866                 struct drm_amdgpu_gem_create_in info;
 867                 void __user *out = u64_to_user_ptr(args->value);
 868
 869                 info.bo_size = robj->tbo.base.size;
 870                 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
 871                 info.domains = robj->preferred_domains;
 872                 info.domain_flags = robj->flags;
 873                 amdgpu_bo_unreserve(robj);
 874                 if (copy_to_user(out, &info, sizeof(info)))
 875                         r = -EFAULT;
 876                 break;
 877         }
 878         case AMDGPU_GEM_OP_SET_PLACEMENT:
 879                 if (robj->tbo.base.import_attach &&
 880                     args->value & AMDGPU_GEM_DOMAIN_VRAM) {
 881                         r = -EINVAL;
 882                         amdgpu_bo_unreserve(robj);
 883                         break;
 884                 }
 885                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 886                         r = -EPERM;
 887                         amdgpu_bo_unreserve(robj);
 888                         break;
 889                 }
 890                 for (base = robj->vm_bo; base; base = base->next)
 891                         if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
 892                                 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
 893                                 r = -EINVAL;
 894                                 amdgpu_bo_unreserve(robj);
 895                                 goto out;
 896                         }
 897
 898
 899                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 900                                                         AMDGPU_GEM_DOMAIN_GTT |
 901                                                         AMDGPU_GEM_DOMAIN_CPU);
 902                 robj->allowed_domains = robj->preferred_domains;
 903                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 904                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 905
 906                 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 907                         amdgpu_vm_bo_invalidate(adev, robj, true);
 908
 909                 amdgpu_bo_unreserve(robj);
 910                 break;
 911         default:
 912                 amdgpu_bo_unreserve(robj);
 913                 r = -EINVAL;
 914         }
 915
 916 out:
 917         drm_gem_object_put(gobj);
 918         return r;
 919 }
 920
 921 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
 922                                   int width,
 923                                   int cpp,
 924                                   bool tiled)
 925 {
 926         int aligned = width;
 927         int pitch_mask = 0;
 928
 929         switch (cpp) {
 930         case 1:
 931                 pitch_mask = 255;
 932                 break;
 933         case 2:
 934                 pitch_mask = 127;
 935                 break;
 936         case 3:
 937         case 4:
 938                 pitch_mask = 63;
 939                 break;
 940         }
 941
 942         aligned += pitch_mask;
 943         aligned &= ~pitch_mask;
 944         return aligned * cpp;
 945 }
 946
 947 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 948                             struct drm_device *dev,
 949                             struct drm_mode_create_dumb *args)
 950 {
 951         struct amdgpu_device *adev = drm_to_adev(dev);
 952         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 953         struct drm_gem_object *gobj;
 954         uint32_t handle;
 955         u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 956                     AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 957                     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 958         u32 domain;
 959         int r;
 960
 961         /*
 962          * The buffer returned from this function should be cleared, but
 963          * it can only be done if the ring is enabled or we'll fail to
 964          * create the buffer.
 965          */
 966         if (adev->mman.buffer_funcs_enabled)
 967                 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
 968
 969         args->pitch = amdgpu_gem_align_pitch(adev, args->width,
 970                                              DIV_ROUND_UP(args->bpp, 8), 0);
 971         args->size = (u64)args->pitch * args->height;
 972         args->size = ALIGN(args->size, PAGE_SIZE);
 973         domain = amdgpu_bo_get_preferred_domain(adev,
 974                                 amdgpu_display_supported_domains(adev, flags));
 975         r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
 976                                      ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 977         if (r)
 978                 return -ENOMEM;
 979
 980         r = drm_gem_handle_create(file_priv, gobj, &handle);
 981         /* drop reference from allocate - handle holds it now */
 982         drm_gem_object_put(gobj);
 983         if (r)
 984                 return r;
 985
 986         args->handle = handle;
 987         return 0;
 988 }
 989
 990 #if defined(CONFIG_DEBUG_FS)
 991 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
 992 {
 993         struct amdgpu_device *adev = m->private;
 994         struct drm_device *dev = adev_to_drm(adev);
 995         struct drm_file *file;
 996         int r;
 997
 998         r = mutex_lock_interruptible(&dev->filelist_mutex);
 999         if (r)
1000                 return r;
1001
1002         list_for_each_entry(file, &dev->filelist, lhead) {
1003                 struct task_struct *task;
1004                 struct drm_gem_object *gobj;
1005                 struct pid *pid;
1006                 int id;
1007
1008                 /*
1009                  * Although we have a valid reference on file->pid, that does
1010                  * not guarantee that the task_struct who called get_pid() is
1011                  * still alive (e.g. get_pid(current) => fork() => exit()).
1012                  * Therefore, we need to protect this ->comm access using RCU.
1013                  */
1014                 rcu_read_lock();
1015                 pid = rcu_dereference(file->pid);
1016                 task = pid_task(pid, PIDTYPE_TGID);
1017                 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid),
1018                            task ? task->comm : "<unknown>");
1019                 rcu_read_unlock();
1020
1021                 spin_lock(&file->table_lock);
1022                 idr_for_each_entry(&file->object_idr, gobj, id) {
1023                         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1024
1025                         amdgpu_bo_print_info(id, bo, m);
1026                 }
1027                 spin_unlock(&file->table_lock);
1028         }
1029
1030         mutex_unlock(&dev->filelist_mutex);
1031         return 0;
1032 }
1033
1034 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
1035
1036 #endif
1037
1038 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1039 {
1040 #if defined(CONFIG_DEBUG_FS)
1041         struct drm_minor *minor = adev_to_drm(adev)->primary;
1042         struct dentry *root = minor->debugfs_root;
1043
1044         debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1045                             &amdgpu_debugfs_gem_info_fops);
1046 #endif
1047 }