drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_MES_H__
  25 #define __AMDGPU_MES_H__
  26
  27 #include "amdgpu_irq.h"
  28 #include "kgd_kfd_interface.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_doorbell.h"
  31 #include <linux/sched/mm.h>
  32
  33 #define AMDGPU_MES_MAX_COMPUTE_PIPES        8
  34 #define AMDGPU_MES_MAX_GFX_PIPES            2
  35 #define AMDGPU_MES_MAX_SDMA_PIPES           2
  36
  37 #define AMDGPU_MES_API_VERSION_SHIFT    12
  38 #define AMDGPU_MES_FEAT_VERSION_SHIFT   24
  39
  40 #define AMDGPU_MES_VERSION_MASK         0x00000fff
  41 #define AMDGPU_MES_API_VERSION_MASK     0x00fff000
  42 #define AMDGPU_MES_FEAT_VERSION_MASK    0xff000000
  43
  44 enum amdgpu_mes_priority_level {
  45         AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,
  46         AMDGPU_MES_PRIORITY_LEVEL_NORMAL    = 1,
  47         AMDGPU_MES_PRIORITY_LEVEL_MEDIUM    = 2,
  48         AMDGPU_MES_PRIORITY_LEVEL_HIGH      = 3,
  49         AMDGPU_MES_PRIORITY_LEVEL_REALTIME  = 4,
  50         AMDGPU_MES_PRIORITY_NUM_LEVELS
  51 };
  52
  53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
  54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
  55
  56 struct amdgpu_mes_funcs;
  57
  58 enum admgpu_mes_pipe {
  59         AMDGPU_MES_SCHED_PIPE = 0,
  60         AMDGPU_MES_KIQ_PIPE,
  61         AMDGPU_MAX_MES_PIPES = 2,
  62 };
  63
  64 struct amdgpu_mes {
  65         struct amdgpu_device            *adev;
  66
  67         struct mutex                    mutex_hidden;
  68
  69         struct idr                      pasid_idr;
  70         struct idr                      gang_id_idr;
  71         struct idr                      queue_id_idr;
  72         struct ida                      doorbell_ida;
  73
  74         spinlock_t                      queue_id_lock;
  75
  76         uint32_t                        sched_version;
  77         uint32_t                        kiq_version;
  78         uint32_t                        fw_version[AMDGPU_MAX_MES_PIPES];
  79         bool                            enable_legacy_queue_map;
  80
  81         uint32_t                        total_max_queue;
  82         uint32_t                        max_doorbell_slices;
  83
  84         uint64_t                        default_process_quantum;
  85         uint64_t                        default_gang_quantum;
  86
  87         struct amdgpu_ring              ring[AMDGPU_MAX_MES_PIPES];
  88         spinlock_t                      ring_lock[AMDGPU_MAX_MES_PIPES];
  89
  90         const struct firmware           *fw[AMDGPU_MAX_MES_PIPES];
  91
  92         /* mes ucode */
  93         struct amdgpu_bo                *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
  94         uint64_t                        ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
  95         uint32_t                        *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
  96         uint64_t                        uc_start_addr[AMDGPU_MAX_MES_PIPES];
  97
  98         /* mes ucode data */
  99         struct amdgpu_bo                *data_fw_obj[AMDGPU_MAX_MES_PIPES];
 100         uint64_t                        data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
 101         uint32_t                        *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
 102         uint64_t                        data_start_addr[AMDGPU_MAX_MES_PIPES];
 103
 104         /* eop gpu obj */
 105         struct amdgpu_bo                *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
 106         uint64_t                        eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
 107
 108         void                            *mqd_backup[AMDGPU_MAX_MES_PIPES];
 109         struct amdgpu_irq_src           irq[AMDGPU_MAX_MES_PIPES];
 110
 111         uint32_t                        vmid_mask_gfxhub;
 112         uint32_t                        vmid_mask_mmhub;
 113         uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
 114         uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
 115         uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
 116         uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
 117         uint32_t                        sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
 118         uint64_t                        sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
 119         uint64_t                        *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
 120         uint32_t                        query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
 121         uint64_t                        query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
 122         uint64_t                        *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];
 123         uint32_t                        read_val_offs;
 124         uint64_t                        read_val_gpu_addr;
 125         uint32_t                        *read_val_ptr;
 126
 127         uint32_t                        saved_flags;
 128
 129         /* initialize kiq pipe */
 130         int                             (*kiq_hw_init)(struct amdgpu_device *adev);
 131         int                             (*kiq_hw_fini)(struct amdgpu_device *adev);
 132
 133         /* MES doorbells */
 134         uint32_t                        db_start_dw_offset;
 135         uint32_t                        num_mes_dbs;
 136         unsigned long                   *doorbell_bitmap;
 137
 138         /* MES event log buffer */
 139         uint32_t                        event_log_size;
 140         struct amdgpu_bo        *event_log_gpu_obj;
 141         uint64_t                        event_log_gpu_addr;
 142         void                            *event_log_cpu_addr;
 143
 144         /* ip specific functions */
 145         const struct amdgpu_mes_funcs   *funcs;
 146
 147         /* mes resource_1 bo*/
 148         struct amdgpu_bo    *resource_1;
 149         uint64_t            resource_1_gpu_addr;
 150         void                *resource_1_addr;
 151
 152 };
 153
 154 struct amdgpu_mes_process {
 155         int                     pasid;
 156         struct                  amdgpu_vm *vm;
 157         uint64_t                pd_gpu_addr;
 158         struct amdgpu_bo        *proc_ctx_bo;
 159         uint64_t                proc_ctx_gpu_addr;
 160         void                    *proc_ctx_cpu_ptr;
 161         uint64_t                process_quantum;
 162         struct                  list_head gang_list;
 163         uint32_t                doorbell_index;
 164         struct mutex            doorbell_lock;
 165 };
 166
 167 struct amdgpu_mes_gang {
 168         int                             gang_id;
 169         int                             priority;
 170         int                             inprocess_gang_priority;
 171         int                             global_priority_level;
 172         struct list_head                list;
 173         struct amdgpu_mes_process       *process;
 174         struct amdgpu_bo                *gang_ctx_bo;
 175         uint64_t                        gang_ctx_gpu_addr;
 176         void                            *gang_ctx_cpu_ptr;
 177         uint64_t                        gang_quantum;
 178         struct list_head                queue_list;
 179 };
 180
 181 struct amdgpu_mes_queue {
 182         struct list_head                list;
 183         struct amdgpu_mes_gang          *gang;
 184         int                             queue_id;
 185         uint64_t                        doorbell_off;
 186         struct amdgpu_bo                *mqd_obj;
 187         void                            *mqd_cpu_ptr;
 188         uint64_t                        mqd_gpu_addr;
 189         uint64_t                        wptr_gpu_addr;
 190         int                             queue_type;
 191         int                             paging;
 192         struct amdgpu_ring              *ring;
 193 };
 194
 195 struct amdgpu_mes_queue_properties {
 196         int                     queue_type;
 197         uint64_t                hqd_base_gpu_addr;
 198         uint64_t                rptr_gpu_addr;
 199         uint64_t                wptr_gpu_addr;
 200         uint64_t                wptr_mc_addr;
 201         uint32_t                queue_size;
 202         uint64_t                eop_gpu_addr;
 203         uint32_t                hqd_pipe_priority;
 204         uint32_t                hqd_queue_priority;
 205         bool                    paging;
 206         struct amdgpu_ring      *ring;
 207         /* out */
 208         uint64_t                doorbell_off;
 209 };
 210
 211 struct amdgpu_mes_gang_properties {
 212         uint32_t        priority;
 213         uint32_t        gang_quantum;
 214         uint32_t        inprocess_gang_priority;
 215         uint32_t        priority_level;
 216         int             global_priority_level;
 217 };
 218
 219 struct mes_add_queue_input {
 220         uint32_t        process_id;
 221         uint64_t        page_table_base_addr;
 222         uint64_t        process_va_start;
 223         uint64_t        process_va_end;
 224         uint64_t        process_quantum;
 225         uint64_t        process_context_addr;
 226         uint64_t        gang_quantum;
 227         uint64_t        gang_context_addr;
 228         uint32_t        inprocess_gang_priority;
 229         uint32_t        gang_global_priority_level;
 230         uint32_t        doorbell_offset;
 231         uint64_t        mqd_addr;
 232         uint64_t        wptr_addr;
 233         uint64_t        wptr_mc_addr;
 234         uint32_t        queue_type;
 235         uint32_t        paging;
 236         uint32_t        gws_base;
 237         uint32_t        gws_size;
 238         uint64_t        tba_addr;
 239         uint64_t        tma_addr;
 240         uint32_t        trap_en;
 241         uint32_t        skip_process_ctx_clear;
 242         uint32_t        is_kfd_process;
 243         uint32_t        is_aql_queue;
 244         uint32_t        queue_size;
 245         uint32_t        exclusively_scheduled;
 246 };
 247
 248 struct mes_remove_queue_input {
 249         uint32_t        doorbell_offset;
 250         uint64_t        gang_context_addr;
 251 };
 252
 253 struct mes_reset_queue_input {
 254         uint32_t        doorbell_offset;
 255         uint64_t        gang_context_addr;
 256         bool            use_mmio;
 257         uint32_t        queue_type;
 258         uint32_t        me_id;
 259         uint32_t        pipe_id;
 260         uint32_t        queue_id;
 261         uint32_t        xcc_id;
 262         uint32_t        vmid;
 263 };
 264
 265 struct mes_map_legacy_queue_input {
 266         uint32_t                           queue_type;
 267         uint32_t                           doorbell_offset;
 268         uint32_t                           pipe_id;
 269         uint32_t                           queue_id;
 270         uint64_t                           mqd_addr;
 271         uint64_t                           wptr_addr;
 272 };
 273
 274 struct mes_unmap_legacy_queue_input {
 275         enum amdgpu_unmap_queues_action    action;
 276         uint32_t                           queue_type;
 277         uint32_t                           doorbell_offset;
 278         uint32_t                           pipe_id;
 279         uint32_t                           queue_id;
 280         uint64_t                           trail_fence_addr;
 281         uint64_t                           trail_fence_data;
 282 };
 283
 284 struct mes_suspend_gang_input {
 285         bool            suspend_all_gangs;
 286         uint64_t        gang_context_addr;
 287         uint64_t        suspend_fence_addr;
 288         uint32_t        suspend_fence_value;
 289 };
 290
 291 struct mes_resume_gang_input {
 292         bool            resume_all_gangs;
 293         uint64_t        gang_context_addr;
 294 };
 295
 296 struct mes_reset_legacy_queue_input {
 297         uint32_t                           queue_type;
 298         uint32_t                           doorbell_offset;
 299         bool                               use_mmio;
 300         uint32_t                           me_id;
 301         uint32_t                           pipe_id;
 302         uint32_t                           queue_id;
 303         uint64_t                           mqd_addr;
 304         uint64_t                           wptr_addr;
 305         uint32_t                           vmid;
 306 };
 307
 308 enum mes_misc_opcode {
 309         MES_MISC_OP_WRITE_REG,
 310         MES_MISC_OP_READ_REG,
 311         MES_MISC_OP_WRM_REG_WAIT,
 312         MES_MISC_OP_WRM_REG_WR_WAIT,
 313         MES_MISC_OP_SET_SHADER_DEBUGGER,
 314 };
 315
 316 struct mes_misc_op_input {
 317         enum mes_misc_opcode op;
 318
 319         union {
 320                 struct {
 321                         uint32_t                  reg_offset;
 322                         uint64_t                  buffer_addr;
 323                 } read_reg;
 324
 325                 struct {
 326                         uint32_t                  reg_offset;
 327                         uint32_t                  reg_value;
 328                 } write_reg;
 329
 330                 struct {
 331                         uint32_t                   ref;
 332                         uint32_t                   mask;
 333                         uint32_t                   reg0;
 334                         uint32_t                   reg1;
 335                 } wrm_reg;
 336
 337                 struct {
 338                         uint64_t process_context_addr;
 339                         union {
 340                                 struct {
 341                                         uint32_t single_memop : 1;
 342                                         uint32_t single_alu_op : 1;
 343                                         uint32_t reserved: 29;
 344                                         uint32_t process_ctx_flush: 1;
 345                                 };
 346                                 uint32_t u32all;
 347                         } flags;
 348                         uint32_t spi_gdbg_per_vmid_cntl;
 349                         uint32_t tcp_watch_cntl[4];
 350                         uint32_t trap_en;
 351                 } set_shader_debugger;
 352         };
 353 };
 354
 355 struct amdgpu_mes_funcs {
 356         int (*add_hw_queue)(struct amdgpu_mes *mes,
 357                             struct mes_add_queue_input *input);
 358
 359         int (*remove_hw_queue)(struct amdgpu_mes *mes,
 360                                struct mes_remove_queue_input *input);
 361
 362         int (*map_legacy_queue)(struct amdgpu_mes *mes,
 363                                 struct mes_map_legacy_queue_input *input);
 364
 365         int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
 366                                   struct mes_unmap_legacy_queue_input *input);
 367
 368         int (*suspend_gang)(struct amdgpu_mes *mes,
 369                             struct mes_suspend_gang_input *input);
 370
 371         int (*resume_gang)(struct amdgpu_mes *mes,
 372                            struct mes_resume_gang_input *input);
 373
 374         int (*misc_op)(struct amdgpu_mes *mes,
 375                        struct mes_misc_op_input *input);
 376
 377         int (*reset_legacy_queue)(struct amdgpu_mes *mes,
 378                                   struct mes_reset_legacy_queue_input *input);
 379
 380         int (*reset_hw_queue)(struct amdgpu_mes *mes,
 381                               struct mes_reset_queue_input *input);
 382 };
 383
 384 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
 385 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
 386
 387 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
 388
 389 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
 390 int amdgpu_mes_init(struct amdgpu_device *adev);
 391 void amdgpu_mes_fini(struct amdgpu_device *adev);
 392
 393 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
 394                               struct amdgpu_vm *vm);
 395 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
 396
 397 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
 398                         struct amdgpu_mes_gang_properties *gprops,
 399                         int *gang_id);
 400 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
 401
 402 int amdgpu_mes_suspend(struct amdgpu_device *adev);
 403 int amdgpu_mes_resume(struct amdgpu_device *adev);
 404
 405 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
 406                             struct amdgpu_mes_queue_properties *qprops,
 407                             int *queue_id);
 408 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
 409 int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id);
 410 int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type,
 411                                    int me_id, int pipe_id, int queue_id, int vmid);
 412
 413 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
 414                                 struct amdgpu_ring *ring);
 415 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
 416                                   struct amdgpu_ring *ring,
 417                                   enum amdgpu_unmap_queues_action action,
 418                                   u64 gpu_addr, u64 seq);
 419 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
 420                                   struct amdgpu_ring *ring,
 421                                   unsigned int vmid,
 422                                   bool use_mmio);
 423
 424 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
 425 int amdgpu_mes_wreg(struct amdgpu_device *adev,
 426                     uint32_t reg, uint32_t val);
 427 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
 428                         uint32_t val, uint32_t mask);
 429 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
 430                                   uint32_t reg0, uint32_t reg1,
 431                                   uint32_t ref, uint32_t mask);
 432 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
 433                                 uint64_t process_context_addr,
 434                                 uint32_t spi_gdbg_per_vmid_cntl,
 435                                 const uint32_t *tcp_watch_cntl,
 436                                 uint32_t flags,
 437                                 bool trap_en);
 438 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
 439                                 uint64_t process_context_addr);
 440 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
 441                         int queue_type, int idx,
 442                         struct amdgpu_mes_ctx_data *ctx_data,
 443                         struct amdgpu_ring **out);
 444 void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
 445                             struct amdgpu_ring *ring);
 446
 447 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
 448                                                    enum amdgpu_mes_priority_level prio);
 449
 450 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
 451                                    struct amdgpu_mes_ctx_data *ctx_data);
 452 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
 453 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
 454                                  struct amdgpu_vm *vm,
 455                                  struct amdgpu_mes_ctx_data *ctx_data);
 456 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
 457                                    struct amdgpu_mes_ctx_data *ctx_data);
 458
 459 int amdgpu_mes_self_test(struct amdgpu_device *adev);
 460
 461 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
 462
 463 /*
 464  * MES lock can be taken in MMU notifiers.
 465  *
 466  * A bit more detail about why to set no-FS reclaim with MES lock:
 467  *
 468  * The purpose of the MMU notifier is to stop GPU access to memory so
 469  * that the Linux VM subsystem can move pages around safely. This is
 470  * done by preempting user mode queues for the affected process. When
 471  * MES is used, MES lock needs to be taken to preempt the queues.
 472  *
 473  * The MMU notifier callback entry point in the driver is
 474  * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
 475  * there is:
 476  * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
 477  * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
 478  *
 479  * The last part of the chain is a function pointer where we take the
 480  * MES lock.
 481  *
 482  * The problem with taking locks in the MMU notifier is, that MMU
 483  * notifiers can be called in reclaim-FS context. That's where the
 484  * kernel frees up pages to make room for new page allocations under
 485  * memory pressure. While we are running in reclaim-FS context, we must
 486  * not trigger another memory reclaim operation because that would
 487  * recursively reenter the reclaim code and cause a deadlock. The
 488  * memalloc_nofs_save/restore calls guarantee that.
 489  *
 490  * In addition we also need to avoid lock dependencies on other locks taken
 491  * under the MES lock, for example reservation locks. Here is a possible
 492  * scenario of a deadlock:
 493  * Thread A: takes and holds reservation lock | triggers reclaim-FS |
 494  * MMU notifier | blocks trying to take MES lock
 495  * Thread B: takes and holds MES lock | blocks trying to take reservation lock
 496  *
 497  * In this scenario Thread B gets involved in a deadlock even without
 498  * triggering a reclaim-FS operation itself.
 499  * To fix this and break the lock dependency chain you'd need to either:
 500  * 1. protect reservation locks with memalloc_nofs_save/restore, or
 501  * 2. avoid taking reservation locks under the MES lock.
 502  *
 503  * Reservation locks are taken all over the kernel in different subsystems, we
 504  * have no control over them and their lock dependencies.So the only workable
 505  * solution is to avoid taking other locks under the MES lock.
 506  * As a result, make sure no reclaim-FS happens while holding this lock anywhere
 507  * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
 508  */
 509 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
 510 {
 511         mutex_lock(&mes->mutex_hidden);
 512         mes->saved_flags = memalloc_noreclaim_save();
 513 }
 514
 515 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
 516 {
 517         memalloc_noreclaim_restore(mes->saved_flags);
 518         mutex_unlock(&mes->mutex_hidden);
 519 }
 520
 521 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
 522 #endif /* __AMDGPU_MES_H__ */