drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/ktime.h>
  29 #include <linux/module.h>
  30 #include <linux/pagemap.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-buf.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_exec.h>
  37 #include <drm/drm_gem_ttm_helper.h>
  38 #include <drm/ttm/ttm_tt.h>
  39
  40 #include "amdgpu.h"
  41 #include "amdgpu_display.h"
  42 #include "amdgpu_dma_buf.h"
  43 #include "amdgpu_hmm.h"
  44 #include "amdgpu_xgmi.h"
  45
  46 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
  47
  48 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
  49 {
  50         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
  51         struct drm_device *ddev = bo->base.dev;
  52         vm_fault_t ret;
  53         int idx;
  54
  55         ret = ttm_bo_vm_reserve(bo, vmf);
  56         if (ret)
  57                 return ret;
  58
  59         if (drm_dev_enter(ddev, &idx)) {
  60                 ret = amdgpu_bo_fault_reserve_notify(bo);
  61                 if (ret) {
  62                         drm_dev_exit(idx);
  63                         goto unlock;
  64                 }
  65
  66                 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
  67                                                TTM_BO_VM_NUM_PREFAULT);
  68
  69                 drm_dev_exit(idx);
  70         } else {
  71                 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
  72         }
  73         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
  74                 return ret;
  75
  76 unlock:
  77         dma_resv_unlock(bo->base.resv);
  78         return ret;
  79 }
  80
  81 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
  82         .fault = amdgpu_gem_fault,
  83         .open = ttm_bo_vm_open,
  84         .close = ttm_bo_vm_close,
  85         .access = ttm_bo_vm_access
  86 };
  87
  88 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
  89 {
  90         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
  91
  92         if (robj) {
  93                 amdgpu_hmm_unregister(robj);
  94                 amdgpu_bo_unref(&robj);
  95         }
  96 }
  97
  98 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
  99                              int alignment, u32 initial_domain,
 100                              u64 flags, enum ttm_bo_type type,
 101                              struct dma_resv *resv,
 102                              struct drm_gem_object **obj, int8_t xcp_id_plus1)
 103 {
 104         struct amdgpu_bo *bo;
 105         struct amdgpu_bo_user *ubo;
 106         struct amdgpu_bo_param bp;
 107         int r;
 108
 109         memset(&bp, 0, sizeof(bp));
 110         *obj = NULL;
 111
 112         bp.size = size;
 113         bp.byte_align = alignment;
 114         bp.type = type;
 115         bp.resv = resv;
 116         bp.preferred_domain = initial_domain;
 117         bp.flags = flags;
 118         bp.domain = initial_domain;
 119         bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 120         bp.xcp_id_plus1 = xcp_id_plus1;
 121
 122         r = amdgpu_bo_create_user(adev, &bp, &ubo);
 123         if (r)
 124                 return r;
 125
 126         bo = &ubo->bo;
 127         *obj = &bo->tbo.base;
 128         (*obj)->funcs = &amdgpu_gem_object_funcs;
 129
 130         return 0;
 131 }
 132
 133 void amdgpu_gem_force_release(struct amdgpu_device *adev)
 134 {
 135         struct drm_device *ddev = adev_to_drm(adev);
 136         struct drm_file *file;
 137
 138         mutex_lock(&ddev->filelist_mutex);
 139
 140         list_for_each_entry(file, &ddev->filelist, lhead) {
 141                 struct drm_gem_object *gobj;
 142                 int handle;
 143
 144                 WARN_ONCE(1, "Still active user space clients!\n");
 145                 spin_lock(&file->table_lock);
 146                 idr_for_each_entry(&file->object_idr, gobj, handle) {
 147                         WARN_ONCE(1, "And also active allocations!\n");
 148                         drm_gem_object_put(gobj);
 149                 }
 150                 idr_destroy(&file->object_idr);
 151                 spin_unlock(&file->table_lock);
 152         }
 153
 154         mutex_unlock(&ddev->filelist_mutex);
 155 }
 156
 157 /*
 158  * Call from drm_gem_handle_create which appear in both new and open ioctl
 159  * case.
 160  */
 161 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
 162                                   struct drm_file *file_priv)
 163 {
 164         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
 165         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
 166         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 167         struct amdgpu_vm *vm = &fpriv->vm;
 168         struct amdgpu_bo_va *bo_va;
 169         struct mm_struct *mm;
 170         int r;
 171
 172         mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
 173         if (mm && mm != current->mm)
 174                 return -EPERM;
 175
 176         if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
 177             !amdgpu_vm_is_bo_always_valid(vm, abo))
 178                 return -EPERM;
 179
 180         r = amdgpu_bo_reserve(abo, false);
 181         if (r)
 182                 return r;
 183
 184         bo_va = amdgpu_vm_bo_find(vm, abo);
 185         if (!bo_va)
 186                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
 187         else
 188                 ++bo_va->ref_count;
 189         amdgpu_bo_unreserve(abo);
 190
 191         /* Validate and add eviction fence to DMABuf imports with dynamic
 192          * attachment in compute VMs. Re-validation will be done by
 193          * amdgpu_vm_validate. Fences are on the reservation shared with the
 194          * export, which is currently required to be validated and fenced
 195          * already by amdgpu_amdkfd_gpuvm_restore_process_bos.
 196          *
 197          * Nested locking below for the case that a GEM object is opened in
 198          * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,
 199          * but not for export, this is a different lock class that cannot lead to
 200          * circular lock dependencies.
 201          */
 202         if (!vm->is_compute_context || !vm->process_info)
 203                 return 0;
 204         if (!obj->import_attach ||
 205             !dma_buf_is_dynamic(obj->import_attach->dmabuf))
 206                 return 0;
 207         mutex_lock_nested(&vm->process_info->lock, 1);
 208         if (!WARN_ON(!vm->process_info->eviction_fence)) {
 209                 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT,
 210                                                         &vm->process_info->eviction_fence->base);
 211                 if (r) {
 212                         struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
 213
 214                         dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);
 215                         if (ti) {
 216                                 dev_warn(adev->dev, "pid %d\n", ti->pid);
 217                                 amdgpu_vm_put_task_info(ti);
 218                         }
 219                 }
 220         }
 221         mutex_unlock(&vm->process_info->lock);
 222
 223         return r;
 224 }
 225
 226 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
 227                                     struct drm_file *file_priv)
 228 {
 229         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 230         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 231         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 232         struct amdgpu_vm *vm = &fpriv->vm;
 233
 234         struct dma_fence *fence = NULL;
 235         struct amdgpu_bo_va *bo_va;
 236         struct drm_exec exec;
 237         long r;
 238
 239         drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
 240         drm_exec_until_all_locked(&exec) {
 241                 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
 242                 drm_exec_retry_on_contention(&exec);
 243                 if (unlikely(r))
 244                         goto out_unlock;
 245
 246                 r = amdgpu_vm_lock_pd(vm, &exec, 0);
 247                 drm_exec_retry_on_contention(&exec);
 248                 if (unlikely(r))
 249                         goto out_unlock;
 250         }
 251
 252         bo_va = amdgpu_vm_bo_find(vm, bo);
 253         if (!bo_va || --bo_va->ref_count)
 254                 goto out_unlock;
 255
 256         amdgpu_vm_bo_del(adev, bo_va);
 257         if (!amdgpu_vm_ready(vm))
 258                 goto out_unlock;
 259
 260         r = amdgpu_vm_clear_freed(adev, vm, &fence);
 261         if (unlikely(r < 0))
 262                 dev_err(adev->dev, "failed to clear page "
 263                         "tables on GEM object close (%ld)\n", r);
 264         if (r || !fence)
 265                 goto out_unlock;
 266
 267         amdgpu_bo_fence(bo, fence, true);
 268         dma_fence_put(fence);
 269
 270 out_unlock:
 271         if (r)
 272                 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
 273         drm_exec_fini(&exec);
 274 }
 275
 276 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 277 {
 278         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 279
 280         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 281                 return -EPERM;
 282         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 283                 return -EPERM;
 284
 285         /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
 286          * for debugger access to invisible VRAM. Should have used MAP_SHARED
 287          * instead. Clearing VM_MAYWRITE prevents the mapping from ever
 288          * becoming writable and makes is_cow_mapping(vm_flags) false.
 289          */
 290         if (is_cow_mapping(vma->vm_flags) &&
 291             !(vma->vm_flags & VM_ACCESS_FLAGS))
 292                 vm_flags_clear(vma, VM_MAYWRITE);
 293
 294         return drm_gem_ttm_mmap(obj, vma);
 295 }
 296
 297 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
 298         .free = amdgpu_gem_object_free,
 299         .open = amdgpu_gem_object_open,
 300         .close = amdgpu_gem_object_close,
 301         .export = amdgpu_gem_prime_export,
 302         .vmap = drm_gem_ttm_vmap,
 303         .vunmap = drm_gem_ttm_vunmap,
 304         .mmap = amdgpu_gem_object_mmap,
 305         .vm_ops = &amdgpu_gem_vm_ops,
 306 };
 307
 308 /*
 309  * GEM ioctls.
 310  */
 311 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 312                             struct drm_file *filp)
 313 {
 314         struct amdgpu_device *adev = drm_to_adev(dev);
 315         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 316         struct amdgpu_vm *vm = &fpriv->vm;
 317         union drm_amdgpu_gem_create *args = data;
 318         uint64_t flags = args->in.domain_flags;
 319         uint64_t size = args->in.bo_size;
 320         struct dma_resv *resv = NULL;
 321         struct drm_gem_object *gobj;
 322         uint32_t handle, initial_domain;
 323         int r;
 324
 325         /* reject DOORBELLs until userspace code to use it is available */
 326         if (args->in.domains & AMDGPU_GEM_DOMAIN_DOORBELL)
 327                 return -EINVAL;
 328
 329         /* reject invalid gem flags */
 330         if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 331                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 332                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 333                       AMDGPU_GEM_CREATE_VRAM_CLEARED |
 334                       AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
 335                       AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
 336                       AMDGPU_GEM_CREATE_ENCRYPTED |
 337                       AMDGPU_GEM_CREATE_GFX12_DCC |
 338                       AMDGPU_GEM_CREATE_DISCARDABLE))
 339                 return -EINVAL;
 340
 341         /* reject invalid gem domains */
 342         if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
 343                 return -EINVAL;
 344
 345         if ((flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
 346             ((amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) ||
 347              !(args->in.domains & AMDGPU_GEM_DOMAIN_VRAM)))
 348                 return -EINVAL;
 349
 350         if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
 351                 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
 352                 return -EINVAL;
 353         }
 354
 355         /* create a gem object to contain this object in */
 356         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
 357             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 358                 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 359                         /* if gds bo is created from user space, it must be
 360                          * passed to bo list
 361                          */
 362                         DRM_ERROR("GDS bo cannot be per-vm-bo\n");
 363                         return -EINVAL;
 364                 }
 365                 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 366         }
 367
 368         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 369                 r = amdgpu_bo_reserve(vm->root.bo, false);
 370                 if (r)
 371                         return r;
 372
 373                 resv = vm->root.bo->tbo.base.resv;
 374         }
 375
 376         initial_domain = (u32)(0xffffffff & args->in.domains);
 377 retry:
 378         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
 379                                      initial_domain,
 380                                      flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
 381         if (r && r != -ERESTARTSYS) {
 382                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 383                         flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 384                         goto retry;
 385                 }
 386
 387                 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
 388                         initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
 389                         goto retry;
 390                 }
 391                 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
 392                                 size, initial_domain, args->in.alignment, r);
 393         }
 394
 395         if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
 396                 if (!r) {
 397                         struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
 398
 399                         abo->parent = amdgpu_bo_ref(vm->root.bo);
 400                 }
 401                 amdgpu_bo_unreserve(vm->root.bo);
 402         }
 403         if (r)
 404                 return r;
 405
 406         r = drm_gem_handle_create(filp, gobj, &handle);
 407         /* drop reference from allocate - handle holds it now */
 408         drm_gem_object_put(gobj);
 409         if (r)
 410                 return r;
 411
 412         memset(args, 0, sizeof(*args));
 413         args->out.handle = handle;
 414         return 0;
 415 }
 416
 417 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 418                              struct drm_file *filp)
 419 {
 420         struct ttm_operation_ctx ctx = { true, false };
 421         struct amdgpu_device *adev = drm_to_adev(dev);
 422         struct drm_amdgpu_gem_userptr *args = data;
 423         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 424         struct drm_gem_object *gobj;
 425         struct hmm_range *range;
 426         struct amdgpu_bo *bo;
 427         uint32_t handle;
 428         int r;
 429
 430         args->addr = untagged_addr(args->addr);
 431
 432         if (offset_in_page(args->addr | args->size))
 433                 return -EINVAL;
 434
 435         /* reject unknown flag values */
 436         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 437             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
 438             AMDGPU_GEM_USERPTR_REGISTER))
 439                 return -EINVAL;
 440
 441         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
 442              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
 443
 444                 /* if we want to write to it we must install a MMU notifier */
 445                 return -EACCES;
 446         }
 447
 448         /* create a gem object to contain this object in */
 449         r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
 450                                      0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 451         if (r)
 452                 return r;
 453
 454         bo = gem_to_amdgpu_bo(gobj);
 455         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
 456         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
 457         r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
 458         if (r)
 459                 goto release_object;
 460
 461         r = amdgpu_hmm_register(bo, args->addr);
 462         if (r)
 463                 goto release_object;
 464
 465         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
 466                 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
 467                                                  &range);
 468                 if (r)
 469                         goto release_object;
 470
 471                 r = amdgpu_bo_reserve(bo, true);
 472                 if (r)
 473                         goto user_pages_done;
 474
 475                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 476                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 477                 amdgpu_bo_unreserve(bo);
 478                 if (r)
 479                         goto user_pages_done;
 480         }
 481
 482         r = drm_gem_handle_create(filp, gobj, &handle);
 483         if (r)
 484                 goto user_pages_done;
 485
 486         args->handle = handle;
 487
 488 user_pages_done:
 489         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
 490                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
 491
 492 release_object:
 493         drm_gem_object_put(gobj);
 494
 495         return r;
 496 }
 497
 498 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
 499                           struct drm_device *dev,
 500                           uint32_t handle, uint64_t *offset_p)
 501 {
 502         struct drm_gem_object *gobj;
 503         struct amdgpu_bo *robj;
 504
 505         gobj = drm_gem_object_lookup(filp, handle);
 506         if (!gobj)
 507                 return -ENOENT;
 508
 509         robj = gem_to_amdgpu_bo(gobj);
 510         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
 511             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 512                 drm_gem_object_put(gobj);
 513                 return -EPERM;
 514         }
 515         *offset_p = amdgpu_bo_mmap_offset(robj);
 516         drm_gem_object_put(gobj);
 517         return 0;
 518 }
 519
 520 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
 521                           struct drm_file *filp)
 522 {
 523         union drm_amdgpu_gem_mmap *args = data;
 524         uint32_t handle = args->in.handle;
 525
 526         memset(args, 0, sizeof(*args));
 527         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
 528 }
 529
 530 /**
 531  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
 532  *
 533  * @timeout_ns: timeout in ns
 534  *
 535  * Calculate the timeout in jiffies from an absolute timeout in ns.
 536  */
 537 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
 538 {
 539         unsigned long timeout_jiffies;
 540         ktime_t timeout;
 541
 542         /* clamp timeout if it's to large */
 543         if (((int64_t)timeout_ns) < 0)
 544                 return MAX_SCHEDULE_TIMEOUT;
 545
 546         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
 547         if (ktime_to_ns(timeout) < 0)
 548                 return 0;
 549
 550         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
 551         /*  clamp timeout to avoid unsigned-> signed overflow */
 552         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
 553                 return MAX_SCHEDULE_TIMEOUT - 1;
 554
 555         return timeout_jiffies;
 556 }
 557
 558 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 559                               struct drm_file *filp)
 560 {
 561         union drm_amdgpu_gem_wait_idle *args = data;
 562         struct drm_gem_object *gobj;
 563         struct amdgpu_bo *robj;
 564         uint32_t handle = args->in.handle;
 565         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
 566         int r = 0;
 567         long ret;
 568
 569         gobj = drm_gem_object_lookup(filp, handle);
 570         if (!gobj)
 571                 return -ENOENT;
 572
 573         robj = gem_to_amdgpu_bo(gobj);
 574         ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
 575                                     true, timeout);
 576
 577         /* ret == 0 means not signaled,
 578          * ret > 0 means signaled
 579          * ret < 0 means interrupted before timeout
 580          */
 581         if (ret >= 0) {
 582                 memset(args, 0, sizeof(*args));
 583                 args->out.status = (ret == 0);
 584         } else
 585                 r = ret;
 586
 587         drm_gem_object_put(gobj);
 588         return r;
 589 }
 590
 591 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 592                                 struct drm_file *filp)
 593 {
 594         struct drm_amdgpu_gem_metadata *args = data;
 595         struct drm_gem_object *gobj;
 596         struct amdgpu_bo *robj;
 597         int r = -1;
 598
 599         DRM_DEBUG("%d\n", args->handle);
 600         gobj = drm_gem_object_lookup(filp, args->handle);
 601         if (gobj == NULL)
 602                 return -ENOENT;
 603         robj = gem_to_amdgpu_bo(gobj);
 604
 605         r = amdgpu_bo_reserve(robj, false);
 606         if (unlikely(r != 0))
 607                 goto out;
 608
 609         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
 610                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
 611                 r = amdgpu_bo_get_metadata(robj, args->data.data,
 612                                            sizeof(args->data.data),
 613                                            &args->data.data_size_bytes,
 614                                            &args->data.flags);
 615         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
 616                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
 617                         r = -EINVAL;
 618                         goto unreserve;
 619                 }
 620                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
 621                 if (!r)
 622                         r = amdgpu_bo_set_metadata(robj, args->data.data,
 623                                                    args->data.data_size_bytes,
 624                                                    args->data.flags);
 625         }
 626
 627 unreserve:
 628         amdgpu_bo_unreserve(robj);
 629 out:
 630         drm_gem_object_put(gobj);
 631         return r;
 632 }
 633
 634 /**
 635  * amdgpu_gem_va_update_vm -update the bo_va in its VM
 636  *
 637  * @adev: amdgpu_device pointer
 638  * @vm: vm to update
 639  * @bo_va: bo_va to update
 640  * @operation: map, unmap or clear
 641  *
 642  * Update the bo_va directly after setting its address. Errors are not
 643  * vital here, so they are not reported back to userspace.
 644  */
 645 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 646                                     struct amdgpu_vm *vm,
 647                                     struct amdgpu_bo_va *bo_va,
 648                                     uint32_t operation)
 649 {
 650         int r;
 651
 652         if (!amdgpu_vm_ready(vm))
 653                 return;
 654
 655         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 656         if (r)
 657                 goto error;
 658
 659         if (operation == AMDGPU_VA_OP_MAP ||
 660             operation == AMDGPU_VA_OP_REPLACE) {
 661                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 662                 if (r)
 663                         goto error;
 664         }
 665
 666         r = amdgpu_vm_update_pdes(adev, vm, false);
 667
 668 error:
 669         if (r && r != -ERESTARTSYS)
 670                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
 671 }
 672
 673 /**
 674  * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
 675  *
 676  * @adev: amdgpu_device pointer
 677  * @flags: GEM UAPI flags
 678  *
 679  * Returns the GEM UAPI flags mapped into hardware for the ASIC.
 680  */
 681 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
 682 {
 683         uint64_t pte_flag = 0;
 684
 685         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 686                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 687         if (flags & AMDGPU_VM_PAGE_READABLE)
 688                 pte_flag |= AMDGPU_PTE_READABLE;
 689         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 690                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 691         if (flags & AMDGPU_VM_PAGE_PRT)
 692                 pte_flag |= AMDGPU_PTE_PRT_FLAG(adev);
 693         if (flags & AMDGPU_VM_PAGE_NOALLOC)
 694                 pte_flag |= AMDGPU_PTE_NOALLOC;
 695
 696         if (adev->gmc.gmc_funcs->map_mtype)
 697                 pte_flag |= amdgpu_gmc_map_mtype(adev,
 698                                                  flags & AMDGPU_VM_MTYPE_MASK);
 699
 700         return pte_flag;
 701 }
 702
 703 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 704                           struct drm_file *filp)
 705 {
 706         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
 707                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
 708                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
 709                 AMDGPU_VM_PAGE_NOALLOC;
 710         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
 711                 AMDGPU_VM_PAGE_PRT;
 712
 713         struct drm_amdgpu_gem_va *args = data;
 714         struct drm_gem_object *gobj;
 715         struct amdgpu_device *adev = drm_to_adev(dev);
 716         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 717         struct amdgpu_bo *abo;
 718         struct amdgpu_bo_va *bo_va;
 719         struct drm_exec exec;
 720         uint64_t va_flags;
 721         uint64_t vm_size;
 722         int r = 0;
 723
 724         if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) {
 725                 dev_dbg(dev->dev,
 726                         "va_address 0x%llx is in reserved area 0x%llx\n",
 727                         args->va_address, AMDGPU_VA_RESERVED_BOTTOM);
 728                 return -EINVAL;
 729         }
 730
 731         if (args->va_address >= AMDGPU_GMC_HOLE_START &&
 732             args->va_address < AMDGPU_GMC_HOLE_END) {
 733                 dev_dbg(dev->dev,
 734                         "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
 735                         args->va_address, AMDGPU_GMC_HOLE_START,
 736                         AMDGPU_GMC_HOLE_END);
 737                 return -EINVAL;
 738         }
 739
 740         args->va_address &= AMDGPU_GMC_HOLE_MASK;
 741
 742         vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 743         vm_size -= AMDGPU_VA_RESERVED_TOP;
 744         if (args->va_address + args->map_size > vm_size) {
 745                 dev_dbg(dev->dev,
 746                         "va_address 0x%llx is in top reserved area 0x%llx\n",
 747                         args->va_address + args->map_size, vm_size);
 748                 return -EINVAL;
 749         }
 750
 751         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 752                 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
 753                         args->flags);
 754                 return -EINVAL;
 755         }
 756
 757         switch (args->operation) {
 758         case AMDGPU_VA_OP_MAP:
 759         case AMDGPU_VA_OP_UNMAP:
 760         case AMDGPU_VA_OP_CLEAR:
 761         case AMDGPU_VA_OP_REPLACE:
 762                 break;
 763         default:
 764                 dev_dbg(dev->dev, "unsupported operation %d\n",
 765                         args->operation);
 766                 return -EINVAL;
 767         }
 768
 769         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
 770             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
 771                 gobj = drm_gem_object_lookup(filp, args->handle);
 772                 if (gobj == NULL)
 773                         return -ENOENT;
 774                 abo = gem_to_amdgpu_bo(gobj);
 775         } else {
 776                 gobj = NULL;
 777                 abo = NULL;
 778         }
 779
 780         drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
 781                       DRM_EXEC_IGNORE_DUPLICATES, 0);
 782         drm_exec_until_all_locked(&exec) {
 783                 if (gobj) {
 784                         r = drm_exec_lock_obj(&exec, gobj);
 785                         drm_exec_retry_on_contention(&exec);
 786                         if (unlikely(r))
 787                                 goto error;
 788                 }
 789
 790                 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
 791                 drm_exec_retry_on_contention(&exec);
 792                 if (unlikely(r))
 793                         goto error;
 794         }
 795
 796         if (abo) {
 797                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
 798                 if (!bo_va) {
 799                         r = -ENOENT;
 800                         goto error;
 801                 }
 802         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
 803                 bo_va = fpriv->prt_va;
 804         } else {
 805                 bo_va = NULL;
 806         }
 807
 808         switch (args->operation) {
 809         case AMDGPU_VA_OP_MAP:
 810                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 811                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 812                                      args->offset_in_bo, args->map_size,
 813                                      va_flags);
 814                 break;
 815         case AMDGPU_VA_OP_UNMAP:
 816                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
 817                 break;
 818
 819         case AMDGPU_VA_OP_CLEAR:
 820                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
 821                                                 args->va_address,
 822                                                 args->map_size);
 823                 break;
 824         case AMDGPU_VA_OP_REPLACE:
 825                 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
 826                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
 827                                              args->offset_in_bo, args->map_size,
 828                                              va_flags);
 829                 break;
 830         default:
 831                 break;
 832         }
 833         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm)
 834                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
 835                                         args->operation);
 836
 837 error:
 838         drm_exec_fini(&exec);
 839         drm_gem_object_put(gobj);
 840         return r;
 841 }
 842
 843 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 844                         struct drm_file *filp)
 845 {
 846         struct amdgpu_device *adev = drm_to_adev(dev);
 847         struct drm_amdgpu_gem_op *args = data;
 848         struct drm_gem_object *gobj;
 849         struct amdgpu_vm_bo_base *base;
 850         struct amdgpu_bo *robj;
 851         int r;
 852
 853         gobj = drm_gem_object_lookup(filp, args->handle);
 854         if (!gobj)
 855                 return -ENOENT;
 856
 857         robj = gem_to_amdgpu_bo(gobj);
 858
 859         r = amdgpu_bo_reserve(robj, false);
 860         if (unlikely(r))
 861                 goto out;
 862
 863         switch (args->op) {
 864         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
 865                 struct drm_amdgpu_gem_create_in info;
 866                 void __user *out = u64_to_user_ptr(args->value);
 867
 868                 info.bo_size = robj->tbo.base.size;
 869                 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
 870                 info.domains = robj->preferred_domains;
 871                 info.domain_flags = robj->flags;
 872                 amdgpu_bo_unreserve(robj);
 873                 if (copy_to_user(out, &info, sizeof(info)))
 874                         r = -EFAULT;
 875                 break;
 876         }
 877         case AMDGPU_GEM_OP_SET_PLACEMENT:
 878                 if (robj->tbo.base.import_attach &&
 879                     args->value & AMDGPU_GEM_DOMAIN_VRAM) {
 880                         r = -EINVAL;
 881                         amdgpu_bo_unreserve(robj);
 882                         break;
 883                 }
 884                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
 885                         r = -EPERM;
 886                         amdgpu_bo_unreserve(robj);
 887                         break;
 888                 }
 889                 for (base = robj->vm_bo; base; base = base->next)
 890                         if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
 891                                 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
 892                                 r = -EINVAL;
 893                                 amdgpu_bo_unreserve(robj);
 894                                 goto out;
 895                         }
 896
 897
 898                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
 899                                                         AMDGPU_GEM_DOMAIN_GTT |
 900                                                         AMDGPU_GEM_DOMAIN_CPU);
 901                 robj->allowed_domains = robj->preferred_domains;
 902                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 903                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 904
 905                 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
 906                         amdgpu_vm_bo_invalidate(adev, robj, true);
 907
 908                 amdgpu_bo_unreserve(robj);
 909                 break;
 910         default:
 911                 amdgpu_bo_unreserve(robj);
 912                 r = -EINVAL;
 913         }
 914
 915 out:
 916         drm_gem_object_put(gobj);
 917         return r;
 918 }
 919
 920 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
 921                                   int width,
 922                                   int cpp,
 923                                   bool tiled)
 924 {
 925         int aligned = width;
 926         int pitch_mask = 0;
 927
 928         switch (cpp) {
 929         case 1:
 930                 pitch_mask = 255;
 931                 break;
 932         case 2:
 933                 pitch_mask = 127;
 934                 break;
 935         case 3:
 936         case 4:
 937                 pitch_mask = 63;
 938                 break;
 939         }
 940
 941         aligned += pitch_mask;
 942         aligned &= ~pitch_mask;
 943         return aligned * cpp;
 944 }
 945
 946 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 947                             struct drm_device *dev,
 948                             struct drm_mode_create_dumb *args)
 949 {
 950         struct amdgpu_device *adev = drm_to_adev(dev);
 951         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 952         struct drm_gem_object *gobj;
 953         uint32_t handle;
 954         u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 955                     AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 956                     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 957         u32 domain;
 958         int r;
 959
 960         /*
 961          * The buffer returned from this function should be cleared, but
 962          * it can only be done if the ring is enabled or we'll fail to
 963          * create the buffer.
 964          */
 965         if (adev->mman.buffer_funcs_enabled)
 966                 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
 967
 968         args->pitch = amdgpu_gem_align_pitch(adev, args->width,
 969                                              DIV_ROUND_UP(args->bpp, 8), 0);
 970         args->size = (u64)args->pitch * args->height;
 971         args->size = ALIGN(args->size, PAGE_SIZE);
 972         domain = amdgpu_bo_get_preferred_domain(adev,
 973                                 amdgpu_display_supported_domains(adev, flags));
 974         r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
 975                                      ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
 976         if (r)
 977                 return -ENOMEM;
 978
 979         r = drm_gem_handle_create(file_priv, gobj, &handle);
 980         /* drop reference from allocate - handle holds it now */
 981         drm_gem_object_put(gobj);
 982         if (r)
 983                 return r;
 984
 985         args->handle = handle;
 986         return 0;
 987 }
 988
 989 #if defined(CONFIG_DEBUG_FS)
 990 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
 991 {
 992         struct amdgpu_device *adev = m->private;
 993         struct drm_device *dev = adev_to_drm(adev);
 994         struct drm_file *file;
 995         int r;
 996
 997         r = mutex_lock_interruptible(&dev->filelist_mutex);
 998         if (r)
 999                 return r;
1000
1001         list_for_each_entry(file, &dev->filelist, lhead) {
1002                 struct task_struct *task;
1003                 struct drm_gem_object *gobj;
1004                 struct pid *pid;
1005                 int id;
1006
1007                 /*
1008                  * Although we have a valid reference on file->pid, that does
1009                  * not guarantee that the task_struct who called get_pid() is
1010                  * still alive (e.g. get_pid(current) => fork() => exit()).
1011                  * Therefore, we need to protect this ->comm access using RCU.
1012                  */
1013                 rcu_read_lock();
1014                 pid = rcu_dereference(file->pid);
1015                 task = pid_task(pid, PIDTYPE_TGID);
1016                 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid),
1017                            task ? task->comm : "<unknown>");
1018                 rcu_read_unlock();
1019
1020                 spin_lock(&file->table_lock);
1021                 idr_for_each_entry(&file->object_idr, gobj, id) {
1022                         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1023
1024                         amdgpu_bo_print_info(id, bo, m);
1025                 }
1026                 spin_unlock(&file->table_lock);
1027         }
1028
1029         mutex_unlock(&dev->filelist_mutex);
1030         return 0;
1031 }
1032
1033 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
1034
1035 #endif
1036
1037 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1038 {
1039 #if defined(CONFIG_DEBUG_FS)
1040         struct drm_minor *minor = adev_to_drm(adev)->primary;
1041         struct dentry *root = minor->debugfs_root;
1042
1043         debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1044                             &amdgpu_debugfs_gem_info_fops);
1045 #endif
1046 }