drivers/net/ethernet/intel/igc/igc_ptp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c)  2019 Intel Corporation */
   3
   4 #include "igc.h"
   5
   6 #include <linux/module.h>
   7 #include <linux/device.h>
   8 #include <linux/pci.h>
   9 #include <linux/ptp_classify.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/ktime.h>
  12 #include <linux/delay.h>
  13 #include <linux/iopoll.h>
  14
  15 #define INCVALUE_MASK           0x7fffffff
  16 #define ISGN                    0x80000000
  17
  18 #define IGC_PTP_TX_TIMEOUT              (HZ * 15)
  19
  20 #define IGC_PTM_STAT_SLEEP              2
  21 #define IGC_PTM_STAT_TIMEOUT            100
  22
  23 /* SYSTIM read access for I225 */
  24 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
  25 {
  26         struct igc_hw *hw = &adapter->hw;
  27         u32 sec, nsec;
  28
  29         /* The timestamp is latched when SYSTIML is read. */
  30         nsec = rd32(IGC_SYSTIML);
  31         sec = rd32(IGC_SYSTIMH);
  32
  33         ts->tv_sec = sec;
  34         ts->tv_nsec = nsec;
  35 }
  36
  37 static void igc_ptp_write_i225(struct igc_adapter *adapter,
  38                                const struct timespec64 *ts)
  39 {
  40         struct igc_hw *hw = &adapter->hw;
  41
  42         wr32(IGC_SYSTIML, ts->tv_nsec);
  43         wr32(IGC_SYSTIMH, ts->tv_sec);
  44 }
  45
  46 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
  47 {
  48         struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
  49                                                ptp_caps);
  50         struct igc_hw *hw = &igc->hw;
  51         int neg_adj = 0;
  52         u64 rate;
  53         u32 inca;
  54
  55         if (scaled_ppm < 0) {
  56                 neg_adj = 1;
  57                 scaled_ppm = -scaled_ppm;
  58         }
  59         rate = scaled_ppm;
  60         rate <<= 14;
  61         rate = div_u64(rate, 78125);
  62
  63         inca = rate & INCVALUE_MASK;
  64         if (neg_adj)
  65                 inca |= ISGN;
  66
  67         wr32(IGC_TIMINCA, inca);
  68
  69         return 0;
  70 }
  71
  72 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
  73 {
  74         struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
  75                                                ptp_caps);
  76         struct timespec64 now, then = ns_to_timespec64(delta);
  77         unsigned long flags;
  78
  79         spin_lock_irqsave(&igc->tmreg_lock, flags);
  80
  81         igc_ptp_read(igc, &now);
  82         now = timespec64_add(now, then);
  83         igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
  84
  85         spin_unlock_irqrestore(&igc->tmreg_lock, flags);
  86
  87         return 0;
  88 }
  89
  90 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
  91                                    struct timespec64 *ts,
  92                                    struct ptp_system_timestamp *sts)
  93 {
  94         struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
  95                                                ptp_caps);
  96         struct igc_hw *hw = &igc->hw;
  97         unsigned long flags;
  98
  99         spin_lock_irqsave(&igc->tmreg_lock, flags);
 100
 101         ptp_read_system_prets(sts);
 102         ts->tv_nsec = rd32(IGC_SYSTIML);
 103         ts->tv_sec = rd32(IGC_SYSTIMH);
 104         ptp_read_system_postts(sts);
 105
 106         spin_unlock_irqrestore(&igc->tmreg_lock, flags);
 107
 108         return 0;
 109 }
 110
 111 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
 112                                 const struct timespec64 *ts)
 113 {
 114         struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
 115                                                ptp_caps);
 116         unsigned long flags;
 117
 118         spin_lock_irqsave(&igc->tmreg_lock, flags);
 119
 120         igc_ptp_write_i225(igc, ts);
 121
 122         spin_unlock_irqrestore(&igc->tmreg_lock, flags);
 123
 124         return 0;
 125 }
 126
 127 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
 128 {
 129         u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
 130         static const u32 mask[IGC_N_SDP] = {
 131                 IGC_CTRL_SDP0_DIR,
 132                 IGC_CTRL_SDP1_DIR,
 133                 IGC_CTRL_EXT_SDP2_DIR,
 134                 IGC_CTRL_EXT_SDP3_DIR,
 135         };
 136
 137         if (input)
 138                 *ptr &= ~mask[pin];
 139         else
 140                 *ptr |= mask[pin];
 141 }
 142
 143 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
 144 {
 145         static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
 146                 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
 147         };
 148         static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
 149                 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
 150         };
 151         static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
 152                 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
 153         };
 154         static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
 155                 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
 156                 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
 157         };
 158         static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
 159                 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
 160                 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
 161         };
 162         static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
 163                 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
 164                 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
 165         };
 166         static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
 167                 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
 168                 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
 169         };
 170         static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
 171                 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
 172                 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
 173         };
 174         struct igc_hw *hw = &igc->hw;
 175         u32 ctrl, ctrl_ext, tssdp = 0;
 176
 177         ctrl = rd32(IGC_CTRL);
 178         ctrl_ext = rd32(IGC_CTRL_EXT);
 179         tssdp = rd32(IGC_TSSDP);
 180
 181         igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
 182
 183         /* Make sure this pin is not enabled as an input. */
 184         if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
 185                 tssdp &= ~IGC_AUX0_TS_SDP_EN;
 186
 187         if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
 188                 tssdp &= ~IGC_AUX1_TS_SDP_EN;
 189
 190         tssdp &= ~igc_ts_sdp_sel_clr[pin];
 191         if (freq) {
 192                 if (chan == 1)
 193                         tssdp |= igc_ts_sdp_sel_fc1[pin];
 194                 else
 195                         tssdp |= igc_ts_sdp_sel_fc0[pin];
 196         } else {
 197                 if (chan == 1)
 198                         tssdp |= igc_ts_sdp_sel_tt1[pin];
 199                 else
 200                         tssdp |= igc_ts_sdp_sel_tt0[pin];
 201         }
 202         tssdp |= igc_ts_sdp_en[pin];
 203
 204         wr32(IGC_TSSDP, tssdp);
 205         wr32(IGC_CTRL, ctrl);
 206         wr32(IGC_CTRL_EXT, ctrl_ext);
 207 }
 208
 209 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
 210 {
 211         static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
 212                 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
 213         };
 214         static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
 215                 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
 216         };
 217         static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
 218                 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
 219         };
 220         struct igc_hw *hw = &igc->hw;
 221         u32 ctrl, ctrl_ext, tssdp = 0;
 222
 223         ctrl = rd32(IGC_CTRL);
 224         ctrl_ext = rd32(IGC_CTRL_EXT);
 225         tssdp = rd32(IGC_TSSDP);
 226
 227         igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
 228
 229         /* Make sure this pin is not enabled as an output. */
 230         tssdp &= ~igc_ts_sdp_en[pin];
 231
 232         if (chan == 1) {
 233                 tssdp &= ~IGC_AUX1_SEL_SDP3;
 234                 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
 235         } else {
 236                 tssdp &= ~IGC_AUX0_SEL_SDP3;
 237                 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
 238         }
 239
 240         wr32(IGC_TSSDP, tssdp);
 241         wr32(IGC_CTRL, ctrl);
 242         wr32(IGC_CTRL_EXT, ctrl_ext);
 243 }
 244
 245 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
 246                                        struct ptp_clock_request *rq, int on)
 247 {
 248         struct igc_adapter *igc =
 249                 container_of(ptp, struct igc_adapter, ptp_caps);
 250         struct igc_hw *hw = &igc->hw;
 251         unsigned long flags;
 252         struct timespec64 ts;
 253         int use_freq = 0, pin = -1;
 254         u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
 255         s64 ns;
 256
 257         switch (rq->type) {
 258         case PTP_CLK_REQ_EXTTS:
 259                 /* Reject requests with unsupported flags */
 260                 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
 261                                         PTP_RISING_EDGE |
 262                                         PTP_FALLING_EDGE |
 263                                         PTP_STRICT_FLAGS))
 264                         return -EOPNOTSUPP;
 265
 266                 /* Reject requests failing to enable both edges. */
 267                 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
 268                     (rq->extts.flags & PTP_ENABLE_FEATURE) &&
 269                     (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
 270                         return -EOPNOTSUPP;
 271
 272                 if (on) {
 273                         pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
 274                                            rq->extts.index);
 275                         if (pin < 0)
 276                                 return -EBUSY;
 277                 }
 278                 if (rq->extts.index == 1) {
 279                         tsauxc_mask = IGC_TSAUXC_EN_TS1;
 280                         tsim_mask = IGC_TSICR_AUTT1;
 281                 } else {
 282                         tsauxc_mask = IGC_TSAUXC_EN_TS0;
 283                         tsim_mask = IGC_TSICR_AUTT0;
 284                 }
 285                 spin_lock_irqsave(&igc->tmreg_lock, flags);
 286                 tsauxc = rd32(IGC_TSAUXC);
 287                 tsim = rd32(IGC_TSIM);
 288                 if (on) {
 289                         igc_pin_extts(igc, rq->extts.index, pin);
 290                         tsauxc |= tsauxc_mask;
 291                         tsim |= tsim_mask;
 292                 } else {
 293                         tsauxc &= ~tsauxc_mask;
 294                         tsim &= ~tsim_mask;
 295                 }
 296                 wr32(IGC_TSAUXC, tsauxc);
 297                 wr32(IGC_TSIM, tsim);
 298                 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
 299                 return 0;
 300
 301         case PTP_CLK_REQ_PEROUT:
 302                 /* Reject requests with unsupported flags */
 303                 if (rq->perout.flags)
 304                         return -EOPNOTSUPP;
 305
 306                 if (on) {
 307                         pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
 308                                            rq->perout.index);
 309                         if (pin < 0)
 310                                 return -EBUSY;
 311                 }
 312                 ts.tv_sec = rq->perout.period.sec;
 313                 ts.tv_nsec = rq->perout.period.nsec;
 314                 ns = timespec64_to_ns(&ts);
 315                 ns = ns >> 1;
 316                 if (on && (ns <= 70000000LL || ns == 125000000LL ||
 317                            ns == 250000000LL || ns == 500000000LL)) {
 318                         if (ns < 8LL)
 319                                 return -EINVAL;
 320                         use_freq = 1;
 321                 }
 322                 ts = ns_to_timespec64(ns);
 323                 if (rq->perout.index == 1) {
 324                         if (use_freq) {
 325                                 tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1;
 326                                 tsim_mask = 0;
 327                         } else {
 328                                 tsauxc_mask = IGC_TSAUXC_EN_TT1;
 329                                 tsim_mask = IGC_TSICR_TT1;
 330                         }
 331                         trgttiml = IGC_TRGTTIML1;
 332                         trgttimh = IGC_TRGTTIMH1;
 333                         freqout = IGC_FREQOUT1;
 334                 } else {
 335                         if (use_freq) {
 336                                 tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0;
 337                                 tsim_mask = 0;
 338                         } else {
 339                                 tsauxc_mask = IGC_TSAUXC_EN_TT0;
 340                                 tsim_mask = IGC_TSICR_TT0;
 341                         }
 342                         trgttiml = IGC_TRGTTIML0;
 343                         trgttimh = IGC_TRGTTIMH0;
 344                         freqout = IGC_FREQOUT0;
 345                 }
 346                 spin_lock_irqsave(&igc->tmreg_lock, flags);
 347                 tsauxc = rd32(IGC_TSAUXC);
 348                 tsim = rd32(IGC_TSIM);
 349                 if (rq->perout.index == 1) {
 350                         tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 |
 351                                     IGC_TSAUXC_ST1);
 352                         tsim &= ~IGC_TSICR_TT1;
 353                 } else {
 354                         tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 |
 355                                     IGC_TSAUXC_ST0);
 356                         tsim &= ~IGC_TSICR_TT0;
 357                 }
 358                 if (on) {
 359                         int i = rq->perout.index;
 360
 361                         igc_pin_perout(igc, i, pin, use_freq);
 362                         igc->perout[i].start.tv_sec = rq->perout.start.sec;
 363                         igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
 364                         igc->perout[i].period.tv_sec = ts.tv_sec;
 365                         igc->perout[i].period.tv_nsec = ts.tv_nsec;
 366                         wr32(trgttimh, rq->perout.start.sec);
 367                         /* For now, always select timer 0 as source. */
 368                         wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
 369                         if (use_freq)
 370                                 wr32(freqout, ns);
 371                         tsauxc |= tsauxc_mask;
 372                         tsim |= tsim_mask;
 373                 }
 374                 wr32(IGC_TSAUXC, tsauxc);
 375                 wr32(IGC_TSIM, tsim);
 376                 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
 377                 return 0;
 378
 379         case PTP_CLK_REQ_PPS:
 380                 spin_lock_irqsave(&igc->tmreg_lock, flags);
 381                 tsim = rd32(IGC_TSIM);
 382                 if (on)
 383                         tsim |= IGC_TSICR_SYS_WRAP;
 384                 else
 385                         tsim &= ~IGC_TSICR_SYS_WRAP;
 386                 igc->pps_sys_wrap_on = on;
 387                 wr32(IGC_TSIM, tsim);
 388                 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
 389                 return 0;
 390
 391         default:
 392                 break;
 393         }
 394
 395         return -EOPNOTSUPP;
 396 }
 397
 398 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
 399                               enum ptp_pin_function func, unsigned int chan)
 400 {
 401         switch (func) {
 402         case PTP_PF_NONE:
 403         case PTP_PF_EXTTS:
 404         case PTP_PF_PEROUT:
 405                 break;
 406         case PTP_PF_PHYSYNC:
 407                 return -1;
 408         }
 409         return 0;
 410 }
 411
 412 /**
 413  * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
 414  * @adapter: board private structure
 415  * @hwtstamps: timestamp structure to update
 416  * @systim: unsigned 64bit system time value
 417  *
 418  * We need to convert the system time value stored in the RX/TXSTMP registers
 419  * into a hwtstamp which can be used by the upper level timestamping functions.
 420  *
 421  * Returns 0 on success.
 422  **/
 423 static int igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
 424                                       struct skb_shared_hwtstamps *hwtstamps,
 425                                       u64 systim)
 426 {
 427         switch (adapter->hw.mac.type) {
 428         case igc_i225:
 429                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 430                 /* Upper 32 bits contain s, lower 32 bits contain ns. */
 431                 hwtstamps->hwtstamp = ktime_set(systim >> 32,
 432                                                 systim & 0xFFFFFFFF);
 433                 break;
 434         default:
 435                 return -EINVAL;
 436         }
 437         return 0;
 438 }
 439
 440 /**
 441  * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
 442  * @adapter: Pointer to adapter the packet buffer belongs to
 443  * @buf: Pointer to packet buffer
 444  *
 445  * This function retrieves the timestamp saved in the beginning of packet
 446  * buffer. While two timestamps are available, one in timer0 reference and the
 447  * other in timer1 reference, this function considers only the timestamp in
 448  * timer0 reference.
 449  *
 450  * Returns timestamp value.
 451  */
 452 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
 453 {
 454         ktime_t timestamp;
 455         u32 secs, nsecs;
 456         int adjust;
 457
 458         /* Timestamps are saved in little endian at the beginning of the packet
 459          * buffer following the layout:
 460          *
 461          * DWORD: | 0              | 1              | 2              | 3              |
 462          * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
 463          *
 464          * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
 465          * part of the timestamp.
 466          */
 467         nsecs = le32_to_cpu(buf[2]);
 468         secs = le32_to_cpu(buf[3]);
 469
 470         timestamp = ktime_set(secs, nsecs);
 471
 472         /* Adjust timestamp for the RX latency based on link speed */
 473         switch (adapter->link_speed) {
 474         case SPEED_10:
 475                 adjust = IGC_I225_RX_LATENCY_10;
 476                 break;
 477         case SPEED_100:
 478                 adjust = IGC_I225_RX_LATENCY_100;
 479                 break;
 480         case SPEED_1000:
 481                 adjust = IGC_I225_RX_LATENCY_1000;
 482                 break;
 483         case SPEED_2500:
 484                 adjust = IGC_I225_RX_LATENCY_2500;
 485                 break;
 486         default:
 487                 adjust = 0;
 488                 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
 489                 break;
 490         }
 491
 492         return ktime_sub_ns(timestamp, adjust);
 493 }
 494
 495 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
 496 {
 497         struct igc_hw *hw = &adapter->hw;
 498         u32 val;
 499         int i;
 500
 501         wr32(IGC_TSYNCRXCTL, 0);
 502
 503         for (i = 0; i < adapter->num_rx_queues; i++) {
 504                 val = rd32(IGC_SRRCTL(i));
 505                 val &= ~IGC_SRRCTL_TIMESTAMP;
 506                 wr32(IGC_SRRCTL(i), val);
 507         }
 508
 509         val = rd32(IGC_RXPBS);
 510         val &= ~IGC_RXPBS_CFG_TS_EN;
 511         wr32(IGC_RXPBS, val);
 512 }
 513
 514 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
 515 {
 516         struct igc_hw *hw = &adapter->hw;
 517         u32 val;
 518         int i;
 519
 520         val = rd32(IGC_RXPBS);
 521         val |= IGC_RXPBS_CFG_TS_EN;
 522         wr32(IGC_RXPBS, val);
 523
 524         for (i = 0; i < adapter->num_rx_queues; i++) {
 525                 val = rd32(IGC_SRRCTL(i));
 526                 /* FIXME: For now, only support retrieving RX timestamps from
 527                  * timer 0.
 528                  */
 529                 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
 530                        IGC_SRRCTL_TIMESTAMP;
 531                 wr32(IGC_SRRCTL(i), val);
 532         }
 533
 534         val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
 535               IGC_TSYNCRXCTL_RXSYNSIG;
 536         wr32(IGC_TSYNCRXCTL, val);
 537 }
 538
 539 static void igc_ptp_clear_tx_tstamp(struct igc_adapter *adapter)
 540 {
 541         unsigned long flags;
 542
 543         spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
 544
 545         dev_kfree_skb_any(adapter->ptp_tx_skb);
 546         adapter->ptp_tx_skb = NULL;
 547
 548         spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
 549 }
 550
 551 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
 552 {
 553         struct igc_hw *hw = &adapter->hw;
 554         int i;
 555
 556         /* Clear the flags first to avoid new packets to be enqueued
 557          * for TX timestamping.
 558          */
 559         for (i = 0; i < adapter->num_tx_queues; i++) {
 560                 struct igc_ring *tx_ring = adapter->tx_ring[i];
 561
 562                 clear_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags);
 563         }
 564
 565         /* Now we can clean the pending TX timestamp requests. */
 566         igc_ptp_clear_tx_tstamp(adapter);
 567
 568         wr32(IGC_TSYNCTXCTL, 0);
 569 }
 570
 571 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
 572 {
 573         struct igc_hw *hw = &adapter->hw;
 574         int i;
 575
 576         wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
 577
 578         /* Read TXSTMP registers to discard any timestamp previously stored. */
 579         rd32(IGC_TXSTMPL);
 580         rd32(IGC_TXSTMPH);
 581
 582         /* The hardware is ready to accept TX timestamp requests,
 583          * notify the transmit path.
 584          */
 585         for (i = 0; i < adapter->num_tx_queues; i++) {
 586                 struct igc_ring *tx_ring = adapter->tx_ring[i];
 587
 588                 set_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags);
 589         }
 590
 591 }
 592
 593 /**
 594  * igc_ptp_set_timestamp_mode - setup hardware for timestamping
 595  * @adapter: networking device structure
 596  * @config: hwtstamp configuration
 597  *
 598  * Return: 0 in case of success, negative errno code otherwise.
 599  */
 600 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
 601                                       struct hwtstamp_config *config)
 602 {
 603         switch (config->tx_type) {
 604         case HWTSTAMP_TX_OFF:
 605                 igc_ptp_disable_tx_timestamp(adapter);
 606                 break;
 607         case HWTSTAMP_TX_ON:
 608                 igc_ptp_enable_tx_timestamp(adapter);
 609                 break;
 610         default:
 611                 return -ERANGE;
 612         }
 613
 614         switch (config->rx_filter) {
 615         case HWTSTAMP_FILTER_NONE:
 616                 igc_ptp_disable_rx_timestamp(adapter);
 617                 break;
 618         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 619         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 620         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 621         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 622         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 623         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 624         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 625         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 626         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 627         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 628         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 629         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 630         case HWTSTAMP_FILTER_NTP_ALL:
 631         case HWTSTAMP_FILTER_ALL:
 632                 igc_ptp_enable_rx_timestamp(adapter);
 633                 config->rx_filter = HWTSTAMP_FILTER_ALL;
 634                 break;
 635         default:
 636                 return -ERANGE;
 637         }
 638
 639         return 0;
 640 }
 641
 642 /* Requires adapter->ptp_tx_lock held by caller. */
 643 static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
 644 {
 645         struct igc_hw *hw = &adapter->hw;
 646
 647         dev_kfree_skb_any(adapter->ptp_tx_skb);
 648         adapter->ptp_tx_skb = NULL;
 649         adapter->tx_hwtstamp_timeouts++;
 650         /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
 651         rd32(IGC_TXSTMPH);
 652         netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
 653 }
 654
 655 void igc_ptp_tx_hang(struct igc_adapter *adapter)
 656 {
 657         unsigned long flags;
 658
 659         spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
 660
 661         if (!adapter->ptp_tx_skb)
 662                 goto unlock;
 663
 664         if (time_is_after_jiffies(adapter->ptp_tx_start + IGC_PTP_TX_TIMEOUT))
 665                 goto unlock;
 666
 667         igc_ptp_tx_timeout(adapter);
 668
 669 unlock:
 670         spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
 671 }
 672
 673 /**
 674  * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 675  * @adapter: Board private structure
 676  *
 677  * If we were asked to do hardware stamping and such a time stamp is
 678  * available, then it must have been for this skb here because we only
 679  * allow only one such packet into the queue.
 680  *
 681  * Context: Expects adapter->ptp_tx_lock to be held by caller.
 682  */
 683 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
 684 {
 685         struct sk_buff *skb = adapter->ptp_tx_skb;
 686         struct skb_shared_hwtstamps shhwtstamps;
 687         struct igc_hw *hw = &adapter->hw;
 688         u32 tsynctxctl;
 689         int adjust = 0;
 690         u64 regval;
 691
 692         if (WARN_ON_ONCE(!skb))
 693                 return;
 694
 695         tsynctxctl = rd32(IGC_TSYNCTXCTL);
 696         tsynctxctl &= IGC_TSYNCTXCTL_TXTT_0;
 697         if (tsynctxctl) {
 698                 regval = rd32(IGC_TXSTMPL);
 699                 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
 700         } else {
 701                 /* There's a bug in the hardware that could cause
 702                  * missing interrupts for TX timestamping. The issue
 703                  * is that for new interrupts to be triggered, the
 704                  * IGC_TXSTMPH_0 register must be read.
 705                  *
 706                  * To avoid discarding a valid timestamp that just
 707                  * happened at the "wrong" time, we need to confirm
 708                  * that there was no timestamp captured, we do that by
 709                  * assuming that no two timestamps in sequence have
 710                  * the same nanosecond value.
 711                  *
 712                  * So, we read the "low" register, read the "high"
 713                  * register (to latch a new timestamp) and read the
 714                  * "low" register again, if "old" and "new" versions
 715                  * of the "low" register are different, a valid
 716                  * timestamp was captured, we can read the "high"
 717                  * register again.
 718                  */
 719                 u32 txstmpl_old, txstmpl_new;
 720
 721                 txstmpl_old = rd32(IGC_TXSTMPL);
 722                 rd32(IGC_TXSTMPH);
 723                 txstmpl_new = rd32(IGC_TXSTMPL);
 724
 725                 if (txstmpl_old == txstmpl_new)
 726                         return;
 727
 728                 regval = txstmpl_new;
 729                 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
 730         }
 731         if (igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval))
 732                 return;
 733
 734         switch (adapter->link_speed) {
 735         case SPEED_10:
 736                 adjust = IGC_I225_TX_LATENCY_10;
 737                 break;
 738         case SPEED_100:
 739                 adjust = IGC_I225_TX_LATENCY_100;
 740                 break;
 741         case SPEED_1000:
 742                 adjust = IGC_I225_TX_LATENCY_1000;
 743                 break;
 744         case SPEED_2500:
 745                 adjust = IGC_I225_TX_LATENCY_2500;
 746                 break;
 747         }
 748
 749         shhwtstamps.hwtstamp =
 750                 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
 751
 752         adapter->ptp_tx_skb = NULL;
 753
 754         /* Notify the stack and free the skb after we've unlocked */
 755         skb_tstamp_tx(skb, &shhwtstamps);
 756         dev_kfree_skb_any(skb);
 757 }
 758
 759 /**
 760  * igc_ptp_tx_tstamp_event
 761  * @adapter: board private structure
 762  *
 763  * Called when a TX timestamp interrupt happens to retrieve the
 764  * timestamp and send it up to the socket.
 765  */
 766 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter)
 767 {
 768         unsigned long flags;
 769
 770         spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
 771
 772         if (!adapter->ptp_tx_skb)
 773                 goto unlock;
 774
 775         igc_ptp_tx_hwtstamp(adapter);
 776
 777 unlock:
 778         spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
 779 }
 780
 781 /**
 782  * igc_ptp_set_ts_config - set hardware time stamping config
 783  * @netdev: network interface device structure
 784  * @ifr: interface request data
 785  *
 786  **/
 787 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
 788 {
 789         struct igc_adapter *adapter = netdev_priv(netdev);
 790         struct hwtstamp_config config;
 791         int err;
 792
 793         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 794                 return -EFAULT;
 795
 796         err = igc_ptp_set_timestamp_mode(adapter, &config);
 797         if (err)
 798                 return err;
 799
 800         /* save these settings for future reference */
 801         memcpy(&adapter->tstamp_config, &config,
 802                sizeof(adapter->tstamp_config));
 803
 804         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 805                 -EFAULT : 0;
 806 }
 807
 808 /**
 809  * igc_ptp_get_ts_config - get hardware time stamping config
 810  * @netdev: network interface device structure
 811  * @ifr: interface request data
 812  *
 813  * Get the hwtstamp_config settings to return to the user. Rather than attempt
 814  * to deconstruct the settings from the registers, just return a shadow copy
 815  * of the last known settings.
 816  **/
 817 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
 818 {
 819         struct igc_adapter *adapter = netdev_priv(netdev);
 820         struct hwtstamp_config *config = &adapter->tstamp_config;
 821
 822         return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
 823                 -EFAULT : 0;
 824 }
 825
 826 /* The two conditions below must be met for cross timestamping via
 827  * PCIe PTM:
 828  *
 829  * 1. We have an way to convert the timestamps in the PTM messages
 830  *    to something related to the system clocks (right now, only
 831  *    X86 systems with support for the Always Running Timer allow that);
 832  *
 833  * 2. We have PTM enabled in the path from the device to the PCIe root port.
 834  */
 835 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
 836 {
 837         if (!IS_ENABLED(CONFIG_X86_TSC))
 838                 return false;
 839
 840         /* FIXME: it was noticed that enabling support for PCIe PTM in
 841          * some i225-V models could cause lockups when bringing the
 842          * interface up/down. There should be no downsides to
 843          * disabling crosstimestamping support for i225-V, as it
 844          * doesn't have any PTP support. That way we gain some time
 845          * while root causing the issue.
 846          */
 847         if (adapter->pdev->device == IGC_DEV_ID_I225_V)
 848                 return false;
 849
 850         return pcie_ptm_enabled(adapter->pdev);
 851 }
 852
 853 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
 854 {
 855 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
 856         return convert_art_ns_to_tsc(tstamp);
 857 #else
 858         return (struct system_counterval_t) { };
 859 #endif
 860 }
 861
 862 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
 863 {
 864         struct net_device *netdev = adapter->netdev;
 865
 866         switch (ptm_stat) {
 867         case IGC_PTM_STAT_RET_ERR:
 868                 netdev_err(netdev, "PTM Error: Root port timeout\n");
 869                 break;
 870         case IGC_PTM_STAT_BAD_PTM_RES:
 871                 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
 872                 break;
 873         case IGC_PTM_STAT_T4M1_OVFL:
 874                 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
 875                 break;
 876         case IGC_PTM_STAT_ADJUST_1ST:
 877                 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
 878                 break;
 879         case IGC_PTM_STAT_ADJUST_CYC:
 880                 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
 881                 break;
 882         default:
 883                 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
 884                 break;
 885         }
 886 }
 887
 888 static int igc_phc_get_syncdevicetime(ktime_t *device,
 889                                       struct system_counterval_t *system,
 890                                       void *ctx)
 891 {
 892         u32 stat, t2_curr_h, t2_curr_l, ctrl;
 893         struct igc_adapter *adapter = ctx;
 894         struct igc_hw *hw = &adapter->hw;
 895         int err, count = 100;
 896         ktime_t t1, t2_curr;
 897
 898         /* Get a snapshot of system clocks to use as historic value. */
 899         ktime_get_snapshot(&adapter->snapshot);
 900
 901         do {
 902                 /* Doing this in a loop because in the event of a
 903                  * badly timed (ha!) system clock adjustment, we may
 904                  * get PTM errors from the PCI root, but these errors
 905                  * are transitory. Repeating the process returns valid
 906                  * data eventually.
 907                  */
 908
 909                 /* To "manually" start the PTM cycle we need to clear and
 910                  * then set again the TRIG bit.
 911                  */
 912                 ctrl = rd32(IGC_PTM_CTRL);
 913                 ctrl &= ~IGC_PTM_CTRL_TRIG;
 914                 wr32(IGC_PTM_CTRL, ctrl);
 915                 ctrl |= IGC_PTM_CTRL_TRIG;
 916                 wr32(IGC_PTM_CTRL, ctrl);
 917
 918                 /* The cycle only starts "for real" when software notifies
 919                  * that it has read the registers, this is done by setting
 920                  * VALID bit.
 921                  */
 922                 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
 923
 924                 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
 925                                          stat, IGC_PTM_STAT_SLEEP,
 926                                          IGC_PTM_STAT_TIMEOUT);
 927                 if (err < 0) {
 928                         netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
 929                         return err;
 930                 }
 931
 932                 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
 933                         break;
 934
 935                 if (stat & ~IGC_PTM_STAT_VALID) {
 936                         /* An error occurred, log it. */
 937                         igc_ptm_log_error(adapter, stat);
 938                         /* The STAT register is write-1-to-clear (W1C),
 939                          * so write the previous error status to clear it.
 940                          */
 941                         wr32(IGC_PTM_STAT, stat);
 942                         continue;
 943                 }
 944         } while (--count);
 945
 946         if (!count) {
 947                 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
 948                 return -ETIMEDOUT;
 949         }
 950
 951         t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
 952
 953         t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
 954         t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
 955
 956         /* FIXME: When the register that tells the endianness of the
 957          * PTM registers are implemented, check them here and add the
 958          * appropriate conversion.
 959          */
 960         t2_curr_h = swab32(t2_curr_h);
 961
 962         t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
 963
 964         *device = t1;
 965         *system = igc_device_tstamp_to_system(t2_curr);
 966
 967         return 0;
 968 }
 969
 970 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
 971                                   struct system_device_crosststamp *cts)
 972 {
 973         struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
 974                                                    ptp_caps);
 975
 976         return get_device_system_crosststamp(igc_phc_get_syncdevicetime,
 977                                              adapter, &adapter->snapshot, cts);
 978 }
 979
 980 /**
 981  * igc_ptp_init - Initialize PTP functionality
 982  * @adapter: Board private structure
 983  *
 984  * This function is called at device probe to initialize the PTP
 985  * functionality.
 986  */
 987 void igc_ptp_init(struct igc_adapter *adapter)
 988 {
 989         struct net_device *netdev = adapter->netdev;
 990         struct igc_hw *hw = &adapter->hw;
 991         int i;
 992
 993         switch (hw->mac.type) {
 994         case igc_i225:
 995                 for (i = 0; i < IGC_N_SDP; i++) {
 996                         struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
 997
 998                         snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
 999                         ppd->index = i;
1000                         ppd->func = PTP_PF_NONE;
1001                 }
1002                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1003                 adapter->ptp_caps.owner = THIS_MODULE;
1004                 adapter->ptp_caps.max_adj = 62499999;
1005                 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
1006                 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
1007                 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
1008                 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
1009                 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
1010                 adapter->ptp_caps.pps = 1;
1011                 adapter->ptp_caps.pin_config = adapter->sdp_config;
1012                 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
1013                 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
1014                 adapter->ptp_caps.n_pins = IGC_N_SDP;
1015                 adapter->ptp_caps.verify = igc_ptp_verify_pin;
1016
1017                 if (!igc_is_crosststamp_supported(adapter))
1018                         break;
1019
1020                 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
1021                 break;
1022         default:
1023                 adapter->ptp_clock = NULL;
1024                 return;
1025         }
1026
1027         spin_lock_init(&adapter->ptp_tx_lock);
1028         spin_lock_init(&adapter->tmreg_lock);
1029
1030         adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1031         adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1032
1033         adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
1034         adapter->ptp_reset_start = ktime_get();
1035
1036         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1037                                                 &adapter->pdev->dev);
1038         if (IS_ERR(adapter->ptp_clock)) {
1039                 adapter->ptp_clock = NULL;
1040                 netdev_err(netdev, "ptp_clock_register failed\n");
1041         } else if (adapter->ptp_clock) {
1042                 netdev_info(netdev, "PHC added\n");
1043                 adapter->ptp_flags |= IGC_PTP_ENABLED;
1044         }
1045 }
1046
1047 static void igc_ptp_time_save(struct igc_adapter *adapter)
1048 {
1049         igc_ptp_read(adapter, &adapter->prev_ptp_time);
1050         adapter->ptp_reset_start = ktime_get();
1051 }
1052
1053 static void igc_ptp_time_restore(struct igc_adapter *adapter)
1054 {
1055         struct timespec64 ts = adapter->prev_ptp_time;
1056         ktime_t delta;
1057
1058         delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
1059
1060         timespec64_add_ns(&ts, ktime_to_ns(delta));
1061
1062         igc_ptp_write_i225(adapter, &ts);
1063 }
1064
1065 static void igc_ptm_stop(struct igc_adapter *adapter)
1066 {
1067         struct igc_hw *hw = &adapter->hw;
1068         u32 ctrl;
1069
1070         ctrl = rd32(IGC_PTM_CTRL);
1071         ctrl &= ~IGC_PTM_CTRL_EN;
1072
1073         wr32(IGC_PTM_CTRL, ctrl);
1074 }
1075
1076 /**
1077  * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1078  * @adapter: Board private structure
1079  *
1080  * This function stops the overflow check work and PTP Tx timestamp work, and
1081  * will prepare the device for OS suspend.
1082  */
1083 void igc_ptp_suspend(struct igc_adapter *adapter)
1084 {
1085         if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1086                 return;
1087
1088         igc_ptp_clear_tx_tstamp(adapter);
1089
1090         if (pci_device_is_present(adapter->pdev)) {
1091                 igc_ptp_time_save(adapter);
1092                 igc_ptm_stop(adapter);
1093         }
1094 }
1095
1096 /**
1097  * igc_ptp_stop - Disable PTP device and stop the overflow check.
1098  * @adapter: Board private structure.
1099  *
1100  * This function stops the PTP support and cancels the delayed work.
1101  **/
1102 void igc_ptp_stop(struct igc_adapter *adapter)
1103 {
1104         igc_ptp_suspend(adapter);
1105
1106         if (adapter->ptp_clock) {
1107                 ptp_clock_unregister(adapter->ptp_clock);
1108                 netdev_info(adapter->netdev, "PHC removed\n");
1109                 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1110         }
1111 }
1112
1113 /**
1114  * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1115  * @adapter: Board private structure.
1116  *
1117  * This function handles the reset work required to re-enable the PTP device.
1118  **/
1119 void igc_ptp_reset(struct igc_adapter *adapter)
1120 {
1121         struct igc_hw *hw = &adapter->hw;
1122         u32 cycle_ctrl, ctrl;
1123         unsigned long flags;
1124         u32 timadj;
1125
1126         /* reset the tstamp_config */
1127         igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1128
1129         spin_lock_irqsave(&adapter->tmreg_lock, flags);
1130
1131         switch (adapter->hw.mac.type) {
1132         case igc_i225:
1133                 timadj = rd32(IGC_TIMADJ);
1134                 timadj |= IGC_TIMADJ_ADJUST_METH;
1135                 wr32(IGC_TIMADJ, timadj);
1136
1137                 wr32(IGC_TSAUXC, 0x0);
1138                 wr32(IGC_TSSDP, 0x0);
1139                 wr32(IGC_TSIM,
1140                      IGC_TSICR_INTERRUPTS |
1141                      (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1142                 wr32(IGC_IMS, IGC_IMS_TS);
1143
1144                 if (!igc_is_crosststamp_supported(adapter))
1145                         break;
1146
1147                 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1148                 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1149
1150                 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1151
1152                 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1153
1154                 ctrl = IGC_PTM_CTRL_EN |
1155                         IGC_PTM_CTRL_START_NOW |
1156                         IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1157                         IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1158                         IGC_PTM_CTRL_TRIG;
1159
1160                 wr32(IGC_PTM_CTRL, ctrl);
1161
1162                 /* Force the first cycle to run. */
1163                 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1164
1165                 break;
1166         default:
1167                 /* No work to do. */
1168                 goto out;
1169         }
1170
1171         /* Re-initialize the timer. */
1172         if (hw->mac.type == igc_i225) {
1173                 igc_ptp_time_restore(adapter);
1174         } else {
1175                 timecounter_init(&adapter->tc, &adapter->cc,
1176                                  ktime_to_ns(ktime_get_real()));
1177         }
1178 out:
1179         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1180
1181         wrfl();
1182 }