drivers/pwm/pwm-stm32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  *
   5  * Author: Gerald Baeza <[email protected]>
   6  *
   7  * Inspired by timer-stm32.c from Maxime Coquelin
   8  *             pwm-atmel.c from Bo Shen
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/mfd/stm32-timers.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/pinctrl/consumer.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pwm.h>
  18
  19 #define CCMR_CHANNEL_SHIFT 8
  20 #define CCMR_CHANNEL_MASK  0xFF
  21 #define MAX_BREAKINPUT 2
  22
  23 struct stm32_breakinput {
  24         u32 index;
  25         u32 level;
  26         u32 filter;
  27 };
  28
  29 struct stm32_pwm {
  30         struct mutex lock; /* protect pwm config/enable */
  31         struct clk *clk;
  32         struct regmap *regmap;
  33         u32 max_arr;
  34         bool have_complementary_output;
  35         struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
  36         unsigned int num_breakinputs;
  37         u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
  38 };
  39
  40 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
  41 {
  42         return pwmchip_get_drvdata(chip);
  43 }
  44
  45 static u32 active_channels(struct stm32_pwm *dev)
  46 {
  47         u32 ccer;
  48
  49         regmap_read(dev->regmap, TIM_CCER, &ccer);
  50
  51         return ccer & TIM_CCER_CCXE;
  52 }
  53
  54 struct stm32_pwm_waveform {
  55         u32 ccer;
  56         u32 psc;
  57         u32 arr;
  58         u32 ccr;
  59 };
  60
  61 static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip,
  62                                          struct pwm_device *pwm,
  63                                          const struct pwm_waveform *wf,
  64                                          void *_wfhw)
  65 {
  66         struct stm32_pwm_waveform *wfhw = _wfhw;
  67         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
  68         unsigned int ch = pwm->hwpwm;
  69         unsigned long rate;
  70         u64 ccr, duty;
  71         int ret;
  72
  73         if (wf->period_length_ns == 0) {
  74                 *wfhw = (struct stm32_pwm_waveform){
  75                         .ccer = 0,
  76                 };
  77
  78                 return 0;
  79         }
  80
  81         ret = clk_enable(priv->clk);
  82         if (ret)
  83                 return ret;
  84
  85         wfhw->ccer = TIM_CCER_CCxE(ch + 1);
  86         if (priv->have_complementary_output)
  87                 wfhw->ccer = TIM_CCER_CCxNE(ch + 1);
  88
  89         rate = clk_get_rate(priv->clk);
  90
  91         if (active_channels(priv) & ~(1 << ch * 4)) {
  92                 u64 arr;
  93
  94                 /*
  95                  * Other channels are already enabled, so the configured PSC and
  96                  * ARR must be used for this channel, too.
  97                  */
  98                 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
  99                 if (ret)
 100                         goto out;
 101
 102                 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
 103                 if (ret)
 104                         goto out;
 105
 106                 /*
 107                  * calculate the best value for ARR for the given PSC, refuse if
 108                  * the resulting period gets bigger than the requested one.
 109                  */
 110                 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
 111                                           (u64)NSEC_PER_SEC * (wfhw->psc + 1));
 112                 if (arr <= wfhw->arr) {
 113                         /*
 114                          * requested period is small than the currently
 115                          * configured and unchangable period, report back the smallest
 116                          * possible period, i.e. the current state; Initialize
 117                          * ccr to anything valid.
 118                          */
 119                         wfhw->ccr = 0;
 120                         ret = 1;
 121                         goto out;
 122                 }
 123
 124         } else {
 125                 /*
 126                  * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
 127                  * the calculations here won't overflow.
 128                  * First we need to find the minimal value for prescaler such that
 129                  *
 130                  *        period_ns * clkrate
 131                  *   ------------------------------ < max_arr + 1
 132                  *   NSEC_PER_SEC * (prescaler + 1)
 133                  *
 134                  * This equation is equivalent to
 135                  *
 136                  *        period_ns * clkrate
 137                  *   ---------------------------- < prescaler + 1
 138                  *   NSEC_PER_SEC * (max_arr + 1)
 139                  *
 140                  * Using integer division and knowing that the right hand side is
 141                  * integer, this is further equivalent to
 142                  *
 143                  *   (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
 144                  */
 145                 u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate,
 146                                               (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
 147                 u64 arr;
 148
 149                 wfhw->psc = min_t(u64, psc, MAX_TIM_PSC);
 150
 151                 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,
 152                                           (u64)NSEC_PER_SEC * (wfhw->psc + 1));
 153                 if (!arr) {
 154                         /*
 155                          * requested period is too small, report back the smallest
 156                          * possible period, i.e. ARR = 0. The only valid CCR
 157                          * value is then zero, too.
 158                          */
 159                         wfhw->arr = 0;
 160                         wfhw->ccr = 0;
 161                         ret = 1;
 162                         goto out;
 163                 }
 164
 165                 /*
 166                  * ARR is limited intentionally to values less than
 167                  * priv->max_arr to allow 100% duty cycle.
 168                  */
 169                 wfhw->arr = min_t(u64, arr, priv->max_arr) - 1;
 170         }
 171
 172         duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate,
 173                                    (u64)NSEC_PER_SEC * (wfhw->psc + 1));
 174         duty = min_t(u64, duty, wfhw->arr + 1);
 175
 176         if (wf->duty_length_ns && wf->duty_offset_ns &&
 177             wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) {
 178                 wfhw->ccer |= TIM_CCER_CCxP(ch + 1);
 179                 if (priv->have_complementary_output)
 180                         wfhw->ccer |= TIM_CCER_CCxNP(ch + 1);
 181
 182                 ccr = wfhw->arr + 1 - duty;
 183         } else {
 184                 ccr = duty;
 185         }
 186
 187         wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1);
 188
 189         dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n",
 190                 pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
 191                 rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr);
 192
 193 out:
 194         clk_disable(priv->clk);
 195
 196         return ret;
 197 }
 198
 199 /*
 200  * This should be moved to lib/math/div64.c. Currently there are some changes
 201  * pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles.
 202  */
 203 static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c)
 204 {
 205         u64 res = mul_u64_u64_div_u64(a, b, c);
 206         /* Those multiplications might overflow but it doesn't matter */
 207         u64 rem = a * b - c * res;
 208
 209         if (rem)
 210                 res += 1;
 211
 212         return res;
 213 }
 214
 215 static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,
 216                                            struct pwm_device *pwm,
 217                                            const void *_wfhw,
 218                                            struct pwm_waveform *wf)
 219 {
 220         const struct stm32_pwm_waveform *wfhw = _wfhw;
 221         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 222         unsigned int ch = pwm->hwpwm;
 223
 224         if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
 225                 unsigned long rate = clk_get_rate(priv->clk);
 226                 u64 ccr_ns;
 227
 228                 /* The result doesn't overflow for rate >= 15259 */
 229                 wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),
 230                                                                              NSEC_PER_SEC, rate);
 231
 232                 ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr,
 233                                                                NSEC_PER_SEC, rate);
 234
 235                 if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) {
 236                         wf->duty_length_ns =
 237                                 stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),
 238                                                                       NSEC_PER_SEC, rate);
 239
 240                         wf->duty_offset_ns = ccr_ns;
 241                 } else {
 242                         wf->duty_length_ns = ccr_ns;
 243                         wf->duty_offset_ns = 0;
 244                 }
 245
 246                 dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n",
 247                         pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate,
 248                         wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);
 249
 250         } else {
 251                 *wf = (struct pwm_waveform){
 252                         .period_length_ns = 0,
 253                 };
 254         }
 255
 256         return 0;
 257 }
 258
 259 static int stm32_pwm_read_waveform(struct pwm_chip *chip,
 260                                      struct pwm_device *pwm,
 261                                      void *_wfhw)
 262 {
 263         struct stm32_pwm_waveform *wfhw = _wfhw;
 264         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 265         unsigned int ch = pwm->hwpwm;
 266         int ret;
 267
 268         ret = clk_enable(priv->clk);
 269         if (ret)
 270                 return ret;
 271
 272         ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer);
 273         if (ret)
 274                 goto out;
 275
 276         if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
 277                 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);
 278                 if (ret)
 279                         goto out;
 280
 281                 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);
 282                 if (ret)
 283                         goto out;
 284
 285                 if (wfhw->arr == U32_MAX)
 286                         wfhw->arr -= 1;
 287
 288                 ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr);
 289                 if (ret)
 290                         goto out;
 291
 292                 if (wfhw->ccr > wfhw->arr + 1)
 293                         wfhw->ccr = wfhw->arr + 1;
 294         }
 295
 296 out:
 297         clk_disable(priv->clk);
 298
 299         return ret;
 300 }
 301
 302 static int stm32_pwm_write_waveform(struct pwm_chip *chip,
 303                                       struct pwm_device *pwm,
 304                                       const void *_wfhw)
 305 {
 306         const struct stm32_pwm_waveform *wfhw = _wfhw;
 307         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 308         unsigned int ch = pwm->hwpwm;
 309         int ret;
 310
 311         ret = clk_enable(priv->clk);
 312         if (ret)
 313                 return ret;
 314
 315         if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {
 316                 u32 ccer, mask;
 317                 unsigned int shift;
 318                 u32 ccmr;
 319
 320                 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
 321                 if (ret)
 322                         goto out;
 323
 324                 /* If there are other channels enabled, don't update PSC and ARR */
 325                 if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) {
 326                         u32 psc, arr;
 327
 328                         ret = regmap_read(priv->regmap, TIM_PSC, &psc);
 329                         if (ret)
 330                                 goto out;
 331
 332                         if (psc != wfhw->psc) {
 333                                 ret = -EBUSY;
 334                                 goto out;
 335                         }
 336
 337                         ret = regmap_read(priv->regmap, TIM_ARR, &arr);
 338                         if (ret)
 339                                 goto out;
 340
 341                         if (arr != wfhw->arr) {
 342                                 ret = -EBUSY;
 343                                 goto out;
 344                         }
 345                 } else {
 346                         ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc);
 347                         if (ret)
 348                                 goto out;
 349
 350                         ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr);
 351                         if (ret)
 352                                 goto out;
 353
 354                         ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
 355                         if (ret)
 356                                 goto out;
 357
 358                 }
 359
 360                 /* set polarity */
 361                 mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1);
 362                 ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer);
 363                 if (ret)
 364                         goto out;
 365
 366                 ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr);
 367                 if (ret)
 368                         goto out;
 369
 370                 /* Configure output mode */
 371                 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
 372                 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
 373                 mask = CCMR_CHANNEL_MASK << shift;
 374
 375                 if (ch < 2)
 376                         ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
 377                 else
 378                         ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
 379                 if (ret)
 380                         goto out;
 381
 382                 ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
 383                 if (ret)
 384                         goto out;
 385
 386                 if (!(ccer & TIM_CCER_CCxE(ch + 1))) {
 387                         mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1);
 388
 389                         ret = clk_enable(priv->clk);
 390                         if (ret)
 391                                 goto out;
 392
 393                         ccer = (ccer & ~mask) | (wfhw->ccer & mask);
 394                         regmap_write(priv->regmap, TIM_CCER, ccer);
 395
 396                         /* Make sure that registers are updated */
 397                         regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
 398
 399                         /* Enable controller */
 400                         regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 401                 }
 402
 403         } else {
 404                 /* disable channel */
 405                 u32 mask, ccer;
 406
 407                 mask = TIM_CCER_CCxE(ch + 1);
 408                 if (priv->have_complementary_output)
 409                         mask |= TIM_CCER_CCxNE(ch + 1);
 410
 411                 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
 412                 if (ret)
 413                         goto out;
 414
 415                 if (ccer & mask) {
 416                         ccer = ccer & ~mask;
 417
 418                         ret = regmap_write(priv->regmap, TIM_CCER, ccer);
 419                         if (ret)
 420                                 goto out;
 421
 422                         if (!(ccer & TIM_CCER_CCXE)) {
 423                                 /* When all channels are disabled, we can disable the controller */
 424                                 ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 425                                 if (ret)
 426                                         goto out;
 427                         }
 428
 429                         clk_disable(priv->clk);
 430                 }
 431         }
 432
 433 out:
 434         clk_disable(priv->clk);
 435
 436         return ret;
 437 }
 438
 439 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
 440 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
 441 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
 442 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
 443
 444 /*
 445  * Capture using PWM input mode:
 446  *                              ___          ___
 447  * TI[1, 2, 3 or 4]: ........._|   |________|
 448  *                             ^0  ^1       ^2
 449  *                              .   .        .
 450  *                              .   .        XXXXX
 451  *                              .   .   XXXXX     |
 452  *                              .  XXXXX     .    |
 453  *                            XXXXX .        .    |
 454  * COUNTER:        ______XXXXX  .   .        .    |_XXX
 455  *                 start^       .   .        .        ^stop
 456  *                      .       .   .        .
 457  *                      v       v   .        v
 458  *                                  v
 459  * CCR1/CCR3:       tx..........t0...........t2
 460  * CCR2/CCR4:       tx..............t1.........
 461  *
 462  * DMA burst transfer:          |            |
 463  *                              v            v
 464  * DMA buffer:                  { t0, tx }   { t2, t1 }
 465  * DMA done:                                 ^
 466  *
 467  * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
 468  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
 469  * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
 470  * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
 471  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
 472  *
 473  * DMA done, compute:
 474  * - Period     = t2 - t0
 475  * - Duty cycle = t1 - t0
 476  */
 477 static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm,
 478                                  unsigned long tmo_ms, u32 *raw_prd,
 479                                  u32 *raw_dty)
 480 {
 481         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 482         struct device *parent = pwmchip_parent(chip)->parent;
 483         enum stm32_timers_dmas dma_id;
 484         u32 ccen, ccr;
 485         int ret;
 486
 487         /* Ensure registers have been updated, enable counter and capture */
 488         regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
 489         regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 490
 491         /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
 492         dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
 493         ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
 494         ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
 495         regmap_set_bits(priv->regmap, TIM_CCER, ccen);
 496
 497         /*
 498          * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
 499          * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
 500          * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
 501          * or { CCR3, CCR4 }, { CCR3, CCR4 }
 502          */
 503         ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
 504                                           2, tmo_ms);
 505         if (ret)
 506                 goto stop;
 507
 508         /* Period: t2 - t0 (take care of counter overflow) */
 509         if (priv->capture[0] <= priv->capture[2])
 510                 *raw_prd = priv->capture[2] - priv->capture[0];
 511         else
 512                 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
 513
 514         /* Duty cycle capture requires at least two capture units */
 515         if (pwm->chip->npwm < 2)
 516                 *raw_dty = 0;
 517         else if (priv->capture[0] <= priv->capture[3])
 518                 *raw_dty = priv->capture[3] - priv->capture[0];
 519         else
 520                 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
 521
 522         if (*raw_dty > *raw_prd) {
 523                 /*
 524                  * Race beetween PWM input and DMA: it may happen
 525                  * falling edge triggers new capture on TI2/4 before DMA
 526                  * had a chance to read CCR2/4. It means capture[1]
 527                  * contains period + duty_cycle. So, subtract period.
 528                  */
 529                 *raw_dty -= *raw_prd;
 530         }
 531
 532 stop:
 533         regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
 534         regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 535
 536         return ret;
 537 }
 538
 539 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
 540                              struct pwm_capture *result, unsigned long tmo_ms)
 541 {
 542         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 543         unsigned long long prd, div, dty;
 544         unsigned long rate;
 545         unsigned int psc = 0, icpsc, scale;
 546         u32 raw_prd = 0, raw_dty = 0;
 547         int ret = 0;
 548
 549         mutex_lock(&priv->lock);
 550
 551         if (active_channels(priv)) {
 552                 ret = -EBUSY;
 553                 goto unlock;
 554         }
 555
 556         ret = clk_enable(priv->clk);
 557         if (ret) {
 558                 dev_err(pwmchip_parent(chip), "failed to enable counter clock\n");
 559                 goto unlock;
 560         }
 561
 562         rate = clk_get_rate(priv->clk);
 563         if (!rate) {
 564                 ret = -EINVAL;
 565                 goto clk_dis;
 566         }
 567
 568         /* prescaler: fit timeout window provided by upper layer */
 569         div = (unsigned long long)rate * (unsigned long long)tmo_ms;
 570         do_div(div, MSEC_PER_SEC);
 571         prd = div;
 572         while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
 573                 psc++;
 574                 div = prd;
 575                 do_div(div, psc + 1);
 576         }
 577         regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
 578         regmap_write(priv->regmap, TIM_PSC, psc);
 579
 580         /* Reset input selector to its default input and disable slave mode */
 581         regmap_write(priv->regmap, TIM_TISEL, 0x0);
 582         regmap_write(priv->regmap, TIM_SMCR, 0x0);
 583
 584         /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
 585         regmap_update_bits(priv->regmap,
 586                            pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
 587                            TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
 588                            TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
 589                            TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
 590
 591         /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
 592         regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
 593                            TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
 594                            TIM_CCER_CC2P : TIM_CCER_CC4P);
 595
 596         ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
 597         if (ret)
 598                 goto stop;
 599
 600         /*
 601          * Got a capture. Try to improve accuracy at high rates:
 602          * - decrease counter clock prescaler, scale up to max rate.
 603          * - use input prescaler, capture once every /2 /4 or /8 edges.
 604          */
 605         if (raw_prd) {
 606                 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
 607
 608                 scale = max_arr / min(max_arr, raw_prd);
 609         } else {
 610                 scale = priv->max_arr; /* below resolution, use max scale */
 611         }
 612
 613         if (psc && scale > 1) {
 614                 /* 2nd measure with new scale */
 615                 psc /= scale;
 616                 regmap_write(priv->regmap, TIM_PSC, psc);
 617                 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd,
 618                                             &raw_dty);
 619                 if (ret)
 620                         goto stop;
 621         }
 622
 623         /* Compute intermediate period not to exceed timeout at low rates */
 624         prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
 625         do_div(prd, rate);
 626
 627         for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
 628                 /* input prescaler: also keep arbitrary margin */
 629                 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
 630                         break;
 631                 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
 632                         break;
 633         }
 634
 635         if (!icpsc)
 636                 goto done;
 637
 638         /* Last chance to improve period accuracy, using input prescaler */
 639         regmap_update_bits(priv->regmap,
 640                            pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
 641                            TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
 642                            FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
 643                            FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
 644
 645         ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
 646         if (ret)
 647                 goto stop;
 648
 649         if (raw_dty >= (raw_prd >> icpsc)) {
 650                 /*
 651                  * We may fall here using input prescaler, when input
 652                  * capture starts on high side (before falling edge).
 653                  * Example with icpsc to capture on each 4 events:
 654                  *
 655                  *       start   1st capture                     2nd capture
 656                  *         v     v                               v
 657                  *         ___   _____   _____   _____   _____   ____
 658                  * TI1..4     |__|    |__|    |__|    |__|    |__|
 659                  *            v  v    .  .    .  .    .       v  v
 660                  * icpsc1/3:  .  0    .  1    .  2    .  3    .  0
 661                  * icpsc2/4:  0       1       2       3       0
 662                  *            v  v                            v  v
 663                  * CCR1/3  ......t0..............................t2
 664                  * CCR2/4  ..t1..............................t1'...
 665                  *               .                            .  .
 666                  * Capture0:     .<----------------------------->.
 667                  * Capture1:     .<-------------------------->.  .
 668                  *               .                            .  .
 669                  * Period:       .<------>                    .  .
 670                  * Low side:                                  .<>.
 671                  *
 672                  * Result:
 673                  * - Period = Capture0 / icpsc
 674                  * - Duty = Period - Low side = Period - (Capture0 - Capture1)
 675                  */
 676                 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
 677         }
 678
 679 done:
 680         prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
 681         result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
 682         dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
 683         result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
 684 stop:
 685         regmap_write(priv->regmap, TIM_CCER, 0);
 686         regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
 687         regmap_write(priv->regmap, TIM_PSC, 0);
 688 clk_dis:
 689         clk_disable(priv->clk);
 690 unlock:
 691         mutex_unlock(&priv->lock);
 692
 693         return ret;
 694 }
 695
 696 static const struct pwm_ops stm32pwm_ops = {
 697         .sizeof_wfhw = sizeof(struct stm32_pwm_waveform),
 698         .round_waveform_tohw = stm32_pwm_round_waveform_tohw,
 699         .round_waveform_fromhw = stm32_pwm_round_waveform_fromhw,
 700         .read_waveform = stm32_pwm_read_waveform,
 701         .write_waveform = stm32_pwm_write_waveform,
 702
 703         .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
 704 };
 705
 706 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
 707                                     const struct stm32_breakinput *bi)
 708 {
 709         u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
 710         u32 bke = TIM_BDTR_BKE(bi->index);
 711         u32 bkp = TIM_BDTR_BKP(bi->index);
 712         u32 bkf = TIM_BDTR_BKF(bi->index);
 713         u32 mask = bkf | bkp | bke;
 714         u32 bdtr;
 715
 716         bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
 717
 718         if (bi->level)
 719                 bdtr |= bkp;
 720
 721         regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
 722
 723         regmap_read(priv->regmap, TIM_BDTR, &bdtr);
 724
 725         return (bdtr & bke) ? 0 : -EINVAL;
 726 }
 727
 728 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
 729 {
 730         unsigned int i;
 731         int ret;
 732
 733         for (i = 0; i < priv->num_breakinputs; i++) {
 734                 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
 735                 if (ret < 0)
 736                         return ret;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
 743                                        struct device_node *np)
 744 {
 745         int nb, ret, array_size;
 746         unsigned int i;
 747
 748         nb = of_property_count_elems_of_size(np, "st,breakinput",
 749                                              sizeof(struct stm32_breakinput));
 750
 751         /*
 752          * Because "st,breakinput" parameter is optional do not make probe
 753          * failed if it doesn't exist.
 754          */
 755         if (nb <= 0)
 756                 return 0;
 757
 758         if (nb > MAX_BREAKINPUT)
 759                 return -EINVAL;
 760
 761         priv->num_breakinputs = nb;
 762         array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
 763         ret = of_property_read_u32_array(np, "st,breakinput",
 764                                          (u32 *)priv->breakinputs, array_size);
 765         if (ret)
 766                 return ret;
 767
 768         for (i = 0; i < priv->num_breakinputs; i++) {
 769                 if (priv->breakinputs[i].index > 1 ||
 770                     priv->breakinputs[i].level > 1 ||
 771                     priv->breakinputs[i].filter > 15)
 772                         return -EINVAL;
 773         }
 774
 775         return stm32_pwm_apply_breakinputs(priv);
 776 }
 777
 778 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
 779 {
 780         u32 ccer;
 781
 782         /*
 783          * If complementary bit doesn't exist writing 1 will have no
 784          * effect so we can detect it.
 785          */
 786         regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
 787         regmap_read(priv->regmap, TIM_CCER, &ccer);
 788         regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
 789
 790         priv->have_complementary_output = (ccer != 0);
 791 }
 792
 793 static unsigned int stm32_pwm_detect_channels(struct regmap *regmap,
 794                                               unsigned int *num_enabled)
 795 {
 796         u32 ccer, ccer_backup;
 797
 798         /*
 799          * If channels enable bits don't exist writing 1 will have no
 800          * effect so we can detect and count them.
 801          */
 802         regmap_read(regmap, TIM_CCER, &ccer_backup);
 803         regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);
 804         regmap_read(regmap, TIM_CCER, &ccer);
 805         regmap_write(regmap, TIM_CCER, ccer_backup);
 806
 807         *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
 808
 809         return hweight32(ccer & TIM_CCER_CCXE);
 810 }
 811
 812 static int stm32_pwm_probe(struct platform_device *pdev)
 813 {
 814         struct device *dev = &pdev->dev;
 815         struct device_node *np = dev->of_node;
 816         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 817         struct pwm_chip *chip;
 818         struct stm32_pwm *priv;
 819         unsigned int npwm, num_enabled;
 820         unsigned int i;
 821         int ret;
 822
 823         npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled);
 824
 825         chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv));
 826         if (IS_ERR(chip))
 827                 return PTR_ERR(chip);
 828         priv = to_stm32_pwm_dev(chip);
 829
 830         mutex_init(&priv->lock);
 831         priv->regmap = ddata->regmap;
 832         priv->clk = ddata->clk;
 833         priv->max_arr = ddata->max_arr;
 834
 835         if (!priv->regmap || !priv->clk)
 836                 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n",
 837                                      priv->regmap ? "clk" : "regmap");
 838
 839         ret = stm32_pwm_probe_breakinputs(priv, np);
 840         if (ret)
 841                 return dev_err_probe(dev, ret,
 842                                      "Failed to configure breakinputs\n");
 843
 844         stm32_pwm_detect_complementary(priv);
 845
 846         ret = devm_clk_rate_exclusive_get(dev, priv->clk);
 847         if (ret)
 848                 return dev_err_probe(dev, ret, "Failed to lock clock\n");
 849
 850         /*
 851          * With the clk running with not more than 1 GHz the calculations in
 852          * .apply() won't overflow.
 853          */
 854         if (clk_get_rate(priv->clk) > 1000000000)
 855                 return dev_err_probe(dev, -EINVAL, "Clock freq too high (%lu)\n",
 856                                      clk_get_rate(priv->clk));
 857
 858         chip->ops = &stm32pwm_ops;
 859
 860         /* Initialize clock refcount to number of enabled PWM channels. */
 861         for (i = 0; i < num_enabled; i++)
 862                 clk_enable(priv->clk);
 863
 864         ret = devm_pwmchip_add(dev, chip);
 865         if (ret < 0)
 866                 return dev_err_probe(dev, ret,
 867                                      "Failed to register pwmchip\n");
 868
 869         platform_set_drvdata(pdev, chip);
 870
 871         return 0;
 872 }
 873
 874 static int stm32_pwm_suspend(struct device *dev)
 875 {
 876         struct pwm_chip *chip = dev_get_drvdata(dev);
 877         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 878         unsigned int i;
 879         u32 ccer, mask;
 880
 881         /* Look for active channels */
 882         ccer = active_channels(priv);
 883
 884         for (i = 0; i < chip->npwm; i++) {
 885                 mask = TIM_CCER_CCxE(i + 1);
 886                 if (ccer & mask) {
 887                         dev_err(dev, "PWM %u still in use by consumer %s\n",
 888                                 i, chip->pwms[i].label);
 889                         return -EBUSY;
 890                 }
 891         }
 892
 893         return pinctrl_pm_select_sleep_state(dev);
 894 }
 895
 896 static int stm32_pwm_resume(struct device *dev)
 897 {
 898         struct pwm_chip *chip = dev_get_drvdata(dev);
 899         struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
 900         int ret;
 901
 902         ret = pinctrl_pm_select_default_state(dev);
 903         if (ret)
 904                 return ret;
 905
 906         /* restore breakinput registers that may have been lost in low power */
 907         return stm32_pwm_apply_breakinputs(priv);
 908 }
 909
 910 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
 911
 912 static const struct of_device_id stm32_pwm_of_match[] = {
 913         { .compatible = "st,stm32-pwm", },
 914         { /* end node */ },
 915 };
 916 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
 917
 918 static struct platform_driver stm32_pwm_driver = {
 919         .probe  = stm32_pwm_probe,
 920         .driver = {
 921                 .name = "stm32-pwm",
 922                 .of_match_table = stm32_pwm_of_match,
 923                 .pm = pm_ptr(&stm32_pwm_pm_ops),
 924         },
 925 };
 926 module_platform_driver(stm32_pwm_driver);
 927
 928 MODULE_ALIAS("platform:stm32-pwm");
 929 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
 930 MODULE_LICENSE("GPL v2");