drivers/pwm/pwm-meson.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * PWM controller driver for Amlogic Meson SoCs.
   4  *
   5  * This PWM is only a set of Gates, Dividers and Counters:
   6  * PWM output is achieved by calculating a clock that permits calculating
   7  * two periods (low and high). The counter then has to be set to switch after
   8  * N cycles for the first half period.
   9  * The hardware has no "polarity" setting. This driver reverses the period
  10  * cycles (the low length is inverted with the high length) for
  11  * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
  12  * from the hardware.
  13  * Setting the duty cycle will disable and re-enable the PWM output.
  14  * Disabling the PWM stops the output immediately (without waiting for the
  15  * current period to complete first).
  16  *
  17  * The public S912 (GXM) datasheet contains some documentation for this PWM
  18  * controller starting on page 543:
  19  * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
  20  * An updated version of this IP block is found in S922X (G12B) SoCs. The
  21  * datasheet contains the description for this IP block revision starting at
  22  * page 1084:
  23  * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
  24  *
  25  * Copyright (c) 2016 BayLibre, SAS.
  26  * Author: Neil Armstrong <[email protected]>
  27  * Copyright (C) 2014 Amlogic, Inc.
  28  */
  29
  30 #include <linux/bitfield.h>
  31 #include <linux/bits.h>
  32 #include <linux/clk.h>
  33 #include <linux/clk-provider.h>
  34 #include <linux/err.h>
  35 #include <linux/io.h>
  36 #include <linux/kernel.h>
  37 #include <linux/math64.h>
  38 #include <linux/module.h>
  39 #include <linux/of.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/pwm.h>
  42 #include <linux/slab.h>
  43 #include <linux/spinlock.h>
  44
  45 #define REG_PWM_A               0x0
  46 #define REG_PWM_B               0x4
  47 #define PWM_LOW_MASK            GENMASK(15, 0)
  48 #define PWM_HIGH_MASK           GENMASK(31, 16)
  49
  50 #define REG_MISC_AB             0x8
  51 #define MISC_B_CLK_EN_SHIFT     23
  52 #define MISC_A_CLK_EN_SHIFT     15
  53 #define MISC_CLK_DIV_WIDTH      7
  54 #define MISC_B_CLK_DIV_SHIFT    16
  55 #define MISC_A_CLK_DIV_SHIFT    8
  56 #define MISC_B_CLK_SEL_SHIFT    6
  57 #define MISC_A_CLK_SEL_SHIFT    4
  58 #define MISC_CLK_SEL_MASK       0x3
  59 #define MISC_B_EN               BIT(1)
  60 #define MISC_A_EN               BIT(0)
  61
  62 #define MESON_NUM_PWMS          2
  63 #define MESON_NUM_MUX_PARENTS   4
  64
  65 static struct meson_pwm_channel_data {
  66         u8              reg_offset;
  67         u8              clk_sel_shift;
  68         u8              clk_div_shift;
  69         u8              clk_en_shift;
  70         u32             pwm_en_mask;
  71 } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
  72         {
  73                 .reg_offset     = REG_PWM_A,
  74                 .clk_sel_shift  = MISC_A_CLK_SEL_SHIFT,
  75                 .clk_div_shift  = MISC_A_CLK_DIV_SHIFT,
  76                 .clk_en_shift   = MISC_A_CLK_EN_SHIFT,
  77                 .pwm_en_mask    = MISC_A_EN,
  78         },
  79         {
  80                 .reg_offset     = REG_PWM_B,
  81                 .clk_sel_shift  = MISC_B_CLK_SEL_SHIFT,
  82                 .clk_div_shift  = MISC_B_CLK_DIV_SHIFT,
  83                 .clk_en_shift   = MISC_B_CLK_EN_SHIFT,
  84                 .pwm_en_mask    = MISC_B_EN,
  85         }
  86 };
  87
  88 struct meson_pwm_channel {
  89         unsigned long rate;
  90         unsigned int hi;
  91         unsigned int lo;
  92
  93         struct clk_mux mux;
  94         struct clk_divider div;
  95         struct clk_gate gate;
  96         struct clk *clk;
  97 };
  98
  99 struct meson_pwm_data {
 100         const char *const parent_names[MESON_NUM_MUX_PARENTS];
 101         int (*channels_init)(struct pwm_chip *chip);
 102 };
 103
 104 struct meson_pwm {
 105         const struct meson_pwm_data *data;
 106         struct meson_pwm_channel channels[MESON_NUM_PWMS];
 107         void __iomem *base;
 108         /*
 109          * Protects register (write) access to the REG_MISC_AB register
 110          * that is shared between the two PWMs.
 111          */
 112         spinlock_t lock;
 113 };
 114
 115 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
 116 {
 117         return pwmchip_get_drvdata(chip);
 118 }
 119
 120 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 121 {
 122         struct meson_pwm *meson = to_meson_pwm(chip);
 123         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 124         struct device *dev = pwmchip_parent(chip);
 125         int err;
 126
 127         err = clk_prepare_enable(channel->clk);
 128         if (err < 0) {
 129                 dev_err(dev, "failed to enable clock %s: %d\n",
 130                         __clk_get_name(channel->clk), err);
 131                 return err;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 138 {
 139         struct meson_pwm *meson = to_meson_pwm(chip);
 140         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 141
 142         clk_disable_unprepare(channel->clk);
 143 }
 144
 145 static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm,
 146                           const struct pwm_state *state)
 147 {
 148         struct meson_pwm *meson = to_meson_pwm(chip);
 149         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 150         unsigned int cnt, duty_cnt;
 151         long fin_freq;
 152         u64 duty, period, freq;
 153
 154         duty = state->duty_cycle;
 155         period = state->period;
 156
 157         /*
 158          * Note this is wrong. The result is an output wave that isn't really
 159          * inverted and so is wrongly identified by .get_state as normal.
 160          * Fixing this needs some care however as some machines might rely on
 161          * this.
 162          */
 163         if (state->polarity == PWM_POLARITY_INVERSED)
 164                 duty = period - duty;
 165
 166         freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period);
 167         if (freq > ULONG_MAX)
 168                 freq = ULONG_MAX;
 169
 170         fin_freq = clk_round_rate(channel->clk, freq);
 171         if (fin_freq <= 0) {
 172                 dev_err(pwmchip_parent(chip),
 173                         "invalid source clock frequency %llu\n", freq);
 174                 return fin_freq ? fin_freq : -EINVAL;
 175         }
 176
 177         dev_dbg(pwmchip_parent(chip), "fin_freq: %ld Hz\n", fin_freq);
 178
 179         cnt = mul_u64_u64_div_u64(fin_freq, period, NSEC_PER_SEC);
 180         if (cnt > 0xffff) {
 181                 dev_err(pwmchip_parent(chip), "unable to get period cnt\n");
 182                 return -EINVAL;
 183         }
 184
 185         dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt);
 186
 187         if (duty == period) {
 188                 channel->hi = cnt;
 189                 channel->lo = 0;
 190         } else if (duty == 0) {
 191                 channel->hi = 0;
 192                 channel->lo = cnt;
 193         } else {
 194                 duty_cnt = mul_u64_u64_div_u64(fin_freq, duty, NSEC_PER_SEC);
 195
 196                 dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
 197
 198                 channel->hi = duty_cnt;
 199                 channel->lo = cnt - duty_cnt;
 200         }
 201
 202         channel->rate = fin_freq;
 203
 204         return 0;
 205 }
 206
 207 static void meson_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 208 {
 209         struct meson_pwm *meson = to_meson_pwm(chip);
 210         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 211         struct meson_pwm_channel_data *channel_data;
 212         unsigned long flags;
 213         u32 value;
 214         int err;
 215
 216         channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
 217
 218         err = clk_set_rate(channel->clk, channel->rate);
 219         if (err)
 220                 dev_err(pwmchip_parent(chip), "setting clock rate failed\n");
 221
 222         spin_lock_irqsave(&meson->lock, flags);
 223
 224         value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
 225                 FIELD_PREP(PWM_LOW_MASK, channel->lo);
 226         writel(value, meson->base + channel_data->reg_offset);
 227
 228         value = readl(meson->base + REG_MISC_AB);
 229         value |= channel_data->pwm_en_mask;
 230         writel(value, meson->base + REG_MISC_AB);
 231
 232         spin_unlock_irqrestore(&meson->lock, flags);
 233 }
 234
 235 static void meson_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 236 {
 237         struct meson_pwm *meson = to_meson_pwm(chip);
 238         unsigned long flags;
 239         u32 value;
 240
 241         spin_lock_irqsave(&meson->lock, flags);
 242
 243         value = readl(meson->base + REG_MISC_AB);
 244         value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
 245         writel(value, meson->base + REG_MISC_AB);
 246
 247         spin_unlock_irqrestore(&meson->lock, flags);
 248 }
 249
 250 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 251                            const struct pwm_state *state)
 252 {
 253         struct meson_pwm *meson = to_meson_pwm(chip);
 254         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 255         int err = 0;
 256
 257         if (!state->enabled) {
 258                 if (state->polarity == PWM_POLARITY_INVERSED) {
 259                         /*
 260                          * This IP block revision doesn't have an "always high"
 261                          * setting which we can use for "inverted disabled".
 262                          * Instead we achieve this by setting mux parent with
 263                          * highest rate and minimum divider value, resulting
 264                          * in the shortest possible duration for one "count"
 265                          * and "period == duty_cycle". This results in a signal
 266                          * which is LOW for one "count", while being HIGH for
 267                          * the rest of the (so the signal is HIGH for slightly
 268                          * less than 100% of the period, but this is the best
 269                          * we can achieve).
 270                          */
 271                         channel->rate = ULONG_MAX;
 272                         channel->hi = ~0;
 273                         channel->lo = 0;
 274
 275                         meson_pwm_enable(chip, pwm);
 276                 } else {
 277                         meson_pwm_disable(chip, pwm);
 278                 }
 279         } else {
 280                 err = meson_pwm_calc(chip, pwm, state);
 281                 if (err < 0)
 282                         return err;
 283
 284                 meson_pwm_enable(chip, pwm);
 285         }
 286
 287         return 0;
 288 }
 289
 290 static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm,
 291                                u32 cnt)
 292 {
 293         struct meson_pwm *meson = to_meson_pwm(chip);
 294         struct meson_pwm_channel *channel;
 295         unsigned long fin_freq;
 296
 297         /* to_meson_pwm() can only be used after .get_state() is called */
 298         channel = &meson->channels[pwm->hwpwm];
 299
 300         fin_freq = clk_get_rate(channel->clk);
 301         if (fin_freq == 0)
 302                 return 0;
 303
 304         return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq);
 305 }
 306
 307 static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 308                                struct pwm_state *state)
 309 {
 310         struct meson_pwm *meson = to_meson_pwm(chip);
 311         struct meson_pwm_channel_data *channel_data;
 312         struct meson_pwm_channel *channel;
 313         u32 value;
 314
 315         channel = &meson->channels[pwm->hwpwm];
 316         channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
 317
 318         value = readl(meson->base + REG_MISC_AB);
 319         state->enabled = value & channel_data->pwm_en_mask;
 320
 321         value = readl(meson->base + channel_data->reg_offset);
 322         channel->lo = FIELD_GET(PWM_LOW_MASK, value);
 323         channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
 324
 325         state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
 326         state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
 327
 328         state->polarity = PWM_POLARITY_NORMAL;
 329
 330         return 0;
 331 }
 332
 333 static const struct pwm_ops meson_pwm_ops = {
 334         .request = meson_pwm_request,
 335         .free = meson_pwm_free,
 336         .apply = meson_pwm_apply,
 337         .get_state = meson_pwm_get_state,
 338 };
 339
 340 static int meson_pwm_init_clocks_meson8b(struct pwm_chip *chip,
 341                                          struct clk_parent_data *mux_parent_data)
 342 {
 343         struct meson_pwm *meson = to_meson_pwm(chip);
 344         struct device *dev = pwmchip_parent(chip);
 345         unsigned int i;
 346         char name[255];
 347         int err;
 348
 349         for (i = 0; i < MESON_NUM_PWMS; i++) {
 350                 struct meson_pwm_channel *channel = &meson->channels[i];
 351                 struct clk_parent_data div_parent = {}, gate_parent = {};
 352                 struct clk_init_data init = {};
 353
 354                 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
 355
 356                 init.name = name;
 357                 init.ops = &clk_mux_ops;
 358                 init.flags = 0;
 359                 init.parent_data = mux_parent_data;
 360                 init.num_parents = MESON_NUM_MUX_PARENTS;
 361
 362                 channel->mux.reg = meson->base + REG_MISC_AB;
 363                 channel->mux.shift =
 364                                 meson_pwm_per_channel_data[i].clk_sel_shift;
 365                 channel->mux.mask = MISC_CLK_SEL_MASK;
 366                 channel->mux.flags = 0;
 367                 channel->mux.lock = &meson->lock;
 368                 channel->mux.table = NULL;
 369                 channel->mux.hw.init = &init;
 370
 371                 err = devm_clk_hw_register(dev, &channel->mux.hw);
 372                 if (err)
 373                         return dev_err_probe(dev, err,
 374                                              "failed to register %s\n", name);
 375
 376                 snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i);
 377
 378                 init.name = name;
 379                 init.ops = &clk_divider_ops;
 380                 init.flags = CLK_SET_RATE_PARENT;
 381                 div_parent.index = -1;
 382                 div_parent.hw = &channel->mux.hw;
 383                 init.parent_data = &div_parent;
 384                 init.num_parents = 1;
 385
 386                 channel->div.reg = meson->base + REG_MISC_AB;
 387                 channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift;
 388                 channel->div.width = MISC_CLK_DIV_WIDTH;
 389                 channel->div.hw.init = &init;
 390                 channel->div.flags = 0;
 391                 channel->div.lock = &meson->lock;
 392
 393                 err = devm_clk_hw_register(dev, &channel->div.hw);
 394                 if (err)
 395                         return dev_err_probe(dev, err,
 396                                              "failed to register %s\n", name);
 397
 398                 snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i);
 399
 400                 init.name = name;
 401                 init.ops = &clk_gate_ops;
 402                 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
 403                 gate_parent.index = -1;
 404                 gate_parent.hw = &channel->div.hw;
 405                 init.parent_data = &gate_parent;
 406                 init.num_parents = 1;
 407
 408                 channel->gate.reg = meson->base + REG_MISC_AB;
 409                 channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift;
 410                 channel->gate.hw.init = &init;
 411                 channel->gate.flags = 0;
 412                 channel->gate.lock = &meson->lock;
 413
 414                 err = devm_clk_hw_register(dev, &channel->gate.hw);
 415                 if (err)
 416                         return dev_err_probe(dev, err, "failed to register %s\n", name);
 417
 418                 channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL);
 419                 if (IS_ERR(channel->clk))
 420                         return dev_err_probe(dev, PTR_ERR(channel->clk),
 421                                              "failed to register %s\n", name);
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int meson_pwm_init_channels_meson8b_legacy(struct pwm_chip *chip)
 428 {
 429         struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {};
 430         struct meson_pwm *meson = to_meson_pwm(chip);
 431         int i;
 432
 433         dev_warn_once(pwmchip_parent(chip),
 434                       "using obsolete compatible, please consider updating dt\n");
 435
 436         for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) {
 437                 mux_parent_data[i].index = -1;
 438                 mux_parent_data[i].name = meson->data->parent_names[i];
 439         }
 440
 441         return meson_pwm_init_clocks_meson8b(chip, mux_parent_data);
 442 }
 443
 444 static int meson_pwm_init_channels_meson8b_v2(struct pwm_chip *chip)
 445 {
 446         struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {};
 447         int i;
 448
 449         /*
 450          * NOTE: Instead of relying on the hard coded names in the driver
 451          * as the legacy version, this relies on DT to provide the list of
 452          * clocks.
 453          * For once, using input numbers actually makes more sense than names.
 454          * Also DT requires clock-names to be explicitly ordered, so there is
 455          * no point bothering with clock names in this case.
 456          */
 457         for (i = 0; i < MESON_NUM_MUX_PARENTS; i++)
 458                 mux_parent_data[i].index = i;
 459
 460         return meson_pwm_init_clocks_meson8b(chip, mux_parent_data);
 461 }
 462
 463 static void meson_pwm_s4_put_clk(void *data)
 464 {
 465         struct clk *clk = data;
 466
 467         clk_put(clk);
 468 }
 469
 470 static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
 471 {
 472         struct device *dev = pwmchip_parent(chip);
 473         struct device_node *np = dev->of_node;
 474         struct meson_pwm *meson = to_meson_pwm(chip);
 475         int i, ret;
 476
 477         for (i = 0; i < MESON_NUM_PWMS; i++) {
 478                 meson->channels[i].clk = of_clk_get(np, i);
 479                 if (IS_ERR(meson->channels[i].clk))
 480                         return dev_err_probe(dev,
 481                                              PTR_ERR(meson->channels[i].clk),
 482                                              "Failed to get clk\n");
 483
 484                 ret = devm_add_action_or_reset(dev, meson_pwm_s4_put_clk,
 485                                                meson->channels[i].clk);
 486                 if (ret)
 487                         return dev_err_probe(dev, ret,
 488                                              "Failed to add clk_put action\n");
 489         }
 490
 491         return 0;
 492 }
 493
 494 static const struct meson_pwm_data pwm_meson8b_data = {
 495         .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" },
 496         .channels_init = meson_pwm_init_channels_meson8b_legacy,
 497 };
 498
 499 /*
 500  * Only the 2 first inputs of the GXBB AO PWMs are valid
 501  * The last 2 are grounded
 502  */
 503 static const struct meson_pwm_data pwm_gxbb_ao_data = {
 504         .parent_names = { "xtal", "clk81", NULL, NULL },
 505         .channels_init = meson_pwm_init_channels_meson8b_legacy,
 506 };
 507
 508 static const struct meson_pwm_data pwm_axg_ee_data = {
 509         .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" },
 510         .channels_init = meson_pwm_init_channels_meson8b_legacy,
 511 };
 512
 513 static const struct meson_pwm_data pwm_axg_ao_data = {
 514         .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" },
 515         .channels_init = meson_pwm_init_channels_meson8b_legacy,
 516 };
 517
 518 static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
 519         .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" },
 520         .channels_init = meson_pwm_init_channels_meson8b_legacy,
 521 };
 522
 523 static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
 524         .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL },
 525         .channels_init = meson_pwm_init_channels_meson8b_legacy,
 526 };
 527
 528 static const struct meson_pwm_data pwm_meson8_v2_data = {
 529         .channels_init = meson_pwm_init_channels_meson8b_v2,
 530 };
 531
 532 static const struct meson_pwm_data pwm_s4_data = {
 533         .channels_init = meson_pwm_init_channels_s4,
 534 };
 535
 536 static const struct of_device_id meson_pwm_matches[] = {
 537         {
 538                 .compatible = "amlogic,meson8-pwm-v2",
 539                 .data = &pwm_meson8_v2_data
 540         },
 541         /* The following compatibles are obsolete */
 542         {
 543                 .compatible = "amlogic,meson8b-pwm",
 544                 .data = &pwm_meson8b_data
 545         },
 546         {
 547                 .compatible = "amlogic,meson-gxbb-pwm",
 548                 .data = &pwm_meson8b_data
 549         },
 550         {
 551                 .compatible = "amlogic,meson-gxbb-ao-pwm",
 552                 .data = &pwm_gxbb_ao_data
 553         },
 554         {
 555                 .compatible = "amlogic,meson-axg-ee-pwm",
 556                 .data = &pwm_axg_ee_data
 557         },
 558         {
 559                 .compatible = "amlogic,meson-axg-ao-pwm",
 560                 .data = &pwm_axg_ao_data
 561         },
 562         {
 563                 .compatible = "amlogic,meson-g12a-ee-pwm",
 564                 .data = &pwm_meson8b_data
 565         },
 566         {
 567                 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
 568                 .data = &pwm_g12a_ao_ab_data
 569         },
 570         {
 571                 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
 572                 .data = &pwm_g12a_ao_cd_data
 573         },
 574         {
 575                 .compatible = "amlogic,meson-s4-pwm",
 576                 .data = &pwm_s4_data
 577         },
 578         {},
 579 };
 580 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
 581
 582 static int meson_pwm_probe(struct platform_device *pdev)
 583 {
 584         struct pwm_chip *chip;
 585         struct meson_pwm *meson;
 586         int err;
 587
 588         chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
 589         if (IS_ERR(chip))
 590                 return PTR_ERR(chip);
 591         meson = to_meson_pwm(chip);
 592
 593         meson->base = devm_platform_ioremap_resource(pdev, 0);
 594         if (IS_ERR(meson->base))
 595                 return PTR_ERR(meson->base);
 596
 597         spin_lock_init(&meson->lock);
 598         chip->ops = &meson_pwm_ops;
 599
 600         meson->data = of_device_get_match_data(&pdev->dev);
 601
 602         err = meson->data->channels_init(chip);
 603         if (err < 0)
 604                 return err;
 605
 606         err = devm_pwmchip_add(&pdev->dev, chip);
 607         if (err < 0)
 608                 return dev_err_probe(&pdev->dev, err,
 609                                      "failed to register PWM chip\n");
 610
 611         return 0;
 612 }
 613
 614 static struct platform_driver meson_pwm_driver = {
 615         .driver = {
 616                 .name = "meson-pwm",
 617                 .of_match_table = meson_pwm_matches,
 618         },
 619         .probe = meson_pwm_probe,
 620 };
 621 module_platform_driver(meson_pwm_driver);
 622
 623 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
 624 MODULE_AUTHOR("Neil Armstrong <[email protected]>");
 625 MODULE_LICENSE("Dual BSD/GPL");