drivers/pwm/pwm-imx-tpm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2018-2019 NXP.
   4  *
   5  * Limitations:
   6  * - The TPM counter and period counter are shared between
   7  *   multiple channels, so all channels should use same period
   8  *   settings.
   9  * - Changes to polarity cannot be latched at the time of the
  10  *   next period start.
  11  * - Changing period and duty cycle together isn't atomic,
  12  *   with the wrong timing it might happen that a period is
  13  *   produced with old duty cycle but new period settings.
  14  */
  15
  16 #include <linux/bitfield.h>
  17 #include <linux/bitops.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pwm.h>
  26 #include <linux/slab.h>
  27
  28 #define PWM_IMX_TPM_PARAM       0x4
  29 #define PWM_IMX_TPM_GLOBAL      0x8
  30 #define PWM_IMX_TPM_SC          0x10
  31 #define PWM_IMX_TPM_CNT         0x14
  32 #define PWM_IMX_TPM_MOD         0x18
  33 #define PWM_IMX_TPM_CnSC(n)     (0x20 + (n) * 0x8)
  34 #define PWM_IMX_TPM_CnV(n)      (0x24 + (n) * 0x8)
  35
  36 #define PWM_IMX_TPM_PARAM_CHAN                  GENMASK(7, 0)
  37
  38 #define PWM_IMX_TPM_SC_PS                       GENMASK(2, 0)
  39 #define PWM_IMX_TPM_SC_CMOD                     GENMASK(4, 3)
  40 #define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK       FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
  41 #define PWM_IMX_TPM_SC_CPWMS                    BIT(5)
  42
  43 #define PWM_IMX_TPM_CnSC_CHF    BIT(7)
  44 #define PWM_IMX_TPM_CnSC_MSB    BIT(5)
  45 #define PWM_IMX_TPM_CnSC_MSA    BIT(4)
  46
  47 /*
  48  * The reference manual describes this field as two separate bits. The
  49  * semantic of the two bits isn't orthogonal though, so they are treated
  50  * together as a 2-bit field here.
  51  */
  52 #define PWM_IMX_TPM_CnSC_ELS    GENMASK(3, 2)
  53 #define PWM_IMX_TPM_CnSC_ELS_INVERSED   FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
  54 #define PWM_IMX_TPM_CnSC_ELS_NORMAL     FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
  55
  56
  57 #define PWM_IMX_TPM_MOD_WIDTH   16
  58 #define PWM_IMX_TPM_MOD_MOD     GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
  59
  60 struct imx_tpm_pwm_chip {
  61         struct clk *clk;
  62         void __iomem *base;
  63         struct mutex lock;
  64         u32 user_count;
  65         u32 enable_count;
  66         u32 real_period;
  67 };
  68
  69 struct imx_tpm_pwm_param {
  70         u8 prescale;
  71         u32 mod;
  72         u32 val;
  73 };
  74
  75 static inline struct imx_tpm_pwm_chip *
  76 to_imx_tpm_pwm_chip(struct pwm_chip *chip)
  77 {
  78         return pwmchip_get_drvdata(chip);
  79 }
  80
  81 /*
  82  * This function determines for a given pwm_state *state that a consumer
  83  * might request the pwm_state *real_state that eventually is implemented
  84  * by the hardware and the necessary register values (in *p) to achieve
  85  * this.
  86  */
  87 static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
  88                                    struct imx_tpm_pwm_param *p,
  89                                    struct pwm_state *real_state,
  90                                    const struct pwm_state *state)
  91 {
  92         struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
  93         u32 rate, prescale, period_count, clock_unit;
  94         u64 tmp;
  95
  96         rate = clk_get_rate(tpm->clk);
  97         tmp = (u64)state->period * rate;
  98         clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
  99         if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
 100                 prescale = 0;
 101         else
 102                 prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
 103
 104         if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
 105                 return -ERANGE;
 106         p->prescale = prescale;
 107
 108         period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
 109         if (period_count == 0)
 110                 return -EINVAL;
 111         p->mod = period_count - 1;
 112
 113         /* calculate real period HW can support */
 114         tmp = (u64)period_count << prescale;
 115         tmp *= NSEC_PER_SEC;
 116         real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
 117
 118         /*
 119          * if eventually the PWM output is inactive, either
 120          * duty cycle is 0 or status is disabled, need to
 121          * make sure the output pin is inactive.
 122          */
 123         if (!state->enabled)
 124                 real_state->duty_cycle = 0;
 125         else
 126                 real_state->duty_cycle = state->duty_cycle;
 127
 128         tmp = (u64)p->mod * real_state->duty_cycle;
 129         p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
 130
 131         real_state->polarity = state->polarity;
 132         real_state->enabled = state->enabled;
 133
 134         return 0;
 135 }
 136
 137 static int pwm_imx_tpm_get_state(struct pwm_chip *chip,
 138                                  struct pwm_device *pwm,
 139                                  struct pwm_state *state)
 140 {
 141         struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 142         u32 rate, val, prescale;
 143         u64 tmp;
 144
 145         /* get period */
 146         state->period = tpm->real_period;
 147
 148         /* get duty cycle */
 149         rate = clk_get_rate(tpm->clk);
 150         val = readl(tpm->base + PWM_IMX_TPM_SC);
 151         prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
 152         tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
 153         tmp = (tmp << prescale) * NSEC_PER_SEC;
 154         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
 155
 156         /* get polarity */
 157         val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
 158         if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
 159                 state->polarity = PWM_POLARITY_INVERSED;
 160         else
 161                 /*
 162                  * Assume reserved values (2b00 and 2b11) to yield
 163                  * normal polarity.
 164                  */
 165                 state->polarity = PWM_POLARITY_NORMAL;
 166
 167         /* get channel status */
 168         state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
 169
 170         return 0;
 171 }
 172
 173 /* this function is supposed to be called with mutex hold */
 174 static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
 175                                 struct imx_tpm_pwm_param *p,
 176                                 struct pwm_state *state,
 177                                 struct pwm_device *pwm)
 178 {
 179         struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 180         bool period_update = false;
 181         bool duty_update = false;
 182         u32 val, cmod, cur_prescale;
 183         unsigned long timeout;
 184         struct pwm_state c;
 185
 186         if (state->period != tpm->real_period) {
 187                 /*
 188                  * TPM counter is shared by multiple channels, so
 189                  * prescale and period can NOT be modified when
 190                  * there are multiple channels in use with different
 191                  * period settings.
 192                  */
 193                 if (tpm->user_count > 1)
 194                         return -EBUSY;
 195
 196                 val = readl(tpm->base + PWM_IMX_TPM_SC);
 197                 cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
 198                 cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
 199                 if (cmod && cur_prescale != p->prescale)
 200                         return -EBUSY;
 201
 202                 /* set TPM counter prescale */
 203                 val &= ~PWM_IMX_TPM_SC_PS;
 204                 val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
 205                 writel(val, tpm->base + PWM_IMX_TPM_SC);
 206
 207                 /*
 208                  * set period count:
 209                  * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
 210                  * is updated when MOD register is written.
 211                  *
 212                  * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
 213                  * is latched into hardware when the next period starts.
 214                  */
 215                 writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
 216                 tpm->real_period = state->period;
 217                 period_update = true;
 218         }
 219
 220         pwm_imx_tpm_get_state(chip, pwm, &c);
 221
 222         /* polarity is NOT allowed to be changed if PWM is active */
 223         if (c.enabled && c.polarity != state->polarity)
 224                 return -EBUSY;
 225
 226         if (state->duty_cycle != c.duty_cycle) {
 227                 /*
 228                  * set channel value:
 229                  * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
 230                  * is updated when CnV register is written.
 231                  *
 232                  * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
 233                  * is latched into hardware when the next period starts.
 234                  */
 235                 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
 236                 duty_update = true;
 237         }
 238
 239         /* make sure MOD & CnV registers are updated */
 240         if (period_update || duty_update) {
 241                 timeout = jiffies + msecs_to_jiffies(tpm->real_period /
 242                                                      NSEC_PER_MSEC + 1);
 243                 while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
 244                        || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
 245                        != p->val) {
 246                         if (time_after(jiffies, timeout))
 247                                 return -ETIME;
 248                         cpu_relax();
 249                 }
 250         }
 251
 252         /*
 253          * polarity settings will enabled/disable output status
 254          * immediately, so if the channel is disabled, need to
 255          * make sure MSA/MSB/ELS are set to 0 which means channel
 256          * disabled.
 257          */
 258         val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
 259         val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
 260                  PWM_IMX_TPM_CnSC_MSB);
 261         if (state->enabled) {
 262                 /*
 263                  * set polarity (for edge-aligned PWM modes)
 264                  *
 265                  * ELS[1:0] = 2b10 yields normal polarity behaviour,
 266                  * ELS[1:0] = 2b01 yields inversed polarity.
 267                  * The other values are reserved.
 268                  */
 269                 val |= PWM_IMX_TPM_CnSC_MSB;
 270                 val |= (state->polarity == PWM_POLARITY_NORMAL) ?
 271                         PWM_IMX_TPM_CnSC_ELS_NORMAL :
 272                         PWM_IMX_TPM_CnSC_ELS_INVERSED;
 273         }
 274         writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
 275
 276         /* control the counter status */
 277         if (state->enabled != c.enabled) {
 278                 val = readl(tpm->base + PWM_IMX_TPM_SC);
 279                 if (state->enabled) {
 280                         if (++tpm->enable_count == 1)
 281                                 val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
 282                 } else {
 283                         if (--tpm->enable_count == 0)
 284                                 val &= ~PWM_IMX_TPM_SC_CMOD;
 285                 }
 286                 writel(val, tpm->base + PWM_IMX_TPM_SC);
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int pwm_imx_tpm_apply(struct pwm_chip *chip,
 293                              struct pwm_device *pwm,
 294                              const struct pwm_state *state)
 295 {
 296         struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 297         struct imx_tpm_pwm_param param;
 298         struct pwm_state real_state;
 299         int ret;
 300
 301         ret = pwm_imx_tpm_round_state(chip, &param, &real_state, state);
 302         if (ret)
 303                 return ret;
 304
 305         mutex_lock(&tpm->lock);
 306         ret = pwm_imx_tpm_apply_hw(chip, &param, &real_state, pwm);
 307         mutex_unlock(&tpm->lock);
 308
 309         return ret;
 310 }
 311
 312 static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 313 {
 314         struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 315
 316         mutex_lock(&tpm->lock);
 317         tpm->user_count++;
 318         mutex_unlock(&tpm->lock);
 319
 320         return 0;
 321 }
 322
 323 static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 324 {
 325         struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 326
 327         mutex_lock(&tpm->lock);
 328         tpm->user_count--;
 329         mutex_unlock(&tpm->lock);
 330 }
 331
 332 static const struct pwm_ops imx_tpm_pwm_ops = {
 333         .request = pwm_imx_tpm_request,
 334         .free = pwm_imx_tpm_free,
 335         .get_state = pwm_imx_tpm_get_state,
 336         .apply = pwm_imx_tpm_apply,
 337 };
 338
 339 static int pwm_imx_tpm_probe(struct platform_device *pdev)
 340 {
 341         struct pwm_chip *chip;
 342         struct imx_tpm_pwm_chip *tpm;
 343         struct clk *clk;
 344         void __iomem *base;
 345         int ret;
 346         unsigned int npwm;
 347         u32 val;
 348
 349         base = devm_platform_ioremap_resource(pdev, 0);
 350         if (IS_ERR(base))
 351                 return PTR_ERR(base);
 352
 353         clk = devm_clk_get_enabled(&pdev->dev, NULL);
 354         if (IS_ERR(clk))
 355                 return dev_err_probe(&pdev->dev, PTR_ERR(clk),
 356                                      "failed to get PWM clock\n");
 357
 358         /* get number of channels */
 359         val = readl(base + PWM_IMX_TPM_PARAM);
 360         npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
 361
 362         chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*tpm));
 363         if (IS_ERR(chip))
 364                 return PTR_ERR(chip);
 365         tpm = to_imx_tpm_pwm_chip(chip);
 366
 367         platform_set_drvdata(pdev, tpm);
 368
 369         tpm->base = base;
 370         tpm->clk = clk;
 371
 372         chip->ops = &imx_tpm_pwm_ops;
 373
 374         mutex_init(&tpm->lock);
 375
 376         ret = devm_pwmchip_add(&pdev->dev, chip);
 377         if (ret)
 378                 return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
 379
 380         return 0;
 381 }
 382
 383 static int pwm_imx_tpm_suspend(struct device *dev)
 384 {
 385         struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
 386         int ret;
 387
 388         if (tpm->enable_count > 0)
 389                 return -EBUSY;
 390
 391         /*
 392          * Force 'real_period' to be zero to force period update code
 393          * can be executed after system resume back, since suspend causes
 394          * the period related registers to become their reset values.
 395          */
 396         tpm->real_period = 0;
 397
 398         clk_disable_unprepare(tpm->clk);
 399
 400         ret = pinctrl_pm_select_sleep_state(dev);
 401         if (ret)
 402                 clk_prepare_enable(tpm->clk);
 403
 404         return ret;
 405 }
 406
 407 static int pwm_imx_tpm_resume(struct device *dev)
 408 {
 409         struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
 410         int ret = 0;
 411
 412         ret = pinctrl_pm_select_default_state(dev);
 413         if (ret)
 414                 return ret;
 415
 416         ret = clk_prepare_enable(tpm->clk);
 417         if (ret) {
 418                 dev_err(dev, "failed to prepare or enable clock: %d\n", ret);
 419                 pinctrl_pm_select_sleep_state(dev);
 420         }
 421
 422         return ret;
 423 }
 424
 425 static DEFINE_SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
 426                                 pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
 427
 428 static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
 429         { .compatible = "fsl,imx7ulp-pwm", },
 430         { /* sentinel */ }
 431 };
 432 MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
 433
 434 static struct platform_driver imx_tpm_pwm_driver = {
 435         .driver = {
 436                 .name = "imx7ulp-tpm-pwm",
 437                 .of_match_table = imx_tpm_pwm_dt_ids,
 438                 .pm = pm_ptr(&imx_tpm_pwm_pm),
 439         },
 440         .probe  = pwm_imx_tpm_probe,
 441 };
 442 module_platform_driver(imx_tpm_pwm_driver);
 443
 444 MODULE_AUTHOR("Anson Huang <[email protected]>");
 445 MODULE_DESCRIPTION("i.MX TPM PWM Driver");
 446 MODULE_LICENSE("GPL v2");