drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atomfirmware.h"
  27 #include "gmc_v11_0.h"
  28 #include "umc_v8_7.h"
  29 #include "athub/athub_3_0_0_sh_mask.h"
  30 #include "athub/athub_3_0_0_offset.h"
  31 #include "oss/osssys_6_0_0_offset.h"
  32 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  33 #include "navi10_enum.h"
  34 #include "soc15.h"
  35 #include "soc15d.h"
  36 #include "soc15_common.h"
  37 #include "nbio_v4_3.h"
  38 #include "gfxhub_v3_0.h"
  39 #include "mmhub_v3_0.h"
  40 #include "mmhub_v3_0_1.h"
  41 #include "mmhub_v3_0_2.h"
  42 #include "athub_v3_0.h"
  43
  44
  45 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev,
  46                                          struct amdgpu_irq_src *src,
  47                                          unsigned type,
  48                                          enum amdgpu_interrupt_state state)
  49 {
  50         return 0;
  51 }
  52
  53 static int
  54 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  55                                    struct amdgpu_irq_src *src, unsigned type,
  56                                    enum amdgpu_interrupt_state state)
  57 {
  58         switch (state) {
  59         case AMDGPU_IRQ_STATE_DISABLE:
  60                 /* MM HUB */
  61                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
  62                 /* GFX HUB */
  63                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
  64                 break;
  65         case AMDGPU_IRQ_STATE_ENABLE:
  66                 /* MM HUB */
  67                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
  68                 /* GFX HUB */
  69                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
  70                 break;
  71         default:
  72                 break;
  73         }
  74
  75         return 0;
  76 }
  77
  78 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
  79                                        struct amdgpu_irq_src *source,
  80                                        struct amdgpu_iv_entry *entry)
  81 {
  82         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
  83         uint32_t status = 0;
  84         u64 addr;
  85
  86         addr = (u64)entry->src_data[0] << 12;
  87         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
  88
  89         if (!amdgpu_sriov_vf(adev)) {
  90                 /*
  91                  * Issue a dummy read to wait for the status register to
  92                  * be updated to avoid reading an incorrect value due to
  93                  * the new fast GRBM interface.
  94                  */
  95                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
  96                         RREG32(hub->vm_l2_pro_fault_status);
  97
  98                 status = RREG32(hub->vm_l2_pro_fault_status);
  99                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 100         }
 101
 102         if (printk_ratelimit()) {
 103                 struct amdgpu_task_info task_info;
 104
 105                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 106                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 107
 108                 dev_err(adev->dev,
 109                         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 110                         "for process %s pid %d thread %s pid %d)\n",
 111                         entry->vmid_src ? "mmhub" : "gfxhub",
 112                         entry->src_id, entry->ring_id, entry->vmid,
 113                         entry->pasid, task_info.process_name, task_info.tgid,
 114                         task_info.task_name, task_info.pid);
 115                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 116                         addr, entry->client_id);
 117                 if (!amdgpu_sriov_vf(adev))
 118                         hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
 119         }
 120
 121         return 0;
 122 }
 123
 124 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = {
 125         .set = gmc_v11_0_vm_fault_interrupt_state,
 126         .process = gmc_v11_0_process_interrupt,
 127 };
 128
 129 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = {
 130         .set = gmc_v11_0_ecc_interrupt_state,
 131         .process = amdgpu_umc_process_ecc_irq,
 132 };
 133
 134 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 135 {
 136         adev->gmc.vm_fault.num_types = 1;
 137         adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
 138
 139         if (!amdgpu_sriov_vf(adev)) {
 140                 adev->gmc.ecc_irq.num_types = 1;
 141                 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
 142         }
 143 }
 144
 145 /**
 146  * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore
 147  *
 148  * @adev: amdgpu_device pointer
 149  * @vmhub: vmhub type
 150  *
 151  */
 152 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 153                                        uint32_t vmhub)
 154 {
 155         return ((vmhub == AMDGPU_MMHUB_0) &&
 156                 (!amdgpu_sriov_vf(adev)));
 157 }
 158
 159 static bool gmc_v11_0_get_vmid_pasid_mapping_info(
 160                                         struct amdgpu_device *adev,
 161                                         uint8_t vmid, uint16_t *p_pasid)
 162 {
 163         *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
 164
 165         return !!(*p_pasid);
 166 }
 167
 168 /*
 169  * GART
 170  * VMID 0 is the physical GPU addresses as used by the kernel.
 171  * VMIDs 1-15 are used for userspace clients and are handled
 172  * by the amdgpu vm/hsa code.
 173  */
 174
 175 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 176                                    unsigned int vmhub, uint32_t flush_type)
 177 {
 178         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
 179         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 180         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 181         u32 tmp;
 182         /* Use register 17 for GART */
 183         const unsigned eng = 17;
 184         unsigned int i;
 185
 186         spin_lock(&adev->gmc.invalidate_lock);
 187         /*
 188          * It may lose gpuvm invalidate acknowldege state across power-gating
 189          * off cycle, add semaphore acquire before invalidation and semaphore
 190          * release after invalidation to avoid entering power gated state
 191          * to WA the Issue
 192          */
 193
 194         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 195         if (use_semaphore) {
 196                 for (i = 0; i < adev->usec_timeout; i++) {
 197                         /* a read return value of 1 means semaphore acuqire */
 198                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 199                                             hub->eng_distance * eng);
 200                         if (tmp & 0x1)
 201                                 break;
 202                         udelay(1);
 203                 }
 204
 205                 if (i >= adev->usec_timeout)
 206                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 207         }
 208
 209         WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
 210
 211         /* Wait for ACK with a delay.*/
 212         for (i = 0; i < adev->usec_timeout; i++) {
 213                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
 214                                     hub->eng_distance * eng);
 215                 tmp &= 1 << vmid;
 216                 if (tmp)
 217                         break;
 218
 219                 udelay(1);
 220         }
 221
 222         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 223         if (use_semaphore)
 224                 /*
 225                  * add semaphore release after invalidation,
 226                  * write with 0 means semaphore release
 227                  */
 228                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 229                               hub->eng_distance * eng, 0);
 230
 231         /* Issue additional private vm invalidation to MMHUB */
 232         if ((vmhub != AMDGPU_GFXHUB_0) &&
 233             (hub->vm_l2_bank_select_reserved_cid2)) {
 234                 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 235                 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
 236                 inv_req |= (1 << 25);
 237                 /* Issue private invalidation */
 238                 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
 239                 /* Read back to ensure invalidation is done*/
 240                 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 241         }
 242
 243         spin_unlock(&adev->gmc.invalidate_lock);
 244
 245         if (i < adev->usec_timeout)
 246                 return;
 247
 248         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 249 }
 250
 251 /**
 252  * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
 253  *
 254  * @adev: amdgpu_device pointer
 255  * @vmid: vm instance to flush
 256  *
 257  * Flush the TLB for the requested page table.
 258  */
 259 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 260                                         uint32_t vmhub, uint32_t flush_type)
 261 {
 262         if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
 263                 return;
 264
 265         /* flush hdp cache */
 266         adev->hdp.funcs->flush_hdp(adev, NULL);
 267
 268         /* For SRIOV run time, driver shouldn't access the register through MMIO
 269          * Directly use kiq to do the vm invalidation instead
 270          */
 271         if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) &&
 272             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 273                 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 274                 const unsigned eng = 17;
 275                 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 276                 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 277                 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 278
 279                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 280                                 1 << vmid);
 281                 return;
 282         }
 283
 284         mutex_lock(&adev->mman.gtt_window_lock);
 285         gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
 286         mutex_unlock(&adev->mman.gtt_window_lock);
 287         return;
 288 }
 289
 290 /**
 291  * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid
 292  *
 293  * @adev: amdgpu_device pointer
 294  * @pasid: pasid to be flush
 295  *
 296  * Flush the TLB for the requested pasid.
 297  */
 298 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 299                                         uint16_t pasid, uint32_t flush_type,
 300                                         bool all_hub)
 301 {
 302         int vmid, i;
 303         signed long r;
 304         uint32_t seq;
 305         uint16_t queried_pasid;
 306         bool ret;
 307         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 308         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 309
 310         if (amdgpu_emu_mode == 0 && ring->sched.ready) {
 311                 spin_lock(&adev->gfx.kiq.ring_lock);
 312                 /* 2 dwords flush + 8 dwords fence */
 313                 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
 314                 kiq->pmf->kiq_invalidate_tlbs(ring,
 315                                         pasid, flush_type, all_hub);
 316                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 317                 if (r) {
 318                         amdgpu_ring_undo(ring);
 319                         spin_unlock(&adev->gfx.kiq.ring_lock);
 320                         return -ETIME;
 321                 }
 322
 323                 amdgpu_ring_commit(ring);
 324                 spin_unlock(&adev->gfx.kiq.ring_lock);
 325                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 326                 if (r < 1) {
 327                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 328                         return -ETIME;
 329                 }
 330
 331                 return 0;
 332         }
 333
 334         for (vmid = 1; vmid < 16; vmid++) {
 335
 336                 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
 337                                 &queried_pasid);
 338                 if (ret && queried_pasid == pasid) {
 339                         if (all_hub) {
 340                                 for (i = 0; i < adev->num_vmhubs; i++)
 341                                         gmc_v11_0_flush_gpu_tlb(adev, vmid,
 342                                                         i, flush_type);
 343                         } else {
 344                                 gmc_v11_0_flush_gpu_tlb(adev, vmid,
 345                                                 AMDGPU_GFXHUB_0, flush_type);
 346                         }
 347                 }
 348         }
 349
 350         return 0;
 351 }
 352
 353 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 354                                              unsigned vmid, uint64_t pd_addr)
 355 {
 356         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 357         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 358         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 359         unsigned eng = ring->vm_inv_eng;
 360
 361         /*
 362          * It may lose gpuvm invalidate acknowldege state across power-gating
 363          * off cycle, add semaphore acquire before invalidation and semaphore
 364          * release after invalidation to avoid entering power gated state
 365          * to WA the Issue
 366          */
 367
 368         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 369         if (use_semaphore)
 370                 /* a read return value of 1 means semaphore acuqire */
 371                 amdgpu_ring_emit_reg_wait(ring,
 372                                           hub->vm_inv_eng0_sem +
 373                                           hub->eng_distance * eng, 0x1, 0x1);
 374
 375         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 376                               (hub->ctx_addr_distance * vmid),
 377                               lower_32_bits(pd_addr));
 378
 379         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 380                               (hub->ctx_addr_distance * vmid),
 381                               upper_32_bits(pd_addr));
 382
 383         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 384                                             hub->eng_distance * eng,
 385                                             hub->vm_inv_eng0_ack +
 386                                             hub->eng_distance * eng,
 387                                             req, 1 << vmid);
 388
 389         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 390         if (use_semaphore)
 391                 /*
 392                  * add semaphore release after invalidation,
 393                  * write with 0 means semaphore release
 394                  */
 395                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 396                                       hub->eng_distance * eng, 0);
 397
 398         return pd_addr;
 399 }
 400
 401 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 402                                          unsigned pasid)
 403 {
 404         struct amdgpu_device *adev = ring->adev;
 405         uint32_t reg;
 406
 407         /* MES fw manages IH_VMID_x_LUT updating */
 408         if (ring->is_mes_queue)
 409                 return;
 410
 411         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 412                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
 413         else
 414                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
 415
 416         amdgpu_ring_emit_wreg(ring, reg, pasid);
 417 }
 418
 419 /*
 420  * PTE format:
 421  * 63:59 reserved
 422  * 58:57 reserved
 423  * 56 F
 424  * 55 L
 425  * 54 reserved
 426  * 53:52 SW
 427  * 51 T
 428  * 50:48 mtype
 429  * 47:12 4k physical page base address
 430  * 11:7 fragment
 431  * 6 write
 432  * 5 read
 433  * 4 exe
 434  * 3 Z
 435  * 2 snooped
 436  * 1 system
 437  * 0 valid
 438  *
 439  * PDE format:
 440  * 63:59 block fragment size
 441  * 58:55 reserved
 442  * 54 P
 443  * 53:48 reserved
 444  * 47:6 physical base address of PD or PTE
 445  * 5:3 reserved
 446  * 2 C
 447  * 1 system
 448  * 0 valid
 449  */
 450
 451 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 452 {
 453         switch (flags) {
 454         case AMDGPU_VM_MTYPE_DEFAULT:
 455                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 456         case AMDGPU_VM_MTYPE_NC:
 457                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 458         case AMDGPU_VM_MTYPE_WC:
 459                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 460         case AMDGPU_VM_MTYPE_CC:
 461                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 462         case AMDGPU_VM_MTYPE_UC:
 463                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 464         default:
 465                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 466         }
 467 }
 468
 469 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
 470                                  uint64_t *addr, uint64_t *flags)
 471 {
 472         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 473                 *addr = adev->vm_manager.vram_base_offset + *addr -
 474                         adev->gmc.vram_start;
 475         BUG_ON(*addr & 0xFFFF00000000003FULL);
 476
 477         if (!adev->gmc.translate_further)
 478                 return;
 479
 480         if (level == AMDGPU_VM_PDB1) {
 481                 /* Set the block fragment size */
 482                 if (!(*flags & AMDGPU_PDE_PTE))
 483                         *flags |= AMDGPU_PDE_BFS(0x9);
 484
 485         } else if (level == AMDGPU_VM_PDB0) {
 486                 if (*flags & AMDGPU_PDE_PTE)
 487                         *flags &= ~AMDGPU_PDE_PTE;
 488                 else
 489                         *flags |= AMDGPU_PTE_TF;
 490         }
 491 }
 492
 493 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
 494                                  struct amdgpu_bo_va_mapping *mapping,
 495                                  uint64_t *flags)
 496 {
 497         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 498         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 499
 500         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 501         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 502
 503         *flags &= ~AMDGPU_PTE_NOALLOC;
 504         *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
 505
 506         if (mapping->flags & AMDGPU_PTE_PRT) {
 507                 *flags |= AMDGPU_PTE_PRT;
 508                 *flags |= AMDGPU_PTE_SNOOPED;
 509                 *flags |= AMDGPU_PTE_LOG;
 510                 *flags |= AMDGPU_PTE_SYSTEM;
 511                 *flags &= ~AMDGPU_PTE_VALID;
 512         }
 513 }
 514
 515 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
 516 {
 517         return 0;
 518 }
 519
 520 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
 521         .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
 522         .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
 523         .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
 524         .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
 525         .map_mtype = gmc_v11_0_map_mtype,
 526         .get_vm_pde = gmc_v11_0_get_vm_pde,
 527         .get_vm_pte = gmc_v11_0_get_vm_pte,
 528         .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
 529 };
 530
 531 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev)
 532 {
 533         adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
 534 }
 535
 536 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
 537 {
 538         switch (adev->ip_versions[UMC_HWIP][0]) {
 539         case IP_VERSION(8, 10, 0):
 540         case IP_VERSION(8, 11, 0):
 541                 break;
 542         default:
 543                 break;
 544         }
 545 }
 546
 547
 548 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
 549 {
 550         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 551         case IP_VERSION(3, 0, 1):
 552                 adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
 553                 break;
 554         case IP_VERSION(3, 0, 2):
 555                 adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
 556                 break;
 557         default:
 558                 adev->mmhub.funcs = &mmhub_v3_0_funcs;
 559                 break;
 560         }
 561 }
 562
 563 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 564 {
 565         adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
 566 }
 567
 568 static int gmc_v11_0_early_init(void *handle)
 569 {
 570         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 571
 572         gmc_v11_0_set_gfxhub_funcs(adev);
 573         gmc_v11_0_set_mmhub_funcs(adev);
 574         gmc_v11_0_set_gmc_funcs(adev);
 575         gmc_v11_0_set_irq_funcs(adev);
 576         gmc_v11_0_set_umc_funcs(adev);
 577
 578         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 579         adev->gmc.shared_aperture_end =
 580                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 581         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 582         adev->gmc.private_aperture_end =
 583                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 584
 585         return 0;
 586 }
 587
 588 static int gmc_v11_0_late_init(void *handle)
 589 {
 590         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 591         int r;
 592
 593         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 594         if (r)
 595                 return r;
 596
 597         r = amdgpu_gmc_ras_late_init(adev);
 598         if (r)
 599                 return r;
 600
 601         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 602 }
 603
 604 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
 605                                         struct amdgpu_gmc *mc)
 606 {
 607         u64 base = 0;
 608
 609         base = adev->mmhub.funcs->get_fb_location(adev);
 610
 611         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 612         amdgpu_gmc_gart_location(adev, mc);
 613
 614         /* base offset of vram pages */
 615         adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
 616 }
 617
 618 /**
 619  * gmc_v11_0_mc_init - initialize the memory controller driver params
 620  *
 621  * @adev: amdgpu_device pointer
 622  *
 623  * Look up the amount of vram, vram width, and decide how to place
 624  * vram and gart within the GPU's physical address space.
 625  * Returns 0 for success.
 626  */
 627 static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
 628 {
 629         int r;
 630
 631         /* size in MB on si */
 632         adev->gmc.mc_vram_size =
 633                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 634         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 635
 636         if (!(adev->flags & AMD_IS_APU)) {
 637                 r = amdgpu_device_resize_fb_bar(adev);
 638                 if (r)
 639                         return r;
 640         }
 641         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 642         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 643
 644 #ifdef CONFIG_X86_64
 645         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 646                 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
 647                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 648         }
 649 #endif
 650         /* In case the PCI BAR is larger than the actual amount of vram */
 651         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 652         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 653                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 654
 655         /* set the gart size */
 656         if (amdgpu_gart_size == -1) {
 657                 adev->gmc.gart_size = 512ULL << 20;
 658         } else
 659                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 660
 661         gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
 662
 663         return 0;
 664 }
 665
 666 static int gmc_v11_0_gart_init(struct amdgpu_device *adev)
 667 {
 668         int r;
 669
 670         if (adev->gart.bo) {
 671                 WARN(1, "PCIE GART already initialized\n");
 672                 return 0;
 673         }
 674
 675         /* Initialize common gart structure */
 676         r = amdgpu_gart_init(adev);
 677         if (r)
 678                 return r;
 679
 680         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 681         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 682                                  AMDGPU_PTE_EXECUTABLE;
 683
 684         return amdgpu_gart_table_vram_alloc(adev);
 685 }
 686
 687 static int gmc_v11_0_sw_init(void *handle)
 688 {
 689         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 690         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 691
 692         adev->mmhub.funcs->init(adev);
 693
 694         spin_lock_init(&adev->gmc.invalidate_lock);
 695
 696         r = amdgpu_atomfirmware_get_vram_info(adev,
 697                                               &vram_width, &vram_type, &vram_vendor);
 698         adev->gmc.vram_width = vram_width;
 699
 700         adev->gmc.vram_type = vram_type;
 701         adev->gmc.vram_vendor = vram_vendor;
 702
 703         switch (adev->ip_versions[GC_HWIP][0]) {
 704         case IP_VERSION(11, 0, 0):
 705         case IP_VERSION(11, 0, 1):
 706         case IP_VERSION(11, 0, 2):
 707                 adev->num_vmhubs = 2;
 708                 /*
 709                  * To fulfill 4-level page support,
 710                  * vm size is 256TB (48bit), maximum size,
 711                  * block size 512 (9bit)
 712                  */
 713                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 714                 break;
 715         default:
 716                 break;
 717         }
 718
 719         /* This interrupt is VMC page fault.*/
 720         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,
 721                               VMC_1_0__SRCID__VM_FAULT,
 722                               &adev->gmc.vm_fault);
 723
 724         if (r)
 725                 return r;
 726
 727         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
 728                               UTCL2_1_0__SRCID__FAULT,
 729                               &adev->gmc.vm_fault);
 730         if (r)
 731                 return r;
 732
 733         if (!amdgpu_sriov_vf(adev)) {
 734                 /* interrupt sent to DF. */
 735                 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
 736                                       &adev->gmc.ecc_irq);
 737                 if (r)
 738                         return r;
 739         }
 740
 741         /*
 742          * Set the internal MC address mask This is the max address of the GPU's
 743          * internal address space.
 744          */
 745         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 746
 747         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 748         if (r) {
 749                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 750                 return r;
 751         }
 752
 753         r = gmc_v11_0_mc_init(adev);
 754         if (r)
 755                 return r;
 756
 757         amdgpu_gmc_get_vbios_allocations(adev);
 758
 759         /* Memory manager */
 760         r = amdgpu_bo_init(adev);
 761         if (r)
 762                 return r;
 763
 764         r = gmc_v11_0_gart_init(adev);
 765         if (r)
 766                 return r;
 767
 768         /*
 769          * number of VMs
 770          * VMID 0 is reserved for System
 771          * amdgpu graphics/compute will use VMIDs 1-7
 772          * amdkfd will use VMIDs 8-15
 773          */
 774         adev->vm_manager.first_kfd_vmid = 8;
 775
 776         amdgpu_vm_manager_init(adev);
 777
 778         return 0;
 779 }
 780
 781 /**
 782  * gmc_v11_0_gart_fini - vm fini callback
 783  *
 784  * @adev: amdgpu_device pointer
 785  *
 786  * Tears down the driver GART/VM setup (CIK).
 787  */
 788 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)
 789 {
 790         amdgpu_gart_table_vram_free(adev);
 791 }
 792
 793 static int gmc_v11_0_sw_fini(void *handle)
 794 {
 795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 796
 797         amdgpu_vm_manager_fini(adev);
 798         gmc_v11_0_gart_fini(adev);
 799         amdgpu_gem_force_release(adev);
 800         amdgpu_bo_fini(adev);
 801
 802         return 0;
 803 }
 804
 805 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
 806 {
 807 }
 808
 809 /**
 810  * gmc_v11_0_gart_enable - gart enable
 811  *
 812  * @adev: amdgpu_device pointer
 813  */
 814 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
 815 {
 816         int r;
 817         bool value;
 818
 819         if (adev->gart.bo == NULL) {
 820                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 821                 return -EINVAL;
 822         }
 823
 824         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 825
 826         r = adev->mmhub.funcs->gart_enable(adev);
 827         if (r)
 828                 return r;
 829
 830         /* Flush HDP after it is initialized */
 831         adev->hdp.funcs->flush_hdp(adev, NULL);
 832
 833         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
 834                 false : true;
 835
 836         adev->mmhub.funcs->set_fault_enable_default(adev, value);
 837         gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
 838
 839         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 840                  (unsigned)(adev->gmc.gart_size >> 20),
 841                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 842
 843         return 0;
 844 }
 845
 846 static int gmc_v11_0_hw_init(void *handle)
 847 {
 848         int r;
 849         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 850
 851         /* The sequence of these two function calls matters.*/
 852         gmc_v11_0_init_golden_registers(adev);
 853
 854         r = gmc_v11_0_gart_enable(adev);
 855         if (r)
 856                 return r;
 857
 858         if (adev->umc.funcs && adev->umc.funcs->init_registers)
 859                 adev->umc.funcs->init_registers(adev);
 860
 861         return 0;
 862 }
 863
 864 /**
 865  * gmc_v11_0_gart_disable - gart disable
 866  *
 867  * @adev: amdgpu_device pointer
 868  *
 869  * This disables all VM page table.
 870  */
 871 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)
 872 {
 873         adev->mmhub.funcs->gart_disable(adev);
 874 }
 875
 876 static int gmc_v11_0_hw_fini(void *handle)
 877 {
 878         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 879
 880         if (amdgpu_sriov_vf(adev)) {
 881                 /* full access mode, so don't touch any GMC register */
 882                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 883                 return 0;
 884         }
 885
 886         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
 887         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 888         gmc_v11_0_gart_disable(adev);
 889
 890         return 0;
 891 }
 892
 893 static int gmc_v11_0_suspend(void *handle)
 894 {
 895         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 896
 897         gmc_v11_0_hw_fini(adev);
 898
 899         return 0;
 900 }
 901
 902 static int gmc_v11_0_resume(void *handle)
 903 {
 904         int r;
 905         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 906
 907         r = gmc_v11_0_hw_init(adev);
 908         if (r)
 909                 return r;
 910
 911         amdgpu_vmid_reset_all(adev);
 912
 913         return 0;
 914 }
 915
 916 static bool gmc_v11_0_is_idle(void *handle)
 917 {
 918         /* MC is always ready in GMC v11.*/
 919         return true;
 920 }
 921
 922 static int gmc_v11_0_wait_for_idle(void *handle)
 923 {
 924         /* There is no need to wait for MC idle in GMC v11.*/
 925         return 0;
 926 }
 927
 928 static int gmc_v11_0_soft_reset(void *handle)
 929 {
 930         return 0;
 931 }
 932
 933 static int gmc_v11_0_set_clockgating_state(void *handle,
 934                                            enum amd_clockgating_state state)
 935 {
 936         int r;
 937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 938
 939         r = adev->mmhub.funcs->set_clockgating(adev, state);
 940         if (r)
 941                 return r;
 942
 943         return athub_v3_0_set_clockgating(adev, state);
 944 }
 945
 946 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
 947 {
 948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 949
 950         adev->mmhub.funcs->get_clockgating(adev, flags);
 951
 952         athub_v3_0_get_clockgating(adev, flags);
 953 }
 954
 955 static int gmc_v11_0_set_powergating_state(void *handle,
 956                                            enum amd_powergating_state state)
 957 {
 958         return 0;
 959 }
 960
 961 const struct amd_ip_funcs gmc_v11_0_ip_funcs = {
 962         .name = "gmc_v11_0",
 963         .early_init = gmc_v11_0_early_init,
 964         .sw_init = gmc_v11_0_sw_init,
 965         .hw_init = gmc_v11_0_hw_init,
 966         .late_init = gmc_v11_0_late_init,
 967         .sw_fini = gmc_v11_0_sw_fini,
 968         .hw_fini = gmc_v11_0_hw_fini,
 969         .suspend = gmc_v11_0_suspend,
 970         .resume = gmc_v11_0_resume,
 971         .is_idle = gmc_v11_0_is_idle,
 972         .wait_for_idle = gmc_v11_0_wait_for_idle,
 973         .soft_reset = gmc_v11_0_soft_reset,
 974         .set_clockgating_state = gmc_v11_0_set_clockgating_state,
 975         .set_powergating_state = gmc_v11_0_set_powergating_state,
 976         .get_clockgating_state = gmc_v11_0_get_clockgating_state,
 977 };
 978
 979 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = {
 980         .type = AMD_IP_BLOCK_TYPE_GMC,
 981         .major = 11,
 982         .minor = 0,
 983         .rev = 0,
 984         .funcs = &gmc_v11_0_ip_funcs,
 985 };