drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_fixed.h>
  35
  36 #include "dm_services.h"
  37 #include "amdgpu.h"
  38 #include "dc.h"
  39 #include "amdgpu_dm.h"
  40 #include "amdgpu_dm_irq.h"
  41 #include "amdgpu_dm_mst_types.h"
  42 #include "dpcd_defs.h"
  43 #include "dc/inc/core_types.h"
  44
  45 #include "dm_helpers.h"
  46 #include "ddc_service_types.h"
  47
  48 static u32 edid_extract_panel_id(struct edid *edid)
  49 {
  50         return (u32)edid->mfg_id[0] << 24   |
  51                (u32)edid->mfg_id[1] << 16   |
  52                (u32)EDID_PRODUCT_ID(edid);
  53 }
  54
  55 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
  56 {
  57         uint32_t panel_id = edid_extract_panel_id(edid);
  58
  59         switch (panel_id) {
  60         /* Workaround for some monitors which does not work well with FAMS */
  61         case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  62         case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  63         case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  64                 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
  65                 edid_caps->panel_patch.disable_fams = true;
  66                 break;
  67         /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
  68         case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
  69         case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
  70         case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):
  71         case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):
  72         case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003):
  73                 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
  74                 edid_caps->panel_patch.remove_sink_ext_caps = true;
  75                 break;
  76         default:
  77                 return;
  78         }
  79 }
  80
  81 /**
  82  * dm_helpers_parse_edid_caps() - Parse edid caps
  83  *
  84  * @link: current detected link
  85  * @edid:       [in] pointer to edid
  86  * @edid_caps:  [in] pointer to edid caps
  87  *
  88  * Return: void
  89  */
  90 enum dc_edid_status dm_helpers_parse_edid_caps(
  91                 struct dc_link *link,
  92                 const struct dc_edid *edid,
  93                 struct dc_edid_caps *edid_caps)
  94 {
  95         struct amdgpu_dm_connector *aconnector = link->priv;
  96         struct drm_connector *connector = &aconnector->base;
  97         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  98         struct cea_sad *sads;
  99         int sad_count = -1;
 100         int sadb_count = -1;
 101         int i = 0;
 102         uint8_t *sadb = NULL;
 103
 104         enum dc_edid_status result = EDID_OK;
 105
 106         if (!edid_caps || !edid)
 107                 return EDID_BAD_INPUT;
 108
 109         if (!drm_edid_is_valid(edid_buf))
 110                 result = EDID_BAD_CHECKSUM;
 111
 112         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 113                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
 114         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 115                                         ((uint16_t) edid_buf->prod_code[1])<<8;
 116         edid_caps->serial_number = edid_buf->serial;
 117         edid_caps->manufacture_week = edid_buf->mfg_week;
 118         edid_caps->manufacture_year = edid_buf->mfg_year;
 119
 120         drm_edid_get_monitor_name(edid_buf,
 121                                   edid_caps->display_name,
 122                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 123
 124         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 125
 126         apply_edid_quirks(edid_buf, edid_caps);
 127
 128         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 129         if (sad_count <= 0)
 130                 return result;
 131
 132         edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 133         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 134                 struct cea_sad *sad = &sads[i];
 135
 136                 edid_caps->audio_modes[i].format_code = sad->format;
 137                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 138                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 139                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 140         }
 141
 142         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 143
 144         if (sadb_count < 0) {
 145                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 146                 sadb_count = 0;
 147         }
 148
 149         if (sadb_count)
 150                 edid_caps->speaker_flags = sadb[0];
 151         else
 152                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 153
 154         kfree(sads);
 155         kfree(sadb);
 156
 157         return result;
 158 }
 159
 160 static void
 161 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 162                                    bool enable,
 163                                    struct drm_dp_mst_atomic_payload *target_payload,
 164                                    struct dc_dp_mst_stream_allocation_table *table)
 165 {
 166         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 167         struct dc_dp_mst_stream_allocation *sa;
 168         struct link_mst_stream_allocation_table copy_of_link_table =
 169                                                                                 link->mst_stream_alloc_table;
 170
 171         int i;
 172         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 173         struct link_mst_stream_allocation *dc_alloc;
 174
 175         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 176         if (enable) {
 177                 dc_alloc =
 178                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 179                 dc_alloc->vcp_id = target_payload->vcpi;
 180                 dc_alloc->slot_count = target_payload->time_slots;
 181         } else {
 182                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 183                         dc_alloc =
 184                         &copy_of_link_table.stream_allocations[i];
 185
 186                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 187                                 dc_alloc->vcp_id = 0;
 188                                 dc_alloc->slot_count = 0;
 189                                 break;
 190                         }
 191                 }
 192                 ASSERT(i != copy_of_link_table.stream_count);
 193         }
 194
 195         /* Fill payload info*/
 196         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 197                 dc_alloc =
 198                         &copy_of_link_table.stream_allocations[i];
 199                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 200                         sa = &new_table.stream_allocations[new_table.stream_count];
 201                         sa->slot_count = dc_alloc->slot_count;
 202                         sa->vcp_id = dc_alloc->vcp_id;
 203                         new_table.stream_count++;
 204                 }
 205         }
 206
 207         /* Overwrite the old table */
 208         *table = new_table;
 209 }
 210
 211 void dm_helpers_dp_update_branch_info(
 212         struct dc_context *ctx,
 213         const struct dc_link *link)
 214 {}
 215
 216 static void dm_helpers_construct_old_payload(
 217                         struct drm_dp_mst_topology_mgr *mgr,
 218                         struct drm_dp_mst_topology_state *mst_state,
 219                         struct drm_dp_mst_atomic_payload *new_payload,
 220                         struct drm_dp_mst_atomic_payload *old_payload)
 221 {
 222         struct drm_dp_mst_atomic_payload *pos;
 223         int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);
 224         u8 next_payload_vc_start = mgr->next_start_slot;
 225         u8 payload_vc_start = new_payload->vc_start_slot;
 226         u8 allocated_time_slots;
 227
 228         *old_payload = *new_payload;
 229
 230         /* Set correct time_slots/PBN of old payload.
 231          * other fields (delete & dsc_enabled) in
 232          * struct drm_dp_mst_atomic_payload are don't care fields
 233          * while calling drm_dp_remove_payload_part2()
 234          */
 235         list_for_each_entry(pos, &mst_state->payloads, next) {
 236                 if (pos != new_payload &&
 237                     pos->vc_start_slot > payload_vc_start &&
 238                     pos->vc_start_slot < next_payload_vc_start)
 239                         next_payload_vc_start = pos->vc_start_slot;
 240         }
 241
 242         allocated_time_slots = next_payload_vc_start - payload_vc_start;
 243
 244         old_payload->time_slots = allocated_time_slots;
 245         old_payload->pbn = allocated_time_slots * pbn_per_slot;
 246 }
 247
 248 /*
 249  * Writes payload allocation table in immediate downstream device.
 250  */
 251 bool dm_helpers_dp_mst_write_payload_allocation_table(
 252                 struct dc_context *ctx,
 253                 const struct dc_stream_state *stream,
 254                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 255                 bool enable)
 256 {
 257         struct amdgpu_dm_connector *aconnector;
 258         struct drm_dp_mst_topology_state *mst_state;
 259         struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 260         struct drm_dp_mst_topology_mgr *mst_mgr;
 261
 262         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 263         /* Accessing the connector state is required for vcpi_slots allocation
 264          * and directly relies on behaviour in commit check
 265          * that blocks before commit guaranteeing that the state
 266          * is not gonna be swapped while still in use in commit tail
 267          */
 268
 269         if (!aconnector || !aconnector->mst_root)
 270                 return false;
 271
 272         mst_mgr = &aconnector->mst_root->mst_mgr;
 273         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 274         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 275
 276         if (enable) {
 277                 target_payload = new_payload;
 278
 279                 /* It's OK for this to fail */
 280                 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 281         } else {
 282                 /* construct old payload by VCPI*/
 283                 dm_helpers_construct_old_payload(mst_mgr, mst_state,
 284                                                  new_payload, &old_payload);
 285                 target_payload = &old_payload;
 286
 287                 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
 288         }
 289
 290         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 291          * AUX message. The sequence is slot 1-63 allocated sequence for each
 292          * stream. AMD ASIC stream slot allocation should follow the same
 293          * sequence. copy DRM MST allocation to dc
 294          */
 295         fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 296
 297         return true;
 298 }
 299
 300 /*
 301  * poll pending down reply
 302  */
 303 void dm_helpers_dp_mst_poll_pending_down_reply(
 304         struct dc_context *ctx,
 305         const struct dc_link *link)
 306 {}
 307
 308 /*
 309  * Clear payload allocation table before enable MST DP link.
 310  */
 311 void dm_helpers_dp_mst_clear_payload_allocation_table(
 312         struct dc_context *ctx,
 313         const struct dc_link *link)
 314 {}
 315
 316 /*
 317  * Polls for ACT (allocation change trigger) handled and sends
 318  * ALLOCATE_PAYLOAD message.
 319  */
 320 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 321                 struct dc_context *ctx,
 322                 const struct dc_stream_state *stream)
 323 {
 324         struct amdgpu_dm_connector *aconnector;
 325         struct drm_dp_mst_topology_mgr *mst_mgr;
 326         int ret;
 327
 328         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 329
 330         if (!aconnector || !aconnector->mst_root)
 331                 return ACT_FAILED;
 332
 333         mst_mgr = &aconnector->mst_root->mst_mgr;
 334
 335         if (!mst_mgr->mst_state)
 336                 return ACT_FAILED;
 337
 338         ret = drm_dp_check_act_status(mst_mgr);
 339
 340         if (ret)
 341                 return ACT_FAILED;
 342
 343         return ACT_SUCCESS;
 344 }
 345
 346 void dm_helpers_dp_mst_send_payload_allocation(
 347                 struct dc_context *ctx,
 348                 const struct dc_stream_state *stream)
 349 {
 350         struct amdgpu_dm_connector *aconnector;
 351         struct drm_dp_mst_topology_state *mst_state;
 352         struct drm_dp_mst_topology_mgr *mst_mgr;
 353         struct drm_dp_mst_atomic_payload *new_payload;
 354         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 355         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 356         int ret = 0;
 357
 358         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 359
 360         if (!aconnector || !aconnector->mst_root)
 361                 return;
 362
 363         mst_mgr = &aconnector->mst_root->mst_mgr;
 364         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 365         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 366
 367         ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
 368
 369         if (ret) {
 370                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 371                         set_flag, false);
 372         } else {
 373                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 374                         set_flag, true);
 375                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 376                         clr_flag, false);
 377         }
 378 }
 379
 380 void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(
 381                 struct dc_context *ctx,
 382                 const struct dc_stream_state *stream)
 383 {
 384         struct amdgpu_dm_connector *aconnector;
 385         struct drm_dp_mst_topology_state *mst_state;
 386         struct drm_dp_mst_topology_mgr *mst_mgr;
 387         struct drm_dp_mst_atomic_payload *new_payload, old_payload;
 388         enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 389         enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 390
 391         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 392
 393         if (!aconnector || !aconnector->mst_root)
 394                 return;
 395
 396         mst_mgr = &aconnector->mst_root->mst_mgr;
 397         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 398         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 399         dm_helpers_construct_old_payload(mst_mgr, mst_state,
 400                                          new_payload, &old_payload);
 401
 402         drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);
 403
 404         amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true);
 405         amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false);
 406  }
 407
 408 void dm_dtn_log_begin(struct dc_context *ctx,
 409         struct dc_log_buffer_ctx *log_ctx)
 410 {
 411         static const char msg[] = "[dtn begin]\n";
 412
 413         if (!log_ctx) {
 414                 pr_info("%s", msg);
 415                 return;
 416         }
 417
 418         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 419 }
 420
 421 __printf(3, 4)
 422 void dm_dtn_log_append_v(struct dc_context *ctx,
 423         struct dc_log_buffer_ctx *log_ctx,
 424         const char *msg, ...)
 425 {
 426         va_list args;
 427         size_t total;
 428         int n;
 429
 430         if (!log_ctx) {
 431                 /* No context, redirect to dmesg. */
 432                 struct va_format vaf;
 433
 434                 vaf.fmt = msg;
 435                 vaf.va = &args;
 436
 437                 va_start(args, msg);
 438                 pr_info("%pV", &vaf);
 439                 va_end(args);
 440
 441                 return;
 442         }
 443
 444         /* Measure the output. */
 445         va_start(args, msg);
 446         n = vsnprintf(NULL, 0, msg, args);
 447         va_end(args);
 448
 449         if (n <= 0)
 450                 return;
 451
 452         /* Reallocate the string buffer as needed. */
 453         total = log_ctx->pos + n + 1;
 454
 455         if (total > log_ctx->size) {
 456                 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 457
 458                 if (buf) {
 459                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 460                         kfree(log_ctx->buf);
 461
 462                         log_ctx->buf = buf;
 463                         log_ctx->size = total;
 464                 }
 465         }
 466
 467         if (!log_ctx->buf)
 468                 return;
 469
 470         /* Write the formatted string to the log buffer. */
 471         va_start(args, msg);
 472         n = vscnprintf(
 473                 log_ctx->buf + log_ctx->pos,
 474                 log_ctx->size - log_ctx->pos,
 475                 msg,
 476                 args);
 477         va_end(args);
 478
 479         if (n > 0)
 480                 log_ctx->pos += n;
 481 }
 482
 483 void dm_dtn_log_end(struct dc_context *ctx,
 484         struct dc_log_buffer_ctx *log_ctx)
 485 {
 486         static const char msg[] = "[dtn end]\n";
 487
 488         if (!log_ctx) {
 489                 pr_info("%s", msg);
 490                 return;
 491         }
 492
 493         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 494 }
 495
 496 bool dm_helpers_dp_mst_start_top_mgr(
 497                 struct dc_context *ctx,
 498                 const struct dc_link *link,
 499                 bool boot)
 500 {
 501         struct amdgpu_dm_connector *aconnector = link->priv;
 502         int ret;
 503
 504         if (!aconnector) {
 505                 DRM_ERROR("Failed to find connector for link!");
 506                 return false;
 507         }
 508
 509         if (boot) {
 510                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 511                                         aconnector, aconnector->base.base.id);
 512                 return true;
 513         }
 514
 515         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 516                         aconnector, aconnector->base.base.id);
 517
 518         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 519         if (ret < 0) {
 520                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 521                 return false;
 522         }
 523
 524         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 525                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 526
 527         return true;
 528 }
 529
 530 bool dm_helpers_dp_mst_stop_top_mgr(
 531                 struct dc_context *ctx,
 532                 struct dc_link *link)
 533 {
 534         struct amdgpu_dm_connector *aconnector = link->priv;
 535
 536         if (!aconnector) {
 537                 DRM_ERROR("Failed to find connector for link!");
 538                 return false;
 539         }
 540
 541         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 542                         aconnector, aconnector->base.base.id);
 543
 544         if (aconnector->mst_mgr.mst_state == true) {
 545                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 546                 link->cur_link_settings.lane_count = 0;
 547         }
 548
 549         return false;
 550 }
 551
 552 bool dm_helpers_dp_read_dpcd(
 553                 struct dc_context *ctx,
 554                 const struct dc_link *link,
 555                 uint32_t address,
 556                 uint8_t *data,
 557                 uint32_t size)
 558 {
 559
 560         struct amdgpu_dm_connector *aconnector = link->priv;
 561
 562         if (!aconnector)
 563                 return false;
 564
 565         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 566                                 size) == size;
 567 }
 568
 569 bool dm_helpers_dp_write_dpcd(
 570                 struct dc_context *ctx,
 571                 const struct dc_link *link,
 572                 uint32_t address,
 573                 const uint8_t *data,
 574                 uint32_t size)
 575 {
 576         struct amdgpu_dm_connector *aconnector = link->priv;
 577
 578         if (!aconnector) {
 579                 DRM_ERROR("Failed to find connector for link!");
 580                 return false;
 581         }
 582
 583         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 584                         address, (uint8_t *)data, size) > 0;
 585 }
 586
 587 bool dm_helpers_submit_i2c(
 588                 struct dc_context *ctx,
 589                 const struct dc_link *link,
 590                 struct i2c_command *cmd)
 591 {
 592         struct amdgpu_dm_connector *aconnector = link->priv;
 593         struct i2c_msg *msgs;
 594         int i = 0;
 595         int num = cmd->number_of_payloads;
 596         bool result;
 597
 598         if (!aconnector) {
 599                 DRM_ERROR("Failed to find connector for link!");
 600                 return false;
 601         }
 602
 603         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 604
 605         if (!msgs)
 606                 return false;
 607
 608         for (i = 0; i < num; i++) {
 609                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 610                 msgs[i].addr = cmd->payloads[i].address;
 611                 msgs[i].len = cmd->payloads[i].length;
 612                 msgs[i].buf = cmd->payloads[i].data;
 613         }
 614
 615         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 616
 617         kfree(msgs);
 618
 619         return result;
 620 }
 621
 622 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 623                 bool is_write_cmd,
 624                 unsigned char cmd,
 625                 unsigned int length,
 626                 unsigned int offset,
 627                 unsigned char *data)
 628 {
 629         bool success = false;
 630         unsigned char rc_data[16] = {0};
 631         unsigned char rc_offset[4] = {0};
 632         unsigned char rc_length[2] = {0};
 633         unsigned char rc_cmd = 0;
 634         unsigned char rc_result = 0xFF;
 635         unsigned char i = 0;
 636         int ret;
 637
 638         if (is_write_cmd) {
 639                 // write rc data
 640                 memmove(rc_data, data, length);
 641                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 642         }
 643
 644         // write rc offset
 645         rc_offset[0] = (unsigned char) offset & 0xFF;
 646         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 647         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 648         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 649         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 650
 651         // write rc length
 652         rc_length[0] = (unsigned char) length & 0xFF;
 653         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 654         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 655
 656         // write rc cmd
 657         rc_cmd = cmd | 0x80;
 658         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 659
 660         if (ret < 0) {
 661                 DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 662                 return false;
 663         }
 664
 665         // poll until active is 0
 666         for (i = 0; i < 10; i++) {
 667                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 668                 if (rc_cmd == cmd)
 669                         // active is 0
 670                         break;
 671                 msleep(10);
 672         }
 673
 674         // read rc result
 675         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 676         success = (rc_result == 0);
 677
 678         if (success && !is_write_cmd) {
 679                 // read rc data
 680                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 681         }
 682
 683         drm_dbg_dp(aux->drm_dev, "success = %d\n", success);
 684
 685         return success;
 686 }
 687
 688 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 689 {
 690         unsigned char data[16] = {0};
 691
 692         drm_dbg_dp(aux->drm_dev, "Start\n");
 693
 694         // Step 2
 695         data[0] = 'P';
 696         data[1] = 'R';
 697         data[2] = 'I';
 698         data[3] = 'U';
 699         data[4] = 'S';
 700
 701         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 702                 return;
 703
 704         // Step 3 and 4
 705         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 706                 return;
 707
 708         data[0] &= (~(1 << 1)); // set bit 1 to 0
 709         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 710                 return;
 711
 712         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 713                 return;
 714
 715         data[0] &= (~(1 << 1)); // set bit 1 to 0
 716         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 717                 return;
 718
 719         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 720                 return;
 721
 722         data[0] &= (~(1 << 1)); // set bit 1 to 0
 723         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 724                 return;
 725
 726         // Step 3 and 5
 727         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 728                 return;
 729
 730         data[0] |= (1 << 1); // set bit 1 to 1
 731         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 732                 return;
 733
 734         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 735                 return;
 736
 737         data[0] |= (1 << 1); // set bit 1 to 1
 738
 739         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 740                 return;
 741
 742         data[0] |= (1 << 1); // set bit 1 to 1
 743         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 744                 return;
 745
 746         // Step 6
 747         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 748                 return;
 749
 750         drm_dbg_dp(aux->drm_dev, "Done\n");
 751 }
 752
 753 /* MST Dock */
 754 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 755
 756 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 757                 struct drm_dp_aux *aux,
 758                 const struct dc_stream_state *stream,
 759                 bool enable)
 760 {
 761         uint8_t ret = 0;
 762
 763         drm_dbg_dp(aux->drm_dev,
 764                    "Configure DSC to non-virtual dpcd synaptics\n");
 765
 766         if (enable) {
 767                 /* When DSC is enabled on previous boot and reboot with the hub,
 768                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 769                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 770                  */
 771                 if (!stream->link->link_status.link_active &&
 772                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 773                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 774                         apply_synaptics_fifo_reset_wa(aux);
 775
 776                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 777                 DRM_INFO("Send DSC enable to synaptics\n");
 778
 779         } else {
 780                 /* Synaptics hub not support virtual dpcd,
 781                  * external monitor occur garbage while disable DSC,
 782                  * Disable DSC only when entire link status turn to false,
 783                  */
 784                 if (!stream->link->link_status.link_active) {
 785                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 786                         DRM_INFO("Send DSC disable to synaptics\n");
 787                 }
 788         }
 789
 790         return ret;
 791 }
 792
 793 bool dm_helpers_dp_write_dsc_enable(
 794                 struct dc_context *ctx,
 795                 const struct dc_stream_state *stream,
 796                 bool enable)
 797 {
 798         static const uint8_t DSC_DISABLE;
 799         static const uint8_t DSC_DECODING = 0x01;
 800         static const uint8_t DSC_PASSTHROUGH = 0x02;
 801
 802         struct amdgpu_dm_connector *aconnector =
 803                 (struct amdgpu_dm_connector *)stream->dm_stream_context;
 804         struct drm_device *dev = aconnector->base.dev;
 805         struct drm_dp_mst_port *port;
 806         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 807         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 808         uint8_t ret = 0;
 809
 810         if (!stream)
 811                 return false;
 812
 813         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 814                 if (!aconnector->dsc_aux)
 815                         return false;
 816
 817                 // apply w/a to synaptics
 818                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 819                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 820                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 821                                 aconnector->dsc_aux, stream, enable_dsc);
 822
 823                 port = aconnector->mst_output_port;
 824
 825                 if (enable) {
 826                         if (port->passthrough_aux) {
 827                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 828                                                         DP_DSC_ENABLE,
 829                                                         &enable_passthrough, 1);
 830                                 drm_dbg_dp(dev,
 831                                            "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 832                                            ret);
 833                         }
 834
 835                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 836                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 837                         drm_dbg_dp(dev,
 838                                    "Sent DSC decoding enable to %s port, ret = %u\n",
 839                                    (port->passthrough_aux) ? "remote RX" :
 840                                    "virtual dpcd",
 841                                    ret);
 842                 } else {
 843                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 844                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 845                         drm_dbg_dp(dev,
 846                                    "Sent DSC decoding disable to %s port, ret = %u\n",
 847                                    (port->passthrough_aux) ? "remote RX" :
 848                                    "virtual dpcd",
 849                                    ret);
 850
 851                         if (port->passthrough_aux) {
 852                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 853                                                         DP_DSC_ENABLE,
 854                                                         &enable_passthrough, 1);
 855                                 drm_dbg_dp(dev,
 856                                            "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 857                                            ret);
 858                         }
 859                 }
 860         }
 861
 862         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 863                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 864                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 865                         drm_dbg_dp(dev,
 866                                    "Send DSC %s to SST RX\n",
 867                                    enable_dsc ? "enable" : "disable");
 868                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 869                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 870                         drm_dbg_dp(dev,
 871                                    "Send DSC %s to DP-HDMI PCON\n",
 872                                    enable_dsc ? "enable" : "disable");
 873                 }
 874         }
 875
 876         return ret;
 877 }
 878
 879 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 880 {
 881         bool dp_sink_present;
 882         struct amdgpu_dm_connector *aconnector = link->priv;
 883
 884         if (!aconnector) {
 885                 BUG_ON("Failed to find connector for link!");
 886                 return true;
 887         }
 888
 889         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 890         dp_sink_present = dc_link_is_dp_sink_present(link);
 891         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 892         return dp_sink_present;
 893 }
 894
 895 enum dc_edid_status dm_helpers_read_local_edid(
 896                 struct dc_context *ctx,
 897                 struct dc_link *link,
 898                 struct dc_sink *sink)
 899 {
 900         struct amdgpu_dm_connector *aconnector = link->priv;
 901         struct drm_connector *connector = &aconnector->base;
 902         struct i2c_adapter *ddc;
 903         int retry = 3;
 904         enum dc_edid_status edid_status;
 905         struct edid *edid;
 906
 907         if (link->aux_mode)
 908                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 909         else
 910                 ddc = &aconnector->i2c->base;
 911
 912         /* some dongles read edid incorrectly the first time,
 913          * do check sum and retry to make sure read correct edid.
 914          */
 915         do {
 916
 917                 edid = drm_get_edid(&aconnector->base, ddc);
 918
 919                 /* DP Compliance Test 4.2.2.6 */
 920                 if (link->aux_mode && connector->edid_corrupt)
 921                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 922
 923                 if (!edid && connector->edid_corrupt) {
 924                         connector->edid_corrupt = false;
 925                         return EDID_BAD_CHECKSUM;
 926                 }
 927
 928                 if (!edid)
 929                         return EDID_NO_RESPONSE;
 930
 931                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 932                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 933
 934                 /* We don't need the original edid anymore */
 935                 kfree(edid);
 936
 937                 edid_status = dm_helpers_parse_edid_caps(
 938                                                 link,
 939                                                 &sink->dc_edid,
 940                                                 &sink->edid_caps);
 941
 942         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 943
 944         if (edid_status != EDID_OK)
 945                 DRM_ERROR("EDID err: %d, on connector: %s",
 946                                 edid_status,
 947                                 aconnector->base.name);
 948         if (link->aux_mode) {
 949                 union test_request test_request = {0};
 950                 union test_response test_response = {0};
 951
 952                 dm_helpers_dp_read_dpcd(ctx,
 953                                         link,
 954                                         DP_TEST_REQUEST,
 955                                         &test_request.raw,
 956                                         sizeof(union test_request));
 957
 958                 if (!test_request.bits.EDID_READ)
 959                         return edid_status;
 960
 961                 test_response.bits.EDID_CHECKSUM_WRITE = 1;
 962
 963                 dm_helpers_dp_write_dpcd(ctx,
 964                                         link,
 965                                         DP_TEST_EDID_CHECKSUM,
 966                                         &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
 967                                         1);
 968
 969                 dm_helpers_dp_write_dpcd(ctx,
 970                                         link,
 971                                         DP_TEST_RESPONSE,
 972                                         &test_response.raw,
 973                                         sizeof(test_response));
 974
 975         }
 976
 977         return edid_status;
 978 }
 979 int dm_helper_dmub_aux_transfer_sync(
 980                 struct dc_context *ctx,
 981                 const struct dc_link *link,
 982                 struct aux_payload *payload,
 983                 enum aux_return_code_type *operation_result)
 984 {
 985         if (!link->hpd_status) {
 986                 *operation_result = AUX_RET_ERROR_HPD_DISCON;
 987                 return -1;
 988         }
 989
 990         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 991                         operation_result);
 992 }
 993
 994 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 995                 const struct dc_link *link,
 996                 struct set_config_cmd_payload *payload,
 997                 enum set_config_status *operation_result)
 998 {
 999         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
1000                         operation_result);
1001 }
1002
1003 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
1004 {
1005         /* TODO: something */
1006 }
1007
1008 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
1009 {
1010         // TODO:
1011         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
1012 }
1013
1014 void dm_helpers_init_panel_settings(
1015         struct dc_context *ctx,
1016         struct dc_panel_config *panel_config,
1017         struct dc_sink *sink)
1018 {
1019         // Extra Panel Power Sequence
1020         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
1021         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
1022         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
1023         panel_config->pps.extra_post_t7_ms = 0;
1024         panel_config->pps.extra_pre_t11_ms = 0;
1025         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
1026         panel_config->pps.extra_post_OUI_ms = 0;
1027         // Feature DSC
1028         panel_config->dsc.disable_dsc_edp = false;
1029         panel_config->dsc.force_dsc_edp_policy = 0;
1030 }
1031
1032 void dm_helpers_override_panel_settings(
1033         struct dc_context *ctx,
1034         struct dc_panel_config *panel_config)
1035 {
1036         // Feature DSC
1037         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1038                 panel_config->dsc.disable_dsc_edp = true;
1039 }
1040
1041 void *dm_helpers_allocate_gpu_mem(
1042                 struct dc_context *ctx,
1043                 enum dc_gpu_mem_alloc_type type,
1044                 size_t size,
1045                 long long *addr)
1046 {
1047         struct amdgpu_device *adev = ctx->driver_context;
1048
1049         return dm_allocate_gpu_mem(adev, type, size, addr);
1050 }
1051
1052 void dm_helpers_free_gpu_mem(
1053                 struct dc_context *ctx,
1054                 enum dc_gpu_mem_alloc_type type,
1055                 void *pvMem)
1056 {
1057         struct amdgpu_device *adev = ctx->driver_context;
1058         struct dal_allocation *da;
1059
1060         /* walk the da list in DM */
1061         list_for_each_entry(da, &adev->dm.da_list, list) {
1062                 if (pvMem == da->cpu_ptr) {
1063                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1064                         list_del(&da->list);
1065                         kfree(da);
1066                         break;
1067                 }
1068         }
1069 }
1070
1071 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1072 {
1073         enum dc_irq_source irq_source;
1074         bool ret;
1075
1076         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1077
1078         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1079
1080         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1081                          enable ? "en" : "dis", ret);
1082         return ret;
1083 }
1084
1085 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1086 {
1087         /* TODO: virtual DPCD */
1088         struct dc_link *link = stream->link;
1089         union down_spread_ctrl old_downspread;
1090         union down_spread_ctrl new_downspread;
1091
1092         if (link->aux_access_disabled)
1093                 return;
1094
1095         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1096                                      &old_downspread.raw,
1097                                      sizeof(old_downspread)))
1098                 return;
1099
1100         new_downspread.raw = old_downspread.raw;
1101         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1102                 (stream->ignore_msa_timing_param) ? 1 : 0;
1103
1104         if (new_downspread.raw != old_downspread.raw)
1105                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1106                                          &new_downspread.raw,
1107                                          sizeof(new_downspread));
1108 }
1109
1110 bool dm_helpers_dp_handle_test_pattern_request(
1111                 struct dc_context *ctx,
1112                 const struct dc_link *link,
1113                 union link_test_pattern dpcd_test_pattern,
1114                 union test_misc dpcd_test_params)
1115 {
1116         enum dp_test_pattern test_pattern;
1117         enum dp_test_pattern_color_space test_pattern_color_space =
1118                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1119         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1120         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1121         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1122         struct pipe_ctx *pipe_ctx = NULL;
1123         struct amdgpu_dm_connector *aconnector = link->priv;
1124         struct drm_device *dev = aconnector->base.dev;
1125         int i;
1126
1127         for (i = 0; i < MAX_PIPES; i++) {
1128                 if (pipes[i].stream == NULL)
1129                         continue;
1130
1131                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1132                         !pipes[i].prev_odm_pipe) {
1133                         pipe_ctx = &pipes[i];
1134                         break;
1135                 }
1136         }
1137
1138         if (pipe_ctx == NULL)
1139                 return false;
1140
1141         switch (dpcd_test_pattern.bits.PATTERN) {
1142         case LINK_TEST_PATTERN_COLOR_RAMP:
1143                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1144         break;
1145         case LINK_TEST_PATTERN_VERTICAL_BARS:
1146                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1147         break; /* black and white */
1148         case LINK_TEST_PATTERN_COLOR_SQUARES:
1149                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1150                                 TEST_DYN_RANGE_VESA ?
1151                                 DP_TEST_PATTERN_COLOR_SQUARES :
1152                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1153         break;
1154         default:
1155                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1156         break;
1157         }
1158
1159         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1160                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1161         else
1162                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1163                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1164                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1165
1166         switch (dpcd_test_params.bits.BPC) {
1167         case 0: // 6 bits
1168                 requestColorDepth = COLOR_DEPTH_666;
1169                 break;
1170         case 1: // 8 bits
1171                 requestColorDepth = COLOR_DEPTH_888;
1172                 break;
1173         case 2: // 10 bits
1174                 requestColorDepth = COLOR_DEPTH_101010;
1175                 break;
1176         case 3: // 12 bits
1177                 requestColorDepth = COLOR_DEPTH_121212;
1178                 break;
1179         default:
1180                 break;
1181         }
1182
1183         switch (dpcd_test_params.bits.CLR_FORMAT) {
1184         case 0:
1185                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1186                 break;
1187         case 1:
1188                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1189                 break;
1190         case 2:
1191                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1192                 break;
1193         default:
1194                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1195                 break;
1196         }
1197
1198         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1199                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1200                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1201                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1202                 drm_dbg(dev,
1203                         "original bpc %d pix encoding %d, changing to %d  %d\n",
1204                         pipe_ctx->stream->timing.display_color_depth,
1205                         pipe_ctx->stream->timing.pixel_encoding,
1206                         requestColorDepth,
1207                         requestPixelEncoding);
1208                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1209                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1210
1211                 dc_link_update_dsc_config(pipe_ctx);
1212
1213                 aconnector->timing_changed = true;
1214                 /* store current timing */
1215                 if (aconnector->timing_requested)
1216                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1217                 else
1218                         drm_err(dev, "timing storage failed\n");
1219
1220         }
1221
1222         pipe_ctx->stream->test_pattern.type = test_pattern;
1223         pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
1224
1225         dc_link_dp_set_test_pattern(
1226                 (struct dc_link *) link,
1227                 test_pattern,
1228                 test_pattern_color_space,
1229                 NULL,
1230                 NULL,
1231                 0);
1232
1233         return false;
1234 }
1235
1236 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1237 {
1238        // TODO
1239 }
1240
1241 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1242 {
1243         struct amdgpu_device *adev = ctx->driver_context;
1244
1245         if (adev->dm.idle_workqueue)
1246                 adev->dm.idle_workqueue->enable = enable;
1247 }
1248
1249 void dm_helpers_dp_mst_update_branch_bandwidth(
1250                 struct dc_context *ctx,
1251                 struct dc_link *link)
1252 {
1253         // TODO
1254 }
1255
1256 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1257 {
1258         bool ret_val = false;
1259
1260         switch (branch_dev_id) {
1261         case DP_BRANCH_DEVICE_ID_0060AD:
1262         case DP_BRANCH_DEVICE_ID_00E04C:
1263         case DP_BRANCH_DEVICE_ID_90CC24:
1264                 ret_val = true;
1265                 break;
1266         default:
1267                 break;
1268         }
1269
1270         return ret_val;
1271 }
1272
1273 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1274 {
1275         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1276         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1277
1278         switch (dpcd_caps->dongle_type) {
1279         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1280                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1281                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1282                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1283                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1284                 break;
1285         default:
1286                 break;
1287         }
1288
1289         return as_type;
1290 }