drivers/spi/spi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4  * Author: Addy Ke <[email protected]>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/pinctrl/consumer.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/scatterlist.h>
  17
  18 #define DRIVER_NAME "rockchip-spi"
  19
  20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  21                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  23                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  24
  25 /* SPI register offsets */
  26 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  27 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  28 #define ROCKCHIP_SPI_SSIENR                     0x0008
  29 #define ROCKCHIP_SPI_SER                        0x000c
  30 #define ROCKCHIP_SPI_BAUDR                      0x0010
  31 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  32 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  33 #define ROCKCHIP_SPI_TXFLR                      0x001c
  34 #define ROCKCHIP_SPI_RXFLR                      0x0020
  35 #define ROCKCHIP_SPI_SR                         0x0024
  36 #define ROCKCHIP_SPI_IPR                        0x0028
  37 #define ROCKCHIP_SPI_IMR                        0x002c
  38 #define ROCKCHIP_SPI_ISR                        0x0030
  39 #define ROCKCHIP_SPI_RISR                       0x0034
  40 #define ROCKCHIP_SPI_ICR                        0x0038
  41 #define ROCKCHIP_SPI_DMACR                      0x003c
  42 #define ROCKCHIP_SPI_DMATDLR                    0x0040
  43 #define ROCKCHIP_SPI_DMARDLR                    0x0044
  44 #define ROCKCHIP_SPI_VERSION                    0x0048
  45 #define ROCKCHIP_SPI_TXDR                       0x0400
  46 #define ROCKCHIP_SPI_RXDR                       0x0800
  47
  48 /* Bit fields in CTRLR0 */
  49 #define CR0_DFS_OFFSET                          0
  50 #define CR0_DFS_4BIT                            0x0
  51 #define CR0_DFS_8BIT                            0x1
  52 #define CR0_DFS_16BIT                           0x2
  53
  54 #define CR0_CFS_OFFSET                          2
  55
  56 #define CR0_SCPH_OFFSET                         6
  57
  58 #define CR0_SCPOL_OFFSET                        7
  59
  60 #define CR0_CSM_OFFSET                          8
  61 #define CR0_CSM_KEEP                            0x0
  62 /* ss_n be high for half sclk_out cycles */
  63 #define CR0_CSM_HALF                            0X1
  64 /* ss_n be high for one sclk_out cycle */
  65 #define CR0_CSM_ONE                                     0x2
  66
  67 /* ss_n to sclk_out delay */
  68 #define CR0_SSD_OFFSET                          10
  69 /*
  70  * The period between ss_n active and
  71  * sclk_out active is half sclk_out cycles
  72  */
  73 #define CR0_SSD_HALF                            0x0
  74 /*
  75  * The period between ss_n active and
  76  * sclk_out active is one sclk_out cycle
  77  */
  78 #define CR0_SSD_ONE                                     0x1
  79
  80 #define CR0_EM_OFFSET                           11
  81 #define CR0_EM_LITTLE                           0x0
  82 #define CR0_EM_BIG                                      0x1
  83
  84 #define CR0_FBM_OFFSET                          12
  85 #define CR0_FBM_MSB                                     0x0
  86 #define CR0_FBM_LSB                                     0x1
  87
  88 #define CR0_BHT_OFFSET                          13
  89 #define CR0_BHT_16BIT                           0x0
  90 #define CR0_BHT_8BIT                            0x1
  91
  92 #define CR0_RSD_OFFSET                          14
  93 #define CR0_RSD_MAX                             0x3
  94
  95 #define CR0_FRF_OFFSET                          16
  96 #define CR0_FRF_SPI                                     0x0
  97 #define CR0_FRF_SSP                                     0x1
  98 #define CR0_FRF_MICROWIRE                       0x2
  99
 100 #define CR0_XFM_OFFSET                          18
 101 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 102 #define CR0_XFM_TR                                      0x0
 103 #define CR0_XFM_TO                                      0x1
 104 #define CR0_XFM_RO                                      0x2
 105
 106 #define CR0_OPM_OFFSET                          20
 107 #define CR0_OPM_HOST                            0x0
 108 #define CR0_OPM_TARGET                          0x1
 109
 110 #define CR0_SOI_OFFSET                          23
 111
 112 #define CR0_MTM_OFFSET                          0x21
 113
 114 /* Bit fields in SER, 2bit */
 115 #define SER_MASK                                        0x3
 116
 117 /* Bit fields in BAUDR */
 118 #define BAUDR_SCKDV_MIN                         2
 119 #define BAUDR_SCKDV_MAX                         65534
 120
 121 /* Bit fields in SR, 6bit */
 122 #define SR_MASK                                         0x3f
 123 #define SR_BUSY                                         (1 << 0)
 124 #define SR_TF_FULL                                      (1 << 1)
 125 #define SR_TF_EMPTY                                     (1 << 2)
 126 #define SR_RF_EMPTY                                     (1 << 3)
 127 #define SR_RF_FULL                                      (1 << 4)
 128 #define SR_TARGET_TX_BUSY                               (1 << 5)
 129
 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 131 #define INT_MASK                                        0x1f
 132 #define INT_TF_EMPTY                            (1 << 0)
 133 #define INT_TF_OVERFLOW                         (1 << 1)
 134 #define INT_RF_UNDERFLOW                        (1 << 2)
 135 #define INT_RF_OVERFLOW                         (1 << 3)
 136 #define INT_RF_FULL                             (1 << 4)
 137 #define INT_CS_INACTIVE                         (1 << 6)
 138
 139 /* Bit fields in ICR, 4bit */
 140 #define ICR_MASK                                        0x0f
 141 #define ICR_ALL                                         (1 << 0)
 142 #define ICR_RF_UNDERFLOW                        (1 << 1)
 143 #define ICR_RF_OVERFLOW                         (1 << 2)
 144 #define ICR_TF_OVERFLOW                         (1 << 3)
 145
 146 /* Bit fields in DMACR */
 147 #define RF_DMA_EN                                       (1 << 0)
 148 #define TF_DMA_EN                                       (1 << 1)
 149
 150 /* Driver state flags */
 151 #define RXDMA                                   (1 << 0)
 152 #define TXDMA                                   (1 << 1)
 153
 154 /* sclk_out: spi host internal logic in rk3x can support 50Mhz */
 155 #define MAX_SCLK_OUT                            50000000U
 156
 157 /*
 158  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 159  * the controller seems to hang when given 0x10000, so stick with this for now.
 160  */
 161 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 162
 163 #define ROCKCHIP_SPI_MAX_NATIVE_CS_NUM          2
 164 #define ROCKCHIP_SPI_VER2_TYPE1                 0x05EC0002
 165 #define ROCKCHIP_SPI_VER2_TYPE2                 0x00110002
 166
 167 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT            2000
 168
 169 struct rockchip_spi {
 170         struct device *dev;
 171
 172         struct clk *spiclk;
 173         struct clk *apb_pclk;
 174
 175         void __iomem *regs;
 176         dma_addr_t dma_addr_rx;
 177         dma_addr_t dma_addr_tx;
 178
 179         const void *tx;
 180         void *rx;
 181         unsigned int tx_left;
 182         unsigned int rx_left;
 183
 184         atomic_t state;
 185
 186         /*depth of the FIFO buffer */
 187         u32 fifo_len;
 188         /* frequency of spiclk */
 189         u32 freq;
 190
 191         u8 n_bytes;
 192         u8 rsd;
 193
 194         bool target_abort;
 195         bool cs_inactive; /* spi target tansmition stop when cs inactive */
 196         bool cs_high_supported; /* native CS supports active-high polarity */
 197
 198         struct spi_transfer *xfer; /* Store xfer temporarily */
 199 };
 200
 201 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 202 {
 203         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 204 }
 205
 206 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool target_mode)
 207 {
 208         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 209
 210         do {
 211                 if (target_mode) {
 212                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) &&
 213                             !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
 214                                 return;
 215                 } else {
 216                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 217                                 return;
 218                 }
 219         } while (!time_after(jiffies, timeout));
 220
 221         dev_warn(rs->dev, "spi controller is in busy state!\n");
 222 }
 223
 224 static u32 get_fifo_len(struct rockchip_spi *rs)
 225 {
 226         u32 ver;
 227
 228         ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
 229
 230         switch (ver) {
 231         case ROCKCHIP_SPI_VER2_TYPE1:
 232         case ROCKCHIP_SPI_VER2_TYPE2:
 233                 return 64;
 234         default:
 235                 return 32;
 236         }
 237 }
 238
 239 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 240 {
 241         struct spi_controller *ctlr = spi->controller;
 242         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 243         bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
 244
 245         if (cs_asserted) {
 246                 /* Keep things powered as long as CS is asserted */
 247                 pm_runtime_get_sync(rs->dev);
 248
 249                 if (spi_get_csgpiod(spi, 0))
 250                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 251                 else
 252                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 253                                               BIT(spi_get_chipselect(spi, 0)));
 254         } else {
 255                 if (spi_get_csgpiod(spi, 0))
 256                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 257                 else
 258                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 259                                               BIT(spi_get_chipselect(spi, 0)));
 260
 261                 /* Drop reference from when we first asserted CS */
 262                 pm_runtime_put(rs->dev);
 263         }
 264 }
 265
 266 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
 267                                     struct spi_message *msg)
 268 {
 269         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 270
 271         /* stop running spi transfer
 272          * this also flushes both rx and tx fifos
 273          */
 274         spi_enable_chip(rs, false);
 275
 276         /* make sure all interrupts are masked and status cleared */
 277         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 278         writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 279
 280         if (atomic_read(&rs->state) & TXDMA)
 281                 dmaengine_terminate_async(ctlr->dma_tx);
 282
 283         if (atomic_read(&rs->state) & RXDMA)
 284                 dmaengine_terminate_async(ctlr->dma_rx);
 285 }
 286
 287 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 288 {
 289         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 290         u32 words = min(rs->tx_left, tx_free);
 291
 292         rs->tx_left -= words;
 293         for (; words; words--) {
 294                 u32 txw;
 295
 296                 if (rs->n_bytes == 1)
 297                         txw = *(u8 *)rs->tx;
 298                 else
 299                         txw = *(u16 *)rs->tx;
 300
 301                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 302                 rs->tx += rs->n_bytes;
 303         }
 304 }
 305
 306 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 307 {
 308         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 309         u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
 310
 311         /* the hardware doesn't allow us to change fifo threshold
 312          * level while spi is enabled, so instead make sure to leave
 313          * enough words in the rx fifo to get the last interrupt
 314          * exactly when all words have been received
 315          */
 316         if (rx_left) {
 317                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 318
 319                 if (rx_left < ftl) {
 320                         rx_left = ftl;
 321                         words = rs->rx_left - rx_left;
 322                 }
 323         }
 324
 325         rs->rx_left = rx_left;
 326         for (; words; words--) {
 327                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 328
 329                 if (!rs->rx)
 330                         continue;
 331
 332                 if (rs->n_bytes == 1)
 333                         *(u8 *)rs->rx = (u8)rxw;
 334                 else
 335                         *(u16 *)rs->rx = (u16)rxw;
 336                 rs->rx += rs->n_bytes;
 337         }
 338 }
 339
 340 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 341 {
 342         struct spi_controller *ctlr = dev_id;
 343         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 344
 345         /* When int_cs_inactive comes, spi target abort */
 346         if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
 347                 ctlr->target_abort(ctlr);
 348                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 349                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 350
 351                 return IRQ_HANDLED;
 352         }
 353
 354         if (rs->tx_left)
 355                 rockchip_spi_pio_writer(rs);
 356
 357         rockchip_spi_pio_reader(rs);
 358         if (!rs->rx_left) {
 359                 spi_enable_chip(rs, false);
 360                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 361                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 362                 spi_finalize_current_transfer(ctlr);
 363         }
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 369                                     struct spi_controller *ctlr,
 370                                     struct spi_transfer *xfer)
 371 {
 372         rs->tx = xfer->tx_buf;
 373         rs->rx = xfer->rx_buf;
 374         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 375         rs->rx_left = xfer->len / rs->n_bytes;
 376
 377         writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 378
 379         spi_enable_chip(rs, true);
 380
 381         if (rs->tx_left)
 382                 rockchip_spi_pio_writer(rs);
 383
 384         if (rs->cs_inactive)
 385                 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 386         else
 387                 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 388
 389         /* 1 means the transfer is in progress */
 390         return 1;
 391 }
 392
 393 static void rockchip_spi_dma_rxcb(void *data)
 394 {
 395         struct spi_controller *ctlr = data;
 396         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 397         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 398
 399         if (state & TXDMA && !rs->target_abort)
 400                 return;
 401
 402         if (rs->cs_inactive)
 403                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 404
 405         spi_enable_chip(rs, false);
 406         spi_finalize_current_transfer(ctlr);
 407 }
 408
 409 static void rockchip_spi_dma_txcb(void *data)
 410 {
 411         struct spi_controller *ctlr = data;
 412         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 413         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 414
 415         if (state & RXDMA && !rs->target_abort)
 416                 return;
 417
 418         /* Wait until the FIFO data completely. */
 419         wait_for_tx_idle(rs, ctlr->target);
 420
 421         spi_enable_chip(rs, false);
 422         spi_finalize_current_transfer(ctlr);
 423 }
 424
 425 static u32 rockchip_spi_calc_burst_size(u32 data_len)
 426 {
 427         u32 i;
 428
 429         /* burst size: 1, 2, 4, 8 */
 430         for (i = 1; i < 8; i <<= 1) {
 431                 if (data_len & i)
 432                         break;
 433         }
 434
 435         return i;
 436 }
 437
 438 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 439                 struct spi_controller *ctlr, struct spi_transfer *xfer)
 440 {
 441         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 442
 443         atomic_set(&rs->state, 0);
 444
 445         rs->tx = xfer->tx_buf;
 446         rs->rx = xfer->rx_buf;
 447
 448         rxdesc = NULL;
 449         if (xfer->rx_buf) {
 450                 struct dma_slave_config rxconf = {
 451                         .direction = DMA_DEV_TO_MEM,
 452                         .src_addr = rs->dma_addr_rx,
 453                         .src_addr_width = rs->n_bytes,
 454                         .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
 455                 };
 456
 457                 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
 458
 459                 rxdesc = dmaengine_prep_slave_sg(
 460                                 ctlr->dma_rx,
 461                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 462                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 463                 if (!rxdesc)
 464                         return -EINVAL;
 465
 466                 rxdesc->callback = rockchip_spi_dma_rxcb;
 467                 rxdesc->callback_param = ctlr;
 468         }
 469
 470         txdesc = NULL;
 471         if (xfer->tx_buf) {
 472                 struct dma_slave_config txconf = {
 473                         .direction = DMA_MEM_TO_DEV,
 474                         .dst_addr = rs->dma_addr_tx,
 475                         .dst_addr_width = rs->n_bytes,
 476                         .dst_maxburst = rs->fifo_len / 4,
 477                 };
 478
 479                 dmaengine_slave_config(ctlr->dma_tx, &txconf);
 480
 481                 txdesc = dmaengine_prep_slave_sg(
 482                                 ctlr->dma_tx,
 483                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 484                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 485                 if (!txdesc) {
 486                         if (rxdesc)
 487                                 dmaengine_terminate_sync(ctlr->dma_rx);
 488                         return -EINVAL;
 489                 }
 490
 491                 txdesc->callback = rockchip_spi_dma_txcb;
 492                 txdesc->callback_param = ctlr;
 493         }
 494
 495         /* rx must be started before tx due to spi instinct */
 496         if (rxdesc) {
 497                 atomic_or(RXDMA, &rs->state);
 498                 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
 499                 dma_async_issue_pending(ctlr->dma_rx);
 500         }
 501
 502         if (rs->cs_inactive)
 503                 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 504
 505         spi_enable_chip(rs, true);
 506
 507         if (txdesc) {
 508                 atomic_or(TXDMA, &rs->state);
 509                 dmaengine_submit(txdesc);
 510                 dma_async_issue_pending(ctlr->dma_tx);
 511         }
 512
 513         /* 1 means the transfer is in progress */
 514         return 1;
 515 }
 516
 517 static int rockchip_spi_config(struct rockchip_spi *rs,
 518                 struct spi_device *spi, struct spi_transfer *xfer,
 519                 bool use_dma, bool target_mode)
 520 {
 521         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 522                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 523                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 524                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 525         u32 cr1;
 526         u32 dmacr = 0;
 527
 528         if (target_mode)
 529                 cr0 |= CR0_OPM_TARGET << CR0_OPM_OFFSET;
 530         rs->target_abort = false;
 531
 532         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 533         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 534         if (spi->mode & SPI_LSB_FIRST)
 535                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 536         if (spi->mode & SPI_CS_HIGH)
 537                 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
 538
 539         if (xfer->rx_buf && xfer->tx_buf)
 540                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 541         else if (xfer->rx_buf)
 542                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 543         else if (use_dma)
 544                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 545
 546         switch (xfer->bits_per_word) {
 547         case 4:
 548                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 549                 cr1 = xfer->len - 1;
 550                 break;
 551         case 8:
 552                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 553                 cr1 = xfer->len - 1;
 554                 break;
 555         case 16:
 556                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 557                 cr1 = xfer->len / 2 - 1;
 558                 break;
 559         default:
 560                 /* we only whitelist 4, 8 and 16 bit words in
 561                  * ctlr->bits_per_word_mask, so this shouldn't
 562                  * happen
 563                  */
 564                 dev_err(rs->dev, "unknown bits per word: %d\n",
 565                         xfer->bits_per_word);
 566                 return -EINVAL;
 567         }
 568
 569         if (use_dma) {
 570                 if (xfer->tx_buf)
 571                         dmacr |= TF_DMA_EN;
 572                 if (xfer->rx_buf)
 573                         dmacr |= RF_DMA_EN;
 574         }
 575
 576         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 577         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 578
 579         /* unfortunately setting the fifo threshold level to generate an
 580          * interrupt exactly when the fifo is full doesn't seem to work,
 581          * so we need the strict inequality here
 582          */
 583         if ((xfer->len / rs->n_bytes) < rs->fifo_len)
 584                 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 585         else
 586                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 587
 588         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 589         writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
 590                        rs->regs + ROCKCHIP_SPI_DMARDLR);
 591         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 592
 593         /* the hardware only supports an even clock divisor, so
 594          * round divisor = spiclk / speed up to nearest even number
 595          * so that the resulting speed is <= the requested speed
 596          */
 597         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 598                         rs->regs + ROCKCHIP_SPI_BAUDR);
 599
 600         return 0;
 601 }
 602
 603 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 604 {
 605         return ROCKCHIP_SPI_MAX_TRANLEN;
 606 }
 607
 608 static int rockchip_spi_target_abort(struct spi_controller *ctlr)
 609 {
 610         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 611         u32 rx_fifo_left;
 612         struct dma_tx_state state;
 613         enum dma_status status;
 614
 615         /* Get current dma rx point */
 616         if (atomic_read(&rs->state) & RXDMA) {
 617                 dmaengine_pause(ctlr->dma_rx);
 618                 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
 619                 if (status == DMA_ERROR) {
 620                         rs->rx = rs->xfer->rx_buf;
 621                         rs->xfer->len = 0;
 622                         rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 623                         for (; rx_fifo_left; rx_fifo_left--)
 624                                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 625                         goto out;
 626                 } else {
 627                         rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
 628                 }
 629         }
 630
 631         /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
 632         if (rs->rx) {
 633                 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 634                 for (; rx_fifo_left; rx_fifo_left--) {
 635                         u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 636
 637                         if (rs->n_bytes == 1)
 638                                 *(u8 *)rs->rx = (u8)rxw;
 639                         else
 640                                 *(u16 *)rs->rx = (u16)rxw;
 641                         rs->rx += rs->n_bytes;
 642                 }
 643                 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
 644         }
 645
 646 out:
 647         if (atomic_read(&rs->state) & RXDMA)
 648                 dmaengine_terminate_sync(ctlr->dma_rx);
 649         if (atomic_read(&rs->state) & TXDMA)
 650                 dmaengine_terminate_sync(ctlr->dma_tx);
 651         atomic_set(&rs->state, 0);
 652         spi_enable_chip(rs, false);
 653         rs->target_abort = true;
 654         spi_finalize_current_transfer(ctlr);
 655
 656         return 0;
 657 }
 658
 659 static int rockchip_spi_transfer_one(
 660                 struct spi_controller *ctlr,
 661                 struct spi_device *spi,
 662                 struct spi_transfer *xfer)
 663 {
 664         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 665         int ret;
 666         bool use_dma;
 667
 668         /* Zero length transfers won't trigger an interrupt on completion */
 669         if (!xfer->len) {
 670                 spi_finalize_current_transfer(ctlr);
 671                 return 1;
 672         }
 673
 674         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 675                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 676
 677         if (!xfer->tx_buf && !xfer->rx_buf) {
 678                 dev_err(rs->dev, "No buffer for transfer\n");
 679                 return -EINVAL;
 680         }
 681
 682         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 683                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 684                 return -EINVAL;
 685         }
 686
 687         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 688         rs->xfer = xfer;
 689         use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
 690
 691         ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->target);
 692         if (ret)
 693                 return ret;
 694
 695         if (use_dma)
 696                 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
 697
 698         return rockchip_spi_prepare_irq(rs, ctlr, xfer);
 699 }
 700
 701 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
 702                                  struct spi_device *spi,
 703                                  struct spi_transfer *xfer)
 704 {
 705         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 706         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 707
 708         /* if the numbor of spi words to transfer is less than the fifo
 709          * length we can just fill the fifo and wait for a single irq,
 710          * so don't bother setting up dma
 711          */
 712         return xfer->len / bytes_per_word >= rs->fifo_len;
 713 }
 714
 715 static int rockchip_spi_setup(struct spi_device *spi)
 716 {
 717         struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
 718         u32 cr0;
 719
 720         if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
 721                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
 722                 return -EINVAL;
 723         }
 724
 725         pm_runtime_get_sync(rs->dev);
 726
 727         cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
 728
 729         cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
 730         cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
 731         if (spi->mode & SPI_CS_HIGH && spi_get_chipselect(spi, 0) <= 1)
 732                 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
 733         else if (spi_get_chipselect(spi, 0) <= 1)
 734                 cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET);
 735
 736         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 737
 738         pm_runtime_put(rs->dev);
 739
 740         return 0;
 741 }
 742
 743 static int rockchip_spi_probe(struct platform_device *pdev)
 744 {
 745         int ret;
 746         struct rockchip_spi *rs;
 747         struct spi_controller *ctlr;
 748         struct resource *mem;
 749         struct device_node *np = pdev->dev.of_node;
 750         u32 rsd_nsecs, num_cs;
 751         bool target_mode;
 752
 753         target_mode = of_property_read_bool(np, "spi-slave");
 754
 755         if (target_mode)
 756                 ctlr = spi_alloc_target(&pdev->dev,
 757                                 sizeof(struct rockchip_spi));
 758         else
 759                 ctlr = spi_alloc_host(&pdev->dev,
 760                                 sizeof(struct rockchip_spi));
 761
 762         if (!ctlr)
 763                 return -ENOMEM;
 764
 765         platform_set_drvdata(pdev, ctlr);
 766
 767         rs = spi_controller_get_devdata(ctlr);
 768
 769         /* Get basic io resource and map it */
 770         rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
 771         if (IS_ERR(rs->regs)) {
 772                 ret =  PTR_ERR(rs->regs);
 773                 goto err_put_ctlr;
 774         }
 775
 776         rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
 777         if (IS_ERR(rs->apb_pclk)) {
 778                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 779                 ret = PTR_ERR(rs->apb_pclk);
 780                 goto err_put_ctlr;
 781         }
 782
 783         rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk");
 784         if (IS_ERR(rs->spiclk)) {
 785                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 786                 ret = PTR_ERR(rs->spiclk);
 787                 goto err_put_ctlr;
 788         }
 789
 790         spi_enable_chip(rs, false);
 791
 792         ret = platform_get_irq(pdev, 0);
 793         if (ret < 0)
 794                 goto err_put_ctlr;
 795
 796         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 797                         IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
 798         if (ret)
 799                 goto err_put_ctlr;
 800
 801         rs->dev = &pdev->dev;
 802         rs->freq = clk_get_rate(rs->spiclk);
 803
 804         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 805                                   &rsd_nsecs)) {
 806                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 807                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 808                                 1000000000 >> 8);
 809                 if (!rsd) {
 810                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 811                                         rs->freq, rsd_nsecs);
 812                 } else if (rsd > CR0_RSD_MAX) {
 813                         rsd = CR0_RSD_MAX;
 814                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 815                                         rs->freq, rsd_nsecs,
 816                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 817                 }
 818                 rs->rsd = rsd;
 819         }
 820
 821         rs->fifo_len = get_fifo_len(rs);
 822         if (!rs->fifo_len) {
 823                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 824                 ret = -EINVAL;
 825                 goto err_put_ctlr;
 826         }
 827
 828         pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
 829         pm_runtime_use_autosuspend(&pdev->dev);
 830         pm_runtime_set_active(&pdev->dev);
 831         pm_runtime_enable(&pdev->dev);
 832
 833         ctlr->auto_runtime_pm = true;
 834         ctlr->bus_num = pdev->id;
 835         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 836         if (target_mode) {
 837                 ctlr->mode_bits |= SPI_NO_CS;
 838                 ctlr->target_abort = rockchip_spi_target_abort;
 839         } else {
 840                 ctlr->flags = SPI_CONTROLLER_GPIO_SS;
 841                 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_NATIVE_CS_NUM;
 842                 /*
 843                  * rk spi0 has two native cs, spi1..5 one cs only
 844                  * if num-cs is missing in the dts, default to 1
 845                  */
 846                 if (of_property_read_u32(np, "num-cs", &num_cs))
 847                         num_cs = 1;
 848                 ctlr->num_chipselect = num_cs;
 849                 ctlr->use_gpio_descriptors = true;
 850         }
 851         ctlr->dev.of_node = pdev->dev.of_node;
 852         ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 853         ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 854         ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 855
 856         ctlr->setup = rockchip_spi_setup;
 857         ctlr->set_cs = rockchip_spi_set_cs;
 858         ctlr->transfer_one = rockchip_spi_transfer_one;
 859         ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
 860         ctlr->handle_err = rockchip_spi_handle_err;
 861
 862         ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
 863         if (IS_ERR(ctlr->dma_tx)) {
 864                 /* Check tx to see if we need defer probing driver */
 865                 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
 866                         ret = -EPROBE_DEFER;
 867                         goto err_disable_pm_runtime;
 868                 }
 869                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 870                 ctlr->dma_tx = NULL;
 871         }
 872
 873         ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
 874         if (IS_ERR(ctlr->dma_rx)) {
 875                 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
 876                         ret = -EPROBE_DEFER;
 877                         goto err_free_dma_tx;
 878                 }
 879                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 880                 ctlr->dma_rx = NULL;
 881         }
 882
 883         if (ctlr->dma_tx && ctlr->dma_rx) {
 884                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 885                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 886                 ctlr->can_dma = rockchip_spi_can_dma;
 887         }
 888
 889         switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
 890         case ROCKCHIP_SPI_VER2_TYPE2:
 891                 rs->cs_high_supported = true;
 892                 ctlr->mode_bits |= SPI_CS_HIGH;
 893                 if (ctlr->can_dma && target_mode)
 894                         rs->cs_inactive = true;
 895                 else
 896                         rs->cs_inactive = false;
 897                 break;
 898         default:
 899                 rs->cs_inactive = false;
 900                 break;
 901         }
 902
 903         ret = devm_spi_register_controller(&pdev->dev, ctlr);
 904         if (ret < 0) {
 905                 dev_err(&pdev->dev, "Failed to register controller\n");
 906                 goto err_free_dma_rx;
 907         }
 908
 909         return 0;
 910
 911 err_free_dma_rx:
 912         if (ctlr->dma_rx)
 913                 dma_release_channel(ctlr->dma_rx);
 914 err_free_dma_tx:
 915         if (ctlr->dma_tx)
 916                 dma_release_channel(ctlr->dma_tx);
 917 err_disable_pm_runtime:
 918         pm_runtime_disable(&pdev->dev);
 919 err_put_ctlr:
 920         spi_controller_put(ctlr);
 921
 922         return ret;
 923 }
 924
 925 static void rockchip_spi_remove(struct platform_device *pdev)
 926 {
 927         struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
 928
 929         pm_runtime_get_sync(&pdev->dev);
 930
 931         pm_runtime_put_noidle(&pdev->dev);
 932         pm_runtime_disable(&pdev->dev);
 933         pm_runtime_set_suspended(&pdev->dev);
 934
 935         if (ctlr->dma_tx)
 936                 dma_release_channel(ctlr->dma_tx);
 937         if (ctlr->dma_rx)
 938                 dma_release_channel(ctlr->dma_rx);
 939
 940         spi_controller_put(ctlr);
 941 }
 942
 943 #ifdef CONFIG_PM_SLEEP
 944 static int rockchip_spi_suspend(struct device *dev)
 945 {
 946         int ret;
 947         struct spi_controller *ctlr = dev_get_drvdata(dev);
 948         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 949
 950         ret = spi_controller_suspend(ctlr);
 951         if (ret < 0)
 952                 return ret;
 953
 954         clk_disable_unprepare(rs->spiclk);
 955         clk_disable_unprepare(rs->apb_pclk);
 956
 957         pinctrl_pm_select_sleep_state(dev);
 958
 959         return 0;
 960 }
 961
 962 static int rockchip_spi_resume(struct device *dev)
 963 {
 964         int ret;
 965         struct spi_controller *ctlr = dev_get_drvdata(dev);
 966         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 967
 968         pinctrl_pm_select_default_state(dev);
 969
 970         ret = clk_prepare_enable(rs->apb_pclk);
 971         if (ret < 0)
 972                 return ret;
 973
 974         ret = clk_prepare_enable(rs->spiclk);
 975         if (ret < 0)
 976                 clk_disable_unprepare(rs->apb_pclk);
 977
 978         ret = spi_controller_resume(ctlr);
 979         if (ret < 0) {
 980                 clk_disable_unprepare(rs->spiclk);
 981                 clk_disable_unprepare(rs->apb_pclk);
 982         }
 983
 984         return 0;
 985 }
 986 #endif /* CONFIG_PM_SLEEP */
 987
 988 #ifdef CONFIG_PM
 989 static int rockchip_spi_runtime_suspend(struct device *dev)
 990 {
 991         struct spi_controller *ctlr = dev_get_drvdata(dev);
 992         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 993
 994         clk_disable_unprepare(rs->spiclk);
 995         clk_disable_unprepare(rs->apb_pclk);
 996
 997         return 0;
 998 }
 999
1000 static int rockchip_spi_runtime_resume(struct device *dev)
1001 {
1002         int ret;
1003         struct spi_controller *ctlr = dev_get_drvdata(dev);
1004         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1005
1006         ret = clk_prepare_enable(rs->apb_pclk);
1007         if (ret < 0)
1008                 return ret;
1009
1010         ret = clk_prepare_enable(rs->spiclk);
1011         if (ret < 0)
1012                 clk_disable_unprepare(rs->apb_pclk);
1013
1014         return 0;
1015 }
1016 #endif /* CONFIG_PM */
1017
1018 static const struct dev_pm_ops rockchip_spi_pm = {
1019         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1020         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1021                            rockchip_spi_runtime_resume, NULL)
1022 };
1023
1024 static const struct of_device_id rockchip_spi_dt_match[] = {
1025         { .compatible = "rockchip,px30-spi", },
1026         { .compatible = "rockchip,rk3036-spi", },
1027         { .compatible = "rockchip,rk3066-spi", },
1028         { .compatible = "rockchip,rk3188-spi", },
1029         { .compatible = "rockchip,rk3228-spi", },
1030         { .compatible = "rockchip,rk3288-spi", },
1031         { .compatible = "rockchip,rk3308-spi", },
1032         { .compatible = "rockchip,rk3328-spi", },
1033         { .compatible = "rockchip,rk3368-spi", },
1034         { .compatible = "rockchip,rk3399-spi", },
1035         { .compatible = "rockchip,rv1108-spi", },
1036         { .compatible = "rockchip,rv1126-spi", },
1037         { },
1038 };
1039 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1040
1041 static struct platform_driver rockchip_spi_driver = {
1042         .driver = {
1043                 .name   = DRIVER_NAME,
1044                 .pm = &rockchip_spi_pm,
1045                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1046         },
1047         .probe = rockchip_spi_probe,
1048         .remove_new = rockchip_spi_remove,
1049 };
1050
1051 module_platform_driver(rockchip_spi_driver);
1052
1053 MODULE_AUTHOR("Addy Ke <[email protected]>");
1054 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1055 MODULE_LICENSE("GPL v2");