drivers/phy/qualcomm/phy-qcom-qmp-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include "phy-qcom-qmp-common.h"
  23
  24 #include "phy-qcom-qmp.h"
  25 #include "phy-qcom-qmp-pcs-misc-v3.h"
  26 #include "phy-qcom-qmp-pcs-misc-v4.h"
  27 #include "phy-qcom-qmp-pcs-usb-v4.h"
  28 #include "phy-qcom-qmp-pcs-usb-v5.h"
  29 #include "phy-qcom-qmp-pcs-usb-v6.h"
  30 #include "phy-qcom-qmp-pcs-usb-v7.h"
  31
  32 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  33
  34 /* set of registers with offsets different per-PHY */
  35 enum qphy_reg_layout {
  36         /* PCS registers */
  37         QPHY_SW_RESET,
  38         QPHY_START_CTRL,
  39         QPHY_PCS_STATUS,
  40         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
  41         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
  42         QPHY_PCS_POWER_DOWN_CONTROL,
  43         QPHY_PCS_MISC_CLAMP_ENABLE,
  44         /* Keep last to ensure regs_layout arrays are properly initialized */
  45         QPHY_LAYOUT_SIZE
  46 };
  47
  48 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
  49         [QPHY_SW_RESET]                 = QPHY_V2_PCS_SW_RESET,
  50         [QPHY_START_CTRL]               = QPHY_V2_PCS_START_CONTROL,
  51         [QPHY_PCS_STATUS]               = QPHY_V2_PCS_USB_PCS_STATUS,
  52         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
  53         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
  54         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_POWER_DOWN_CONTROL,
  55 };
  56
  57 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
  58         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
  59         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
  60         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
  61         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
  62         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
  63         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
  64         [QPHY_PCS_MISC_CLAMP_ENABLE]    = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
  65 };
  66
  67 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
  68         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
  69         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
  70         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
  71         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
  72
  73         /* In PCS_USB */
  74         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
  75         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
  76         [QPHY_PCS_MISC_CLAMP_ENABLE]    = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
  77 };
  78
  79 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
  80         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
  81         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
  82         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
  83         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
  84
  85         /* In PCS_USB */
  86         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
  87         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
  88 };
  89
  90 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
  91         [QPHY_SW_RESET]                 = QPHY_V6_PCS_SW_RESET,
  92         [QPHY_START_CTRL]               = QPHY_V6_PCS_START_CONTROL,
  93         [QPHY_PCS_STATUS]               = QPHY_V6_PCS_PCS_STATUS1,
  94         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_POWER_DOWN_CONTROL,
  95
  96         /* In PCS_USB */
  97         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
  98         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
  99 };
 100
 101 static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 102         [QPHY_SW_RESET]                 = QPHY_V7_PCS_SW_RESET,
 103         [QPHY_START_CTRL]               = QPHY_V7_PCS_START_CONTROL,
 104         [QPHY_PCS_STATUS]               = QPHY_V7_PCS_PCS_STATUS1,
 105         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V7_PCS_POWER_DOWN_CONTROL,
 106
 107         /* In PCS_USB */
 108         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 109         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 110 };
 111
 112 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
 113         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 114         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 115         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 116         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 117         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 118         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 119         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 120         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 121         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 122         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 123         /* PLL and Loop filter settings */
 124         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
 125         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
 126         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
 127         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
 128         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
 129         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 130         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 131         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
 132         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
 133         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
 134         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 135         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 136         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 137         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 138         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 139         /* SSC settings */
 140         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 141         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
 142         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 143         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 144         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 145         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
 146         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
 147 };
 148
 149 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
 150         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 151         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 152         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 153 };
 154
 155 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
 156         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 157         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 158         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
 159         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 160         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 161         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 162         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 163         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 164         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 165         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
 166 };
 167
 168 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
 169         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 170         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 171         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 172         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 173         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 174         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 175         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 176         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 177         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 178         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 179         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 180         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 181         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 182         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 183         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 184         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 185         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 186         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 187         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 188         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 189         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 190         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 191         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 192 };
 193
 194 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 195         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 199         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 203         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 204         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 205         /* PLL and Loop filter settings */
 206         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 207         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 208         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 209         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 210         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 211         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 212         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 213         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 214         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 215         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 216         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 217         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 218         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 219         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 220         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 221         /* SSC settings */
 222         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 223         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 224         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 225         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 226         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 227         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 228         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 229 };
 230
 231 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 232         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 233         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 234         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 235         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 236         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 237         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 238         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 239         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 240         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 241 };
 242
 243 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 244         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 245         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 246         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 247         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 248         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 249         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 250         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 251         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 252         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 253         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 254         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 255         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 256         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 257         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 258         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 259         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 260         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 261         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 262         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 263         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 264         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 265         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 266         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 267 };
 268
 269 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 270         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 272         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 273         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 278         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 279         /* PLL and Loop filter settings */
 280         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 281         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 282         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 283         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 284         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 285         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 286         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 294         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 295         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 296         /* SSC settings */
 297         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 302         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 304 };
 305
 306 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 307         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 308         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 309         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 310 };
 311
 312 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 313         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 314         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 315         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 316         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 317         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 318         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 319         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 320         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 321         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 322         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 323 };
 324
 325 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 326         /* FLL settings */
 327         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
 328         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
 329         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
 330         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
 331         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
 332
 333         /* Lock Det settings */
 334         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 335         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 336         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
 337         QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
 338 };
 339
 340 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 341         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 342         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 343         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 344         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 345         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 346         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 347         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 348         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 349         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 350         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 351         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 352         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 353         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 354         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 355         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 356         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 357         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 358         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 359         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 360         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 361         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 362         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 363         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 364         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 365         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 366         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 367         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 368         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 369         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 370         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 371         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 372         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 373         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 374         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 375         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 376         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 377 };
 378
 379 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 380         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 381         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 382         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 383         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 385 };
 386
 387 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 388         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 399 };
 400
 401 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 402         /* FLL settings */
 403         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 404         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 405         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 406         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 407         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 408
 409         /* Lock Det settings */
 410         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 411         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 412         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 413         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 414
 415         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 416         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 417         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 418         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 419         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 420         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 421         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 422         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 423         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 424         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 425         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 426         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 427         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 428         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 429         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 430         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 431         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 432         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 433         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 434
 435         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 436         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 437         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 438         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 439         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 440         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 441         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 442         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 443         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 444         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 445         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 446
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 449 };
 450
 451 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
 452         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 453         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 454         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 455         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 456         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 457         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 458         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 459         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 460         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 461         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 462         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 463         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 464         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 465         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 466         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 467         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 468         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 469         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 470         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 471         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 472         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 473         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 474         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 475         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 476         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 477         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 483         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 484         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 485         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 486         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 487         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 489         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 490         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 491         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 492 };
 493
 494 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
 495         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 496         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
 497         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 498         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
 499 };
 500
 501 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
 502         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 503         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 504         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
 505         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 508         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 511         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 512         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 513         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 514         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 515         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 516         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 517         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 518         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 519         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 520         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 521         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 524         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 525         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 526         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 527         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 528         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 529         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 530         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 538 };
 539
 540 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
 541         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 542         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 543         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 544         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 545         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 546         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 547         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 548         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
 549         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 550         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 551         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 552         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 553         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 554         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 555 };
 556
 557 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
 558         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 559         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 560 };
 561
 562 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
 563         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 564         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 565         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
 566         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 567         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 568         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 569 };
 570
 571 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
 572         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 573         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
 574         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 575         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 576         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 577         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 578         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 579         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 580         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 581         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 582         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 583         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 584         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 585         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 586         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 587         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 588         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 589         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 590         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 591         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
 592         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 593         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 594         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 595         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 596         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 597         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 598         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 599         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 600         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 601         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 602         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 603         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 604         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 605         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 606         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 608 };
 609
 610 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
 611         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 612         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 613         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 614         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 615         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 616         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 617         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 618         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 619         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 620         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 621         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 622         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 623         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 624         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 625 };
 626
 627 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
 628         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 629         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 630 };
 631
 632 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
 633         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 634         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 635         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
 636         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 637         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
 638 };
 639
 640 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
 641         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
 642         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 643         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 644         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 645         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 646         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 647         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 648         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 649         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 650         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 651         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 652         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
 653         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 654         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
 655         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
 656         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 657         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 658         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 659         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 660         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
 661         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 662         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 663         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 664         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 665         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 666         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 667         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 668         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 669         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 670         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 671         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 672         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 673         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 674         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 675         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 676         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 677 };
 678
 679 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
 680         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 681         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 682         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 683         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 684         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 685         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 686         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
 687 };
 688
 689 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
 690         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 691         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 692         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 693         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 694         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 695         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 696         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 697         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 698         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 699         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 700         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 701         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 702         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 703         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 704         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 705         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 706         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 707         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 708         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 709         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 710         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 711         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 712         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 713         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 714         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 715         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 716         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 717         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 718         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 719         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 720         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
 721 };
 722
 723 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = {
 724         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e),
 725         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 726         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
 727         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
 728         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
 729         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
 730         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),
 731         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),
 732         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
 733         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
 734         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea),
 735         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
 736         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 737         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
 738         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
 739         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),
 740         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 741         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),
 742         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 743         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e),
 744         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
 745         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
 746         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 747         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 748         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),
 749         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),
 750         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
 751         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
 752         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
 753         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
 754         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
 755         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
 756         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
 757         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
 758         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
 759         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
 760         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
 761         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
 762         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
 763         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 764         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
 765         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 766         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
 767         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
 768         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
 769         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
 770 };
 771
 772 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = {
 773         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
 774         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
 775         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 776         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 777         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
 778         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
 779         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
 780         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
 781         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
 782         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21),
 783 };
 784
 785 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = {
 786         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
 787         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
 788         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 789         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 790         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 791         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 792         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
 793         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
 794         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
 795         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
 796         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
 797         QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 798         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
 799         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
 800         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
 801         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 802         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 803         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 804         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
 805         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 806         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 807         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
 808         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 809         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
 810         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
 811         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff),
 812         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf),
 813         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed),
 814         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
 815         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
 816         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
 817         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
 818         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
 819         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
 820         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 821         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
 822         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
 823         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
 824         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
 825 };
 826
 827 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = {
 828         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
 829         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
 830         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
 831         QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
 832         QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
 833         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa),
 834         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 835         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 836         QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
 837         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 838         QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 839         QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
 840         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
 841         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
 842 };
 843
 844 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = {
 845         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 846         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 847         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 848         QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 849 };
 850
 851 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
 852         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 853         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 854         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 855         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 856         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 857         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
 858         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 859 };
 860
 861 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
 862         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
 863         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 864         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 865         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 866         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 867         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 868         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 869         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 870         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 871         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 872         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 873         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 874         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 875         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 876         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 877         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 878         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 879         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 880         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 881         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 882         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 883         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 884         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 885         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 886         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 887         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 888         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 889         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 890         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 891         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 892         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
 893 };
 894
 895 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
 896         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 897         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 898         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 899         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 900         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 901         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 902         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 903         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 904         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 905         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 906         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 907         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 908         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 909         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 910 };
 911
 912 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
 913         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 914         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 915 };
 916
 917 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
 918         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
 919         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 920         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
 921         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
 922         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
 923         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
 924         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
 925         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 926         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 927         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
 928         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
 929         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
 930         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
 931         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
 932         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
 933         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
 934         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
 935         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
 936         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
 937         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
 938         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
 939         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
 940         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
 941         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
 942         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
 943         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
 944         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
 945         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
 946         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
 947         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 948         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 949         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
 950         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
 951         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
 952         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 953         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 954         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 955         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 956         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
 957 };
 958
 959 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
 960         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 961         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 962         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 963         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 964         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 965         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
 966         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 967 };
 968
 969 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
 970         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
 971         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 972         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 973         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 974         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 975         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 976         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 977         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 978         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 979         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 980         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 981         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 982         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 983         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 984         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 985         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 986         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 987         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 988         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
 989         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 990         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 991         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 992         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 993         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 994         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 995         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 996         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 997         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 998         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 999         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1000         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1001 };
1002
1003 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1004         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1005         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1006         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1007         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1008         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1009         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1010         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1011         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1012         QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1013         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1014         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1015         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1016         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1017         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1018 };
1019
1020 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {
1021         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1022         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1023 };
1024
1025 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1026         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1027         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1028         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1029         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1030         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1031         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1032         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1033         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1034         QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1035         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1036         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1037         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1038         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1039         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1040 };
1041
1042 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {
1043         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1044         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1045         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1046 };
1047
1048 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = {
1049         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1050         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1051         QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),
1052         QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),
1053         QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),
1054         QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),
1055         QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16),
1056         QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41),
1057         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41),
1058         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),
1059         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75),
1060         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),
1061         QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),
1062         QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25),
1063         QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02),
1064         QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1065         QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1066         QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1067         QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1068         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1069         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1070         QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),
1071         QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),
1072         QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),
1073         QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08),
1074         QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a),
1075         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),
1076         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55),
1077         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75),
1078         QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),
1079         QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25),
1080         QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02),
1081         QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),
1082         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01),
1083         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),
1084         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),
1085         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a),
1086         QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a),
1087         QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14),
1088         QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04),
1089         QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20),
1090         QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),
1091         QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1092         QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
1093         QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
1094         QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c),
1095 };
1096
1097 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = {
1098         QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00),
1099         QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00),
1100         QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1101         QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1102         QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5),
1103         QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f),
1104         QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f),
1105         QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f),
1106         QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12),
1107         QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21),
1108 };
1109
1110 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = {
1111         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a),
1112         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06),
1113         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1114         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1115         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1116         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1117         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99),
1118         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),
1119         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),
1120         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00),
1121         QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a),
1122         QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1123         QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54),
1124         QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f),
1125         QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13),
1126         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1127         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1128         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1129         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1130         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1131         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1132         QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04),
1133         QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1134         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f),
1135         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf),
1136         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff),
1137         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf),
1138         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed),
1139         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc),
1140         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c),
1141         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c),
1142         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d),
1143         QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09),
1144         QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04),
1145         QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1146         QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c),
1147         QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10),
1148         QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14),
1149         QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),
1150 };
1151
1152 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = {
1153         QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1154         QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89),
1155         QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20),
1156         QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13),
1157         QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21),
1158         QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa),
1159         QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1160         QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1161         QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a),
1162         QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1163         QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1164         QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c),
1165         QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b),
1166         QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10),
1167 };
1168
1169 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = {
1170         QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1171         QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1172         QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1173         QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1174 };
1175
1176 struct qmp_usb_offsets {
1177         u16 serdes;
1178         u16 pcs;
1179         u16 pcs_misc;
1180         u16 pcs_usb;
1181         u16 tx;
1182         u16 rx;
1183 };
1184
1185 /* struct qmp_phy_cfg - per-PHY initialization config */
1186 struct qmp_phy_cfg {
1187         const struct qmp_usb_offsets *offsets;
1188
1189         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1190         const struct qmp_phy_init_tbl *serdes_tbl;
1191         int serdes_tbl_num;
1192         const struct qmp_phy_init_tbl *tx_tbl;
1193         int tx_tbl_num;
1194         const struct qmp_phy_init_tbl *rx_tbl;
1195         int rx_tbl_num;
1196         const struct qmp_phy_init_tbl *pcs_tbl;
1197         int pcs_tbl_num;
1198         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1199         int pcs_usb_tbl_num;
1200
1201         /* regulators to be requested */
1202         const char * const *vreg_list;
1203         int num_vregs;
1204
1205         /* array of registers with different offsets */
1206         const unsigned int *regs;
1207
1208         /* true, if PHY needs delay after POWER_DOWN */
1209         bool has_pwrdn_delay;
1210
1211         /* Offset from PCS to PCS_USB region */
1212         unsigned int pcs_usb_offset;
1213 };
1214
1215 struct qmp_usb {
1216         struct device *dev;
1217
1218         const struct qmp_phy_cfg *cfg;
1219
1220         void __iomem *serdes;
1221         void __iomem *pcs;
1222         void __iomem *pcs_misc;
1223         void __iomem *pcs_usb;
1224         void __iomem *tx;
1225         void __iomem *rx;
1226
1227         struct clk *pipe_clk;
1228         struct clk_bulk_data *clks;
1229         int num_clks;
1230         int num_resets;
1231         struct reset_control_bulk_data *resets;
1232         struct regulator_bulk_data *vregs;
1233
1234         enum phy_mode mode;
1235
1236         struct phy *phy;
1237
1238         struct clk_fixed_rate pipe_clk_fixed;
1239 };
1240
1241 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1242 {
1243         u32 reg;
1244
1245         reg = readl(base + offset);
1246         reg |= val;
1247         writel(reg, base + offset);
1248
1249         /* ensure that above write is through */
1250         readl(base + offset);
1251 }
1252
1253 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1254 {
1255         u32 reg;
1256
1257         reg = readl(base + offset);
1258         reg &= ~val;
1259         writel(reg, base + offset);
1260
1261         /* ensure that above write is through */
1262         readl(base + offset);
1263 }
1264
1265 /* list of clocks required by phy */
1266 static const char * const qmp_usb_phy_clk_l[] = {
1267         "aux", "cfg_ahb", "ref", "com_aux",
1268 };
1269
1270 /* list of resets */
1271 static const char * const usb3phy_legacy_reset_l[] = {
1272         "phy", "common",
1273 };
1274
1275 static const char * const usb3phy_reset_l[] = {
1276         "phy_phy", "phy",
1277 };
1278
1279 /* list of regulators */
1280 static const char * const qmp_phy_vreg_l[] = {
1281         "vdda-phy", "vdda-pll",
1282 };
1283
1284 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1285         .serdes         = 0,
1286         .pcs            = 0x800,
1287         .pcs_misc       = 0x600,
1288         .tx             = 0x200,
1289         .rx             = 0x400,
1290 };
1291
1292 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1293         .serdes         = 0,
1294         .pcs            = 0x800,
1295         .pcs_usb        = 0x800,
1296         .tx             = 0x200,
1297         .rx             = 0x400,
1298 };
1299
1300 static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = {
1301         .serdes         = 0,
1302         .pcs            = 0x600,
1303         .tx             = 0x200,
1304         .rx             = 0x400,
1305 };
1306
1307 static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
1308         .serdes         = 0,
1309         .pcs            = 0x0800,
1310         .pcs_usb        = 0x0e00,
1311         .tx             = 0x0200,
1312         .rx             = 0x0400,
1313 };
1314
1315 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1316         .serdes         = 0,
1317         .pcs            = 0x0200,
1318         .pcs_usb        = 0x1200,
1319         .tx             = 0x0e00,
1320         .rx             = 0x1000,
1321 };
1322
1323 static const struct qmp_usb_offsets qmp_usb_offsets_v6 = {
1324         .serdes         = 0,
1325         .pcs            = 0x0200,
1326         .pcs_usb        = 0x1200,
1327         .tx             = 0x0e00,
1328         .rx             = 0x1000,
1329 };
1330
1331 static const struct qmp_usb_offsets qmp_usb_offsets_v7 = {
1332         .serdes         = 0,
1333         .pcs            = 0x0200,
1334         .pcs_usb        = 0x1200,
1335         .tx             = 0x0e00,
1336         .rx             = 0x1000,
1337 };
1338
1339 static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
1340         .offsets                = &qmp_usb_offsets_v3,
1341
1342         .serdes_tbl             = ipq9574_usb3_serdes_tbl,
1343         .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1344         .tx_tbl                 = msm8996_usb3_tx_tbl,
1345         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1346         .rx_tbl                 = ipq8074_usb3_rx_tbl,
1347         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1348         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
1349         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1350         .vreg_list              = qmp_phy_vreg_l,
1351         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1352         .regs                   = qmp_v3_usb3phy_regs_layout,
1353 };
1354
1355 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1356         .offsets                = &qmp_usb_offsets_v3,
1357
1358         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
1359         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1360         .tx_tbl                 = msm8996_usb3_tx_tbl,
1361         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1362         .rx_tbl                 = ipq8074_usb3_rx_tbl,
1363         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1364         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
1365         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1366         .vreg_list              = qmp_phy_vreg_l,
1367         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1368         .regs                   = qmp_v3_usb3phy_regs_layout,
1369 };
1370
1371 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1372         .offsets                = &qmp_usb_offsets_ipq9574,
1373
1374         .serdes_tbl             = ipq9574_usb3_serdes_tbl,
1375         .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1376         .tx_tbl                 = ipq9574_usb3_tx_tbl,
1377         .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1378         .rx_tbl                 = ipq9574_usb3_rx_tbl,
1379         .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1380         .pcs_tbl                = ipq9574_usb3_pcs_tbl,
1381         .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1382         .vreg_list              = qmp_phy_vreg_l,
1383         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1384         .regs                   = qmp_v3_usb3phy_regs_layout,
1385 };
1386
1387 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1388         .offsets                = &qmp_usb_offsets_v3_msm8996,
1389
1390         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1391         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1392         .tx_tbl                 = msm8996_usb3_tx_tbl,
1393         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1394         .rx_tbl                 = msm8996_usb3_rx_tbl,
1395         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1396         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1397         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1398         .vreg_list              = qmp_phy_vreg_l,
1399         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1400         .regs                   = qmp_v2_usb3phy_regs_layout,
1401 };
1402
1403 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1404         .offsets                = &qmp_usb_offsets_v5,
1405
1406         .serdes_tbl             = sc8280xp_usb3_uniphy_serdes_tbl,
1407         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1408         .tx_tbl                 = sc8280xp_usb3_uniphy_tx_tbl,
1409         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1410         .rx_tbl                 = sc8280xp_usb3_uniphy_rx_tbl,
1411         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1412         .pcs_tbl                = sa8775p_usb3_uniphy_pcs_tbl,
1413         .pcs_tbl_num            = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1414         .pcs_usb_tbl            = sa8775p_usb3_uniphy_pcs_usb_tbl,
1415         .pcs_usb_tbl_num        = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1416         .vreg_list              = qmp_phy_vreg_l,
1417         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1418         .regs                   = qmp_v5_usb3phy_regs_layout,
1419 };
1420
1421 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1422         .offsets                = &qmp_usb_offsets_v5,
1423
1424         .serdes_tbl             = sc8280xp_usb3_uniphy_serdes_tbl,
1425         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1426         .tx_tbl                 = sc8280xp_usb3_uniphy_tx_tbl,
1427         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1428         .rx_tbl                 = sc8280xp_usb3_uniphy_rx_tbl,
1429         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1430         .pcs_tbl                = sc8280xp_usb3_uniphy_pcs_tbl,
1431         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1432         .pcs_usb_tbl            = sc8280xp_usb3_uniphy_pcs_usb_tbl,
1433         .pcs_usb_tbl_num        = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),
1434         .vreg_list              = qmp_phy_vreg_l,
1435         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1436         .regs                   = qmp_v5_usb3phy_regs_layout,
1437 };
1438
1439 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1440         .offsets                = &qmp_usb_offsets_v3,
1441
1442         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1443         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1444         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1445         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1446         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1447         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1448         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1449         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1450         .vreg_list              = qmp_phy_vreg_l,
1451         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1452         .regs                   = qmp_v3_usb3phy_regs_layout,
1453
1454         .has_pwrdn_delay        = true,
1455 };
1456
1457 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1458         .offsets                = &qmp_usb_offsets_v4,
1459
1460         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1461         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1462         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
1463         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1464         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
1465         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1466         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
1467         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1468         .pcs_usb_tbl            = sm8150_usb3_uniphy_pcs_usb_tbl,
1469         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1470         .vreg_list              = qmp_phy_vreg_l,
1471         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1472         .regs                   = qmp_v4_usb3phy_regs_layout,
1473         .pcs_usb_offset         = 0x600,
1474
1475         .has_pwrdn_delay        = true,
1476 };
1477
1478 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1479         .offsets                = &qmp_usb_offsets_v4,
1480
1481         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1482         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1483         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
1484         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1485         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
1486         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1487         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1488         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1489         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1490         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1491         .vreg_list              = qmp_phy_vreg_l,
1492         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1493         .regs                   = qmp_v4_usb3phy_regs_layout,
1494         .pcs_usb_offset         = 0x600,
1495
1496         .has_pwrdn_delay        = true,
1497 };
1498
1499 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1500         .offsets                = &qmp_usb_offsets_v4,
1501
1502         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1503         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1504         .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
1505         .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1506         .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
1507         .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1508         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1509         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1510         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1511         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1512         .vreg_list              = qmp_phy_vreg_l,
1513         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1514         .regs                   = qmp_v4_usb3phy_regs_layout,
1515         .pcs_usb_offset         = 0x600,
1516
1517         .has_pwrdn_delay        = true,
1518 };
1519
1520 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1521         .offsets                = &qmp_usb_offsets_v5,
1522
1523         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1524         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1525         .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
1526         .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1527         .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
1528         .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1529         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1530         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1531         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1532         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1533         .vreg_list              = qmp_phy_vreg_l,
1534         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1535         .regs                   = qmp_v5_usb3phy_regs_layout,
1536         .pcs_usb_offset         = 0x1000,
1537
1538         .has_pwrdn_delay        = true,
1539 };
1540
1541 static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {
1542         .offsets                = &qmp_usb_offsets_v6,
1543
1544         .serdes_tbl             = sdx75_usb3_uniphy_serdes_tbl,
1545         .serdes_tbl_num         = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),
1546         .tx_tbl                 = sdx75_usb3_uniphy_tx_tbl,
1547         .tx_tbl_num             = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),
1548         .rx_tbl                 = sdx75_usb3_uniphy_rx_tbl,
1549         .rx_tbl_num             = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),
1550         .pcs_tbl                = sdx75_usb3_uniphy_pcs_tbl,
1551         .pcs_tbl_num            = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),
1552         .pcs_usb_tbl            = sdx75_usb3_uniphy_pcs_usb_tbl,
1553         .pcs_usb_tbl_num        = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),
1554         .vreg_list              = qmp_phy_vreg_l,
1555         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1556         .regs                   = qmp_v6_usb3phy_regs_layout,
1557         .pcs_usb_offset         = 0x1000,
1558
1559         .has_pwrdn_delay        = true,
1560 };
1561
1562 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1563         .offsets                = &qmp_usb_offsets_v5,
1564
1565         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1566         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1567         .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
1568         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1569         .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
1570         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1571         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1572         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1573         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1574         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1575         .vreg_list              = qmp_phy_vreg_l,
1576         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1577         .regs                   = qmp_v5_usb3phy_regs_layout,
1578         .pcs_usb_offset         = 0x1000,
1579
1580         .has_pwrdn_delay        = true,
1581 };
1582
1583 static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {
1584         .offsets                = &qmp_usb_offsets_v7,
1585
1586         .serdes_tbl             = x1e80100_usb3_uniphy_serdes_tbl,
1587         .serdes_tbl_num         = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl),
1588         .tx_tbl                 = x1e80100_usb3_uniphy_tx_tbl,
1589         .tx_tbl_num             = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl),
1590         .rx_tbl                 = x1e80100_usb3_uniphy_rx_tbl,
1591         .rx_tbl_num             = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl),
1592         .pcs_tbl                = x1e80100_usb3_uniphy_pcs_tbl,
1593         .pcs_tbl_num            = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl),
1594         .pcs_usb_tbl            = x1e80100_usb3_uniphy_pcs_usb_tbl,
1595         .pcs_usb_tbl_num        = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl),
1596         .vreg_list              = qmp_phy_vreg_l,
1597         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1598         .regs                   = qmp_v7_usb3phy_regs_layout,
1599 };
1600
1601 static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1602 {
1603         const struct qmp_phy_cfg *cfg = qmp->cfg;
1604         void __iomem *serdes = qmp->serdes;
1605         const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1606         int serdes_tbl_num = cfg->serdes_tbl_num;
1607
1608         qmp_configure(serdes, serdes_tbl, serdes_tbl_num);
1609
1610         return 0;
1611 }
1612
1613 static int qmp_usb_init(struct phy *phy)
1614 {
1615         struct qmp_usb *qmp = phy_get_drvdata(phy);
1616         const struct qmp_phy_cfg *cfg = qmp->cfg;
1617         void __iomem *pcs = qmp->pcs;
1618         int ret;
1619
1620         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1621         if (ret) {
1622                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1623                 return ret;
1624         }
1625
1626         ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1627         if (ret) {
1628                 dev_err(qmp->dev, "reset assert failed\n");
1629                 goto err_disable_regulators;
1630         }
1631
1632         ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
1633         if (ret) {
1634                 dev_err(qmp->dev, "reset deassert failed\n");
1635                 goto err_disable_regulators;
1636         }
1637
1638         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1639         if (ret)
1640                 goto err_assert_reset;
1641
1642         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1643
1644         return 0;
1645
1646 err_assert_reset:
1647         reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1648 err_disable_regulators:
1649         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1650
1651         return ret;
1652 }
1653
1654 static int qmp_usb_exit(struct phy *phy)
1655 {
1656         struct qmp_usb *qmp = phy_get_drvdata(phy);
1657         const struct qmp_phy_cfg *cfg = qmp->cfg;
1658
1659         reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1660
1661         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1662
1663         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1664
1665         return 0;
1666 }
1667
1668 static int qmp_usb_power_on(struct phy *phy)
1669 {
1670         struct qmp_usb *qmp = phy_get_drvdata(phy);
1671         const struct qmp_phy_cfg *cfg = qmp->cfg;
1672         void __iomem *tx = qmp->tx;
1673         void __iomem *rx = qmp->rx;
1674         void __iomem *pcs = qmp->pcs;
1675         void __iomem *pcs_usb = qmp->pcs_usb;
1676         void __iomem *status;
1677         unsigned int val;
1678         int ret;
1679
1680         qmp_usb_serdes_init(qmp);
1681
1682         ret = clk_prepare_enable(qmp->pipe_clk);
1683         if (ret) {
1684                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1685                 return ret;
1686         }
1687
1688         /* Tx, Rx, and PCS configurations */
1689         qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1690         qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1691
1692         qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1693
1694         if (pcs_usb)
1695                 qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
1696
1697         if (cfg->has_pwrdn_delay)
1698                 usleep_range(10, 20);
1699
1700         /* Pull PHY out of reset state */
1701         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1702
1703         /* start SerDes and Phy-Coding-Sublayer */
1704         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
1705
1706         status = pcs + cfg->regs[QPHY_PCS_STATUS];
1707         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
1708                                  PHY_INIT_COMPLETE_TIMEOUT);
1709         if (ret) {
1710                 dev_err(qmp->dev, "phy initialization timed-out\n");
1711                 goto err_disable_pipe_clk;
1712         }
1713
1714         return 0;
1715
1716 err_disable_pipe_clk:
1717         clk_disable_unprepare(qmp->pipe_clk);
1718
1719         return ret;
1720 }
1721
1722 static int qmp_usb_power_off(struct phy *phy)
1723 {
1724         struct qmp_usb *qmp = phy_get_drvdata(phy);
1725         const struct qmp_phy_cfg *cfg = qmp->cfg;
1726
1727         clk_disable_unprepare(qmp->pipe_clk);
1728
1729         /* PHY reset */
1730         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1731
1732         /* stop SerDes and Phy-Coding-Sublayer */
1733         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
1734                         SERDES_START | PCS_START);
1735
1736         /* Put PHY into POWER DOWN state: active low */
1737         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1738                         SW_PWRDN);
1739
1740         return 0;
1741 }
1742
1743 static int qmp_usb_enable(struct phy *phy)
1744 {
1745         int ret;
1746
1747         ret = qmp_usb_init(phy);
1748         if (ret)
1749                 return ret;
1750
1751         ret = qmp_usb_power_on(phy);
1752         if (ret)
1753                 qmp_usb_exit(phy);
1754
1755         return ret;
1756 }
1757
1758 static int qmp_usb_disable(struct phy *phy)
1759 {
1760         int ret;
1761
1762         ret = qmp_usb_power_off(phy);
1763         if (ret)
1764                 return ret;
1765         return qmp_usb_exit(phy);
1766 }
1767
1768 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1769 {
1770         struct qmp_usb *qmp = phy_get_drvdata(phy);
1771
1772         qmp->mode = mode;
1773
1774         return 0;
1775 }
1776
1777 static const struct phy_ops qmp_usb_phy_ops = {
1778         .init           = qmp_usb_enable,
1779         .exit           = qmp_usb_disable,
1780         .set_mode       = qmp_usb_set_mode,
1781         .owner          = THIS_MODULE,
1782 };
1783
1784 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
1785 {
1786         const struct qmp_phy_cfg *cfg = qmp->cfg;
1787         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1788         void __iomem *pcs_misc = qmp->pcs_misc;
1789         u32 intr_mask;
1790
1791         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1792             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1793                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1794         else
1795                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1796
1797         /* Clear any pending interrupts status */
1798         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1799         /* Writing 1 followed by 0 clears the interrupt */
1800         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1801
1802         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1803                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1804
1805         /* Enable required PHY autonomous mode interrupts */
1806         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1807
1808         /* Enable i/o clamp_n for autonomous mode */
1809         if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1810                 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1811 }
1812
1813 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
1814 {
1815         const struct qmp_phy_cfg *cfg = qmp->cfg;
1816         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1817         void __iomem *pcs_misc = qmp->pcs_misc;
1818
1819         /* Disable i/o clamp_n on resume for normal mode */
1820         if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1821                 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1822
1823         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1824                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1825
1826         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1827         /* Writing 1 followed by 0 clears the interrupt */
1828         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1829 }
1830
1831 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
1832 {
1833         struct qmp_usb *qmp = dev_get_drvdata(dev);
1834
1835         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1836
1837         if (!qmp->phy->init_count) {
1838                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1839                 return 0;
1840         }
1841
1842         qmp_usb_enable_autonomous_mode(qmp);
1843
1844         clk_disable_unprepare(qmp->pipe_clk);
1845         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1846
1847         return 0;
1848 }
1849
1850 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
1851 {
1852         struct qmp_usb *qmp = dev_get_drvdata(dev);
1853         int ret = 0;
1854
1855         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1856
1857         if (!qmp->phy->init_count) {
1858                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1859                 return 0;
1860         }
1861
1862         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1863         if (ret)
1864                 return ret;
1865
1866         ret = clk_prepare_enable(qmp->pipe_clk);
1867         if (ret) {
1868                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1869                 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1870                 return ret;
1871         }
1872
1873         qmp_usb_disable_autonomous_mode(qmp);
1874
1875         return 0;
1876 }
1877
1878 static const struct dev_pm_ops qmp_usb_pm_ops = {
1879         SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
1880                            qmp_usb_runtime_resume, NULL)
1881 };
1882
1883 static int qmp_usb_vreg_init(struct qmp_usb *qmp)
1884 {
1885         const struct qmp_phy_cfg *cfg = qmp->cfg;
1886         struct device *dev = qmp->dev;
1887         int num = cfg->num_vregs;
1888         int i;
1889
1890         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1891         if (!qmp->vregs)
1892                 return -ENOMEM;
1893
1894         for (i = 0; i < num; i++)
1895                 qmp->vregs[i].supply = cfg->vreg_list[i];
1896
1897         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1898 }
1899
1900 static int qmp_usb_reset_init(struct qmp_usb *qmp,
1901                               const char *const *reset_list,
1902                               int num_resets)
1903 {
1904         struct device *dev = qmp->dev;
1905         int i;
1906         int ret;
1907
1908         qmp->resets = devm_kcalloc(dev, num_resets,
1909                                    sizeof(*qmp->resets), GFP_KERNEL);
1910         if (!qmp->resets)
1911                 return -ENOMEM;
1912
1913         for (i = 0; i < num_resets; i++)
1914                 qmp->resets[i].id = reset_list[i];
1915
1916         qmp->num_resets = num_resets;
1917
1918         ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
1919         if (ret)
1920                 return dev_err_probe(dev, ret, "failed to get resets\n");
1921
1922         return 0;
1923 }
1924
1925 static int qmp_usb_clk_init(struct qmp_usb *qmp)
1926 {
1927         struct device *dev = qmp->dev;
1928         int num = ARRAY_SIZE(qmp_usb_phy_clk_l);
1929         int i;
1930
1931         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1932         if (!qmp->clks)
1933                 return -ENOMEM;
1934
1935         for (i = 0; i < num; i++)
1936                 qmp->clks[i].id = qmp_usb_phy_clk_l[i];
1937
1938         qmp->num_clks = num;
1939
1940         return devm_clk_bulk_get_optional(dev, num, qmp->clks);
1941 }
1942
1943 static void phy_clk_release_provider(void *res)
1944 {
1945         of_clk_del_provider(res);
1946 }
1947
1948 /*
1949  * Register a fixed rate pipe clock.
1950  *
1951  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1952  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1953  * by the PHY driver for its operations.
1954  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1955  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1956  * Below picture shows this relationship.
1957  *
1958  *         +---------------+
1959  *         |   PHY block   |<<---------------------------------------+
1960  *         |               |                                         |
1961  *         |   +-------+   |                   +-----+               |
1962  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1963  *    clk  |   +-------+   |                   +-----+
1964  *         +---------------+
1965  */
1966 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
1967 {
1968         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
1969         struct clk_init_data init = { };
1970         int ret;
1971
1972         ret = of_property_read_string(np, "clock-output-names", &init.name);
1973         if (ret) {
1974                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1975                 return ret;
1976         }
1977
1978         init.ops = &clk_fixed_rate_ops;
1979
1980         /* controllers using QMP phys use 125MHz pipe clock interface */
1981         fixed->fixed_rate = 125000000;
1982         fixed->hw.init = &init;
1983
1984         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
1985         if (ret)
1986                 return ret;
1987
1988         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
1989         if (ret)
1990                 return ret;
1991
1992         /*
1993          * Roll a devm action because the clock provider is the child node, but
1994          * the child node is not actually a device.
1995          */
1996         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
1997 }
1998
1999 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2000                                         int index, bool exclusive)
2001 {
2002         struct resource res;
2003
2004         if (!exclusive) {
2005                 if (of_address_to_resource(np, index, &res))
2006                         return IOMEM_ERR_PTR(-EINVAL);
2007
2008                 return devm_ioremap(dev, res.start, resource_size(&res));
2009         }
2010
2011         return devm_of_iomap(dev, np, index, NULL);
2012 }
2013
2014 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2015 {
2016         struct platform_device *pdev = to_platform_device(qmp->dev);
2017         const struct qmp_phy_cfg *cfg = qmp->cfg;
2018         struct device *dev = qmp->dev;
2019         bool exclusive = true;
2020         int ret;
2021
2022         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2023         if (IS_ERR(qmp->serdes))
2024                 return PTR_ERR(qmp->serdes);
2025
2026         /*
2027          * FIXME: These bindings should be fixed to not rely on overlapping
2028          *        mappings for PCS.
2029          */
2030         if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2031                 exclusive = false;
2032         if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2033                 exclusive = false;
2034
2035         /*
2036          * Get memory resources for the PHY:
2037          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2038          * For single lane PHYs: pcs_misc (optional) -> 3.
2039          */
2040         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2041         if (IS_ERR(qmp->tx))
2042                 return PTR_ERR(qmp->tx);
2043
2044         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2045         if (IS_ERR(qmp->rx))
2046                 return PTR_ERR(qmp->rx);
2047
2048         qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2049         if (IS_ERR(qmp->pcs))
2050                 return PTR_ERR(qmp->pcs);
2051
2052         if (cfg->pcs_usb_offset)
2053                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2054
2055         qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2056
2057         if (IS_ERR(qmp->pcs_misc)) {
2058                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2059                 qmp->pcs_misc = NULL;
2060         }
2061
2062         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2063         if (IS_ERR(qmp->pipe_clk)) {
2064                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2065                                      "failed to get pipe clock\n");
2066         }
2067
2068         ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
2069         if (ret < 0)
2070                 return ret;
2071
2072         qmp->num_clks = ret;
2073
2074         ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,
2075                                  ARRAY_SIZE(usb3phy_legacy_reset_l));
2076         if (ret)
2077                 return ret;
2078
2079         return 0;
2080 }
2081
2082 static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2083 {
2084         struct platform_device *pdev = to_platform_device(qmp->dev);
2085         const struct qmp_phy_cfg *cfg = qmp->cfg;
2086         const struct qmp_usb_offsets *offs = cfg->offsets;
2087         struct device *dev = qmp->dev;
2088         void __iomem *base;
2089         int ret;
2090
2091         if (!offs)
2092                 return -EINVAL;
2093
2094         base = devm_platform_ioremap_resource(pdev, 0);
2095         if (IS_ERR(base))
2096                 return PTR_ERR(base);
2097
2098         qmp->serdes = base + offs->serdes;
2099         qmp->pcs = base + offs->pcs;
2100         if (offs->pcs_usb)
2101                 qmp->pcs_usb = base + offs->pcs_usb;
2102         if (offs->pcs_misc)
2103                 qmp->pcs_misc = base + offs->pcs_misc;
2104         qmp->tx = base + offs->tx;
2105         qmp->rx = base + offs->rx;
2106
2107         ret = qmp_usb_clk_init(qmp);
2108         if (ret)
2109                 return ret;
2110
2111         qmp->pipe_clk = devm_clk_get(dev, "pipe");
2112         if (IS_ERR(qmp->pipe_clk)) {
2113                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2114                                      "failed to get pipe clock\n");
2115         }
2116
2117         ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,
2118                                  ARRAY_SIZE(usb3phy_reset_l));
2119         if (ret)
2120                 return ret;
2121
2122         return 0;
2123 }
2124
2125 static int qmp_usb_probe(struct platform_device *pdev)
2126 {
2127         struct device *dev = &pdev->dev;
2128         struct phy_provider *phy_provider;
2129         struct device_node *np;
2130         struct qmp_usb *qmp;
2131         int ret;
2132
2133         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2134         if (!qmp)
2135                 return -ENOMEM;
2136
2137         qmp->dev = dev;
2138
2139         qmp->cfg = of_device_get_match_data(dev);
2140         if (!qmp->cfg)
2141                 return -EINVAL;
2142
2143         ret = qmp_usb_vreg_init(qmp);
2144         if (ret)
2145                 return ret;
2146
2147         /* Check for legacy binding with child node. */
2148         np = of_get_next_available_child(dev->of_node, NULL);
2149         if (np) {
2150                 ret = qmp_usb_parse_dt_legacy(qmp, np);
2151         } else {
2152                 np = of_node_get(dev->of_node);
2153                 ret = qmp_usb_parse_dt(qmp);
2154         }
2155         if (ret)
2156                 goto err_node_put;
2157
2158         pm_runtime_set_active(dev);
2159         ret = devm_pm_runtime_enable(dev);
2160         if (ret)
2161                 goto err_node_put;
2162         /*
2163          * Prevent runtime pm from being ON by default. Users can enable
2164          * it using power/control in sysfs.
2165          */
2166         pm_runtime_forbid(dev);
2167
2168         ret = phy_pipe_clk_register(qmp, np);
2169         if (ret)
2170                 goto err_node_put;
2171
2172         qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2173         if (IS_ERR(qmp->phy)) {
2174                 ret = PTR_ERR(qmp->phy);
2175                 dev_err(dev, "failed to create PHY: %d\n", ret);
2176                 goto err_node_put;
2177         }
2178
2179         phy_set_drvdata(qmp->phy, qmp);
2180
2181         of_node_put(np);
2182
2183         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2184
2185         return PTR_ERR_OR_ZERO(phy_provider);
2186
2187 err_node_put:
2188         of_node_put(np);
2189         return ret;
2190 }
2191
2192 static const struct of_device_id qmp_usb_of_match_table[] = {
2193         {
2194                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2195                 .data = &ipq6018_usb3phy_cfg,
2196         }, {
2197                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2198                 .data = &ipq8074_usb3phy_cfg,
2199         }, {
2200                 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2201                 .data = &ipq9574_usb3phy_cfg,
2202         }, {
2203                 .compatible = "qcom,msm8996-qmp-usb3-phy",
2204                 .data = &msm8996_usb3phy_cfg,
2205         }, {
2206                 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2207                 .data = &sa8775p_usb3_uniphy_cfg,
2208         }, {
2209                 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2210                 .data = &sc8280xp_usb3_uniphy_cfg,
2211         }, {
2212                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2213                 .data = &qmp_v3_usb3_uniphy_cfg,
2214         }, {
2215                 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2216                 .data = &sdx55_usb3_uniphy_cfg,
2217         }, {
2218                 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2219                 .data = &sdx65_usb3_uniphy_cfg,
2220         }, {
2221                 .compatible = "qcom,sdx75-qmp-usb3-uni-phy",
2222                 .data = &sdx75_usb3_uniphy_cfg,
2223         }, {
2224                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2225                 .data = &sm8150_usb3_uniphy_cfg,
2226         }, {
2227                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2228                 .data = &sm8250_usb3_uniphy_cfg,
2229         }, {
2230                 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2231                 .data = &sm8350_usb3_uniphy_cfg,
2232         }, {
2233                 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy",
2234                 .data = &x1e80100_usb3_uniphy_cfg,
2235         },
2236         { },
2237 };
2238 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2239
2240 static struct platform_driver qmp_usb_driver = {
2241         .probe          = qmp_usb_probe,
2242         .driver = {
2243                 .name   = "qcom-qmp-usb-phy",
2244                 .pm     = &qmp_usb_pm_ops,
2245                 .of_match_table = qmp_usb_of_match_table,
2246         },
2247 };
2248
2249 module_platform_driver(qmp_usb_driver);
2250
2251 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
2252 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2253 MODULE_LICENSE("GPL v2");