drivers/net/wireless/ath/ath12k/qmi.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #ifndef ATH12K_QMI_H
   8 #define ATH12K_QMI_H
   9
  10 #include <linux/mutex.h>
  11 #include <linux/soc/qcom/qmi.h>
  12
  13 #define ATH12K_HOST_VERSION_STRING              "WIN"
  14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS            10000
  15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE       64
  16 #define ATH12K_QMI_CALDB_ADDRESS                0x4BA00000
  17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01  128
  18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01          0x45
  19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01        0x01
  20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01      0x02
  21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1
  22
  23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274      0x07
  24 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
  25 #define ATH12K_QMI_RESP_LEN_MAX                 8192
  26 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01   52
  27 #define ATH12K_QMI_CALDB_SIZE                   0x480000
  28 #define ATH12K_QMI_BDF_EXT_STR_LENGTH           0x20
  29 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT       3
  30 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
  31 #define ATH12K_QMI_DEVMEM_CMEM_INDEX    0
  32
  33 #define QMI_WLFW_REQUEST_MEM_IND_V01            0x0035
  34 #define QMI_WLFW_FW_MEM_READY_IND_V01           0x0037
  35 #define QMI_WLFW_FW_READY_IND_V01               0x0038
  36
  37 #define QMI_WLANFW_MAX_DATA_SIZE_V01            6144
  38 #define ATH12K_FIRMWARE_MODE_OFF                4
  39 #define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT      0
  40
  41 #define ATH12K_BOARD_ID_DEFAULT 0xFF
  42
  43 struct ath12k_base;
  44
  45 enum ath12k_qmi_file_type {
  46         ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0,
  47         ATH12K_QMI_FILE_TYPE_CALDATA    = 2,
  48         ATH12K_QMI_FILE_TYPE_EEPROM     = 3,
  49         ATH12K_QMI_MAX_FILE_TYPE        = 4,
  50 };
  51
  52 enum ath12k_qmi_bdf_type {
  53         ATH12K_QMI_BDF_TYPE_BIN                 = 0,
  54         ATH12K_QMI_BDF_TYPE_ELF                 = 1,
  55         ATH12K_QMI_BDF_TYPE_REGDB               = 4,
  56         ATH12K_QMI_BDF_TYPE_CALIBRATION         = 5,
  57 };
  58
  59 enum ath12k_qmi_event_type {
  60         ATH12K_QMI_EVENT_SERVER_ARRIVE,
  61         ATH12K_QMI_EVENT_SERVER_EXIT,
  62         ATH12K_QMI_EVENT_REQUEST_MEM,
  63         ATH12K_QMI_EVENT_FW_MEM_READY,
  64         ATH12K_QMI_EVENT_FW_READY,
  65         ATH12K_QMI_EVENT_REGISTER_DRIVER,
  66         ATH12K_QMI_EVENT_UNREGISTER_DRIVER,
  67         ATH12K_QMI_EVENT_RECOVERY,
  68         ATH12K_QMI_EVENT_FORCE_FW_ASSERT,
  69         ATH12K_QMI_EVENT_POWER_UP,
  70         ATH12K_QMI_EVENT_POWER_DOWN,
  71         ATH12K_QMI_EVENT_MAX,
  72 };
  73
  74 struct ath12k_qmi_driver_event {
  75         struct list_head list;
  76         enum ath12k_qmi_event_type type;
  77         void *data;
  78 };
  79
  80 struct ath12k_qmi_ce_cfg {
  81         const struct ce_pipe_config *tgt_ce;
  82         int tgt_ce_len;
  83         const struct service_to_pipe *svc_to_ce_map;
  84         int svc_to_ce_map_len;
  85         const u8 *shadow_reg;
  86         int shadow_reg_len;
  87         u32 *shadow_reg_v3;
  88         int shadow_reg_v3_len;
  89 };
  90
  91 struct ath12k_qmi_event_msg {
  92         struct list_head list;
  93         enum ath12k_qmi_event_type type;
  94 };
  95
  96 struct target_mem_chunk {
  97         u32 size;
  98         u32 type;
  99         dma_addr_t paddr;
 100         union {
 101                 void __iomem *ioaddr;
 102                 void *addr;
 103         } v;
 104 };
 105
 106 struct target_info {
 107         u32 chip_id;
 108         u32 chip_family;
 109         u32 board_id;
 110         u32 soc_id;
 111         u32 fw_version;
 112         u32 eeprom_caldata;
 113         char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
 114         char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
 115         char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
 116 };
 117
 118 struct m3_mem_region {
 119         u32 size;
 120         dma_addr_t paddr;
 121         void *vaddr;
 122 };
 123
 124 struct dev_mem_info {
 125         u64 start;
 126         u64 size;
 127 };
 128
 129 struct ath12k_qmi {
 130         struct ath12k_base *ab;
 131         struct qmi_handle handle;
 132         struct sockaddr_qrtr sq;
 133         struct work_struct event_work;
 134         struct workqueue_struct *event_wq;
 135         struct list_head event_list;
 136         spinlock_t event_lock; /* spinlock for qmi event list */
 137         struct ath12k_qmi_ce_cfg ce_cfg;
 138         struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 139         u32 mem_seg_count;
 140         u32 target_mem_mode;
 141         bool target_mem_delayed;
 142         u8 cal_done;
 143         u8 num_radios;
 144         struct target_info target;
 145         struct m3_mem_region m3_mem;
 146         unsigned int service_ins_id;
 147         struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
 148 };
 149
 150 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN         261
 151 #define QMI_WLANFW_HOST_CAP_REQ_V01                     0x0034
 152 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN        7
 153 #define QMI_WLFW_HOST_CAP_RESP_V01                      0x0034
 154 #define QMI_WLFW_MAX_NUM_GPIO_V01                       32
 155 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01            64
 156 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01          3
 157
 158 struct qmi_wlanfw_host_ddr_range {
 159         u64 start;
 160         u64 size;
 161 };
 162
 163 enum ath12k_qmi_target_mem {
 164         HOST_DDR_REGION_TYPE = 0x1,
 165         BDF_MEM_REGION_TYPE = 0x2,
 166         M3_DUMP_REGION_TYPE = 0x3,
 167         CALDB_MEM_REGION_TYPE = 0x4,
 168         PAGEABLE_MEM_REGION_TYPE = 0x9,
 169 };
 170
 171 enum qmi_wlanfw_host_build_type {
 172         WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
 173         QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
 174         QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
 175         QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
 176         WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
 177 };
 178
 179 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
 180 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
 181
 182 struct wlfw_host_mlo_chip_info_s_v01 {
 183         u8 chip_id;
 184         u8 num_local_links;
 185         u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
 186         u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
 187 };
 188
 189 enum ath12k_qmi_cnss_feature {
 190         CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
 191         CNSS_QDSS_CFG_MISS_V01 = 3,
 192         CNSS_PCIE_PERST_NO_PULL_V01 = 4,
 193         CNSS_MAX_FEATURE_V01 = 64,
 194         CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
 195 };
 196
 197 struct qmi_wlanfw_host_cap_req_msg_v01 {
 198         u8 num_clients_valid;
 199         u32 num_clients;
 200         u8 wake_msi_valid;
 201         u32 wake_msi;
 202         u8 gpios_valid;
 203         u32 gpios_len;
 204         u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
 205         u8 nm_modem_valid;
 206         u8 nm_modem;
 207         u8 bdf_support_valid;
 208         u8 bdf_support;
 209         u8 bdf_cache_support_valid;
 210         u8 bdf_cache_support;
 211         u8 m3_support_valid;
 212         u8 m3_support;
 213         u8 m3_cache_support_valid;
 214         u8 m3_cache_support;
 215         u8 cal_filesys_support_valid;
 216         u8 cal_filesys_support;
 217         u8 cal_cache_support_valid;
 218         u8 cal_cache_support;
 219         u8 cal_done_valid;
 220         u8 cal_done;
 221         u8 mem_bucket_valid;
 222         u32 mem_bucket;
 223         u8 mem_cfg_mode_valid;
 224         u8 mem_cfg_mode;
 225         u8 cal_duration_valid;
 226         u16 cal_duraiton;
 227         u8 platform_name_valid;
 228         char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
 229         u8 ddr_range_valid;
 230         struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
 231         u8 host_build_type_valid;
 232         enum qmi_wlanfw_host_build_type host_build_type;
 233         u8 mlo_capable_valid;
 234         u8 mlo_capable;
 235         u8 mlo_chip_id_valid;
 236         u16 mlo_chip_id;
 237         u8 mlo_group_id_valid;
 238         u8 mlo_group_id;
 239         u8 max_mlo_peer_valid;
 240         u16 max_mlo_peer;
 241         u8 mlo_num_chips_valid;
 242         u8 mlo_num_chips;
 243         u8 mlo_chip_info_valid;
 244         struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
 245         u8 feature_list_valid;
 246         u64 feature_list;
 247
 248 };
 249
 250 struct qmi_wlanfw_host_cap_resp_msg_v01 {
 251         struct qmi_response_type_v01 resp;
 252 };
 253
 254 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN          0
 255 #define QMI_WLANFW_PHY_CAP_REQ_V01                      0x0057
 256 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN         18
 257 #define QMI_WLANFW_PHY_CAP_RESP_V01                     0x0057
 258
 259 struct qmi_wlanfw_phy_cap_req_msg_v01 {
 260 };
 261
 262 struct qmi_wlanfw_phy_cap_resp_msg_v01 {
 263         struct qmi_response_type_v01 resp;
 264         u8 num_phy_valid;
 265         u8 num_phy;
 266         u8 board_id_valid;
 267         u32 board_id;
 268 };
 269
 270 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN             54
 271 #define QMI_WLANFW_IND_REGISTER_REQ_V01                         0x0020
 272 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN            18
 273 #define QMI_WLANFW_IND_REGISTER_RESP_V01                        0x0020
 274 #define QMI_WLANFW_CLIENT_ID                                    0x4b4e454c
 275
 276 struct qmi_wlanfw_ind_register_req_msg_v01 {
 277         u8 fw_ready_enable_valid;
 278         u8 fw_ready_enable;
 279         u8 initiate_cal_download_enable_valid;
 280         u8 initiate_cal_download_enable;
 281         u8 initiate_cal_update_enable_valid;
 282         u8 initiate_cal_update_enable;
 283         u8 msa_ready_enable_valid;
 284         u8 msa_ready_enable;
 285         u8 pin_connect_result_enable_valid;
 286         u8 pin_connect_result_enable;
 287         u8 client_id_valid;
 288         u32 client_id;
 289         u8 request_mem_enable_valid;
 290         u8 request_mem_enable;
 291         u8 fw_mem_ready_enable_valid;
 292         u8 fw_mem_ready_enable;
 293         u8 fw_init_done_enable_valid;
 294         u8 fw_init_done_enable;
 295         u8 rejuvenate_enable_valid;
 296         u32 rejuvenate_enable;
 297         u8 xo_cal_enable_valid;
 298         u8 xo_cal_enable;
 299         u8 cal_done_enable_valid;
 300         u8 cal_done_enable;
 301 };
 302
 303 struct qmi_wlanfw_ind_register_resp_msg_v01 {
 304         struct qmi_response_type_v01 resp;
 305         u8 fw_status_valid;
 306         u64 fw_status;
 307 };
 308
 309 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN      1824
 310 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN      888
 311 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN     7
 312 #define QMI_WLANFW_REQUEST_MEM_IND_V01                  0x0035
 313 #define QMI_WLANFW_RESPOND_MEM_REQ_V01                  0x0036
 314 #define QMI_WLANFW_RESPOND_MEM_RESP_V01                 0x0036
 315 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01                  2
 316 #define QMI_WLANFW_MAX_STR_LEN_V01                      16
 317
 318 struct qmi_wlanfw_mem_cfg_s_v01 {
 319         u64 offset;
 320         u32 size;
 321         u8 secure_flag;
 322 };
 323
 324 enum qmi_wlanfw_mem_type_enum_v01 {
 325         WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
 326         QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
 327         QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
 328         QMI_WLANFW_MEM_BDF_V01 = 2,
 329         QMI_WLANFW_MEM_M3_V01 = 3,
 330         QMI_WLANFW_MEM_CAL_V01 = 4,
 331         QMI_WLANFW_MEM_DPD_V01 = 5,
 332         WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
 333 };
 334
 335 struct qmi_wlanfw_mem_seg_s_v01 {
 336         u32 size;
 337         enum qmi_wlanfw_mem_type_enum_v01 type;
 338         u32 mem_cfg_len;
 339         struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
 340 };
 341
 342 struct qmi_wlanfw_request_mem_ind_msg_v01 {
 343         u32 mem_seg_len;
 344         struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 345 };
 346
 347 struct qmi_wlanfw_mem_seg_resp_s_v01 {
 348         u64 addr;
 349         u32 size;
 350         enum qmi_wlanfw_mem_type_enum_v01 type;
 351         u8 restore;
 352 };
 353
 354 struct qmi_wlanfw_respond_mem_req_msg_v01 {
 355         u32 mem_seg_len;
 356         struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 357 };
 358
 359 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
 360         struct qmi_response_type_v01 resp;
 361 };
 362
 363 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
 364         char placeholder;
 365 };
 366
 367 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
 368         char placeholder;
 369 };
 370
 371 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN      0
 372 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN     207
 373 #define QMI_WLANFW_CAP_REQ_V01                  0x0024
 374 #define QMI_WLANFW_CAP_RESP_V01                 0x0024
 375
 376 enum qmi_wlanfw_pipedir_enum_v01 {
 377         QMI_WLFW_PIPEDIR_NONE_V01 = 0,
 378         QMI_WLFW_PIPEDIR_IN_V01 = 1,
 379         QMI_WLFW_PIPEDIR_OUT_V01 = 2,
 380         QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
 381 };
 382
 383 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
 384         __le32 pipe_num;
 385         __le32 pipe_dir;
 386         __le32 nentries;
 387         __le32 nbytes_max;
 388         __le32 flags;
 389 };
 390
 391 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
 392         __le32 service_id;
 393         __le32 pipe_dir;
 394         __le32 pipe_num;
 395 };
 396
 397 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
 398         u16 id;
 399         u16 offset;
 400 };
 401
 402 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
 403         u32 addr;
 404 };
 405
 406 struct qmi_wlanfw_memory_region_info_s_v01 {
 407         u64 region_addr;
 408         u32 size;
 409         u8 secure_flag;
 410 };
 411
 412 struct qmi_wlanfw_rf_chip_info_s_v01 {
 413         u32 chip_id;
 414         u32 chip_family;
 415 };
 416
 417 struct qmi_wlanfw_rf_board_info_s_v01 {
 418         u32 board_id;
 419 };
 420
 421 struct qmi_wlanfw_soc_info_s_v01 {
 422         u32 soc_id;
 423 };
 424
 425 struct qmi_wlanfw_fw_version_info_s_v01 {
 426         u32 fw_version;
 427         char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
 428 };
 429
 430 struct qmi_wlanfw_dev_mem_info_s_v01 {
 431         u64 start;
 432         u64 size;
 433 };
 434
 435 enum qmi_wlanfw_cal_temp_id_enum_v01 {
 436         QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
 437         QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
 438         QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
 439         QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
 440         QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
 441         QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
 442 };
 443
 444 enum qmi_wlanfw_rd_card_chain_cap_v01 {
 445         WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
 446         WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
 447         WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
 448         WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
 449         WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
 450 };
 451
 452 struct qmi_wlanfw_cap_resp_msg_v01 {
 453         struct qmi_response_type_v01 resp;
 454         u8 chip_info_valid;
 455         struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
 456         u8 board_info_valid;
 457         struct qmi_wlanfw_rf_board_info_s_v01 board_info;
 458         u8 soc_info_valid;
 459         struct qmi_wlanfw_soc_info_s_v01 soc_info;
 460         u8 fw_version_info_valid;
 461         struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
 462         u8 fw_build_id_valid;
 463         char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
 464         u8 num_macs_valid;
 465         u8 num_macs;
 466         u8 voltage_mv_valid;
 467         u32 voltage_mv;
 468         u8 time_freq_hz_valid;
 469         u32 time_freq_hz;
 470         u8 otp_version_valid;
 471         u32 otp_version;
 472         u8 eeprom_caldata_read_timeout_valid;
 473         u32 eeprom_caldata_read_timeout;
 474         u8 fw_caps_valid;
 475         u64 fw_caps;
 476         u8 rd_card_chain_cap_valid;
 477         enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
 478         u8 dev_mem_info_valid;
 479         struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
 480 };
 481
 482 struct qmi_wlanfw_cap_req_msg_v01 {
 483         char placeholder;
 484 };
 485
 486 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN     6182
 487 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN    7
 488 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01                0x0025
 489 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01                 0x0025
 490 /* TODO: Need to check with MCL and FW team that data can be pointer and
 491  * can be last element in structure
 492  */
 493 struct qmi_wlanfw_bdf_download_req_msg_v01 {
 494         u8 valid;
 495         u8 file_id_valid;
 496         enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
 497         u8 total_size_valid;
 498         u32 total_size;
 499         u8 seg_id_valid;
 500         u32 seg_id;
 501         u8 data_valid;
 502         u32 data_len;
 503         u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
 504         u8 end_valid;
 505         u8 end;
 506         u8 bdf_type_valid;
 507         u8 bdf_type;
 508
 509 };
 510
 511 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
 512         struct qmi_response_type_v01 resp;
 513 };
 514
 515 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN      18
 516 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN     7
 517 #define QMI_WLANFW_M3_INFO_RESP_V01             0x003C
 518 #define QMI_WLANFW_M3_INFO_REQ_V01              0x003C
 519
 520 struct qmi_wlanfw_m3_info_req_msg_v01 {
 521         u64 addr;
 522         u32 size;
 523 };
 524
 525 struct qmi_wlanfw_m3_info_resp_msg_v01 {
 526         struct qmi_response_type_v01 resp;
 527 };
 528
 529 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN        11
 530 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN       7
 531 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN         803
 532 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN        7
 533 #define QMI_WLANFW_WLAN_MODE_REQ_V01                    0x0022
 534 #define QMI_WLANFW_WLAN_MODE_RESP_V01                   0x0022
 535 #define QMI_WLANFW_WLAN_CFG_REQ_V01                     0x0023
 536 #define QMI_WLANFW_WLAN_CFG_RESP_V01                    0x0023
 537 #define QMI_WLANFW_MAX_STR_LEN_V01                      16
 538 #define QMI_WLANFW_MAX_NUM_CE_V01                       12
 539 #define QMI_WLANFW_MAX_NUM_SVC_V01                      24
 540 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01               24
 541 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01            60
 542
 543 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
 544         u32 mode;
 545         u8 hw_debug_valid;
 546         u8 hw_debug;
 547 };
 548
 549 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
 550         struct qmi_response_type_v01 resp;
 551 };
 552
 553 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
 554         u8 host_version_valid;
 555         char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
 556         u8  tgt_cfg_valid;
 557         u32  tgt_cfg_len;
 558         struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
 559                         tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
 560         u8  svc_cfg_valid;
 561         u32 svc_cfg_len;
 562         struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
 563                         svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
 564         u8 shadow_reg_valid;
 565         u32 shadow_reg_len;
 566         struct qmi_wlanfw_shadow_reg_cfg_s_v01
 567                 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
 568         u8 shadow_reg_v3_valid;
 569         u32 shadow_reg_v3_len;
 570         struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
 571                 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
 572 };
 573
 574 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
 575         struct qmi_response_type_v01 resp;
 576 };
 577
 578 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01      0x002F
 579 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01     0x002F
 580 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN         7
 581 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN        7
 582
 583 struct qmi_wlanfw_wlan_ini_req_msg_v01 {
 584         /* Must be set to true if enable_fwlog is being passed */
 585         u8 enable_fwlog_valid;
 586         u8 enable_fwlog;
 587 };
 588
 589 struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
 590         struct qmi_response_type_v01 resp;
 591 };
 592
 593 int ath12k_qmi_firmware_start(struct ath12k_base *ab,
 594                               u32 mode);
 595 void ath12k_qmi_firmware_stop(struct ath12k_base *ab);
 596 void ath12k_qmi_deinit_service(struct ath12k_base *ab);
 597 int ath12k_qmi_init_service(struct ath12k_base *ab);
 598 void ath12k_qmi_free_resource(struct ath12k_base *ab);
 599
 600 #endif