drivers/net/wireless/ath/ath12k/hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #ifndef ATH12K_HW_H
   8 #define ATH12K_HW_H
   9
  10 #include <linux/mhi.h>
  11
  12 #include "wmi.h"
  13 #include "hal.h"
  14
  15 /* Target configuration defines */
  16
  17 /* Num VDEVS per radio */
  18 #define TARGET_NUM_VDEVS        (16 + 1)
  19
  20 #define TARGET_NUM_PEERS_PDEV_SINGLE    (TARGET_NUM_STATIONS_SINGLE + \
  21                                          TARGET_NUM_VDEVS)
  22 #define TARGET_NUM_PEERS_PDEV_DBS       (TARGET_NUM_STATIONS_DBS + \
  23                                          TARGET_NUM_VDEVS)
  24 #define TARGET_NUM_PEERS_PDEV_DBS_SBS   (TARGET_NUM_STATIONS_DBS_SBS + \
  25                                          TARGET_NUM_VDEVS)
  26
  27 /* Num of peers for Single Radio mode */
  28 #define TARGET_NUM_PEERS_SINGLE         (TARGET_NUM_PEERS_PDEV_SINGLE)
  29
  30 /* Num of peers for DBS */
  31 #define TARGET_NUM_PEERS_DBS            (2 * TARGET_NUM_PEERS_PDEV_DBS)
  32
  33 /* Num of peers for DBS_SBS */
  34 #define TARGET_NUM_PEERS_DBS_SBS        (3 * TARGET_NUM_PEERS_PDEV_DBS_SBS)
  35
  36 /* Max num of stations for Single Radio mode */
  37 #define TARGET_NUM_STATIONS_SINGLE      512
  38
  39 /* Max num of stations for DBS */
  40 #define TARGET_NUM_STATIONS_DBS         128
  41
  42 /* Max num of stations for DBS_SBS */
  43 #define TARGET_NUM_STATIONS_DBS_SBS     128
  44
  45 #define TARGET_NUM_PEERS(x)     TARGET_NUM_PEERS_##x
  46 #define TARGET_NUM_PEER_KEYS    2
  47 #define TARGET_NUM_TIDS(x)      (2 * TARGET_NUM_PEERS(x) + \
  48                                  4 * TARGET_NUM_VDEVS + 8)
  49
  50 #define TARGET_AST_SKID_LIMIT   16
  51 #define TARGET_NUM_OFFLD_PEERS  4
  52 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
  53
  54 #define TARGET_TX_CHAIN_MASK    (BIT(0) | BIT(1) | BIT(2) | BIT(4))
  55 #define TARGET_RX_CHAIN_MASK    (BIT(0) | BIT(1) | BIT(2) | BIT(4))
  56 #define TARGET_RX_TIMEOUT_LO_PRI        100
  57 #define TARGET_RX_TIMEOUT_HI_PRI        40
  58
  59 #define TARGET_DECAP_MODE_RAW           0
  60 #define TARGET_DECAP_MODE_NATIVE_WIFI   1
  61 #define TARGET_DECAP_MODE_ETH           2
  62
  63 #define TARGET_SCAN_MAX_PENDING_REQS    4
  64 #define TARGET_BMISS_OFFLOAD_MAX_VDEV   3
  65 #define TARGET_ROAM_OFFLOAD_MAX_VDEV    3
  66 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES     8
  67 #define TARGET_GTK_OFFLOAD_MAX_VDEV     3
  68 #define TARGET_NUM_MCAST_GROUPS         12
  69 #define TARGET_NUM_MCAST_TABLE_ELEMS    64
  70 #define TARGET_MCAST2UCAST_MODE         2
  71 #define TARGET_TX_DBG_LOG_SIZE          1024
  72 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
  73 #define TARGET_VOW_CONFIG               0
  74 #define TARGET_NUM_MSDU_DESC            (2500)
  75 #define TARGET_MAX_FRAG_ENTRIES         6
  76 #define TARGET_MAX_BCN_OFFLD            16
  77 #define TARGET_NUM_WDS_ENTRIES          32
  78 #define TARGET_DMA_BURST_SIZE           1
  79 #define TARGET_RX_BATCHMODE             1
  80 #define TARGET_RX_PEER_METADATA_VER_V1A 2
  81 #define TARGET_RX_PEER_METADATA_VER_V1B 3
  82
  83 #define ATH12K_HW_MAX_QUEUES            4
  84 #define ATH12K_QUEUE_LEN                4096
  85
  86 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK  0x4
  87
  88 #define ATH12K_FW_DIR                   "ath12k"
  89
  90 #define ATH12K_BOARD_MAGIC              "QCA-ATH12K-BOARD"
  91 #define ATH12K_BOARD_API2_FILE          "board-2.bin"
  92 #define ATH12K_DEFAULT_BOARD_FILE       "board.bin"
  93 #define ATH12K_DEFAULT_CAL_FILE         "caldata.bin"
  94 #define ATH12K_AMSS_FILE                "amss.bin"
  95 #define ATH12K_M3_FILE                  "m3.bin"
  96 #define ATH12K_REGDB_FILE_NAME          "regdb.bin"
  97
  98 enum ath12k_hw_rate_cck {
  99         ATH12K_HW_RATE_CCK_LP_11M = 0,
 100         ATH12K_HW_RATE_CCK_LP_5_5M,
 101         ATH12K_HW_RATE_CCK_LP_2M,
 102         ATH12K_HW_RATE_CCK_LP_1M,
 103         ATH12K_HW_RATE_CCK_SP_11M,
 104         ATH12K_HW_RATE_CCK_SP_5_5M,
 105         ATH12K_HW_RATE_CCK_SP_2M,
 106 };
 107
 108 enum ath12k_hw_rate_ofdm {
 109         ATH12K_HW_RATE_OFDM_48M = 0,
 110         ATH12K_HW_RATE_OFDM_24M,
 111         ATH12K_HW_RATE_OFDM_12M,
 112         ATH12K_HW_RATE_OFDM_6M,
 113         ATH12K_HW_RATE_OFDM_54M,
 114         ATH12K_HW_RATE_OFDM_36M,
 115         ATH12K_HW_RATE_OFDM_18M,
 116         ATH12K_HW_RATE_OFDM_9M,
 117 };
 118
 119 enum ath12k_bus {
 120         ATH12K_BUS_PCI,
 121 };
 122
 123 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11
 124
 125 struct hal_rx_desc;
 126 struct hal_tcl_data_cmd;
 127 struct htt_rx_ring_tlv_filter;
 128 enum hal_encrypt_type;
 129
 130 struct ath12k_hw_ring_mask {
 131         u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 132         u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 133         u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 134         u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 135         u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 136         u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 137         u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 138         u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
 139 };
 140
 141 struct ath12k_hw_hal_params {
 142         enum hal_rx_buf_return_buf_manager rx_buf_rbm;
 143         u32       wbm2sw_cc_enable;
 144 };
 145
 146 struct ath12k_hw_params {
 147         const char *name;
 148         u16 hw_rev;
 149
 150         struct {
 151                 const char *dir;
 152                 size_t board_size;
 153                 size_t cal_offset;
 154         } fw;
 155
 156         u8 max_radios;
 157         bool single_pdev_only:1;
 158         u32 qmi_service_ins_id;
 159         bool internal_sleep_clock:1;
 160
 161         const struct ath12k_hw_ops *hw_ops;
 162         const struct ath12k_hw_ring_mask *ring_mask;
 163         const struct ath12k_hw_regs *regs;
 164
 165         const struct ce_attr *host_ce_config;
 166         u32 ce_count;
 167         const struct ce_pipe_config *target_ce_config;
 168         u32 target_ce_count;
 169         const struct service_to_pipe *svc_to_ce_map;
 170         u32 svc_to_ce_map_len;
 171
 172         const struct ath12k_hw_hal_params *hal_params;
 173
 174         bool rxdma1_enable:1;
 175         int num_rxmda_per_pdev;
 176         int num_rxdma_dst_ring;
 177         bool rx_mac_buf_ring:1;
 178         bool vdev_start_delay:1;
 179
 180         u16 interface_modes;
 181         bool supports_monitor:1;
 182
 183         bool idle_ps:1;
 184         bool download_calib:1;
 185         bool supports_suspend:1;
 186         bool tcl_ring_retry:1;
 187         bool reoq_lut_support:1;
 188         bool supports_shadow_regs:1;
 189
 190         u32 num_tcl_banks;
 191         u32 max_tx_ring;
 192
 193         const struct mhi_controller_config *mhi_config;
 194
 195         void (*wmi_init)(struct ath12k_base *ab,
 196                          struct ath12k_wmi_resource_config_arg *config);
 197
 198         const struct hal_ops *hal_ops;
 199
 200         u64 qmi_cnss_feature_bitmap;
 201
 202         u32 rfkill_pin;
 203         u32 rfkill_cfg;
 204         u32 rfkill_on_level;
 205
 206         u32 rddm_size;
 207
 208         u8 def_num_link;
 209         u16 max_mlo_peer;
 210
 211         u32 otp_board_id_register;
 212
 213         bool supports_sta_ps;
 214 };
 215
 216 struct ath12k_hw_ops {
 217         u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
 218         int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id);
 219         int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id);
 220         int (*rxdma_ring_sel_config)(struct ath12k_base *ab);
 221         u8 (*get_ring_selector)(struct sk_buff *skb);
 222         bool (*dp_srng_is_tx_comp_ring)(int ring_num);
 223 };
 224
 225 static inline
 226 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw,
 227                                    int pdev_idx)
 228 {
 229         if (hw->hw_ops->get_hw_mac_from_pdev_id)
 230                 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
 231
 232         return 0;
 233 }
 234
 235 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw,
 236                                               int mac_id)
 237 {
 238         if (hw->hw_ops->mac_id_to_pdev_id)
 239                 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
 240
 241         return 0;
 242 }
 243
 244 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw,
 245                                               int mac_id)
 246 {
 247         if (hw->hw_ops->mac_id_to_srng_id)
 248                 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
 249
 250         return 0;
 251 }
 252
 253 struct ath12k_fw_ie {
 254         __le32 id;
 255         __le32 len;
 256         u8 data[];
 257 };
 258
 259 enum ath12k_bd_ie_board_type {
 260         ATH12K_BD_IE_BOARD_NAME = 0,
 261         ATH12K_BD_IE_BOARD_DATA = 1,
 262 };
 263
 264 enum ath12k_bd_ie_regdb_type {
 265         ATH12K_BD_IE_REGDB_NAME = 0,
 266         ATH12K_BD_IE_REGDB_DATA = 1,
 267 };
 268
 269 enum ath12k_bd_ie_type {
 270         /* contains sub IEs of enum ath12k_bd_ie_board_type */
 271         ATH12K_BD_IE_BOARD = 0,
 272         /* contains sub IEs of enum ath12k_bd_ie_regdb_type */
 273         ATH12K_BD_IE_REGDB = 1,
 274 };
 275
 276 struct ath12k_hw_regs {
 277         u32 hal_tcl1_ring_id;
 278         u32 hal_tcl1_ring_misc;
 279         u32 hal_tcl1_ring_tp_addr_lsb;
 280         u32 hal_tcl1_ring_tp_addr_msb;
 281         u32 hal_tcl1_ring_consumer_int_setup_ix0;
 282         u32 hal_tcl1_ring_consumer_int_setup_ix1;
 283         u32 hal_tcl1_ring_msi1_base_lsb;
 284         u32 hal_tcl1_ring_msi1_base_msb;
 285         u32 hal_tcl1_ring_msi1_data;
 286         u32 hal_tcl_ring_base_lsb;
 287
 288         u32 hal_tcl_status_ring_base_lsb;
 289
 290         u32 hal_wbm_idle_ring_base_lsb;
 291         u32 hal_wbm_idle_ring_misc_addr;
 292         u32 hal_wbm_r0_idle_list_cntl_addr;
 293         u32 hal_wbm_r0_idle_list_size_addr;
 294         u32 hal_wbm_scattered_ring_base_lsb;
 295         u32 hal_wbm_scattered_ring_base_msb;
 296         u32 hal_wbm_scattered_desc_head_info_ix0;
 297         u32 hal_wbm_scattered_desc_head_info_ix1;
 298         u32 hal_wbm_scattered_desc_tail_info_ix0;
 299         u32 hal_wbm_scattered_desc_tail_info_ix1;
 300         u32 hal_wbm_scattered_desc_ptr_hp_addr;
 301
 302         u32 hal_wbm_sw_release_ring_base_lsb;
 303         u32 hal_wbm_sw1_release_ring_base_lsb;
 304         u32 hal_wbm0_release_ring_base_lsb;
 305         u32 hal_wbm1_release_ring_base_lsb;
 306
 307         u32 pcie_qserdes_sysclk_en_sel;
 308         u32 pcie_pcs_osc_dtct_config_base;
 309
 310         u32 hal_ppe_rel_ring_base;
 311
 312         u32 hal_reo2_ring_base;
 313         u32 hal_reo1_misc_ctrl_addr;
 314         u32 hal_reo1_sw_cookie_cfg0;
 315         u32 hal_reo1_sw_cookie_cfg1;
 316         u32 hal_reo1_qdesc_lut_base0;
 317         u32 hal_reo1_qdesc_lut_base1;
 318         u32 hal_reo1_ring_base_lsb;
 319         u32 hal_reo1_ring_base_msb;
 320         u32 hal_reo1_ring_id;
 321         u32 hal_reo1_ring_misc;
 322         u32 hal_reo1_ring_hp_addr_lsb;
 323         u32 hal_reo1_ring_hp_addr_msb;
 324         u32 hal_reo1_ring_producer_int_setup;
 325         u32 hal_reo1_ring_msi1_base_lsb;
 326         u32 hal_reo1_ring_msi1_base_msb;
 327         u32 hal_reo1_ring_msi1_data;
 328         u32 hal_reo1_aging_thres_ix0;
 329         u32 hal_reo1_aging_thres_ix1;
 330         u32 hal_reo1_aging_thres_ix2;
 331         u32 hal_reo1_aging_thres_ix3;
 332
 333         u32 hal_reo2_sw0_ring_base;
 334
 335         u32 hal_sw2reo_ring_base;
 336         u32 hal_sw2reo1_ring_base;
 337
 338         u32 hal_reo_cmd_ring_base;
 339
 340         u32 hal_reo_status_ring_base;
 341 };
 342
 343 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)
 344 {
 345         switch (type) {
 346         case ATH12K_BD_IE_BOARD:
 347                 return "board data";
 348         case ATH12K_BD_IE_REGDB:
 349                 return "regdb data";
 350         }
 351
 352         return "unknown";
 353 }
 354
 355 int ath12k_hw_init(struct ath12k_base *ab);
 356
 357 #endif