drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* drivers/net/phy/realtek.c
   3  *
   4  * Driver for Realtek PHYs
   5  *
   6  * Author: Johnson Leung <[email protected]>
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  */
  10 #include <linux/bitops.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16
  17 #define RTL821x_PHYSR                           0x11
  18 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  19 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  20
  21 #define RTL821x_INER                            0x12
  22 #define RTL8211B_INER_INIT                      0x6400
  23 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  24 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  25
  26 #define RTL821x_INSR                            0x13
  27
  28 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  29 #define RTL821x_PAGE_SELECT                     0x1f
  30
  31 #define RTL8211F_PHYCR1                         0x18
  32 #define RTL8211F_PHYCR2                         0x19
  33 #define RTL8211F_INSR                           0x1d
  34
  35 #define RTL8211F_TX_DELAY                       BIT(8)
  36 #define RTL8211F_RX_DELAY                       BIT(3)
  37
  38 #define RTL8211F_ALDPS_PLL_OFF                  BIT(1)
  39 #define RTL8211F_ALDPS_ENABLE                   BIT(2)
  40 #define RTL8211F_ALDPS_XTAL_OFF                 BIT(12)
  41
  42 #define RTL8211E_CTRL_DELAY                     BIT(13)
  43 #define RTL8211E_TX_DELAY                       BIT(12)
  44 #define RTL8211E_RX_DELAY                       BIT(11)
  45
  46 #define RTL8211F_CLKOUT_EN                      BIT(0)
  47
  48 #define RTL8201F_ISR                            0x1e
  49 #define RTL8201F_ISR_ANERR                      BIT(15)
  50 #define RTL8201F_ISR_DUPLEX                     BIT(13)
  51 #define RTL8201F_ISR_LINK                       BIT(11)
  52 #define RTL8201F_ISR_MASK                       (RTL8201F_ISR_ANERR | \
  53                                                  RTL8201F_ISR_DUPLEX | \
  54                                                  RTL8201F_ISR_LINK)
  55 #define RTL8201F_IER                            0x13
  56
  57 #define RTL8366RB_POWER_SAVE                    0x15
  58 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  59
  60 #define RTL9000A_GINMR                          0x14
  61 #define RTL9000A_GINMR_LINK_STATUS              BIT(4)
  62
  63 #define RTLGEN_SPEED_MASK                       0x0630
  64
  65 #define RTL_GENERIC_PHYID                       0x001cc800
  66 #define RTL_8211FVD_PHYID                       0x001cc878
  67
  68 MODULE_DESCRIPTION("Realtek PHY driver");
  69 MODULE_AUTHOR("Johnson Leung");
  70 MODULE_LICENSE("GPL");
  71
  72 struct rtl821x_priv {
  73         u16 phycr1;
  74         u16 phycr2;
  75         bool has_phycr2;
  76         struct clk *clk;
  77 };
  78
  79 static int rtl821x_read_page(struct phy_device *phydev)
  80 {
  81         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  82 }
  83
  84 static int rtl821x_write_page(struct phy_device *phydev, int page)
  85 {
  86         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  87 }
  88
  89 static int rtl821x_probe(struct phy_device *phydev)
  90 {
  91         struct device *dev = &phydev->mdio.dev;
  92         struct rtl821x_priv *priv;
  93         u32 phy_id = phydev->drv->phy_id;
  94         int ret;
  95
  96         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  97         if (!priv)
  98                 return -ENOMEM;
  99
 100         priv->clk = devm_clk_get_optional_enabled(dev, NULL);
 101         if (IS_ERR(priv->clk))
 102                 return dev_err_probe(dev, PTR_ERR(priv->clk),
 103                                      "failed to get phy clock\n");
 104
 105         ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
 106         if (ret < 0)
 107                 return ret;
 108
 109         priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
 110         if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
 111                 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
 112
 113         priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
 114         if (priv->has_phycr2) {
 115                 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
 116                 if (ret < 0)
 117                         return ret;
 118
 119                 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
 120                 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
 121                         priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
 122         }
 123
 124         phydev->priv = priv;
 125
 126         return 0;
 127 }
 128
 129 static int rtl8201_ack_interrupt(struct phy_device *phydev)
 130 {
 131         int err;
 132
 133         err = phy_read(phydev, RTL8201F_ISR);
 134
 135         return (err < 0) ? err : 0;
 136 }
 137
 138 static int rtl821x_ack_interrupt(struct phy_device *phydev)
 139 {
 140         int err;
 141
 142         err = phy_read(phydev, RTL821x_INSR);
 143
 144         return (err < 0) ? err : 0;
 145 }
 146
 147 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
 148 {
 149         int err;
 150
 151         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 152
 153         return (err < 0) ? err : 0;
 154 }
 155
 156 static int rtl8201_config_intr(struct phy_device *phydev)
 157 {
 158         u16 val;
 159         int err;
 160
 161         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 162                 err = rtl8201_ack_interrupt(phydev);
 163                 if (err)
 164                         return err;
 165
 166                 val = BIT(13) | BIT(12) | BIT(11);
 167                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 168         } else {
 169                 val = 0;
 170                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 171                 if (err)
 172                         return err;
 173
 174                 err = rtl8201_ack_interrupt(phydev);
 175         }
 176
 177         return err;
 178 }
 179
 180 static int rtl8211b_config_intr(struct phy_device *phydev)
 181 {
 182         int err;
 183
 184         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 185                 err = rtl821x_ack_interrupt(phydev);
 186                 if (err)
 187                         return err;
 188
 189                 err = phy_write(phydev, RTL821x_INER,
 190                                 RTL8211B_INER_INIT);
 191         } else {
 192                 err = phy_write(phydev, RTL821x_INER, 0);
 193                 if (err)
 194                         return err;
 195
 196                 err = rtl821x_ack_interrupt(phydev);
 197         }
 198
 199         return err;
 200 }
 201
 202 static int rtl8211e_config_intr(struct phy_device *phydev)
 203 {
 204         int err;
 205
 206         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 207                 err = rtl821x_ack_interrupt(phydev);
 208                 if (err)
 209                         return err;
 210
 211                 err = phy_write(phydev, RTL821x_INER,
 212                                 RTL8211E_INER_LINK_STATUS);
 213         } else {
 214                 err = phy_write(phydev, RTL821x_INER, 0);
 215                 if (err)
 216                         return err;
 217
 218                 err = rtl821x_ack_interrupt(phydev);
 219         }
 220
 221         return err;
 222 }
 223
 224 static int rtl8211f_config_intr(struct phy_device *phydev)
 225 {
 226         u16 val;
 227         int err;
 228
 229         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 230                 err = rtl8211f_ack_interrupt(phydev);
 231                 if (err)
 232                         return err;
 233
 234                 val = RTL8211F_INER_LINK_STATUS;
 235                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 236         } else {
 237                 val = 0;
 238                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 239                 if (err)
 240                         return err;
 241
 242                 err = rtl8211f_ack_interrupt(phydev);
 243         }
 244
 245         return err;
 246 }
 247
 248 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
 249 {
 250         int irq_status;
 251
 252         irq_status = phy_read(phydev, RTL8201F_ISR);
 253         if (irq_status < 0) {
 254                 phy_error(phydev);
 255                 return IRQ_NONE;
 256         }
 257
 258         if (!(irq_status & RTL8201F_ISR_MASK))
 259                 return IRQ_NONE;
 260
 261         phy_trigger_machine(phydev);
 262
 263         return IRQ_HANDLED;
 264 }
 265
 266 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
 267 {
 268         int irq_status, irq_enabled;
 269
 270         irq_status = phy_read(phydev, RTL821x_INSR);
 271         if (irq_status < 0) {
 272                 phy_error(phydev);
 273                 return IRQ_NONE;
 274         }
 275
 276         irq_enabled = phy_read(phydev, RTL821x_INER);
 277         if (irq_enabled < 0) {
 278                 phy_error(phydev);
 279                 return IRQ_NONE;
 280         }
 281
 282         if (!(irq_status & irq_enabled))
 283                 return IRQ_NONE;
 284
 285         phy_trigger_machine(phydev);
 286
 287         return IRQ_HANDLED;
 288 }
 289
 290 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
 291 {
 292         int irq_status;
 293
 294         irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 295         if (irq_status < 0) {
 296                 phy_error(phydev);
 297                 return IRQ_NONE;
 298         }
 299
 300         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
 301                 return IRQ_NONE;
 302
 303         phy_trigger_machine(phydev);
 304
 305         return IRQ_HANDLED;
 306 }
 307
 308 static int rtl8211_config_aneg(struct phy_device *phydev)
 309 {
 310         int ret;
 311
 312         ret = genphy_config_aneg(phydev);
 313         if (ret < 0)
 314                 return ret;
 315
 316         /* Quirk was copied from vendor driver. Unfortunately it includes no
 317          * description of the magic numbers.
 318          */
 319         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 320                 phy_write(phydev, 0x17, 0x2138);
 321                 phy_write(phydev, 0x0e, 0x0260);
 322         } else {
 323                 phy_write(phydev, 0x17, 0x2108);
 324                 phy_write(phydev, 0x0e, 0x0000);
 325         }
 326
 327         return 0;
 328 }
 329
 330 static int rtl8211c_config_init(struct phy_device *phydev)
 331 {
 332         /* RTL8211C has an issue when operating in Gigabit slave mode */
 333         return phy_set_bits(phydev, MII_CTRL1000,
 334                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 335 }
 336
 337 static int rtl8211f_config_init(struct phy_device *phydev)
 338 {
 339         struct rtl821x_priv *priv = phydev->priv;
 340         struct device *dev = &phydev->mdio.dev;
 341         u16 val_txdly, val_rxdly;
 342         int ret;
 343
 344         ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
 345                                        RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
 346                                        priv->phycr1);
 347         if (ret < 0) {
 348                 dev_err(dev, "aldps mode  configuration failed: %pe\n",
 349                         ERR_PTR(ret));
 350                 return ret;
 351         }
 352
 353         switch (phydev->interface) {
 354         case PHY_INTERFACE_MODE_RGMII:
 355                 val_txdly = 0;
 356                 val_rxdly = 0;
 357                 break;
 358
 359         case PHY_INTERFACE_MODE_RGMII_RXID:
 360                 val_txdly = 0;
 361                 val_rxdly = RTL8211F_RX_DELAY;
 362                 break;
 363
 364         case PHY_INTERFACE_MODE_RGMII_TXID:
 365                 val_txdly = RTL8211F_TX_DELAY;
 366                 val_rxdly = 0;
 367                 break;
 368
 369         case PHY_INTERFACE_MODE_RGMII_ID:
 370                 val_txdly = RTL8211F_TX_DELAY;
 371                 val_rxdly = RTL8211F_RX_DELAY;
 372                 break;
 373
 374         default: /* the rest of the modes imply leaving delay as is. */
 375                 return 0;
 376         }
 377
 378         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 379                                        val_txdly);
 380         if (ret < 0) {
 381                 dev_err(dev, "Failed to update the TX delay register\n");
 382                 return ret;
 383         } else if (ret) {
 384                 dev_dbg(dev,
 385                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 386                         val_txdly ? "Enabling" : "Disabling");
 387         } else {
 388                 dev_dbg(dev,
 389                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 390                         val_txdly ? "enabled" : "disabled");
 391         }
 392
 393         ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
 394                                        val_rxdly);
 395         if (ret < 0) {
 396                 dev_err(dev, "Failed to update the RX delay register\n");
 397                 return ret;
 398         } else if (ret) {
 399                 dev_dbg(dev,
 400                         "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
 401                         val_rxdly ? "Enabling" : "Disabling");
 402         } else {
 403                 dev_dbg(dev,
 404                         "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
 405                         val_rxdly ? "enabled" : "disabled");
 406         }
 407
 408         if (priv->has_phycr2) {
 409                 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
 410                                        RTL8211F_CLKOUT_EN, priv->phycr2);
 411                 if (ret < 0) {
 412                         dev_err(dev, "clkout configuration failed: %pe\n",
 413                                 ERR_PTR(ret));
 414                         return ret;
 415                 }
 416
 417                 return genphy_soft_reset(phydev);
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int rtl821x_suspend(struct phy_device *phydev)
 424 {
 425         struct rtl821x_priv *priv = phydev->priv;
 426         int ret = 0;
 427
 428         if (!phydev->wol_enabled) {
 429                 ret = genphy_suspend(phydev);
 430
 431                 if (ret)
 432                         return ret;
 433
 434                 clk_disable_unprepare(priv->clk);
 435         }
 436
 437         return ret;
 438 }
 439
 440 static int rtl821x_resume(struct phy_device *phydev)
 441 {
 442         struct rtl821x_priv *priv = phydev->priv;
 443         int ret;
 444
 445         if (!phydev->wol_enabled)
 446                 clk_prepare_enable(priv->clk);
 447
 448         ret = genphy_resume(phydev);
 449         if (ret < 0)
 450                 return ret;
 451
 452         msleep(20);
 453
 454         return 0;
 455 }
 456
 457 static int rtl8211e_config_init(struct phy_device *phydev)
 458 {
 459         int ret = 0, oldpage;
 460         u16 val;
 461
 462         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 463         switch (phydev->interface) {
 464         case PHY_INTERFACE_MODE_RGMII:
 465                 val = RTL8211E_CTRL_DELAY | 0;
 466                 break;
 467         case PHY_INTERFACE_MODE_RGMII_ID:
 468                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 469                 break;
 470         case PHY_INTERFACE_MODE_RGMII_RXID:
 471                 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
 472                 break;
 473         case PHY_INTERFACE_MODE_RGMII_TXID:
 474                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
 475                 break;
 476         default: /* the rest of the modes imply leaving delays as is. */
 477                 return 0;
 478         }
 479
 480         /* According to a sample driver there is a 0x1c config register on the
 481          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 482          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
 483          * The configuration register definition:
 484          * 14 = reserved
 485          * 13 = Force Tx RX Delay controlled by bit12 bit11,
 486          * 12 = RX Delay, 11 = TX Delay
 487          * 10:0 = Test && debug settings reserved by realtek
 488          */
 489         oldpage = phy_select_page(phydev, 0x7);
 490         if (oldpage < 0)
 491                 goto err_restore_page;
 492
 493         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 494         if (ret)
 495                 goto err_restore_page;
 496
 497         ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
 498                            | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 499                            val);
 500
 501 err_restore_page:
 502         return phy_restore_page(phydev, oldpage, ret);
 503 }
 504
 505 static int rtl8211b_suspend(struct phy_device *phydev)
 506 {
 507         phy_write(phydev, MII_MMD_DATA, BIT(9));
 508
 509         return genphy_suspend(phydev);
 510 }
 511
 512 static int rtl8211b_resume(struct phy_device *phydev)
 513 {
 514         phy_write(phydev, MII_MMD_DATA, 0);
 515
 516         return genphy_resume(phydev);
 517 }
 518
 519 static int rtl8366rb_config_init(struct phy_device *phydev)
 520 {
 521         int ret;
 522
 523         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 524                            RTL8366RB_POWER_SAVE_ON);
 525         if (ret) {
 526                 dev_err(&phydev->mdio.dev,
 527                         "error enabling power management\n");
 528         }
 529
 530         return ret;
 531 }
 532
 533 /* get actual speed to cover the downshift case */
 534 static int rtlgen_get_speed(struct phy_device *phydev)
 535 {
 536         int val;
 537
 538         if (!phydev->link)
 539                 return 0;
 540
 541         val = phy_read_paged(phydev, 0xa43, 0x12);
 542         if (val < 0)
 543                 return val;
 544
 545         switch (val & RTLGEN_SPEED_MASK) {
 546         case 0x0000:
 547                 phydev->speed = SPEED_10;
 548                 break;
 549         case 0x0010:
 550                 phydev->speed = SPEED_100;
 551                 break;
 552         case 0x0020:
 553                 phydev->speed = SPEED_1000;
 554                 break;
 555         case 0x0200:
 556                 phydev->speed = SPEED_10000;
 557                 break;
 558         case 0x0210:
 559                 phydev->speed = SPEED_2500;
 560                 break;
 561         case 0x0220:
 562                 phydev->speed = SPEED_5000;
 563                 break;
 564         default:
 565                 break;
 566         }
 567
 568         return 0;
 569 }
 570
 571 static int rtlgen_read_status(struct phy_device *phydev)
 572 {
 573         int ret;
 574
 575         ret = genphy_read_status(phydev);
 576         if (ret < 0)
 577                 return ret;
 578
 579         return rtlgen_get_speed(phydev);
 580 }
 581
 582 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 583 {
 584         int ret;
 585
 586         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 587                 rtl821x_write_page(phydev, 0xa5c);
 588                 ret = __phy_read(phydev, 0x12);
 589                 rtl821x_write_page(phydev, 0);
 590         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 591                 rtl821x_write_page(phydev, 0xa5d);
 592                 ret = __phy_read(phydev, 0x10);
 593                 rtl821x_write_page(phydev, 0);
 594         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 595                 rtl821x_write_page(phydev, 0xa5d);
 596                 ret = __phy_read(phydev, 0x11);
 597                 rtl821x_write_page(phydev, 0);
 598         } else {
 599                 ret = -EOPNOTSUPP;
 600         }
 601
 602         return ret;
 603 }
 604
 605 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 606                             u16 val)
 607 {
 608         int ret;
 609
 610         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 611                 rtl821x_write_page(phydev, 0xa5d);
 612                 ret = __phy_write(phydev, 0x10, val);
 613                 rtl821x_write_page(phydev, 0);
 614         } else {
 615                 ret = -EOPNOTSUPP;
 616         }
 617
 618         return ret;
 619 }
 620
 621 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 622 {
 623         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 624
 625         if (ret != -EOPNOTSUPP)
 626                 return ret;
 627
 628         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 629                 rtl821x_write_page(phydev, 0xa6e);
 630                 ret = __phy_read(phydev, 0x16);
 631                 rtl821x_write_page(phydev, 0);
 632         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 633                 rtl821x_write_page(phydev, 0xa6d);
 634                 ret = __phy_read(phydev, 0x12);
 635                 rtl821x_write_page(phydev, 0);
 636         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 637                 rtl821x_write_page(phydev, 0xa6d);
 638                 ret = __phy_read(phydev, 0x10);
 639                 rtl821x_write_page(phydev, 0);
 640         }
 641
 642         return ret;
 643 }
 644
 645 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 646                              u16 val)
 647 {
 648         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 649
 650         if (ret != -EOPNOTSUPP)
 651                 return ret;
 652
 653         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 654                 rtl821x_write_page(phydev, 0xa6d);
 655                 ret = __phy_write(phydev, 0x12, val);
 656                 rtl821x_write_page(phydev, 0);
 657         }
 658
 659         return ret;
 660 }
 661
 662 static int rtl822x_get_features(struct phy_device *phydev)
 663 {
 664         int val;
 665
 666         val = phy_read_paged(phydev, 0xa61, 0x13);
 667         if (val < 0)
 668                 return val;
 669
 670         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 671                          phydev->supported, val & MDIO_PMA_SPEED_2_5G);
 672         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 673                          phydev->supported, val & MDIO_PMA_SPEED_5G);
 674         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 675                          phydev->supported, val & MDIO_SPEED_10G);
 676
 677         return genphy_read_abilities(phydev);
 678 }
 679
 680 static int rtl822x_config_aneg(struct phy_device *phydev)
 681 {
 682         int ret = 0;
 683
 684         if (phydev->autoneg == AUTONEG_ENABLE) {
 685                 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 686
 687                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 688                                                MDIO_AN_10GBT_CTRL_ADV2_5G |
 689                                                MDIO_AN_10GBT_CTRL_ADV5G,
 690                                                adv);
 691                 if (ret < 0)
 692                         return ret;
 693         }
 694
 695         return __genphy_config_aneg(phydev, ret);
 696 }
 697
 698 static int rtl822x_read_status(struct phy_device *phydev)
 699 {
 700         int ret;
 701
 702         if (phydev->autoneg == AUTONEG_ENABLE) {
 703                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 704
 705                 if (lpadv < 0)
 706                         return lpadv;
 707
 708                 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising,
 709                                                   lpadv);
 710         }
 711
 712         ret = genphy_read_status(phydev);
 713         if (ret < 0)
 714                 return ret;
 715
 716         return rtlgen_get_speed(phydev);
 717 }
 718
 719 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 720 {
 721         int val;
 722
 723         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
 724         val = phy_read(phydev, 0x13);
 725         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
 726
 727         return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
 728 }
 729
 730 static int rtlgen_match_phy_device(struct phy_device *phydev)
 731 {
 732         return phydev->phy_id == RTL_GENERIC_PHYID &&
 733                !rtlgen_supports_2_5gbps(phydev);
 734 }
 735
 736 static int rtl8226_match_phy_device(struct phy_device *phydev)
 737 {
 738         return phydev->phy_id == RTL_GENERIC_PHYID &&
 739                rtlgen_supports_2_5gbps(phydev);
 740 }
 741
 742 static int rtlgen_resume(struct phy_device *phydev)
 743 {
 744         int ret = genphy_resume(phydev);
 745
 746         /* Internal PHY's from RTL8168h up may not be instantly ready */
 747         msleep(20);
 748
 749         return ret;
 750 }
 751
 752 static int rtl9000a_config_init(struct phy_device *phydev)
 753 {
 754         phydev->autoneg = AUTONEG_DISABLE;
 755         phydev->speed = SPEED_100;
 756         phydev->duplex = DUPLEX_FULL;
 757
 758         return 0;
 759 }
 760
 761 static int rtl9000a_config_aneg(struct phy_device *phydev)
 762 {
 763         int ret;
 764         u16 ctl = 0;
 765
 766         switch (phydev->master_slave_set) {
 767         case MASTER_SLAVE_CFG_MASTER_FORCE:
 768                 ctl |= CTL1000_AS_MASTER;
 769                 break;
 770         case MASTER_SLAVE_CFG_SLAVE_FORCE:
 771                 break;
 772         case MASTER_SLAVE_CFG_UNKNOWN:
 773         case MASTER_SLAVE_CFG_UNSUPPORTED:
 774                 return 0;
 775         default:
 776                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
 777                 return -EOPNOTSUPP;
 778         }
 779
 780         ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
 781         if (ret == 1)
 782                 ret = genphy_soft_reset(phydev);
 783
 784         return ret;
 785 }
 786
 787 static int rtl9000a_read_status(struct phy_device *phydev)
 788 {
 789         int ret;
 790
 791         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
 792         phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
 793
 794         ret = genphy_update_link(phydev);
 795         if (ret)
 796                 return ret;
 797
 798         ret = phy_read(phydev, MII_CTRL1000);
 799         if (ret < 0)
 800                 return ret;
 801         if (ret & CTL1000_AS_MASTER)
 802                 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
 803         else
 804                 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
 805
 806         ret = phy_read(phydev, MII_STAT1000);
 807         if (ret < 0)
 808                 return ret;
 809         if (ret & LPA_1000MSRES)
 810                 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
 811         else
 812                 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
 813
 814         return 0;
 815 }
 816
 817 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
 818 {
 819         int err;
 820
 821         err = phy_read(phydev, RTL8211F_INSR);
 822
 823         return (err < 0) ? err : 0;
 824 }
 825
 826 static int rtl9000a_config_intr(struct phy_device *phydev)
 827 {
 828         u16 val;
 829         int err;
 830
 831         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 832                 err = rtl9000a_ack_interrupt(phydev);
 833                 if (err)
 834                         return err;
 835
 836                 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
 837                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
 838         } else {
 839                 val = ~0;
 840                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
 841                 if (err)
 842                         return err;
 843
 844                 err = rtl9000a_ack_interrupt(phydev);
 845         }
 846
 847         return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
 848 }
 849
 850 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
 851 {
 852         int irq_status;
 853
 854         irq_status = phy_read(phydev, RTL8211F_INSR);
 855         if (irq_status < 0) {
 856                 phy_error(phydev);
 857                 return IRQ_NONE;
 858         }
 859
 860         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
 861                 return IRQ_NONE;
 862
 863         phy_trigger_machine(phydev);
 864
 865         return IRQ_HANDLED;
 866 }
 867
 868 static struct phy_driver realtek_drvs[] = {
 869         {
 870                 PHY_ID_MATCH_EXACT(0x00008201),
 871                 .name           = "RTL8201CP Ethernet",
 872                 .read_page      = rtl821x_read_page,
 873                 .write_page     = rtl821x_write_page,
 874         }, {
 875                 PHY_ID_MATCH_EXACT(0x001cc816),
 876                 .name           = "RTL8201F Fast Ethernet",
 877                 .config_intr    = &rtl8201_config_intr,
 878                 .handle_interrupt = rtl8201_handle_interrupt,
 879                 .suspend        = genphy_suspend,
 880                 .resume         = genphy_resume,
 881                 .read_page      = rtl821x_read_page,
 882                 .write_page     = rtl821x_write_page,
 883         }, {
 884                 PHY_ID_MATCH_MODEL(0x001cc880),
 885                 .name           = "RTL8208 Fast Ethernet",
 886                 .read_mmd       = genphy_read_mmd_unsupported,
 887                 .write_mmd      = genphy_write_mmd_unsupported,
 888                 .suspend        = genphy_suspend,
 889                 .resume         = genphy_resume,
 890                 .read_page      = rtl821x_read_page,
 891                 .write_page     = rtl821x_write_page,
 892         }, {
 893                 PHY_ID_MATCH_EXACT(0x001cc910),
 894                 .name           = "RTL8211 Gigabit Ethernet",
 895                 .config_aneg    = rtl8211_config_aneg,
 896                 .read_mmd       = &genphy_read_mmd_unsupported,
 897                 .write_mmd      = &genphy_write_mmd_unsupported,
 898                 .read_page      = rtl821x_read_page,
 899                 .write_page     = rtl821x_write_page,
 900         }, {
 901                 PHY_ID_MATCH_EXACT(0x001cc912),
 902                 .name           = "RTL8211B Gigabit Ethernet",
 903                 .config_intr    = &rtl8211b_config_intr,
 904                 .handle_interrupt = rtl821x_handle_interrupt,
 905                 .read_mmd       = &genphy_read_mmd_unsupported,
 906                 .write_mmd      = &genphy_write_mmd_unsupported,
 907                 .suspend        = rtl8211b_suspend,
 908                 .resume         = rtl8211b_resume,
 909                 .read_page      = rtl821x_read_page,
 910                 .write_page     = rtl821x_write_page,
 911         }, {
 912                 PHY_ID_MATCH_EXACT(0x001cc913),
 913                 .name           = "RTL8211C Gigabit Ethernet",
 914                 .config_init    = rtl8211c_config_init,
 915                 .read_mmd       = &genphy_read_mmd_unsupported,
 916                 .write_mmd      = &genphy_write_mmd_unsupported,
 917                 .read_page      = rtl821x_read_page,
 918                 .write_page     = rtl821x_write_page,
 919         }, {
 920                 PHY_ID_MATCH_EXACT(0x001cc914),
 921                 .name           = "RTL8211DN Gigabit Ethernet",
 922                 .config_intr    = rtl8211e_config_intr,
 923                 .handle_interrupt = rtl821x_handle_interrupt,
 924                 .suspend        = genphy_suspend,
 925                 .resume         = genphy_resume,
 926                 .read_page      = rtl821x_read_page,
 927                 .write_page     = rtl821x_write_page,
 928         }, {
 929                 PHY_ID_MATCH_EXACT(0x001cc915),
 930                 .name           = "RTL8211E Gigabit Ethernet",
 931                 .config_init    = &rtl8211e_config_init,
 932                 .config_intr    = &rtl8211e_config_intr,
 933                 .handle_interrupt = rtl821x_handle_interrupt,
 934                 .suspend        = genphy_suspend,
 935                 .resume         = genphy_resume,
 936                 .read_page      = rtl821x_read_page,
 937                 .write_page     = rtl821x_write_page,
 938         }, {
 939                 PHY_ID_MATCH_EXACT(0x001cc916),
 940                 .name           = "RTL8211F Gigabit Ethernet",
 941                 .probe          = rtl821x_probe,
 942                 .config_init    = &rtl8211f_config_init,
 943                 .read_status    = rtlgen_read_status,
 944                 .config_intr    = &rtl8211f_config_intr,
 945                 .handle_interrupt = rtl8211f_handle_interrupt,
 946                 .suspend        = rtl821x_suspend,
 947                 .resume         = rtl821x_resume,
 948                 .read_page      = rtl821x_read_page,
 949                 .write_page     = rtl821x_write_page,
 950                 .flags          = PHY_ALWAYS_CALL_SUSPEND,
 951         }, {
 952                 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
 953                 .name           = "RTL8211F-VD Gigabit Ethernet",
 954                 .probe          = rtl821x_probe,
 955                 .config_init    = &rtl8211f_config_init,
 956                 .read_status    = rtlgen_read_status,
 957                 .config_intr    = &rtl8211f_config_intr,
 958                 .handle_interrupt = rtl8211f_handle_interrupt,
 959                 .suspend        = rtl821x_suspend,
 960                 .resume         = rtl821x_resume,
 961                 .read_page      = rtl821x_read_page,
 962                 .write_page     = rtl821x_write_page,
 963                 .flags          = PHY_ALWAYS_CALL_SUSPEND,
 964         }, {
 965                 .name           = "Generic FE-GE Realtek PHY",
 966                 .match_phy_device = rtlgen_match_phy_device,
 967                 .read_status    = rtlgen_read_status,
 968                 .suspend        = genphy_suspend,
 969                 .resume         = rtlgen_resume,
 970                 .read_page      = rtl821x_read_page,
 971                 .write_page     = rtl821x_write_page,
 972                 .read_mmd       = rtlgen_read_mmd,
 973                 .write_mmd      = rtlgen_write_mmd,
 974         }, {
 975                 .name           = "RTL8226 2.5Gbps PHY",
 976                 .match_phy_device = rtl8226_match_phy_device,
 977                 .get_features   = rtl822x_get_features,
 978                 .config_aneg    = rtl822x_config_aneg,
 979                 .read_status    = rtl822x_read_status,
 980                 .suspend        = genphy_suspend,
 981                 .resume         = rtlgen_resume,
 982                 .read_page      = rtl821x_read_page,
 983                 .write_page     = rtl821x_write_page,
 984                 .read_mmd       = rtl822x_read_mmd,
 985                 .write_mmd      = rtl822x_write_mmd,
 986         }, {
 987                 PHY_ID_MATCH_EXACT(0x001cc840),
 988                 .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
 989                 .get_features   = rtl822x_get_features,
 990                 .config_aneg    = rtl822x_config_aneg,
 991                 .read_status    = rtl822x_read_status,
 992                 .suspend        = genphy_suspend,
 993                 .resume         = rtlgen_resume,
 994                 .read_page      = rtl821x_read_page,
 995                 .write_page     = rtl821x_write_page,
 996                 .read_mmd       = rtl822x_read_mmd,
 997                 .write_mmd      = rtl822x_write_mmd,
 998         }, {
 999                 PHY_ID_MATCH_EXACT(0x001cc838),
1000                 .name           = "RTL8226-CG 2.5Gbps PHY",
1001                 .get_features   = rtl822x_get_features,
1002                 .config_aneg    = rtl822x_config_aneg,
1003                 .read_status    = rtl822x_read_status,
1004                 .suspend        = genphy_suspend,
1005                 .resume         = rtlgen_resume,
1006                 .read_page      = rtl821x_read_page,
1007                 .write_page     = rtl821x_write_page,
1008         }, {
1009                 PHY_ID_MATCH_EXACT(0x001cc848),
1010                 .name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1011                 .get_features   = rtl822x_get_features,
1012                 .config_aneg    = rtl822x_config_aneg,
1013                 .read_status    = rtl822x_read_status,
1014                 .suspend        = genphy_suspend,
1015                 .resume         = rtlgen_resume,
1016                 .read_page      = rtl821x_read_page,
1017                 .write_page     = rtl821x_write_page,
1018         }, {
1019                 PHY_ID_MATCH_EXACT(0x001cc849),
1020                 .name           = "RTL8221B-VB-CG 2.5Gbps PHY",
1021                 .get_features   = rtl822x_get_features,
1022                 .config_aneg    = rtl822x_config_aneg,
1023                 .read_status    = rtl822x_read_status,
1024                 .suspend        = genphy_suspend,
1025                 .resume         = rtlgen_resume,
1026                 .read_page      = rtl821x_read_page,
1027                 .write_page     = rtl821x_write_page,
1028         }, {
1029                 PHY_ID_MATCH_EXACT(0x001cc84a),
1030                 .name           = "RTL8221B-VM-CG 2.5Gbps PHY",
1031                 .get_features   = rtl822x_get_features,
1032                 .config_aneg    = rtl822x_config_aneg,
1033                 .read_status    = rtl822x_read_status,
1034                 .suspend        = genphy_suspend,
1035                 .resume         = rtlgen_resume,
1036                 .read_page      = rtl821x_read_page,
1037                 .write_page     = rtl821x_write_page,
1038         }, {
1039                 PHY_ID_MATCH_EXACT(0x001cc862),
1040                 .name           = "RTL8251B 5Gbps PHY",
1041                 .get_features   = rtl822x_get_features,
1042                 .config_aneg    = rtl822x_config_aneg,
1043                 .read_status    = rtl822x_read_status,
1044                 .suspend        = genphy_suspend,
1045                 .resume         = rtlgen_resume,
1046                 .read_page      = rtl821x_read_page,
1047                 .write_page     = rtl821x_write_page,
1048         }, {
1049                 PHY_ID_MATCH_EXACT(0x001cc961),
1050                 .name           = "RTL8366RB Gigabit Ethernet",
1051                 .config_init    = &rtl8366rb_config_init,
1052                 /* These interrupts are handled by the irq controller
1053                  * embedded inside the RTL8366RB, they get unmasked when the
1054                  * irq is requested and ACKed by reading the status register,
1055                  * which is done by the irqchip code.
1056                  */
1057                 .config_intr    = genphy_no_config_intr,
1058                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1059                 .suspend        = genphy_suspend,
1060                 .resume         = genphy_resume,
1061         }, {
1062                 PHY_ID_MATCH_EXACT(0x001ccb00),
1063                 .name           = "RTL9000AA_RTL9000AN Ethernet",
1064                 .features       = PHY_BASIC_T1_FEATURES,
1065                 .config_init    = rtl9000a_config_init,
1066                 .config_aneg    = rtl9000a_config_aneg,
1067                 .read_status    = rtl9000a_read_status,
1068                 .config_intr    = rtl9000a_config_intr,
1069                 .handle_interrupt = rtl9000a_handle_interrupt,
1070                 .suspend        = genphy_suspend,
1071                 .resume         = genphy_resume,
1072                 .read_page      = rtl821x_read_page,
1073                 .write_page     = rtl821x_write_page,
1074         }, {
1075                 PHY_ID_MATCH_EXACT(0x001cc942),
1076                 .name           = "RTL8365MB-VC Gigabit Ethernet",
1077                 /* Interrupt handling analogous to RTL8366RB */
1078                 .config_intr    = genphy_no_config_intr,
1079                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1080                 .suspend        = genphy_suspend,
1081                 .resume         = genphy_resume,
1082         },
1083 };
1084
1085 module_phy_driver(realtek_drvs);
1086
1087 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1088         { PHY_ID_MATCH_VENDOR(0x001cc800) },
1089         { }
1090 };
1091
1092 MODULE_DEVICE_TABLE(mdio, realtek_tbl);