drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <[email protected]>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <[email protected]>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33 #include <net/netdev_queues.h>
  34
  35 #include "r8169.h"
  36 #include "r8169_firmware.h"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  55 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  56 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  57 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  58 #define FIRMWARE_8126A_2        "rtl_nic/rtl8126a-2.fw"
  59
  60 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  61 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  62
  63 #define R8169_REGS_SIZE         256
  64 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  65 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  66 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  67 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  68 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  69 #define R8169_TX_STOP_THRS      (MAX_SKB_FRAGS + 1)
  70 #define R8169_TX_START_THRS     (2 * R8169_TX_STOP_THRS)
  71
  72 #define OCP_STD_PHY_BASE        0xa400
  73
  74 #define RTL_CFG_NO_GBIT 1
  75
  76 /* write/read MMIO register */
  77 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  80 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  81 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  82 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  83
  84 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  85 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  86 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  87 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88
  89 static const struct {
  90         const char *name;
  91         const char *fw_name;
  92 } rtl_chip_infos[] = {
  93         /* PCI devices. */
  94         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  95         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  96         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
  97         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
  98         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
  99         /* PCI-E devices. */
 100         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 101         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 102         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 103         [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"                    },
 104         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 105         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 106         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 107         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 108         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 109         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 110         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 111         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 112         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 113         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 115         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 116         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 117         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 118         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 119         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 120         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 121         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 122         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 123         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 124         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 125         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 126         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 127         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 128         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 129         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 130         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 131         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 132         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 133         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 134         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 135         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 136         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 137         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 138         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 139         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 140         [RTL_GIGA_MAC_VER_65] = {"RTL8126A",            FIRMWARE_8126A_2},
 141 };
 142
 143 static const struct pci_device_id rtl8169_pci_tbl[] = {
 144         { PCI_VDEVICE(REALTEK,  0x2502) },
 145         { PCI_VDEVICE(REALTEK,  0x2600) },
 146         { PCI_VDEVICE(REALTEK,  0x8129) },
 147         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 148         { PCI_VDEVICE(REALTEK,  0x8161) },
 149         { PCI_VDEVICE(REALTEK,  0x8162) },
 150         { PCI_VDEVICE(REALTEK,  0x8167) },
 151         { PCI_VDEVICE(REALTEK,  0x8168) },
 152         { PCI_VDEVICE(NCUBE,    0x8168) },
 153         { PCI_VDEVICE(REALTEK,  0x8169) },
 154         { PCI_VENDOR_ID_DLINK,  0x4300,
 155                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 156         { PCI_VDEVICE(DLINK,    0x4300) },
 157         { PCI_VDEVICE(DLINK,    0x4302) },
 158         { PCI_VDEVICE(AT,       0xc107) },
 159         { PCI_VDEVICE(USR,      0x0116) },
 160         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 161         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 162         { PCI_VDEVICE(REALTEK,  0x8125) },
 163         { PCI_VDEVICE(REALTEK,  0x8126) },
 164         { PCI_VDEVICE(REALTEK,  0x3000) },
 165         {}
 166 };
 167
 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 169
 170 enum rtl_registers {
 171         MAC0            = 0,    /* Ethernet hardware address. */
 172         MAC4            = 4,
 173         MAR0            = 8,    /* Multicast filter. */
 174         CounterAddrLow          = 0x10,
 175         CounterAddrHigh         = 0x14,
 176         TxDescStartAddrLow      = 0x20,
 177         TxDescStartAddrHigh     = 0x24,
 178         TxHDescStartAddrLow     = 0x28,
 179         TxHDescStartAddrHigh    = 0x2c,
 180         FLASH           = 0x30,
 181         ERSR            = 0x36,
 182         ChipCmd         = 0x37,
 183         TxPoll          = 0x38,
 184         IntrMask        = 0x3c,
 185         IntrStatus      = 0x3e,
 186
 187         TxConfig        = 0x40,
 188 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 189 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 190
 191         RxConfig        = 0x44,
 192 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 193 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 194 #define RXCFG_FIFO_SHIFT                13
 195                                         /* No threshold before first PCI xfer */
 196 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 197 #define RX_EARLY_OFF                    (1 << 11)
 198 #define RX_PAUSE_SLOT_ON                (1 << 11)       /* 8125b and later */
 199 #define RXCFG_DMA_SHIFT                 8
 200                                         /* Unlimited maximum PCI burst. */
 201 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 202
 203         Cfg9346         = 0x50,
 204         Config0         = 0x51,
 205         Config1         = 0x52,
 206         Config2         = 0x53,
 207 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 208
 209         Config3         = 0x54,
 210         Config4         = 0x55,
 211         Config5         = 0x56,
 212         PHYAR           = 0x60,
 213         PHYstatus       = 0x6c,
 214         RxMaxSize       = 0xda,
 215         CPlusCmd        = 0xe0,
 216         IntrMitigate    = 0xe2,
 217
 218 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 219 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 220 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 221 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 222
 223 #define RTL_COALESCE_T_MAX      0x0fU
 224 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 225
 226         RxDescAddrLow   = 0xe4,
 227         RxDescAddrHigh  = 0xe8,
 228         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 229
 230 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 231
 232         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 233
 234 #define TxPacketMax     (8064 >> 7)
 235 #define EarlySize       0x27
 236
 237         FuncEvent       = 0xf0,
 238         FuncEventMask   = 0xf4,
 239         FuncPresetState = 0xf8,
 240         IBCR0           = 0xf8,
 241         IBCR2           = 0xf9,
 242         IBIMR0          = 0xfa,
 243         IBISR0          = 0xfb,
 244         FuncForceEvent  = 0xfc,
 245 };
 246
 247 enum rtl8168_8101_registers {
 248         CSIDR                   = 0x64,
 249         CSIAR                   = 0x68,
 250 #define CSIAR_FLAG                      0x80000000
 251 #define CSIAR_WRITE_CMD                 0x80000000
 252 #define CSIAR_BYTE_ENABLE               0x0000f000
 253 #define CSIAR_ADDR_MASK                 0x00000fff
 254         PMCH                    = 0x6f,
 255 #define D3COLD_NO_PLL_DOWN              BIT(7)
 256 #define D3HOT_NO_PLL_DOWN               BIT(6)
 257 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 258         EPHYAR                  = 0x80,
 259 #define EPHYAR_FLAG                     0x80000000
 260 #define EPHYAR_WRITE_CMD                0x80000000
 261 #define EPHYAR_REG_MASK                 0x1f
 262 #define EPHYAR_REG_SHIFT                16
 263 #define EPHYAR_DATA_MASK                0xffff
 264         DLLPR                   = 0xd0,
 265 #define PFM_EN                          (1 << 6)
 266 #define TX_10M_PS_EN                    (1 << 7)
 267         DBG_REG                 = 0xd1,
 268 #define FIX_NAK_1                       (1 << 4)
 269 #define FIX_NAK_2                       (1 << 3)
 270         TWSI                    = 0xd2,
 271         MCU                     = 0xd3,
 272 #define NOW_IS_OOB                      (1 << 7)
 273 #define TX_EMPTY                        (1 << 5)
 274 #define RX_EMPTY                        (1 << 4)
 275 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 276 #define EN_NDP                          (1 << 3)
 277 #define EN_OOB_RESET                    (1 << 2)
 278 #define LINK_LIST_RDY                   (1 << 1)
 279         EFUSEAR                 = 0xdc,
 280 #define EFUSEAR_FLAG                    0x80000000
 281 #define EFUSEAR_WRITE_CMD               0x80000000
 282 #define EFUSEAR_READ_CMD                0x00000000
 283 #define EFUSEAR_REG_MASK                0x03ff
 284 #define EFUSEAR_REG_SHIFT               8
 285 #define EFUSEAR_DATA_MASK               0xff
 286         MISC_1                  = 0xf2,
 287 #define PFM_D3COLD_EN                   (1 << 6)
 288 };
 289
 290 enum rtl8168_registers {
 291         LED_CTRL                = 0x18,
 292         LED_FREQ                = 0x1a,
 293         EEE_LED                 = 0x1b,
 294         ERIDR                   = 0x70,
 295         ERIAR                   = 0x74,
 296 #define ERIAR_FLAG                      0x80000000
 297 #define ERIAR_WRITE_CMD                 0x80000000
 298 #define ERIAR_READ_CMD                  0x00000000
 299 #define ERIAR_ADDR_BYTE_ALIGN           4
 300 #define ERIAR_TYPE_SHIFT                16
 301 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 302 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 303 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 304 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 305 #define ERIAR_MASK_SHIFT                12
 306 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 307 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 308 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 309 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 310 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 311         EPHY_RXER_NUM           = 0x7c,
 312         OCPDR                   = 0xb0, /* OCP GPHY access */
 313 #define OCPDR_WRITE_CMD                 0x80000000
 314 #define OCPDR_READ_CMD                  0x00000000
 315 #define OCPDR_REG_MASK                  0x7f
 316 #define OCPDR_GPHY_REG_SHIFT            16
 317 #define OCPDR_DATA_MASK                 0xffff
 318         OCPAR                   = 0xb4,
 319 #define OCPAR_FLAG                      0x80000000
 320 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 321 #define OCPAR_GPHY_READ_CMD             0x0000f060
 322         GPHY_OCP                = 0xb8,
 323         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 324         MISC                    = 0xf0, /* 8168e only. */
 325 #define TXPLA_RST                       (1 << 29)
 326 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 327 #define PWM_EN                          (1 << 22)
 328 #define RXDV_GATED_EN                   (1 << 19)
 329 #define EARLY_TALLY_EN                  (1 << 16)
 330 };
 331
 332 enum rtl8125_registers {
 333         LEDSEL0                 = 0x18,
 334         INT_CFG0_8125           = 0x34,
 335 #define INT_CFG0_ENABLE_8125            BIT(0)
 336 #define INT_CFG0_CLKREQEN               BIT(3)
 337         IntrMask_8125           = 0x38,
 338         IntrStatus_8125         = 0x3c,
 339         INT_CFG1_8125           = 0x7a,
 340         LEDSEL2                 = 0x84,
 341         LEDSEL1                 = 0x86,
 342         TxPoll_8125             = 0x90,
 343         LEDSEL3                 = 0x96,
 344         MAC0_BKP                = 0x19e0,
 345         EEE_TXIDLE_TIMER_8125   = 0x6048,
 346 };
 347
 348 #define LEDSEL_MASK_8125        0x23f
 349
 350 #define RX_VLAN_INNER_8125      BIT(22)
 351 #define RX_VLAN_OUTER_8125      BIT(23)
 352 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 353
 354 #define RX_FETCH_DFLT_8125      (8 << 27)
 355
 356 enum rtl_register_content {
 357         /* InterruptStatusBits */
 358         SYSErr          = 0x8000,
 359         PCSTimeout      = 0x4000,
 360         SWInt           = 0x0100,
 361         TxDescUnavail   = 0x0080,
 362         RxFIFOOver      = 0x0040,
 363         LinkChg         = 0x0020,
 364         RxOverflow      = 0x0010,
 365         TxErr           = 0x0008,
 366         TxOK            = 0x0004,
 367         RxErr           = 0x0002,
 368         RxOK            = 0x0001,
 369
 370         /* RxStatusDesc */
 371         RxRWT   = (1 << 22),
 372         RxRES   = (1 << 21),
 373         RxRUNT  = (1 << 20),
 374         RxCRC   = (1 << 19),
 375
 376         /* ChipCmdBits */
 377         StopReq         = 0x80,
 378         CmdReset        = 0x10,
 379         CmdRxEnb        = 0x08,
 380         CmdTxEnb        = 0x04,
 381         RxBufEmpty      = 0x01,
 382
 383         /* TXPoll register p.5 */
 384         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 385         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 386         FSWInt          = 0x01,         /* Forced software interrupt */
 387
 388         /* Cfg9346Bits */
 389         Cfg9346_Lock    = 0x00,
 390         Cfg9346_Unlock  = 0xc0,
 391
 392         /* rx_mode_bits */
 393         AcceptErr       = 0x20,
 394         AcceptRunt      = 0x10,
 395 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 396         AcceptBroadcast = 0x08,
 397         AcceptMulticast = 0x04,
 398         AcceptMyPhys    = 0x02,
 399         AcceptAllPhys   = 0x01,
 400 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 401 #define RX_CONFIG_ACCEPT_MASK           0x3f
 402
 403         /* TxConfigBits */
 404         TxInterFrameGapShift = 24,
 405         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 406
 407         /* Config1 register p.24 */
 408         LEDS1           = (1 << 7),
 409         LEDS0           = (1 << 6),
 410         Speed_down      = (1 << 4),
 411         MEMMAP          = (1 << 3),
 412         IOMAP           = (1 << 2),
 413         VPD             = (1 << 1),
 414         PMEnable        = (1 << 0),     /* Power Management Enable */
 415
 416         /* Config2 register p. 25 */
 417         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 418         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 419         PCI_Clock_66MHz = 0x01,
 420         PCI_Clock_33MHz = 0x00,
 421
 422         /* Config3 register p.25 */
 423         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 424         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 425         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 426         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 427         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 428
 429         /* Config4 register */
 430         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 431
 432         /* Config5 register p.27 */
 433         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 434         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 435         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 436         Spi_en          = (1 << 3),
 437         LanWake         = (1 << 1),     /* LanWake enable/disable */
 438         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 439         ASPM_en         = (1 << 0),     /* ASPM enable */
 440
 441         /* CPlusCmd p.31 */
 442         EnableBist      = (1 << 15),    // 8168 8101
 443         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 444         EnAnaPLL        = (1 << 14),    // 8169
 445         Normal_mode     = (1 << 13),    // unused
 446         Force_half_dup  = (1 << 12),    // 8168 8101
 447         Force_rxflow_en = (1 << 11),    // 8168 8101
 448         Force_txflow_en = (1 << 10),    // 8168 8101
 449         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 450         ASF             = (1 << 8),     // 8168 8101
 451         PktCntrDisable  = (1 << 7),     // 8168 8101
 452         Mac_dbgo_sel    = 0x001c,       // 8168
 453         RxVlan          = (1 << 6),
 454         RxChkSum        = (1 << 5),
 455         PCIDAC          = (1 << 4),
 456         PCIMulRW        = (1 << 3),
 457 #define INTT_MASK       GENMASK(1, 0)
 458 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 459
 460         /* rtl8169_PHYstatus */
 461         TBI_Enable      = 0x80,
 462         TxFlowCtrl      = 0x40,
 463         RxFlowCtrl      = 0x20,
 464         _1000bpsF       = 0x10,
 465         _100bps         = 0x08,
 466         _10bps          = 0x04,
 467         LinkStatus      = 0x02,
 468         FullDup         = 0x01,
 469
 470         /* ResetCounterCommand */
 471         CounterReset    = 0x1,
 472
 473         /* DumpCounterCommand */
 474         CounterDump     = 0x8,
 475
 476         /* magic enable v2 */
 477         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 478 };
 479
 480 enum rtl_desc_bit {
 481         /* First doubleword. */
 482         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 483         RingEnd         = (1 << 30), /* End of descriptor ring */
 484         FirstFrag       = (1 << 29), /* First segment of a packet */
 485         LastFrag        = (1 << 28), /* Final segment of a packet */
 486 };
 487
 488 /* Generic case. */
 489 enum rtl_tx_desc_bit {
 490         /* First doubleword. */
 491         TD_LSO          = (1 << 27),            /* Large Send Offload */
 492 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 493
 494         /* Second doubleword. */
 495         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 496 };
 497
 498 /* 8169, 8168b and 810x except 8102e. */
 499 enum rtl_tx_desc_bit_0 {
 500         /* First doubleword. */
 501 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 502         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 503         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 504         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 505 };
 506
 507 /* 8102e, 8168c and beyond. */
 508 enum rtl_tx_desc_bit_1 {
 509         /* First doubleword. */
 510         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 511         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 512 #define GTTCPHO_SHIFT                   18
 513 #define GTTCPHO_MAX                     0x7f
 514
 515         /* Second doubleword. */
 516 #define TCPHO_SHIFT                     18
 517 #define TCPHO_MAX                       0x3ff
 518 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 519         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 520         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 521         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 522         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 523 };
 524
 525 enum rtl_rx_desc_bit {
 526         /* Rx private */
 527         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 528         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 529
 530 #define RxProtoUDP      (PID1)
 531 #define RxProtoTCP      (PID0)
 532 #define RxProtoIP       (PID1 | PID0)
 533 #define RxProtoMask     RxProtoIP
 534
 535         IPFail          = (1 << 16), /* IP checksum failed */
 536         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 537         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 538
 539 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 540
 541         RxVlanTag       = (1 << 16), /* VLAN tag available */
 542 };
 543
 544 #define RTL_GSO_MAX_SIZE_V1     32000
 545 #define RTL_GSO_MAX_SEGS_V1     24
 546 #define RTL_GSO_MAX_SIZE_V2     64000
 547 #define RTL_GSO_MAX_SEGS_V2     64
 548
 549 struct TxDesc {
 550         __le32 opts1;
 551         __le32 opts2;
 552         __le64 addr;
 553 };
 554
 555 struct RxDesc {
 556         __le32 opts1;
 557         __le32 opts2;
 558         __le64 addr;
 559 };
 560
 561 struct ring_info {
 562         struct sk_buff  *skb;
 563         u32             len;
 564 };
 565
 566 struct rtl8169_counters {
 567         __le64  tx_packets;
 568         __le64  rx_packets;
 569         __le64  tx_errors;
 570         __le32  rx_errors;
 571         __le16  rx_missed;
 572         __le16  align_errors;
 573         __le32  tx_one_collision;
 574         __le32  tx_multi_collision;
 575         __le64  rx_unicast;
 576         __le64  rx_broadcast;
 577         __le32  rx_multicast;
 578         __le16  tx_aborted;
 579         __le16  tx_underun;
 580 };
 581
 582 struct rtl8169_tc_offsets {
 583         bool    inited;
 584         __le64  tx_errors;
 585         __le32  tx_multi_collision;
 586         __le16  tx_aborted;
 587         __le16  rx_missed;
 588 };
 589
 590 enum rtl_flag {
 591         RTL_FLAG_TASK_ENABLED = 0,
 592         RTL_FLAG_TASK_RESET_PENDING,
 593         RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
 594         RTL_FLAG_TASK_TX_TIMEOUT,
 595         RTL_FLAG_MAX
 596 };
 597
 598 enum rtl_dash_type {
 599         RTL_DASH_NONE,
 600         RTL_DASH_DP,
 601         RTL_DASH_EP,
 602 };
 603
 604 struct rtl8169_private {
 605         void __iomem *mmio_addr;        /* memory map physical address */
 606         struct pci_dev *pci_dev;
 607         struct net_device *dev;
 608         struct phy_device *phydev;
 609         struct napi_struct napi;
 610         enum mac_version mac_version;
 611         enum rtl_dash_type dash_type;
 612         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 613         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 614         u32 dirty_tx;
 615         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 616         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 617         dma_addr_t TxPhyAddr;
 618         dma_addr_t RxPhyAddr;
 619         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 620         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 621         u16 cp_cmd;
 622         u16 tx_lpi_timer;
 623         u32 irq_mask;
 624         int irq;
 625         struct clk *clk;
 626
 627         struct {
 628                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 629                 struct work_struct work;
 630         } wk;
 631
 632         raw_spinlock_t config25_lock;
 633         raw_spinlock_t mac_ocp_lock;
 634         struct mutex led_lock;  /* serialize LED ctrl RMW access */
 635
 636         raw_spinlock_t cfg9346_usage_lock;
 637         int cfg9346_usage_count;
 638
 639         unsigned supports_gmii:1;
 640         unsigned aspm_manageable:1;
 641         unsigned dash_enabled:1;
 642         dma_addr_t counters_phys_addr;
 643         struct rtl8169_counters *counters;
 644         struct rtl8169_tc_offsets tc_offset;
 645         u32 saved_wolopts;
 646
 647         const char *fw_name;
 648         struct rtl_fw *rtl_fw;
 649
 650         u32 ocp_base;
 651 };
 652
 653 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 654
 655 MODULE_AUTHOR("Realtek and the Linux r8169 crew <[email protected]>");
 656 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 657 MODULE_SOFTDEP("pre: realtek");
 658 MODULE_LICENSE("GPL");
 659 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 660 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 661 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 662 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 663 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 664 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 665 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 666 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 667 MODULE_FIRMWARE(FIRMWARE_8402_1);
 668 MODULE_FIRMWARE(FIRMWARE_8411_1);
 669 MODULE_FIRMWARE(FIRMWARE_8411_2);
 670 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 671 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 672 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 673 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 674 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 675 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 676 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 677 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 678 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 679 MODULE_FIRMWARE(FIRMWARE_8126A_2);
 680
 681 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 682 {
 683         return &tp->pci_dev->dev;
 684 }
 685
 686 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 687 {
 688         unsigned long flags;
 689
 690         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 691         if (!--tp->cfg9346_usage_count)
 692                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 693         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 694 }
 695
 696 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 697 {
 698         unsigned long flags;
 699
 700         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 701         if (!tp->cfg9346_usage_count++)
 702                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 703         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 704 }
 705
 706 static void rtl_pci_commit(struct rtl8169_private *tp)
 707 {
 708         /* Read an arbitrary register to commit a preceding PCI write */
 709         RTL_R8(tp, ChipCmd);
 710 }
 711
 712 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
 713 {
 714         unsigned long flags;
 715         u8 val;
 716
 717         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 718         val = RTL_R8(tp, Config2);
 719         RTL_W8(tp, Config2, (val & ~clear) | set);
 720         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 721 }
 722
 723 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
 724 {
 725         unsigned long flags;
 726         u8 val;
 727
 728         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 729         val = RTL_R8(tp, Config5);
 730         RTL_W8(tp, Config5, (val & ~clear) | set);
 731         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 732 }
 733
 734 static bool rtl_is_8125(struct rtl8169_private *tp)
 735 {
 736         return tp->mac_version >= RTL_GIGA_MAC_VER_61;
 737 }
 738
 739 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 740 {
 741         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 742                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 743                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 744 }
 745
 746 static bool rtl_supports_eee(struct rtl8169_private *tp)
 747 {
 748         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 749                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 750                tp->mac_version != RTL_GIGA_MAC_VER_39;
 751 }
 752
 753 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 754 {
 755         int i;
 756
 757         for (i = 0; i < ETH_ALEN; i++)
 758                 mac[i] = RTL_R8(tp, reg + i);
 759 }
 760
 761 struct rtl_cond {
 762         bool (*check)(struct rtl8169_private *);
 763         const char *msg;
 764 };
 765
 766 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 767                           unsigned long usecs, int n, bool high)
 768 {
 769         int i;
 770
 771         for (i = 0; i < n; i++) {
 772                 if (c->check(tp) == high)
 773                         return true;
 774                 fsleep(usecs);
 775         }
 776
 777         if (net_ratelimit())
 778                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 779                            c->msg, !high, n, usecs);
 780         return false;
 781 }
 782
 783 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 784                                const struct rtl_cond *c,
 785                                unsigned long d, int n)
 786 {
 787         return rtl_loop_wait(tp, c, d, n, true);
 788 }
 789
 790 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 791                               const struct rtl_cond *c,
 792                               unsigned long d, int n)
 793 {
 794         return rtl_loop_wait(tp, c, d, n, false);
 795 }
 796
 797 #define DECLARE_RTL_COND(name)                          \
 798 static bool name ## _check(struct rtl8169_private *);   \
 799                                                         \
 800 static const struct rtl_cond name = {                   \
 801         .check  = name ## _check,                       \
 802         .msg    = #name                                 \
 803 };                                                      \
 804                                                         \
 805 static bool name ## _check(struct rtl8169_private *tp)
 806
 807 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
 808 {
 809         struct device *dev = tp_to_dev(tp);
 810         int ret;
 811
 812         ret = pm_runtime_resume_and_get(dev);
 813         if (ret < 0)
 814                 return ret;
 815
 816         mutex_lock(&tp->led_lock);
 817         RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
 818         mutex_unlock(&tp->led_lock);
 819
 820         pm_runtime_put_sync(dev);
 821
 822         return 0;
 823 }
 824
 825 int rtl8168_get_led_mode(struct rtl8169_private *tp)
 826 {
 827         struct device *dev = tp_to_dev(tp);
 828         int ret;
 829
 830         ret = pm_runtime_resume_and_get(dev);
 831         if (ret < 0)
 832                 return ret;
 833
 834         ret = RTL_R16(tp, LED_CTRL);
 835
 836         pm_runtime_put_sync(dev);
 837
 838         return ret;
 839 }
 840
 841 static int rtl8125_get_led_reg(int index)
 842 {
 843         static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
 844
 845         return led_regs[index];
 846 }
 847
 848 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
 849 {
 850         int reg = rtl8125_get_led_reg(index);
 851         struct device *dev = tp_to_dev(tp);
 852         int ret;
 853         u16 val;
 854
 855         ret = pm_runtime_resume_and_get(dev);
 856         if (ret < 0)
 857                 return ret;
 858
 859         mutex_lock(&tp->led_lock);
 860         val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
 861         RTL_W16(tp, reg, val | mode);
 862         mutex_unlock(&tp->led_lock);
 863
 864         pm_runtime_put_sync(dev);
 865
 866         return 0;
 867 }
 868
 869 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
 870 {
 871         int reg = rtl8125_get_led_reg(index);
 872         struct device *dev = tp_to_dev(tp);
 873         int ret;
 874
 875         ret = pm_runtime_resume_and_get(dev);
 876         if (ret < 0)
 877                 return ret;
 878
 879         ret = RTL_R16(tp, reg);
 880
 881         pm_runtime_put_sync(dev);
 882
 883         return ret;
 884 }
 885
 886 void r8169_get_led_name(struct rtl8169_private *tp, int idx,
 887                         char *buf, int buf_len)
 888 {
 889         struct pci_dev *pdev = tp->pci_dev;
 890         char pdom[8], pfun[8];
 891         int domain;
 892
 893         domain = pci_domain_nr(pdev->bus);
 894         if (domain)
 895                 snprintf(pdom, sizeof(pdom), "P%d", domain);
 896         else
 897                 pdom[0] = '\0';
 898
 899         if (pdev->multifunction)
 900                 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn));
 901         else
 902                 pfun[0] = '\0';
 903
 904         snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
 905                  PCI_SLOT(pdev->devfn), pfun, idx);
 906 }
 907
 908 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 909 {
 910         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 911         if (type == ERIAR_OOB &&
 912             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 913              tp->mac_version == RTL_GIGA_MAC_VER_53))
 914                 *cmd |= 0xf70 << 18;
 915 }
 916
 917 DECLARE_RTL_COND(rtl_eriar_cond)
 918 {
 919         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 920 }
 921
 922 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 923                            u32 val, int type)
 924 {
 925         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 926
 927         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 928                 return;
 929
 930         RTL_W32(tp, ERIDR, val);
 931         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 932         RTL_W32(tp, ERIAR, cmd);
 933
 934         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 935 }
 936
 937 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 938                           u32 val)
 939 {
 940         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 941 }
 942
 943 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 944 {
 945         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 946
 947         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 948         RTL_W32(tp, ERIAR, cmd);
 949
 950         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 951                 RTL_R32(tp, ERIDR) : ~0;
 952 }
 953
 954 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 955 {
 956         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 957 }
 958
 959 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 960 {
 961         u32 val = rtl_eri_read(tp, addr);
 962
 963         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 964 }
 965
 966 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 967 {
 968         rtl_w0w1_eri(tp, addr, p, 0);
 969 }
 970
 971 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 972 {
 973         rtl_w0w1_eri(tp, addr, 0, m);
 974 }
 975
 976 static bool rtl_ocp_reg_failure(u32 reg)
 977 {
 978         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 979 }
 980
 981 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 982 {
 983         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 984 }
 985
 986 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 987 {
 988         if (rtl_ocp_reg_failure(reg))
 989                 return;
 990
 991         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 992
 993         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 994 }
 995
 996 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 997 {
 998         if (rtl_ocp_reg_failure(reg))
 999                 return 0;
1000
1001         RTL_W32(tp, GPHY_OCP, reg << 15);
1002
1003         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1004                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
1005 }
1006
1007 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008 {
1009         if (rtl_ocp_reg_failure(reg))
1010                 return;
1011
1012         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1013 }
1014
1015 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1016 {
1017         unsigned long flags;
1018
1019         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1020         __r8168_mac_ocp_write(tp, reg, data);
1021         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1022 }
1023
1024 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1025 {
1026         if (rtl_ocp_reg_failure(reg))
1027                 return 0;
1028
1029         RTL_W32(tp, OCPDR, reg << 15);
1030
1031         return RTL_R32(tp, OCPDR);
1032 }
1033
1034 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1035 {
1036         unsigned long flags;
1037         u16 val;
1038
1039         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1040         val = __r8168_mac_ocp_read(tp, reg);
1041         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1042
1043         return val;
1044 }
1045
1046 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1047                                  u16 set)
1048 {
1049         unsigned long flags;
1050         u16 data;
1051
1052         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1053         data = __r8168_mac_ocp_read(tp, reg);
1054         __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
1055         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1056 }
1057
1058 /* Work around a hw issue with RTL8168g PHY, the quirk disables
1059  * PHY MCU interrupts before PHY power-down.
1060  */
1061 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1062 {
1063         switch (tp->mac_version) {
1064         case RTL_GIGA_MAC_VER_40:
1065                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1066                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
1067                 else
1068                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
1069                 break;
1070         default:
1071                 break;
1072         }
1073 };
1074
1075 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1076 {
1077         if (reg == 0x1f) {
1078                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1079                 return;
1080         }
1081
1082         if (tp->ocp_base != OCP_STD_PHY_BASE)
1083                 reg -= 0x10;
1084
1085         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1086                 rtl8168g_phy_suspend_quirk(tp, value);
1087
1088         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1089 }
1090
1091 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1092 {
1093         if (reg == 0x1f)
1094                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1095
1096         if (tp->ocp_base != OCP_STD_PHY_BASE)
1097                 reg -= 0x10;
1098
1099         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1100 }
1101
1102 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1103 {
1104         if (reg == 0x1f) {
1105                 tp->ocp_base = value << 4;
1106                 return;
1107         }
1108
1109         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1110 }
1111
1112 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1113 {
1114         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1115 }
1116
1117 DECLARE_RTL_COND(rtl_phyar_cond)
1118 {
1119         return RTL_R32(tp, PHYAR) & 0x80000000;
1120 }
1121
1122 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1123 {
1124         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1125
1126         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1127         /*
1128          * According to hardware specs a 20us delay is required after write
1129          * complete indication, but before sending next command.
1130          */
1131         udelay(20);
1132 }
1133
1134 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1135 {
1136         int value;
1137
1138         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1139
1140         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1141                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1142
1143         /*
1144          * According to hardware specs a 20us delay is required after read
1145          * complete indication, but before sending next command.
1146          */
1147         udelay(20);
1148
1149         return value;
1150 }
1151
1152 DECLARE_RTL_COND(rtl_ocpar_cond)
1153 {
1154         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1155 }
1156
1157 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1158
1159 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1160 {
1161         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1162 }
1163
1164 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1165 {
1166         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1167 }
1168
1169 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1170 {
1171         r8168dp_2_mdio_start(tp);
1172
1173         r8169_mdio_write(tp, reg, value);
1174
1175         r8168dp_2_mdio_stop(tp);
1176 }
1177
1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1179 {
1180         int value;
1181
1182         /* Work around issue with chip reporting wrong PHY ID */
1183         if (reg == MII_PHYSID2)
1184                 return 0xc912;
1185
1186         r8168dp_2_mdio_start(tp);
1187
1188         value = r8169_mdio_read(tp, reg);
1189
1190         r8168dp_2_mdio_stop(tp);
1191
1192         return value;
1193 }
1194
1195 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1196 {
1197         switch (tp->mac_version) {
1198         case RTL_GIGA_MAC_VER_28:
1199         case RTL_GIGA_MAC_VER_31:
1200                 r8168dp_2_mdio_write(tp, location, val);
1201                 break;
1202         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
1203                 r8168g_mdio_write(tp, location, val);
1204                 break;
1205         default:
1206                 r8169_mdio_write(tp, location, val);
1207                 break;
1208         }
1209 }
1210
1211 static int rtl_readphy(struct rtl8169_private *tp, int location)
1212 {
1213         switch (tp->mac_version) {
1214         case RTL_GIGA_MAC_VER_28:
1215         case RTL_GIGA_MAC_VER_31:
1216                 return r8168dp_2_mdio_read(tp, location);
1217         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
1218                 return r8168g_mdio_read(tp, location);
1219         default:
1220                 return r8169_mdio_read(tp, location);
1221         }
1222 }
1223
1224 DECLARE_RTL_COND(rtl_ephyar_cond)
1225 {
1226         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1227 }
1228
1229 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1230 {
1231         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1232                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1233
1234         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1235
1236         udelay(10);
1237 }
1238
1239 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1240 {
1241         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1242
1243         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1244                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1245 }
1246
1247 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1248 {
1249         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1250         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1251                 RTL_R32(tp, OCPDR) : ~0;
1252 }
1253
1254 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1255 {
1256         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1257 }
1258
1259 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1260                               u32 data)
1261 {
1262         RTL_W32(tp, OCPDR, data);
1263         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1264         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1265 }
1266
1267 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1268                               u32 data)
1269 {
1270         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1271                        data, ERIAR_OOB);
1272 }
1273
1274 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1275 {
1276         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1277
1278         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1279 }
1280
1281 #define OOB_CMD_RESET           0x00
1282 #define OOB_CMD_DRIVER_START    0x05
1283 #define OOB_CMD_DRIVER_STOP     0x06
1284
1285 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1286 {
1287         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1288 }
1289
1290 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1291 {
1292         u16 reg;
1293
1294         reg = rtl8168_get_ocp_reg(tp);
1295
1296         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1297 }
1298
1299 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1300 {
1301         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1302 }
1303
1304 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1305 {
1306         return RTL_R8(tp, IBISR0) & 0x20;
1307 }
1308
1309 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1310 {
1311         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1312         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1313         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1314         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1315 }
1316
1317 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1318 {
1319         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1320         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1321 }
1322
1323 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1324 {
1325         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1326         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1327         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1328 }
1329
1330 static void rtl8168_driver_start(struct rtl8169_private *tp)
1331 {
1332         if (tp->dash_type == RTL_DASH_DP)
1333                 rtl8168dp_driver_start(tp);
1334         else
1335                 rtl8168ep_driver_start(tp);
1336 }
1337
1338 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1339 {
1340         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1341         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1342 }
1343
1344 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1345 {
1346         rtl8168ep_stop_cmac(tp);
1347         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1348         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1349         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1350 }
1351
1352 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1353 {
1354         if (tp->dash_type == RTL_DASH_DP)
1355                 rtl8168dp_driver_stop(tp);
1356         else
1357                 rtl8168ep_driver_stop(tp);
1358 }
1359
1360 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1361 {
1362         u16 reg = rtl8168_get_ocp_reg(tp);
1363
1364         return r8168dp_ocp_read(tp, reg) & BIT(15);
1365 }
1366
1367 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1368 {
1369         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1370 }
1371
1372 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1373 {
1374         switch (tp->dash_type) {
1375         case RTL_DASH_DP:
1376                 return r8168dp_check_dash(tp);
1377         case RTL_DASH_EP:
1378                 return r8168ep_check_dash(tp);
1379         default:
1380                 return false;
1381         }
1382 }
1383
1384 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1385 {
1386         switch (tp->mac_version) {
1387         case RTL_GIGA_MAC_VER_28:
1388         case RTL_GIGA_MAC_VER_31:
1389                 return RTL_DASH_DP;
1390         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1391                 return RTL_DASH_EP;
1392         default:
1393                 return RTL_DASH_NONE;
1394         }
1395 }
1396
1397 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1398 {
1399         switch (tp->mac_version) {
1400         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1401         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1402         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1403         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
1404                 if (enable)
1405                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1406                 else
1407                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1408                 break;
1409         default:
1410                 break;
1411         }
1412 }
1413
1414 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1415 {
1416         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1417         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1418 }
1419
1420 DECLARE_RTL_COND(rtl_efusear_cond)
1421 {
1422         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1423 }
1424
1425 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1426 {
1427         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1428
1429         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1430                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1431 }
1432
1433 static u32 rtl_get_events(struct rtl8169_private *tp)
1434 {
1435         if (rtl_is_8125(tp))
1436                 return RTL_R32(tp, IntrStatus_8125);
1437         else
1438                 return RTL_R16(tp, IntrStatus);
1439 }
1440
1441 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1442 {
1443         if (rtl_is_8125(tp))
1444                 RTL_W32(tp, IntrStatus_8125, bits);
1445         else
1446                 RTL_W16(tp, IntrStatus, bits);
1447 }
1448
1449 static void rtl_irq_disable(struct rtl8169_private *tp)
1450 {
1451         if (rtl_is_8125(tp))
1452                 RTL_W32(tp, IntrMask_8125, 0);
1453         else
1454                 RTL_W16(tp, IntrMask, 0);
1455 }
1456
1457 static void rtl_irq_enable(struct rtl8169_private *tp)
1458 {
1459         if (rtl_is_8125(tp))
1460                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1461         else
1462                 RTL_W16(tp, IntrMask, tp->irq_mask);
1463 }
1464
1465 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1466 {
1467         rtl_irq_disable(tp);
1468         rtl_ack_events(tp, 0xffffffff);
1469         rtl_pci_commit(tp);
1470 }
1471
1472 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1473 {
1474         struct phy_device *phydev = tp->phydev;
1475
1476         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1477             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1478                 if (phydev->speed == SPEED_1000) {
1479                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1480                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1481                 } else if (phydev->speed == SPEED_100) {
1482                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1483                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1484                 } else {
1485                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1486                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1487                 }
1488                 rtl_reset_packet_filter(tp);
1489         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1490                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1491                 if (phydev->speed == SPEED_1000) {
1492                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1493                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1494                 } else {
1495                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1496                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1497                 }
1498         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1499                 if (phydev->speed == SPEED_10) {
1500                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1501                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1502                 } else {
1503                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1504                 }
1505         }
1506 }
1507
1508 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1509
1510 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1511 {
1512         struct rtl8169_private *tp = netdev_priv(dev);
1513
1514         wol->supported = WAKE_ANY;
1515         wol->wolopts = tp->saved_wolopts;
1516 }
1517
1518 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1519 {
1520         static const struct {
1521                 u32 opt;
1522                 u16 reg;
1523                 u8  mask;
1524         } cfg[] = {
1525                 { WAKE_PHY,   Config3, LinkUp },
1526                 { WAKE_UCAST, Config5, UWF },
1527                 { WAKE_BCAST, Config5, BWF },
1528                 { WAKE_MCAST, Config5, MWF },
1529                 { WAKE_ANY,   Config5, LanWake },
1530                 { WAKE_MAGIC, Config3, MagicPacket }
1531         };
1532         unsigned int i, tmp = ARRAY_SIZE(cfg);
1533         unsigned long flags;
1534         u8 options;
1535
1536         rtl_unlock_config_regs(tp);
1537
1538         if (rtl_is_8168evl_up(tp)) {
1539                 tmp--;
1540                 if (wolopts & WAKE_MAGIC)
1541                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1542                 else
1543                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1544         } else if (rtl_is_8125(tp)) {
1545                 tmp--;
1546                 if (wolopts & WAKE_MAGIC)
1547                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1548                 else
1549                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1550         }
1551
1552         raw_spin_lock_irqsave(&tp->config25_lock, flags);
1553         for (i = 0; i < tmp; i++) {
1554                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1555                 if (wolopts & cfg[i].opt)
1556                         options |= cfg[i].mask;
1557                 RTL_W8(tp, cfg[i].reg, options);
1558         }
1559         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1560
1561         switch (tp->mac_version) {
1562         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1563                 options = RTL_R8(tp, Config1) & ~PMEnable;
1564                 if (wolopts)
1565                         options |= PMEnable;
1566                 RTL_W8(tp, Config1, options);
1567                 break;
1568         case RTL_GIGA_MAC_VER_34:
1569         case RTL_GIGA_MAC_VER_37:
1570         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
1571                 if (wolopts)
1572                         rtl_mod_config2(tp, 0, PME_SIGNAL);
1573                 else
1574                         rtl_mod_config2(tp, PME_SIGNAL, 0);
1575                 break;
1576         default:
1577                 break;
1578         }
1579
1580         rtl_lock_config_regs(tp);
1581
1582         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1583
1584         if (!tp->dash_enabled) {
1585                 rtl_set_d3_pll_down(tp, !wolopts);
1586                 tp->dev->wol_enabled = wolopts ? 1 : 0;
1587         }
1588 }
1589
1590 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1591 {
1592         struct rtl8169_private *tp = netdev_priv(dev);
1593
1594         if (wol->wolopts & ~WAKE_ANY)
1595                 return -EINVAL;
1596
1597         tp->saved_wolopts = wol->wolopts;
1598         __rtl8169_set_wol(tp, tp->saved_wolopts);
1599
1600         return 0;
1601 }
1602
1603 static void rtl8169_get_drvinfo(struct net_device *dev,
1604                                 struct ethtool_drvinfo *info)
1605 {
1606         struct rtl8169_private *tp = netdev_priv(dev);
1607         struct rtl_fw *rtl_fw = tp->rtl_fw;
1608
1609         strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1610         strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1611         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1612         if (rtl_fw)
1613                 strscpy(info->fw_version, rtl_fw->version,
1614                         sizeof(info->fw_version));
1615 }
1616
1617 static int rtl8169_get_regs_len(struct net_device *dev)
1618 {
1619         return R8169_REGS_SIZE;
1620 }
1621
1622 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1623         netdev_features_t features)
1624 {
1625         struct rtl8169_private *tp = netdev_priv(dev);
1626
1627         if (dev->mtu > TD_MSS_MAX)
1628                 features &= ~NETIF_F_ALL_TSO;
1629
1630         if (dev->mtu > ETH_DATA_LEN &&
1631             tp->mac_version > RTL_GIGA_MAC_VER_06)
1632                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1633
1634         return features;
1635 }
1636
1637 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1638                                        netdev_features_t features)
1639 {
1640         u32 rx_config = RTL_R32(tp, RxConfig);
1641
1642         if (features & NETIF_F_RXALL)
1643                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1644         else
1645                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1646
1647         if (rtl_is_8125(tp)) {
1648                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1649                         rx_config |= RX_VLAN_8125;
1650                 else
1651                         rx_config &= ~RX_VLAN_8125;
1652         }
1653
1654         RTL_W32(tp, RxConfig, rx_config);
1655 }
1656
1657 static int rtl8169_set_features(struct net_device *dev,
1658                                 netdev_features_t features)
1659 {
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661
1662         rtl_set_rx_config_features(tp, features);
1663
1664         if (features & NETIF_F_RXCSUM)
1665                 tp->cp_cmd |= RxChkSum;
1666         else
1667                 tp->cp_cmd &= ~RxChkSum;
1668
1669         if (!rtl_is_8125(tp)) {
1670                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1671                         tp->cp_cmd |= RxVlan;
1672                 else
1673                         tp->cp_cmd &= ~RxVlan;
1674         }
1675
1676         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1677         rtl_pci_commit(tp);
1678
1679         return 0;
1680 }
1681
1682 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1683 {
1684         return (skb_vlan_tag_present(skb)) ?
1685                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1686 }
1687
1688 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1689 {
1690         u32 opts2 = le32_to_cpu(desc->opts2);
1691
1692         if (opts2 & RxVlanTag)
1693                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1694 }
1695
1696 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1697                              void *p)
1698 {
1699         struct rtl8169_private *tp = netdev_priv(dev);
1700         u32 __iomem *data = tp->mmio_addr;
1701         u32 *dw = p;
1702         int i;
1703
1704         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1705                 memcpy_fromio(dw++, data++, 4);
1706 }
1707
1708 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1709         "tx_packets",
1710         "rx_packets",
1711         "tx_errors",
1712         "rx_errors",
1713         "rx_missed",
1714         "align_errors",
1715         "tx_single_collisions",
1716         "tx_multi_collisions",
1717         "unicast",
1718         "broadcast",
1719         "multicast",
1720         "tx_aborted",
1721         "tx_underrun",
1722 };
1723
1724 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1725 {
1726         switch (sset) {
1727         case ETH_SS_STATS:
1728                 return ARRAY_SIZE(rtl8169_gstrings);
1729         default:
1730                 return -EOPNOTSUPP;
1731         }
1732 }
1733
1734 DECLARE_RTL_COND(rtl_counters_cond)
1735 {
1736         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1737 }
1738
1739 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1740 {
1741         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1742
1743         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1744         rtl_pci_commit(tp);
1745         RTL_W32(tp, CounterAddrLow, cmd);
1746         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1747
1748         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1749 }
1750
1751 static void rtl8169_update_counters(struct rtl8169_private *tp)
1752 {
1753         u8 val = RTL_R8(tp, ChipCmd);
1754
1755         /*
1756          * Some chips are unable to dump tally counters when the receiver
1757          * is disabled. If 0xff chip may be in a PCI power-save state.
1758          */
1759         if (val & CmdRxEnb && val != 0xff)
1760                 rtl8169_do_counters(tp, CounterDump);
1761 }
1762
1763 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1764 {
1765         struct rtl8169_counters *counters = tp->counters;
1766
1767         /*
1768          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1769          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1770          * reset by a power cycle, while the counter values collected by the
1771          * driver are reset at every driver unload/load cycle.
1772          *
1773          * To make sure the HW values returned by @get_stats64 match the SW
1774          * values, we collect the initial values at first open(*) and use them
1775          * as offsets to normalize the values returned by @get_stats64.
1776          *
1777          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1778          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1779          * set at open time by rtl_hw_start.
1780          */
1781
1782         if (tp->tc_offset.inited)
1783                 return;
1784
1785         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1786                 rtl8169_do_counters(tp, CounterReset);
1787         } else {
1788                 rtl8169_update_counters(tp);
1789                 tp->tc_offset.tx_errors = counters->tx_errors;
1790                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1791                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1792                 tp->tc_offset.rx_missed = counters->rx_missed;
1793         }
1794
1795         tp->tc_offset.inited = true;
1796 }
1797
1798 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1799                                       struct ethtool_stats *stats, u64 *data)
1800 {
1801         struct rtl8169_private *tp = netdev_priv(dev);
1802         struct rtl8169_counters *counters;
1803
1804         counters = tp->counters;
1805         rtl8169_update_counters(tp);
1806
1807         data[0] = le64_to_cpu(counters->tx_packets);
1808         data[1] = le64_to_cpu(counters->rx_packets);
1809         data[2] = le64_to_cpu(counters->tx_errors);
1810         data[3] = le32_to_cpu(counters->rx_errors);
1811         data[4] = le16_to_cpu(counters->rx_missed);
1812         data[5] = le16_to_cpu(counters->align_errors);
1813         data[6] = le32_to_cpu(counters->tx_one_collision);
1814         data[7] = le32_to_cpu(counters->tx_multi_collision);
1815         data[8] = le64_to_cpu(counters->rx_unicast);
1816         data[9] = le64_to_cpu(counters->rx_broadcast);
1817         data[10] = le32_to_cpu(counters->rx_multicast);
1818         data[11] = le16_to_cpu(counters->tx_aborted);
1819         data[12] = le16_to_cpu(counters->tx_underun);
1820 }
1821
1822 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1823 {
1824         switch(stringset) {
1825         case ETH_SS_STATS:
1826                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1827                 break;
1828         }
1829 }
1830
1831 /*
1832  * Interrupt coalescing
1833  *
1834  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1835  * >     8169, 8168 and 810x line of chipsets
1836  *
1837  * 8169, 8168, and 8136(810x) serial chipsets support it.
1838  *
1839  * > 2 - the Tx timer unit at gigabit speed
1840  *
1841  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1842  * (0xe0) bit 1 and bit 0.
1843  *
1844  * For 8169
1845  * bit[1:0] \ speed        1000M           100M            10M
1846  * 0 0                     320ns           2.56us          40.96us
1847  * 0 1                     2.56us          20.48us         327.7us
1848  * 1 0                     5.12us          40.96us         655.4us
1849  * 1 1                     10.24us         81.92us         1.31ms
1850  *
1851  * For the other
1852  * bit[1:0] \ speed        1000M           100M            10M
1853  * 0 0                     5us             2.56us          40.96us
1854  * 0 1                     40us            20.48us         327.7us
1855  * 1 0                     80us            40.96us         655.4us
1856  * 1 1                     160us           81.92us         1.31ms
1857  */
1858
1859 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1860 struct rtl_coalesce_info {
1861         u32 speed;
1862         u32 scale_nsecs[4];
1863 };
1864
1865 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1866 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1867
1868 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1869         { SPEED_1000,   COALESCE_DELAY(320) },
1870         { SPEED_100,    COALESCE_DELAY(2560) },
1871         { SPEED_10,     COALESCE_DELAY(40960) },
1872         { 0 },
1873 };
1874
1875 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1876         { SPEED_1000,   COALESCE_DELAY(5000) },
1877         { SPEED_100,    COALESCE_DELAY(2560) },
1878         { SPEED_10,     COALESCE_DELAY(40960) },
1879         { 0 },
1880 };
1881 #undef COALESCE_DELAY
1882
1883 /* get rx/tx scale vector corresponding to current speed */
1884 static const struct rtl_coalesce_info *
1885 rtl_coalesce_info(struct rtl8169_private *tp)
1886 {
1887         const struct rtl_coalesce_info *ci;
1888
1889         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1890                 ci = rtl_coalesce_info_8169;
1891         else
1892                 ci = rtl_coalesce_info_8168_8136;
1893
1894         /* if speed is unknown assume highest one */
1895         if (tp->phydev->speed == SPEED_UNKNOWN)
1896                 return ci;
1897
1898         for (; ci->speed; ci++) {
1899                 if (tp->phydev->speed == ci->speed)
1900                         return ci;
1901         }
1902
1903         return ERR_PTR(-ELNRNG);
1904 }
1905
1906 static int rtl_get_coalesce(struct net_device *dev,
1907                             struct ethtool_coalesce *ec,
1908                             struct kernel_ethtool_coalesce *kernel_coal,
1909                             struct netlink_ext_ack *extack)
1910 {
1911         struct rtl8169_private *tp = netdev_priv(dev);
1912         const struct rtl_coalesce_info *ci;
1913         u32 scale, c_us, c_fr;
1914         u16 intrmit;
1915
1916         if (rtl_is_8125(tp))
1917                 return -EOPNOTSUPP;
1918
1919         memset(ec, 0, sizeof(*ec));
1920
1921         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1922         ci = rtl_coalesce_info(tp);
1923         if (IS_ERR(ci))
1924                 return PTR_ERR(ci);
1925
1926         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1927
1928         intrmit = RTL_R16(tp, IntrMitigate);
1929
1930         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1931         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1932
1933         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1934         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1935         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1936
1937         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1938         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1939
1940         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1941         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1942
1943         return 0;
1944 }
1945
1946 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1947 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1948                                      u16 *cp01)
1949 {
1950         const struct rtl_coalesce_info *ci;
1951         u16 i;
1952
1953         ci = rtl_coalesce_info(tp);
1954         if (IS_ERR(ci))
1955                 return PTR_ERR(ci);
1956
1957         for (i = 0; i < 4; i++) {
1958                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1959                         *cp01 = i;
1960                         return ci->scale_nsecs[i];
1961                 }
1962         }
1963
1964         return -ERANGE;
1965 }
1966
1967 static int rtl_set_coalesce(struct net_device *dev,
1968                             struct ethtool_coalesce *ec,
1969                             struct kernel_ethtool_coalesce *kernel_coal,
1970                             struct netlink_ext_ack *extack)
1971 {
1972         struct rtl8169_private *tp = netdev_priv(dev);
1973         u32 tx_fr = ec->tx_max_coalesced_frames;
1974         u32 rx_fr = ec->rx_max_coalesced_frames;
1975         u32 coal_usec_max, units;
1976         u16 w = 0, cp01 = 0;
1977         int scale;
1978
1979         if (rtl_is_8125(tp))
1980                 return -EOPNOTSUPP;
1981
1982         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1983                 return -ERANGE;
1984
1985         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1986         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1987         if (scale < 0)
1988                 return scale;
1989
1990         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1991          * not only when usecs=0 because of e.g. the following scenario:
1992          *
1993          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1994          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1995          * - then user does `ethtool -C eth0 rx-usecs 100`
1996          *
1997          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1998          * if we want to ignore rx_frames then it has to be set to 0.
1999          */
2000         if (rx_fr == 1)
2001                 rx_fr = 0;
2002         if (tx_fr == 1)
2003                 tx_fr = 0;
2004
2005         /* HW requires time limit to be set if frame limit is set */
2006         if ((tx_fr && !ec->tx_coalesce_usecs) ||
2007             (rx_fr && !ec->rx_coalesce_usecs))
2008                 return -EINVAL;
2009
2010         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2011         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
2012
2013         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2014         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2015         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2016         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
2017
2018         RTL_W16(tp, IntrMitigate, w);
2019
2020         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2021         if (rtl_is_8168evl_up(tp)) {
2022                 if (!rx_fr && !tx_fr)
2023                         /* disable packet counter */
2024                         tp->cp_cmd |= PktCntrDisable;
2025                 else
2026                         tp->cp_cmd &= ~PktCntrDisable;
2027         }
2028
2029         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2030         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2031         rtl_pci_commit(tp);
2032
2033         return 0;
2034 }
2035
2036 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2037 {
2038         unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2039
2040         switch (tp->mac_version) {
2041         case RTL_GIGA_MAC_VER_46:
2042         case RTL_GIGA_MAC_VER_48:
2043                 tp->tx_lpi_timer = timer_val;
2044                 r8168_mac_ocp_write(tp, 0xe048, timer_val);
2045                 break;
2046         case RTL_GIGA_MAC_VER_61:
2047         case RTL_GIGA_MAC_VER_63:
2048         case RTL_GIGA_MAC_VER_65:
2049                 tp->tx_lpi_timer = timer_val;
2050                 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2051                 break;
2052         default:
2053                 break;
2054         }
2055 }
2056
2057 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)
2058 {
2059         unsigned int speed = tp->phydev->speed;
2060         unsigned int timer = tp->tx_lpi_timer;
2061
2062         if (!timer || speed == SPEED_UNKNOWN)
2063                 return 0;
2064
2065         /* tx_lpi_timer value is in bytes */
2066         return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);
2067 }
2068
2069 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
2070 {
2071         struct rtl8169_private *tp = netdev_priv(dev);
2072         int ret;
2073
2074         if (!rtl_supports_eee(tp))
2075                 return -EOPNOTSUPP;
2076
2077         ret = phy_ethtool_get_eee(tp->phydev, data);
2078         if (ret)
2079                 return ret;
2080
2081         data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp);
2082
2083         return 0;
2084 }
2085
2086 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
2087 {
2088         struct rtl8169_private *tp = netdev_priv(dev);
2089
2090         if (!rtl_supports_eee(tp))
2091                 return -EOPNOTSUPP;
2092
2093         return phy_ethtool_set_eee(tp->phydev, data);
2094 }
2095
2096 static void rtl8169_get_ringparam(struct net_device *dev,
2097                                   struct ethtool_ringparam *data,
2098                                   struct kernel_ethtool_ringparam *kernel_data,
2099                                   struct netlink_ext_ack *extack)
2100 {
2101         data->rx_max_pending = NUM_RX_DESC;
2102         data->rx_pending = NUM_RX_DESC;
2103         data->tx_max_pending = NUM_TX_DESC;
2104         data->tx_pending = NUM_TX_DESC;
2105 }
2106
2107 static void rtl8169_get_pauseparam(struct net_device *dev,
2108                                    struct ethtool_pauseparam *data)
2109 {
2110         struct rtl8169_private *tp = netdev_priv(dev);
2111         bool tx_pause, rx_pause;
2112
2113         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
2114
2115         data->autoneg = tp->phydev->autoneg;
2116         data->tx_pause = tx_pause ? 1 : 0;
2117         data->rx_pause = rx_pause ? 1 : 0;
2118 }
2119
2120 static int rtl8169_set_pauseparam(struct net_device *dev,
2121                                   struct ethtool_pauseparam *data)
2122 {
2123         struct rtl8169_private *tp = netdev_priv(dev);
2124
2125         if (dev->mtu > ETH_DATA_LEN)
2126                 return -EOPNOTSUPP;
2127
2128         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2129
2130         return 0;
2131 }
2132
2133 static const struct ethtool_ops rtl8169_ethtool_ops = {
2134         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2135                                      ETHTOOL_COALESCE_MAX_FRAMES,
2136         .get_drvinfo            = rtl8169_get_drvinfo,
2137         .get_regs_len           = rtl8169_get_regs_len,
2138         .get_link               = ethtool_op_get_link,
2139         .get_coalesce           = rtl_get_coalesce,
2140         .set_coalesce           = rtl_set_coalesce,
2141         .get_regs               = rtl8169_get_regs,
2142         .get_wol                = rtl8169_get_wol,
2143         .set_wol                = rtl8169_set_wol,
2144         .get_strings            = rtl8169_get_strings,
2145         .get_sset_count         = rtl8169_get_sset_count,
2146         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2147         .get_ts_info            = ethtool_op_get_ts_info,
2148         .nway_reset             = phy_ethtool_nway_reset,
2149         .get_eee                = rtl8169_get_eee,
2150         .set_eee                = rtl8169_set_eee,
2151         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2152         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2153         .get_ringparam          = rtl8169_get_ringparam,
2154         .get_pauseparam         = rtl8169_get_pauseparam,
2155         .set_pauseparam         = rtl8169_set_pauseparam,
2156 };
2157
2158 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2159 {
2160         /*
2161          * The driver currently handles the 8168Bf and the 8168Be identically
2162          * but they can be identified more specifically through the test below
2163          * if needed:
2164          *
2165          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2166          *
2167          * Same thing for the 8101Eb and the 8101Ec:
2168          *
2169          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2170          */
2171         static const struct rtl_mac_info {
2172                 u16 mask;
2173                 u16 val;
2174                 enum mac_version ver;
2175         } mac_info[] = {
2176                 /* 8126A family. */
2177                 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
2178
2179                 /* 8125B family. */
2180                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2181
2182                 /* 8125A family. */
2183                 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2184                 /* It seems only XID 609 made it to the mass market.
2185                  * { 0x7cf, 0x608,      RTL_GIGA_MAC_VER_60 },
2186                  * { 0x7c8, 0x608,      RTL_GIGA_MAC_VER_61 },
2187                  */
2188
2189                 /* RTL8117 */
2190                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2191                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2192
2193                 /* 8168EP family. */
2194                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2195                 /* It seems this chip version never made it to
2196                  * the wild. Let's disable detection.
2197                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
2198                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
2199                  */
2200
2201                 /* 8168H family. */
2202                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2203                 /* It seems this chip version never made it to
2204                  * the wild. Let's disable detection.
2205                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
2206                  */
2207
2208                 /* 8168G family. */
2209                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2210                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2211                 /* It seems this chip version never made it to
2212                  * the wild. Let's disable detection.
2213                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
2214                  */
2215                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2216
2217                 /* 8168F family. */
2218                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2219                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2220                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2221
2222                 /* 8168E family. */
2223                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2224                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2225                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2226
2227                 /* 8168D family. */
2228                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2229                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2230
2231                 /* 8168DP family. */
2232                 /* It seems this early RTL8168dp version never made it to
2233                  * the wild. Support has been removed.
2234                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2235                  */
2236                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2237                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2238
2239                 /* 8168C family. */
2240                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2241                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2242                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2243                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2244                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2245                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2246                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2247
2248                 /* 8168B family. */
2249                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2250                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2251
2252                 /* 8101 family. */
2253                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2254                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2255                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2256                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2257                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2258                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2259                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2260                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2261                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2262                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2263                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2264                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2265
2266                 /* 8110 family. */
2267                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2268                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2269                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2270                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2271                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2272
2273                 /* Catch-all */
2274                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2275         };
2276         const struct rtl_mac_info *p = mac_info;
2277         enum mac_version ver;
2278
2279         while ((xid & p->mask) != p->val)
2280                 p++;
2281         ver = p->ver;
2282
2283         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2284                 if (ver == RTL_GIGA_MAC_VER_42)
2285                         ver = RTL_GIGA_MAC_VER_43;
2286                 else if (ver == RTL_GIGA_MAC_VER_46)
2287                         ver = RTL_GIGA_MAC_VER_48;
2288         }
2289
2290         return ver;
2291 }
2292
2293 static void rtl_release_firmware(struct rtl8169_private *tp)
2294 {
2295         if (tp->rtl_fw) {
2296                 rtl_fw_release_firmware(tp->rtl_fw);
2297                 kfree(tp->rtl_fw);
2298                 tp->rtl_fw = NULL;
2299         }
2300 }
2301
2302 void r8169_apply_firmware(struct rtl8169_private *tp)
2303 {
2304         int val;
2305
2306         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2307         if (tp->rtl_fw) {
2308                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2309                 /* At least one firmware doesn't reset tp->ocp_base. */
2310                 tp->ocp_base = OCP_STD_PHY_BASE;
2311
2312                 /* PHY soft reset may still be in progress */
2313                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2314                                       !(val & BMCR_RESET),
2315                                       50000, 600000, true);
2316         }
2317 }
2318
2319 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2320 {
2321         /* Adjust EEE LED frequency */
2322         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2323                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2324
2325         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2326 }
2327
2328 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2329 {
2330         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2331         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2332 }
2333
2334 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2335 {
2336         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2337 }
2338
2339 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2340 {
2341         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2342         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2343         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2344         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2345 }
2346
2347 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2348 {
2349         u16 data1, data2, ioffset;
2350
2351         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2352         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2353         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2354
2355         ioffset = (data2 >> 1) & 0x7ff8;
2356         ioffset |= data2 & 0x0007;
2357         if (data1 & BIT(7))
2358                 ioffset |= BIT(15);
2359
2360         return ioffset;
2361 }
2362
2363 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2364 {
2365         if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
2366                 return;
2367
2368         set_bit(flag, tp->wk.flags);
2369         schedule_work(&tp->wk.work);
2370 }
2371
2372 static void rtl8169_init_phy(struct rtl8169_private *tp)
2373 {
2374         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2375
2376         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2377                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2378                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2379                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2380                 RTL_W8(tp, 0x82, 0x01);
2381         }
2382
2383         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2384             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2385             tp->pci_dev->subsystem_device == 0xe000)
2386                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2387
2388         /* We may have called phy_speed_down before */
2389         phy_speed_up(tp->phydev);
2390
2391         genphy_soft_reset(tp->phydev);
2392 }
2393
2394 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2395 {
2396         rtl_unlock_config_regs(tp);
2397
2398         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2399         rtl_pci_commit(tp);
2400
2401         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2402         rtl_pci_commit(tp);
2403
2404         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2405                 rtl_rar_exgmac_set(tp, addr);
2406
2407         rtl_lock_config_regs(tp);
2408 }
2409
2410 static int rtl_set_mac_address(struct net_device *dev, void *p)
2411 {
2412         struct rtl8169_private *tp = netdev_priv(dev);
2413         int ret;
2414
2415         ret = eth_mac_addr(dev, p);
2416         if (ret)
2417                 return ret;
2418
2419         rtl_rar_set(tp, dev->dev_addr);
2420
2421         return 0;
2422 }
2423
2424 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2425 {
2426         switch (tp->mac_version) {
2427         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2428         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2429                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2430                 break;
2431         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2432         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2433         case RTL_GIGA_MAC_VER_38:
2434                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2435                 break;
2436         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2437                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2438                 break;
2439         case RTL_GIGA_MAC_VER_61:
2440                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2441                 break;
2442         case RTL_GIGA_MAC_VER_63:
2443         case RTL_GIGA_MAC_VER_65:
2444                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2445                         RX_PAUSE_SLOT_ON);
2446                 break;
2447         default:
2448                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2449                 break;
2450         }
2451 }
2452
2453 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2454 {
2455         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2456 }
2457
2458 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2459 {
2460         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2461         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2462 }
2463
2464 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2465 {
2466         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2467         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2468 }
2469
2470 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2471 {
2472         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2473 }
2474
2475 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2476 {
2477         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2478 }
2479
2480 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2481 {
2482         RTL_W8(tp, MaxTxPacketSize, 0x24);
2483         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2484         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2485 }
2486
2487 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2488 {
2489         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2490         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2491         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2492 }
2493
2494 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2495 {
2496         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2497 }
2498
2499 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2500 {
2501         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2502 }
2503
2504 static void rtl_jumbo_config(struct rtl8169_private *tp)
2505 {
2506         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2507         int readrq = 4096;
2508
2509         rtl_unlock_config_regs(tp);
2510         switch (tp->mac_version) {
2511         case RTL_GIGA_MAC_VER_17:
2512                 if (jumbo) {
2513                         readrq = 512;
2514                         r8168b_1_hw_jumbo_enable(tp);
2515                 } else {
2516                         r8168b_1_hw_jumbo_disable(tp);
2517                 }
2518                 break;
2519         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2520                 if (jumbo) {
2521                         readrq = 512;
2522                         r8168c_hw_jumbo_enable(tp);
2523                 } else {
2524                         r8168c_hw_jumbo_disable(tp);
2525                 }
2526                 break;
2527         case RTL_GIGA_MAC_VER_28:
2528                 if (jumbo)
2529                         r8168dp_hw_jumbo_enable(tp);
2530                 else
2531                         r8168dp_hw_jumbo_disable(tp);
2532                 break;
2533         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2534                 if (jumbo)
2535                         r8168e_hw_jumbo_enable(tp);
2536                 else
2537                         r8168e_hw_jumbo_disable(tp);
2538                 break;
2539         default:
2540                 break;
2541         }
2542         rtl_lock_config_regs(tp);
2543
2544         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2545                 pcie_set_readrq(tp->pci_dev, readrq);
2546
2547         /* Chip doesn't support pause in jumbo mode */
2548         if (jumbo) {
2549                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2550                                    tp->phydev->advertising);
2551                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2552                                    tp->phydev->advertising);
2553                 phy_start_aneg(tp->phydev);
2554         }
2555 }
2556
2557 DECLARE_RTL_COND(rtl_chipcmd_cond)
2558 {
2559         return RTL_R8(tp, ChipCmd) & CmdReset;
2560 }
2561
2562 static void rtl_hw_reset(struct rtl8169_private *tp)
2563 {
2564         RTL_W8(tp, ChipCmd, CmdReset);
2565
2566         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2567 }
2568
2569 static void rtl_request_firmware(struct rtl8169_private *tp)
2570 {
2571         struct rtl_fw *rtl_fw;
2572
2573         /* firmware loaded already or no firmware available */
2574         if (tp->rtl_fw || !tp->fw_name)
2575                 return;
2576
2577         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2578         if (!rtl_fw)
2579                 return;
2580
2581         rtl_fw->phy_write = rtl_writephy;
2582         rtl_fw->phy_read = rtl_readphy;
2583         rtl_fw->mac_mcu_write = mac_mcu_write;
2584         rtl_fw->mac_mcu_read = mac_mcu_read;
2585         rtl_fw->fw_name = tp->fw_name;
2586         rtl_fw->dev = tp_to_dev(tp);
2587
2588         if (rtl_fw_request_firmware(rtl_fw))
2589                 kfree(rtl_fw);
2590         else
2591                 tp->rtl_fw = rtl_fw;
2592 }
2593
2594 static void rtl_rx_close(struct rtl8169_private *tp)
2595 {
2596         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2597 }
2598
2599 DECLARE_RTL_COND(rtl_npq_cond)
2600 {
2601         return RTL_R8(tp, TxPoll) & NPQ;
2602 }
2603
2604 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2605 {
2606         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2607 }
2608
2609 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2610 {
2611         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2612 }
2613
2614 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2615 {
2616         /* IntrMitigate has new functionality on RTL8125 */
2617         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2618 }
2619
2620 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2621 {
2622         switch (tp->mac_version) {
2623         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2624                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2625                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2626                 break;
2627         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2628                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2629                 break;
2630         case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65:
2631                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2632                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2633                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2634                 break;
2635         default:
2636                 break;
2637         }
2638 }
2639
2640 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2641 {
2642         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2643 }
2644
2645 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2646 {
2647         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2648         fsleep(2000);
2649         rtl_wait_txrx_fifo_empty(tp);
2650 }
2651
2652 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2653 {
2654         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2655                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2656                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2657
2658         if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2659                 rtl_disable_rxdvgate(tp);
2660 }
2661
2662 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2663 {
2664         if (tp->dash_enabled)
2665                 return;
2666
2667         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2668             tp->mac_version == RTL_GIGA_MAC_VER_33)
2669                 rtl_ephy_write(tp, 0x19, 0xff64);
2670
2671         if (device_may_wakeup(tp_to_dev(tp))) {
2672                 phy_speed_down(tp->phydev, false);
2673                 rtl_wol_enable_rx(tp);
2674         }
2675 }
2676
2677 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2678 {
2679         u32 val = TX_DMA_BURST << TxDMAShift |
2680                   InterFrameGap << TxInterFrameGapShift;
2681
2682         if (rtl_is_8168evl_up(tp))
2683                 val |= TXCFG_AUTO_FIFO;
2684
2685         RTL_W32(tp, TxConfig, val);
2686 }
2687
2688 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2689 {
2690         /* Low hurts. Let's disable the filtering. */
2691         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2692 }
2693
2694 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2695 {
2696         /*
2697          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2698          * register to be written before TxDescAddrLow to work.
2699          * Switching from MMIO to I/O access fixes the issue as well.
2700          */
2701         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2702         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2703         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2704         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2705 }
2706
2707 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2708 {
2709         u32 val;
2710
2711         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2712                 val = 0x000fff00;
2713         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2714                 val = 0x00ffff00;
2715         else
2716                 return;
2717
2718         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2719                 val |= 0xff;
2720
2721         RTL_W32(tp, 0x7c, val);
2722 }
2723
2724 static void rtl_set_rx_mode(struct net_device *dev)
2725 {
2726         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2727         /* Multicast hash filter */
2728         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2729         struct rtl8169_private *tp = netdev_priv(dev);
2730         u32 tmp;
2731
2732         if (dev->flags & IFF_PROMISC) {
2733                 rx_mode |= AcceptAllPhys;
2734         } else if (!(dev->flags & IFF_MULTICAST)) {
2735                 rx_mode &= ~AcceptMulticast;
2736         } else if (dev->flags & IFF_ALLMULTI ||
2737                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2738                 /* accept all multicasts */
2739         } else if (netdev_mc_empty(dev)) {
2740                 rx_mode &= ~AcceptMulticast;
2741         } else {
2742                 struct netdev_hw_addr *ha;
2743
2744                 mc_filter[1] = mc_filter[0] = 0;
2745                 netdev_for_each_mc_addr(ha, dev) {
2746                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2747                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2748                 }
2749
2750                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2751                         tmp = mc_filter[0];
2752                         mc_filter[0] = swab32(mc_filter[1]);
2753                         mc_filter[1] = swab32(tmp);
2754                 }
2755         }
2756
2757         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2758         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2759
2760         tmp = RTL_R32(tp, RxConfig);
2761         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2762 }
2763
2764 DECLARE_RTL_COND(rtl_csiar_cond)
2765 {
2766         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2767 }
2768
2769 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2770 {
2771         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2772
2773         RTL_W32(tp, CSIDR, value);
2774         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2775                 CSIAR_BYTE_ENABLE | func << 16);
2776
2777         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2778 }
2779
2780 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2781 {
2782         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2783
2784         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2785                 CSIAR_BYTE_ENABLE);
2786
2787         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2788                 RTL_R32(tp, CSIDR) : ~0;
2789 }
2790
2791 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2792 {
2793         struct pci_dev *pdev = tp->pci_dev;
2794         u32 csi;
2795
2796         /* According to Realtek the value at config space address 0x070f
2797          * controls the L0s/L1 entrance latency. We try standard ECAM access
2798          * first and if it fails fall back to CSI.
2799          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2800          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2801          */
2802         if (pdev->cfg_size > 0x070f &&
2803             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2804                 return;
2805
2806         netdev_notice_once(tp->dev,
2807                 "No native access to PCI extended config space, falling back to CSI\n");
2808         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2809         rtl_csi_write(tp, 0x070c, csi | val << 24);
2810 }
2811
2812 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2813 {
2814         /* L0 7us, L1 16us */
2815         rtl_set_aspm_entry_latency(tp, 0x27);
2816 }
2817
2818 struct ephy_info {
2819         unsigned int offset;
2820         u16 mask;
2821         u16 bits;
2822 };
2823
2824 static void __rtl_ephy_init(struct rtl8169_private *tp,
2825                             const struct ephy_info *e, int len)
2826 {
2827         u16 w;
2828
2829         while (len-- > 0) {
2830                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2831                 rtl_ephy_write(tp, e->offset, w);
2832                 e++;
2833         }
2834 }
2835
2836 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2837
2838 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2839 {
2840         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2841                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2842 }
2843
2844 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2845 {
2846         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2847                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2848 }
2849
2850 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2851 {
2852         /* work around an issue when PCI reset occurs during L2/L3 state */
2853         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2854 }
2855
2856 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2857 {
2858         /* Bits control which events trigger ASPM L1 exit:
2859          * Bit 12: rxdv
2860          * Bit 11: ltr_msg
2861          * Bit 10: txdma_poll
2862          * Bit  9: xadm
2863          * Bit  8: pktavi
2864          * Bit  7: txpla
2865          */
2866         switch (tp->mac_version) {
2867         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2868                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2869                 break;
2870         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2871                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2872                 break;
2873         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
2874                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2875                 break;
2876         default:
2877                 break;
2878         }
2879 }
2880
2881 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2882 {
2883         switch (tp->mac_version) {
2884         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2885                 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2886                 break;
2887         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
2888                 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2889                 break;
2890         default:
2891                 break;
2892         }
2893 }
2894
2895 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2896 {
2897         u8 val8;
2898
2899         if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2900                 return;
2901
2902         /* Don't enable ASPM in the chip if OS can't control ASPM */
2903         if (enable && tp->aspm_manageable) {
2904                 /* On these chip versions ASPM can even harm
2905                  * bus communication of other PCI devices.
2906                  */
2907                 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2908                     tp->mac_version == RTL_GIGA_MAC_VER_43)
2909                         return;
2910
2911                 rtl_mod_config5(tp, 0, ASPM_en);
2912                 switch (tp->mac_version) {
2913                 case RTL_GIGA_MAC_VER_65:
2914                         val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
2915                         RTL_W8(tp, INT_CFG0_8125, val8);
2916                         break;
2917                 default:
2918                         rtl_mod_config2(tp, 0, ClkReqEn);
2919                         break;
2920                 }
2921
2922                 switch (tp->mac_version) {
2923                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2924                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
2925                         /* reset ephy tx/rx disable timer */
2926                         r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2927                         /* chip can trigger L1.2 */
2928                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2929                         break;
2930                 default:
2931                         break;
2932                 }
2933         } else {
2934                 switch (tp->mac_version) {
2935                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2936                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
2937                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2938                         break;
2939                 default:
2940                         break;
2941                 }
2942
2943                 switch (tp->mac_version) {
2944                 case RTL_GIGA_MAC_VER_65:
2945                         val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
2946                         RTL_W8(tp, INT_CFG0_8125, val8);
2947                         break;
2948                 default:
2949                         rtl_mod_config2(tp, ClkReqEn, 0);
2950                         break;
2951                 }
2952                 rtl_mod_config5(tp, ASPM_en, 0);
2953         }
2954 }
2955
2956 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2957                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2958 {
2959         /* Usage of dynamic vs. static FIFO is controlled by bit
2960          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2961          */
2962         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2963         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2964 }
2965
2966 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2967                                           u8 low, u8 high)
2968 {
2969         /* FIFO thresholds for pause flow control */
2970         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2971         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2972 }
2973
2974 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2975 {
2976         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2977 }
2978
2979 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2980 {
2981         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2982
2983         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2984
2985         rtl_disable_clock_request(tp);
2986 }
2987
2988 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2989 {
2990         static const struct ephy_info e_info_8168cp[] = {
2991                 { 0x01, 0,      0x0001 },
2992                 { 0x02, 0x0800, 0x1000 },
2993                 { 0x03, 0,      0x0042 },
2994                 { 0x06, 0x0080, 0x0000 },
2995                 { 0x07, 0,      0x2000 }
2996         };
2997
2998         rtl_set_def_aspm_entry_latency(tp);
2999
3000         rtl_ephy_init(tp, e_info_8168cp);
3001
3002         __rtl_hw_start_8168cp(tp);
3003 }
3004
3005 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
3006 {
3007         rtl_set_def_aspm_entry_latency(tp);
3008
3009         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3010 }
3011
3012 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
3013 {
3014         rtl_set_def_aspm_entry_latency(tp);
3015
3016         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3017
3018         /* Magic. */
3019         RTL_W8(tp, DBG_REG, 0x20);
3020 }
3021
3022 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
3023 {
3024         static const struct ephy_info e_info_8168c_1[] = {
3025                 { 0x02, 0x0800, 0x1000 },
3026                 { 0x03, 0,      0x0002 },
3027                 { 0x06, 0x0080, 0x0000 }
3028         };
3029
3030         rtl_set_def_aspm_entry_latency(tp);
3031
3032         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3033
3034         rtl_ephy_init(tp, e_info_8168c_1);
3035
3036         __rtl_hw_start_8168cp(tp);
3037 }
3038
3039 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
3040 {
3041         static const struct ephy_info e_info_8168c_2[] = {
3042                 { 0x01, 0,      0x0001 },
3043                 { 0x03, 0x0400, 0x0020 }
3044         };
3045
3046         rtl_set_def_aspm_entry_latency(tp);
3047
3048         rtl_ephy_init(tp, e_info_8168c_2);
3049
3050         __rtl_hw_start_8168cp(tp);
3051 }
3052
3053 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
3054 {
3055         rtl_set_def_aspm_entry_latency(tp);
3056
3057         __rtl_hw_start_8168cp(tp);
3058 }
3059
3060 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
3061 {
3062         rtl_set_def_aspm_entry_latency(tp);
3063
3064         rtl_disable_clock_request(tp);
3065 }
3066
3067 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
3068 {
3069         static const struct ephy_info e_info_8168d_4[] = {
3070                 { 0x0b, 0x0000, 0x0048 },
3071                 { 0x19, 0x0020, 0x0050 },
3072                 { 0x0c, 0x0100, 0x0020 },
3073                 { 0x10, 0x0004, 0x0000 },
3074         };
3075
3076         rtl_set_def_aspm_entry_latency(tp);
3077
3078         rtl_ephy_init(tp, e_info_8168d_4);
3079
3080         rtl_enable_clock_request(tp);
3081 }
3082
3083 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
3084 {
3085         static const struct ephy_info e_info_8168e_1[] = {
3086                 { 0x00, 0x0200, 0x0100 },
3087                 { 0x00, 0x0000, 0x0004 },
3088                 { 0x06, 0x0002, 0x0001 },
3089                 { 0x06, 0x0000, 0x0030 },
3090                 { 0x07, 0x0000, 0x2000 },
3091                 { 0x00, 0x0000, 0x0020 },
3092                 { 0x03, 0x5800, 0x2000 },
3093                 { 0x03, 0x0000, 0x0001 },
3094                 { 0x01, 0x0800, 0x1000 },
3095                 { 0x07, 0x0000, 0x4000 },
3096                 { 0x1e, 0x0000, 0x2000 },
3097                 { 0x19, 0xffff, 0xfe6c },
3098                 { 0x0a, 0x0000, 0x0040 }
3099         };
3100
3101         rtl_set_def_aspm_entry_latency(tp);
3102
3103         rtl_ephy_init(tp, e_info_8168e_1);
3104
3105         rtl_disable_clock_request(tp);
3106
3107         /* Reset tx FIFO pointer */
3108         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3109         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3110
3111         rtl_mod_config5(tp, Spi_en, 0);
3112 }
3113
3114 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3115 {
3116         static const struct ephy_info e_info_8168e_2[] = {
3117                 { 0x09, 0x0000, 0x0080 },
3118                 { 0x19, 0x0000, 0x0224 },
3119                 { 0x00, 0x0000, 0x0004 },
3120                 { 0x0c, 0x3df0, 0x0200 },
3121         };
3122
3123         rtl_set_def_aspm_entry_latency(tp);
3124
3125         rtl_ephy_init(tp, e_info_8168e_2);
3126
3127         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3128         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3129         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3130         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
3131         rtl_reset_packet_filter(tp);
3132         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3133         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3134         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
3135
3136         rtl_disable_clock_request(tp);
3137
3138         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3139
3140         rtl8168_config_eee_mac(tp);
3141
3142         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3143         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3144         rtl_mod_config5(tp, Spi_en, 0);
3145 }
3146
3147 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3148 {
3149         rtl_set_def_aspm_entry_latency(tp);
3150
3151         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3152         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3153         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3154         rtl_reset_packet_filter(tp);
3155         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3156         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3157         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3158         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3159
3160         rtl_disable_clock_request(tp);
3161
3162         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3163         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3164         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3165         rtl_mod_config5(tp, Spi_en, 0);
3166
3167         rtl8168_config_eee_mac(tp);
3168 }
3169
3170 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3171 {
3172         static const struct ephy_info e_info_8168f_1[] = {
3173                 { 0x06, 0x00c0, 0x0020 },
3174                 { 0x08, 0x0001, 0x0002 },
3175                 { 0x09, 0x0000, 0x0080 },
3176                 { 0x19, 0x0000, 0x0224 },
3177                 { 0x00, 0x0000, 0x0008 },
3178                 { 0x0c, 0x3df0, 0x0200 },
3179         };
3180
3181         rtl_hw_start_8168f(tp);
3182
3183         rtl_ephy_init(tp, e_info_8168f_1);
3184 }
3185
3186 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3187 {
3188         static const struct ephy_info e_info_8168f_1[] = {
3189                 { 0x06, 0x00c0, 0x0020 },
3190                 { 0x0f, 0xffff, 0x5200 },
3191                 { 0x19, 0x0000, 0x0224 },
3192                 { 0x00, 0x0000, 0x0008 },
3193                 { 0x0c, 0x3df0, 0x0200 },
3194         };
3195
3196         rtl_hw_start_8168f(tp);
3197         rtl_pcie_state_l2l3_disable(tp);
3198
3199         rtl_ephy_init(tp, e_info_8168f_1);
3200 }
3201
3202 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3203 {
3204         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3205         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3206
3207         rtl_set_def_aspm_entry_latency(tp);
3208
3209         rtl_reset_packet_filter(tp);
3210         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3211
3212         rtl_disable_rxdvgate(tp);
3213
3214         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3215         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3216
3217         rtl8168_config_eee_mac(tp);
3218
3219         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3220         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3221
3222         rtl_pcie_state_l2l3_disable(tp);
3223 }
3224
3225 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3226 {
3227         static const struct ephy_info e_info_8168g_1[] = {
3228                 { 0x00, 0x0008, 0x0000 },
3229                 { 0x0c, 0x3ff0, 0x0820 },
3230                 { 0x1e, 0x0000, 0x0001 },
3231                 { 0x19, 0x8000, 0x0000 }
3232         };
3233
3234         rtl_hw_start_8168g(tp);
3235         rtl_ephy_init(tp, e_info_8168g_1);
3236 }
3237
3238 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3239 {
3240         static const struct ephy_info e_info_8168g_2[] = {
3241                 { 0x00, 0x0008, 0x0000 },
3242                 { 0x0c, 0x3ff0, 0x0820 },
3243                 { 0x19, 0xffff, 0x7c00 },
3244                 { 0x1e, 0xffff, 0x20eb },
3245                 { 0x0d, 0xffff, 0x1666 },
3246                 { 0x00, 0xffff, 0x10a3 },
3247                 { 0x06, 0xffff, 0xf050 },
3248                 { 0x04, 0x0000, 0x0010 },
3249                 { 0x1d, 0x4000, 0x0000 },
3250         };
3251
3252         rtl_hw_start_8168g(tp);
3253         rtl_ephy_init(tp, e_info_8168g_2);
3254 }
3255
3256 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3257 {
3258         static const u16 fix_data[] = {
3259 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3260 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3261 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3262 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3263 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3264 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3265 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3266 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3267 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3268 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3269 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3270 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3271 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3272 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3273         };
3274         unsigned long flags;
3275         int i;
3276
3277         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3278         for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3279                 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);
3280         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3281 }
3282
3283 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3284 {
3285         static const struct ephy_info e_info_8411_2[] = {
3286                 { 0x00, 0x0008, 0x0000 },
3287                 { 0x0c, 0x37d0, 0x0820 },
3288                 { 0x1e, 0x0000, 0x0001 },
3289                 { 0x19, 0x8021, 0x0000 },
3290                 { 0x1e, 0x0000, 0x2000 },
3291                 { 0x0d, 0x0100, 0x0200 },
3292                 { 0x00, 0x0000, 0x0080 },
3293                 { 0x06, 0x0000, 0x0010 },
3294                 { 0x04, 0x0000, 0x0010 },
3295                 { 0x1d, 0x0000, 0x4000 },
3296         };
3297
3298         rtl_hw_start_8168g(tp);
3299
3300         rtl_ephy_init(tp, e_info_8411_2);
3301
3302         /* The following Realtek-provided magic fixes an issue with the RX unit
3303          * getting confused after the PHY having been powered-down.
3304          */
3305         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3306         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3307         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3308         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3309         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3310         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3311         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3312         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3313         mdelay(3);
3314         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3315
3316         rtl8411b_fix_phy_down(tp);
3317
3318         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3319
3320         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3321         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3322         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3323         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3324         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3325         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3326         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3327 }
3328
3329 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3330 {
3331         static const struct ephy_info e_info_8168h_1[] = {
3332                 { 0x1e, 0x0800, 0x0001 },
3333                 { 0x1d, 0x0000, 0x0800 },
3334                 { 0x05, 0xffff, 0x2089 },
3335                 { 0x06, 0xffff, 0x5881 },
3336                 { 0x04, 0xffff, 0x854a },
3337                 { 0x01, 0xffff, 0x068b }
3338         };
3339         int rg_saw_cnt;
3340
3341         rtl_ephy_init(tp, e_info_8168h_1);
3342
3343         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3344         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3345
3346         rtl_set_def_aspm_entry_latency(tp);
3347
3348         rtl_reset_packet_filter(tp);
3349
3350         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3351
3352         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3353
3354         rtl_disable_rxdvgate(tp);
3355
3356         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3357         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3358
3359         rtl8168_config_eee_mac(tp);
3360
3361         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3362         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3363
3364         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3365
3366         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3367
3368         rtl_pcie_state_l2l3_disable(tp);
3369
3370         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3371         if (rg_saw_cnt > 0) {
3372                 u16 sw_cnt_1ms_ini;
3373
3374                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3375                 sw_cnt_1ms_ini &= 0x0fff;
3376                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3377         }
3378
3379         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3380         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3381         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3382         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3383
3384         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3385         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3386         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3387         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3388 }
3389
3390 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3391 {
3392         rtl8168ep_stop_cmac(tp);
3393
3394         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3395         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3396
3397         rtl_set_def_aspm_entry_latency(tp);
3398
3399         rtl_reset_packet_filter(tp);
3400
3401         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3402
3403         rtl_disable_rxdvgate(tp);
3404
3405         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3406         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3407
3408         rtl8168_config_eee_mac(tp);
3409
3410         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3411
3412         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3413
3414         rtl_pcie_state_l2l3_disable(tp);
3415 }
3416
3417 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3418 {
3419         static const struct ephy_info e_info_8168ep_3[] = {
3420                 { 0x00, 0x0000, 0x0080 },
3421                 { 0x0d, 0x0100, 0x0200 },
3422                 { 0x19, 0x8021, 0x0000 },
3423                 { 0x1e, 0x0000, 0x2000 },
3424         };
3425
3426         rtl_ephy_init(tp, e_info_8168ep_3);
3427
3428         rtl_hw_start_8168ep(tp);
3429
3430         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3431         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3432
3433         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3434         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3435         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3436 }
3437
3438 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3439 {
3440         static const struct ephy_info e_info_8117[] = {
3441                 { 0x19, 0x0040, 0x1100 },
3442                 { 0x59, 0x0040, 0x1100 },
3443         };
3444         int rg_saw_cnt;
3445
3446         rtl8168ep_stop_cmac(tp);
3447         rtl_ephy_init(tp, e_info_8117);
3448
3449         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3450         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3451
3452         rtl_set_def_aspm_entry_latency(tp);
3453
3454         rtl_reset_packet_filter(tp);
3455
3456         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3457
3458         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3459
3460         rtl_disable_rxdvgate(tp);
3461
3462         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3463         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3464
3465         rtl8168_config_eee_mac(tp);
3466
3467         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3468         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3469
3470         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3471
3472         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3473
3474         rtl_pcie_state_l2l3_disable(tp);
3475
3476         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3477         if (rg_saw_cnt > 0) {
3478                 u16 sw_cnt_1ms_ini;
3479
3480                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3481                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3482         }
3483
3484         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3485         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3486         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3487         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3488
3489         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3490         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3491         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3492         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3493
3494         /* firmware is for MAC only */
3495         r8169_apply_firmware(tp);
3496 }
3497
3498 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3499 {
3500         static const struct ephy_info e_info_8102e_1[] = {
3501                 { 0x01, 0, 0x6e65 },
3502                 { 0x02, 0, 0x091f },
3503                 { 0x03, 0, 0xc2f9 },
3504                 { 0x06, 0, 0xafb5 },
3505                 { 0x07, 0, 0x0e00 },
3506                 { 0x19, 0, 0xec80 },
3507                 { 0x01, 0, 0x2e65 },
3508                 { 0x01, 0, 0x6e65 }
3509         };
3510         u8 cfg1;
3511
3512         rtl_set_def_aspm_entry_latency(tp);
3513
3514         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3515
3516         RTL_W8(tp, Config1,
3517                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3518         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3519
3520         cfg1 = RTL_R8(tp, Config1);
3521         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3522                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3523
3524         rtl_ephy_init(tp, e_info_8102e_1);
3525 }
3526
3527 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3528 {
3529         rtl_set_def_aspm_entry_latency(tp);
3530
3531         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3532         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3533 }
3534
3535 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3536 {
3537         rtl_hw_start_8102e_2(tp);
3538
3539         rtl_ephy_write(tp, 0x03, 0xc2f9);
3540 }
3541
3542 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3543 {
3544         static const struct ephy_info e_info_8401[] = {
3545                 { 0x01, 0xffff, 0x6fe5 },
3546                 { 0x03, 0xffff, 0x0599 },
3547                 { 0x06, 0xffff, 0xaf25 },
3548                 { 0x07, 0xffff, 0x8e68 },
3549         };
3550
3551         rtl_ephy_init(tp, e_info_8401);
3552         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3553 }
3554
3555 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3556 {
3557         static const struct ephy_info e_info_8105e_1[] = {
3558                 { 0x07, 0, 0x4000 },
3559                 { 0x19, 0, 0x0200 },
3560                 { 0x19, 0, 0x0020 },
3561                 { 0x1e, 0, 0x2000 },
3562                 { 0x03, 0, 0x0001 },
3563                 { 0x19, 0, 0x0100 },
3564                 { 0x19, 0, 0x0004 },
3565                 { 0x0a, 0, 0x0020 }
3566         };
3567
3568         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3569         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3570
3571         /* Disable Early Tally Counter */
3572         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3573
3574         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3575         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3576
3577         rtl_ephy_init(tp, e_info_8105e_1);
3578
3579         rtl_pcie_state_l2l3_disable(tp);
3580 }
3581
3582 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3583 {
3584         rtl_hw_start_8105e_1(tp);
3585         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3586 }
3587
3588 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3589 {
3590         static const struct ephy_info e_info_8402[] = {
3591                 { 0x19, 0xffff, 0xff64 },
3592                 { 0x1e, 0, 0x4000 }
3593         };
3594
3595         rtl_set_def_aspm_entry_latency(tp);
3596
3597         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3598         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3599
3600         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3601
3602         rtl_ephy_init(tp, e_info_8402);
3603
3604         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3605         rtl_reset_packet_filter(tp);
3606         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3607         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3608         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3609
3610         /* disable EEE */
3611         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3612
3613         rtl_pcie_state_l2l3_disable(tp);
3614 }
3615
3616 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3617 {
3618         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3619         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3620
3621         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3622         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3623         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3624
3625         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3626         rtl_set_aspm_entry_latency(tp, 0x2f);
3627
3628         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3629
3630         /* disable EEE */
3631         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3632
3633         rtl_pcie_state_l2l3_disable(tp);
3634 }
3635
3636 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3637 {
3638         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3639 }
3640
3641 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3642 {
3643         rtl_pcie_state_l2l3_disable(tp);
3644
3645         RTL_W16(tp, 0x382, 0x221b);
3646         RTL_W8(tp, 0x4500, 0);
3647         RTL_W16(tp, 0x4800, 0);
3648
3649         /* disable UPS */
3650         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3651
3652         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3653
3654         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3655         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3656
3657         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3658         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3659         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3660
3661         /* disable new tx descriptor format */
3662         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3663
3664         if (tp->mac_version == RTL_GIGA_MAC_VER_65)
3665                 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3666
3667         if (tp->mac_version == RTL_GIGA_MAC_VER_65)
3668                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3669         else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3670                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3671         else
3672                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
3673
3674         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3675                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3676         else
3677                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3678
3679         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3680         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3681         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3682         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3683         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3684         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3685         if (tp->mac_version == RTL_GIGA_MAC_VER_65)
3686                 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
3687         else
3688                 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3689         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3690         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3691         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3692
3693         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3694         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3695         udelay(1);
3696         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3697         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3698
3699         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3700
3701         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3702
3703         if (tp->mac_version == RTL_GIGA_MAC_VER_61)
3704                 rtl8125a_config_eee_mac(tp);
3705         else
3706                 rtl8125b_config_eee_mac(tp);
3707
3708         rtl_disable_rxdvgate(tp);
3709 }
3710
3711 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3712 {
3713         static const struct ephy_info e_info_8125a_2[] = {
3714                 { 0x04, 0xffff, 0xd000 },
3715                 { 0x0a, 0xffff, 0x8653 },
3716                 { 0x23, 0xffff, 0xab66 },
3717                 { 0x20, 0xffff, 0x9455 },
3718                 { 0x21, 0xffff, 0x99ff },
3719                 { 0x29, 0xffff, 0xfe04 },
3720
3721                 { 0x44, 0xffff, 0xd000 },
3722                 { 0x4a, 0xffff, 0x8653 },
3723                 { 0x63, 0xffff, 0xab66 },
3724                 { 0x60, 0xffff, 0x9455 },
3725                 { 0x61, 0xffff, 0x99ff },
3726                 { 0x69, 0xffff, 0xfe04 },
3727         };
3728
3729         rtl_set_def_aspm_entry_latency(tp);
3730         rtl_ephy_init(tp, e_info_8125a_2);
3731         rtl_hw_start_8125_common(tp);
3732 }
3733
3734 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3735 {
3736         static const struct ephy_info e_info_8125b[] = {
3737                 { 0x0b, 0xffff, 0xa908 },
3738                 { 0x1e, 0xffff, 0x20eb },
3739                 { 0x4b, 0xffff, 0xa908 },
3740                 { 0x5e, 0xffff, 0x20eb },
3741                 { 0x22, 0x0030, 0x0020 },
3742                 { 0x62, 0x0030, 0x0020 },
3743         };
3744
3745         rtl_set_def_aspm_entry_latency(tp);
3746         rtl_ephy_init(tp, e_info_8125b);
3747         rtl_hw_start_8125_common(tp);
3748 }
3749
3750 static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3751 {
3752         rtl_set_def_aspm_entry_latency(tp);
3753         rtl_hw_start_8125_common(tp);
3754 }
3755
3756 static void rtl_hw_config(struct rtl8169_private *tp)
3757 {
3758         static const rtl_generic_fct hw_configs[] = {
3759                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3760                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3761                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3762                 [RTL_GIGA_MAC_VER_10] = NULL,
3763                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3764                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3765                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3766                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3767                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3768                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3769                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3770                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3771                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3772                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3773                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3774                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3775                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3776                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3777                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3778                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3779                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3780                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3781                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3782                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3783                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3784                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3785                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3786                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3787                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3788                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3789                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3790                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3791                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3792                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3793                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3794                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3795                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3796                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3797                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3798                 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
3799         };
3800
3801         if (hw_configs[tp->mac_version])
3802                 hw_configs[tp->mac_version](tp);
3803 }
3804
3805 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3806 {
3807         int i;
3808
3809         RTL_W8(tp, INT_CFG0_8125, 0x00);
3810
3811         /* disable interrupt coalescing */
3812         switch (tp->mac_version) {
3813         case RTL_GIGA_MAC_VER_61:
3814                 for (i = 0xa00; i < 0xb00; i += 4)
3815                         RTL_W32(tp, i, 0);
3816                 break;
3817         case RTL_GIGA_MAC_VER_63:
3818         case RTL_GIGA_MAC_VER_65:
3819                 for (i = 0xa00; i < 0xa80; i += 4)
3820                         RTL_W32(tp, i, 0);
3821                 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3822                 break;
3823         default:
3824                 break;
3825         }
3826
3827         rtl_hw_config(tp);
3828 }
3829
3830 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3831 {
3832         if (rtl_is_8168evl_up(tp))
3833                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3834         else
3835                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3836
3837         rtl_hw_config(tp);
3838
3839         /* disable interrupt coalescing */
3840         RTL_W16(tp, IntrMitigate, 0x0000);
3841 }
3842
3843 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3844 {
3845         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3846
3847         tp->cp_cmd |= PCIMulRW;
3848
3849         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3850             tp->mac_version == RTL_GIGA_MAC_VER_03)
3851                 tp->cp_cmd |= EnAnaPLL;
3852
3853         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3854
3855         rtl8169_set_magic_reg(tp);
3856
3857         /* disable interrupt coalescing */
3858         RTL_W16(tp, IntrMitigate, 0x0000);
3859 }
3860
3861 static void rtl_hw_start(struct  rtl8169_private *tp)
3862 {
3863         rtl_unlock_config_regs(tp);
3864         /* disable aspm and clock request before ephy access */
3865         rtl_hw_aspm_clkreq_enable(tp, false);
3866         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3867
3868         rtl_set_eee_txidle_timer(tp);
3869
3870         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3871                 rtl_hw_start_8169(tp);
3872         else if (rtl_is_8125(tp))
3873                 rtl_hw_start_8125(tp);
3874         else
3875                 rtl_hw_start_8168(tp);
3876
3877         rtl_enable_exit_l1(tp);
3878         rtl_hw_aspm_clkreq_enable(tp, true);
3879         rtl_set_rx_max_size(tp);
3880         rtl_set_rx_tx_desc_registers(tp);
3881         rtl_lock_config_regs(tp);
3882
3883         rtl_jumbo_config(tp);
3884
3885         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3886         rtl_pci_commit(tp);
3887
3888         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3889         rtl_init_rxcfg(tp);
3890         rtl_set_tx_config_registers(tp);
3891         rtl_set_rx_config_features(tp, tp->dev->features);
3892         rtl_set_rx_mode(tp->dev);
3893         rtl_irq_enable(tp);
3894 }
3895
3896 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3897 {
3898         struct rtl8169_private *tp = netdev_priv(dev);
3899
3900         dev->mtu = new_mtu;
3901         netdev_update_features(dev);
3902         rtl_jumbo_config(tp);
3903         rtl_set_eee_txidle_timer(tp);
3904
3905         return 0;
3906 }
3907
3908 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3909 {
3910         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3911
3912         desc->opts2 = 0;
3913         /* Force memory writes to complete before releasing descriptor */
3914         dma_wmb();
3915         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3916 }
3917
3918 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3919                                           struct RxDesc *desc)
3920 {
3921         struct device *d = tp_to_dev(tp);
3922         int node = dev_to_node(d);
3923         dma_addr_t mapping;
3924         struct page *data;
3925
3926         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3927         if (!data)
3928                 return NULL;
3929
3930         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3931         if (unlikely(dma_mapping_error(d, mapping))) {
3932                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3933                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3934                 return NULL;
3935         }
3936
3937         desc->addr = cpu_to_le64(mapping);
3938         rtl8169_mark_to_asic(desc);
3939
3940         return data;
3941 }
3942
3943 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3944 {
3945         int i;
3946
3947         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3948                 dma_unmap_page(tp_to_dev(tp),
3949                                le64_to_cpu(tp->RxDescArray[i].addr),
3950                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3951                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3952                 tp->Rx_databuff[i] = NULL;
3953                 tp->RxDescArray[i].addr = 0;
3954                 tp->RxDescArray[i].opts1 = 0;
3955         }
3956 }
3957
3958 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3959 {
3960         int i;
3961
3962         for (i = 0; i < NUM_RX_DESC; i++) {
3963                 struct page *data;
3964
3965                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3966                 if (!data) {
3967                         rtl8169_rx_clear(tp);
3968                         return -ENOMEM;
3969                 }
3970                 tp->Rx_databuff[i] = data;
3971         }
3972
3973         /* mark as last descriptor in the ring */
3974         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3975
3976         return 0;
3977 }
3978
3979 static int rtl8169_init_ring(struct rtl8169_private *tp)
3980 {
3981         rtl8169_init_ring_indexes(tp);
3982
3983         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3984         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3985
3986         return rtl8169_rx_fill(tp);
3987 }
3988
3989 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3990 {
3991         struct ring_info *tx_skb = tp->tx_skb + entry;
3992         struct TxDesc *desc = tp->TxDescArray + entry;
3993
3994         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3995                          DMA_TO_DEVICE);
3996         memset(desc, 0, sizeof(*desc));
3997         memset(tx_skb, 0, sizeof(*tx_skb));
3998 }
3999
4000 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4001                                    unsigned int n)
4002 {
4003         unsigned int i;
4004
4005         for (i = 0; i < n; i++) {
4006                 unsigned int entry = (start + i) % NUM_TX_DESC;
4007                 struct ring_info *tx_skb = tp->tx_skb + entry;
4008                 unsigned int len = tx_skb->len;
4009
4010                 if (len) {
4011                         struct sk_buff *skb = tx_skb->skb;
4012
4013                         rtl8169_unmap_tx_skb(tp, entry);
4014                         if (skb)
4015                                 dev_consume_skb_any(skb);
4016                 }
4017         }
4018 }
4019
4020 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4021 {
4022         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4023         netdev_reset_queue(tp->dev);
4024 }
4025
4026 static void rtl8169_cleanup(struct rtl8169_private *tp)
4027 {
4028         napi_disable(&tp->napi);
4029
4030         /* Give a racing hard_start_xmit a few cycles to complete. */
4031         synchronize_net();
4032
4033         /* Disable interrupts */
4034         rtl8169_irq_mask_and_ack(tp);
4035
4036         rtl_rx_close(tp);
4037
4038         switch (tp->mac_version) {
4039         case RTL_GIGA_MAC_VER_28:
4040         case RTL_GIGA_MAC_VER_31:
4041                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
4042                 break;
4043         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4044                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4045                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4046                 break;
4047         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
4048                 rtl_enable_rxdvgate(tp);
4049                 fsleep(2000);
4050                 break;
4051         default:
4052                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4053                 fsleep(100);
4054                 break;
4055         }
4056
4057         rtl_hw_reset(tp);
4058
4059         rtl8169_tx_clear(tp);
4060         rtl8169_init_ring_indexes(tp);
4061 }
4062
4063 static void rtl_reset_work(struct rtl8169_private *tp)
4064 {
4065         int i;
4066
4067         netif_stop_queue(tp->dev);
4068
4069         rtl8169_cleanup(tp);
4070
4071         for (i = 0; i < NUM_RX_DESC; i++)
4072                 rtl8169_mark_to_asic(tp->RxDescArray + i);
4073
4074         napi_enable(&tp->napi);
4075         rtl_hw_start(tp);
4076 }
4077
4078 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4079 {
4080         struct rtl8169_private *tp = netdev_priv(dev);
4081
4082         rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4083 }
4084
4085 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4086                           void *addr, unsigned int entry, bool desc_own)
4087 {
4088         struct TxDesc *txd = tp->TxDescArray + entry;
4089         struct device *d = tp_to_dev(tp);
4090         dma_addr_t mapping;
4091         u32 opts1;
4092         int ret;
4093
4094         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4095         ret = dma_mapping_error(d, mapping);
4096         if (unlikely(ret)) {
4097                 if (net_ratelimit())
4098                         netdev_err(tp->dev, "Failed to map TX data!\n");
4099                 return ret;
4100         }
4101
4102         txd->addr = cpu_to_le64(mapping);
4103         txd->opts2 = cpu_to_le32(opts[1]);
4104
4105         opts1 = opts[0] | len;
4106         if (entry == NUM_TX_DESC - 1)
4107                 opts1 |= RingEnd;
4108         if (desc_own)
4109                 opts1 |= DescOwn;
4110         txd->opts1 = cpu_to_le32(opts1);
4111
4112         tp->tx_skb[entry].len = len;
4113
4114         return 0;
4115 }
4116
4117 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4118                               const u32 *opts, unsigned int entry)
4119 {
4120         struct skb_shared_info *info = skb_shinfo(skb);
4121         unsigned int cur_frag;
4122
4123         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4124                 const skb_frag_t *frag = info->frags + cur_frag;
4125                 void *addr = skb_frag_address(frag);
4126                 u32 len = skb_frag_size(frag);
4127
4128                 entry = (entry + 1) % NUM_TX_DESC;
4129
4130                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4131                         goto err_out;
4132         }
4133
4134         return 0;
4135
4136 err_out:
4137         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4138         return -EIO;
4139 }
4140
4141 static bool rtl_skb_is_udp(struct sk_buff *skb)
4142 {
4143         int no = skb_network_offset(skb);
4144         struct ipv6hdr *i6h, _i6h;
4145         struct iphdr *ih, _ih;
4146
4147         switch (vlan_get_protocol(skb)) {
4148         case htons(ETH_P_IP):
4149                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4150                 return ih && ih->protocol == IPPROTO_UDP;
4151         case htons(ETH_P_IPV6):
4152                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4153                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4154         default:
4155                 return false;
4156         }
4157 }
4158
4159 #define RTL_MIN_PATCH_LEN       47
4160
4161 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4162 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4163                                             struct sk_buff *skb)
4164 {
4165         unsigned int padto = 0, len = skb->len;
4166
4167         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4168             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4169                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4170                                               skb_transport_header(skb);
4171
4172                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4173                     trans_data_len < RTL_MIN_PATCH_LEN) {
4174                         u16 dest = ntohs(udp_hdr(skb)->dest);
4175
4176                         /* dest is a standard PTP port */
4177                         if (dest == 319 || dest == 320)
4178                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4179                 }
4180
4181                 if (trans_data_len < sizeof(struct udphdr))
4182                         padto = max_t(unsigned int, padto,
4183                                       len + sizeof(struct udphdr) - trans_data_len);
4184         }
4185
4186         return padto;
4187 }
4188
4189 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4190                                            struct sk_buff *skb)
4191 {
4192         unsigned int padto;
4193
4194         padto = rtl8125_quirk_udp_padto(tp, skb);
4195
4196         switch (tp->mac_version) {
4197         case RTL_GIGA_MAC_VER_34:
4198         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
4199                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4200                 break;
4201         default:
4202                 break;
4203         }
4204
4205         return padto;
4206 }
4207
4208 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4209 {
4210         u32 mss = skb_shinfo(skb)->gso_size;
4211
4212         if (mss) {
4213                 opts[0] |= TD_LSO;
4214                 opts[0] |= mss << TD0_MSS_SHIFT;
4215         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4216                 const struct iphdr *ip = ip_hdr(skb);
4217
4218                 if (ip->protocol == IPPROTO_TCP)
4219                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4220                 else if (ip->protocol == IPPROTO_UDP)
4221                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4222                 else
4223                         WARN_ON_ONCE(1);
4224         }
4225 }
4226
4227 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4228                                 struct sk_buff *skb, u32 *opts)
4229 {
4230         struct skb_shared_info *shinfo = skb_shinfo(skb);
4231         u32 mss = shinfo->gso_size;
4232
4233         if (mss) {
4234                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4235                         opts[0] |= TD1_GTSENV4;
4236                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4237                         if (skb_cow_head(skb, 0))
4238                                 return false;
4239
4240                         tcp_v6_gso_csum_prep(skb);
4241                         opts[0] |= TD1_GTSENV6;
4242                 } else {
4243                         WARN_ON_ONCE(1);
4244                 }
4245
4246                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4247                 opts[1] |= mss << TD1_MSS_SHIFT;
4248         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4249                 u8 ip_protocol;
4250
4251                 switch (vlan_get_protocol(skb)) {
4252                 case htons(ETH_P_IP):
4253                         opts[1] |= TD1_IPv4_CS;
4254                         ip_protocol = ip_hdr(skb)->protocol;
4255                         break;
4256
4257                 case htons(ETH_P_IPV6):
4258                         opts[1] |= TD1_IPv6_CS;
4259                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4260                         break;
4261
4262                 default:
4263                         ip_protocol = IPPROTO_RAW;
4264                         break;
4265                 }
4266
4267                 if (ip_protocol == IPPROTO_TCP)
4268                         opts[1] |= TD1_TCP_CS;
4269                 else if (ip_protocol == IPPROTO_UDP)
4270                         opts[1] |= TD1_UDP_CS;
4271                 else
4272                         WARN_ON_ONCE(1);
4273
4274                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4275         } else {
4276                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4277
4278                 /* skb_padto would free the skb on error */
4279                 return !__skb_put_padto(skb, padto, false);
4280         }
4281
4282         return true;
4283 }
4284
4285 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4286 {
4287         return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4288 }
4289
4290 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4291 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4292 {
4293         switch (tp->mac_version) {
4294         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4295         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4296                 return false;
4297         default:
4298                 return true;
4299         }
4300 }
4301
4302 static void rtl8169_doorbell(struct rtl8169_private *tp)
4303 {
4304         if (rtl_is_8125(tp))
4305                 RTL_W16(tp, TxPoll_8125, BIT(0));
4306         else
4307                 RTL_W8(tp, TxPoll, NPQ);
4308 }
4309
4310 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4311                                       struct net_device *dev)
4312 {
4313         unsigned int frags = skb_shinfo(skb)->nr_frags;
4314         struct rtl8169_private *tp = netdev_priv(dev);
4315         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4316         struct TxDesc *txd_first, *txd_last;
4317         bool stop_queue, door_bell;
4318         u32 opts[2];
4319
4320         if (unlikely(!rtl_tx_slots_avail(tp))) {
4321                 if (net_ratelimit())
4322                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4323                 goto err_stop_0;
4324         }
4325
4326         opts[1] = rtl8169_tx_vlan_tag(skb);
4327         opts[0] = 0;
4328
4329         if (!rtl_chip_supports_csum_v2(tp))
4330                 rtl8169_tso_csum_v1(skb, opts);
4331         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4332                 goto err_dma_0;
4333
4334         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4335                                     entry, false)))
4336                 goto err_dma_0;
4337
4338         txd_first = tp->TxDescArray + entry;
4339
4340         if (frags) {
4341                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4342                         goto err_dma_1;
4343                 entry = (entry + frags) % NUM_TX_DESC;
4344         }
4345
4346         txd_last = tp->TxDescArray + entry;
4347         txd_last->opts1 |= cpu_to_le32(LastFrag);
4348         tp->tx_skb[entry].skb = skb;
4349
4350         skb_tx_timestamp(skb);
4351
4352         /* Force memory writes to complete before releasing descriptor */
4353         dma_wmb();
4354
4355         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4356
4357         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4358
4359         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4360         smp_wmb();
4361
4362         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4363
4364         stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4365                                                 R8169_TX_STOP_THRS,
4366                                                 R8169_TX_START_THRS);
4367         if (door_bell || stop_queue)
4368                 rtl8169_doorbell(tp);
4369
4370         return NETDEV_TX_OK;
4371
4372 err_dma_1:
4373         rtl8169_unmap_tx_skb(tp, entry);
4374 err_dma_0:
4375         dev_kfree_skb_any(skb);
4376         dev->stats.tx_dropped++;
4377         return NETDEV_TX_OK;
4378
4379 err_stop_0:
4380         netif_stop_queue(dev);
4381         dev->stats.tx_dropped++;
4382         return NETDEV_TX_BUSY;
4383 }
4384
4385 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4386 {
4387         struct skb_shared_info *info = skb_shinfo(skb);
4388         unsigned int nr_frags = info->nr_frags;
4389
4390         if (!nr_frags)
4391                 return UINT_MAX;
4392
4393         return skb_frag_size(info->frags + nr_frags - 1);
4394 }
4395
4396 /* Workaround for hw issues with TSO on RTL8168evl */
4397 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4398                                             netdev_features_t features)
4399 {
4400         /* IPv4 header has options field */
4401         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4402             ip_hdrlen(skb) > sizeof(struct iphdr))
4403                 features &= ~NETIF_F_ALL_TSO;
4404
4405         /* IPv4 TCP header has options field */
4406         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4407                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4408                 features &= ~NETIF_F_ALL_TSO;
4409
4410         else if (rtl_last_frag_len(skb) <= 6)
4411                 features &= ~NETIF_F_ALL_TSO;
4412
4413         return features;
4414 }
4415
4416 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4417                                                 struct net_device *dev,
4418                                                 netdev_features_t features)
4419 {
4420         struct rtl8169_private *tp = netdev_priv(dev);
4421
4422         if (skb_is_gso(skb)) {
4423                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4424                         features = rtl8168evl_fix_tso(skb, features);
4425
4426                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4427                     rtl_chip_supports_csum_v2(tp))
4428                         features &= ~NETIF_F_ALL_TSO;
4429         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4430                 /* work around hw bug on some chip versions */
4431                 if (skb->len < ETH_ZLEN)
4432                         features &= ~NETIF_F_CSUM_MASK;
4433
4434                 if (rtl_quirk_packet_padto(tp, skb))
4435                         features &= ~NETIF_F_CSUM_MASK;
4436
4437                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4438                     rtl_chip_supports_csum_v2(tp))
4439                         features &= ~NETIF_F_CSUM_MASK;
4440         }
4441
4442         return vlan_features_check(skb, features);
4443 }
4444
4445 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4446 {
4447         struct rtl8169_private *tp = netdev_priv(dev);
4448         struct pci_dev *pdev = tp->pci_dev;
4449         int pci_status_errs;
4450         u16 pci_cmd;
4451
4452         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4453
4454         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4455
4456         if (net_ratelimit())
4457                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4458                            pci_cmd, pci_status_errs);
4459
4460         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4461 }
4462
4463 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4464                    int budget)
4465 {
4466         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4467         struct sk_buff *skb;
4468
4469         dirty_tx = tp->dirty_tx;
4470
4471         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4472                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4473                 u32 status;
4474
4475                 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4476                 if (status & DescOwn)
4477                         break;
4478
4479                 skb = tp->tx_skb[entry].skb;
4480                 rtl8169_unmap_tx_skb(tp, entry);
4481
4482                 if (skb) {
4483                         pkts_compl++;
4484                         bytes_compl += skb->len;
4485                         napi_consume_skb(skb, budget);
4486                 }
4487                 dirty_tx++;
4488         }
4489
4490         if (tp->dirty_tx != dirty_tx) {
4491                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4492                 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4493
4494                 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4495                                               rtl_tx_slots_avail(tp),
4496                                               R8169_TX_START_THRS);
4497                 /*
4498                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4499                  * too close. Let's kick an extra TxPoll request when a burst
4500                  * of start_xmit activity is detected (if it is not detected,
4501                  * it is slow enough). -- FR
4502                  * If skb is NULL then we come here again once a tx irq is
4503                  * triggered after the last fragment is marked transmitted.
4504                  */
4505                 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4506                         rtl8169_doorbell(tp);
4507         }
4508 }
4509
4510 static inline int rtl8169_fragmented_frame(u32 status)
4511 {
4512         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4513 }
4514
4515 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4516 {
4517         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4518
4519         if (status == RxProtoTCP || status == RxProtoUDP)
4520                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4521         else
4522                 skb_checksum_none_assert(skb);
4523 }
4524
4525 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4526 {
4527         struct device *d = tp_to_dev(tp);
4528         int count;
4529
4530         for (count = 0; count < budget; count++, tp->cur_rx++) {
4531                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4532                 struct RxDesc *desc = tp->RxDescArray + entry;
4533                 struct sk_buff *skb;
4534                 const void *rx_buf;
4535                 dma_addr_t addr;
4536                 u32 status;
4537
4538                 status = le32_to_cpu(READ_ONCE(desc->opts1));
4539                 if (status & DescOwn)
4540                         break;
4541
4542                 /* This barrier is needed to keep us from reading
4543                  * any other fields out of the Rx descriptor until
4544                  * we know the status of DescOwn
4545                  */
4546                 dma_rmb();
4547
4548                 if (unlikely(status & RxRES)) {
4549                         if (net_ratelimit())
4550                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4551                                             status);
4552                         dev->stats.rx_errors++;
4553                         if (status & (RxRWT | RxRUNT))
4554                                 dev->stats.rx_length_errors++;
4555                         if (status & RxCRC)
4556                                 dev->stats.rx_crc_errors++;
4557
4558                         if (!(dev->features & NETIF_F_RXALL))
4559                                 goto release_descriptor;
4560                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4561                                 goto release_descriptor;
4562                 }
4563
4564                 pkt_size = status & GENMASK(13, 0);
4565                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4566                         pkt_size -= ETH_FCS_LEN;
4567
4568                 /* The driver does not support incoming fragmented frames.
4569                  * They are seen as a symptom of over-mtu sized frames.
4570                  */
4571                 if (unlikely(rtl8169_fragmented_frame(status))) {
4572                         dev->stats.rx_dropped++;
4573                         dev->stats.rx_length_errors++;
4574                         goto release_descriptor;
4575                 }
4576
4577                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4578                 if (unlikely(!skb)) {
4579                         dev->stats.rx_dropped++;
4580                         goto release_descriptor;
4581                 }
4582
4583                 addr = le64_to_cpu(desc->addr);
4584                 rx_buf = page_address(tp->Rx_databuff[entry]);
4585
4586                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4587                 prefetch(rx_buf);
4588                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4589                 skb->tail += pkt_size;
4590                 skb->len = pkt_size;
4591                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4592
4593                 rtl8169_rx_csum(skb, status);
4594                 skb->protocol = eth_type_trans(skb, dev);
4595
4596                 rtl8169_rx_vlan_tag(desc, skb);
4597
4598                 if (skb->pkt_type == PACKET_MULTICAST)
4599                         dev->stats.multicast++;
4600
4601                 napi_gro_receive(&tp->napi, skb);
4602
4603                 dev_sw_netstats_rx_add(dev, pkt_size);
4604 release_descriptor:
4605                 rtl8169_mark_to_asic(desc);
4606         }
4607
4608         return count;
4609 }
4610
4611 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4612 {
4613         struct rtl8169_private *tp = dev_instance;
4614         u32 status = rtl_get_events(tp);
4615
4616         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4617                 return IRQ_NONE;
4618
4619         if (unlikely(status & SYSErr)) {
4620                 rtl8169_pcierr_interrupt(tp->dev);
4621                 goto out;
4622         }
4623
4624         if (status & LinkChg)
4625                 phy_mac_interrupt(tp->phydev);
4626
4627         if (unlikely(status & RxFIFOOver &&
4628             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4629                 netif_stop_queue(tp->dev);
4630                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4631         }
4632
4633         if (napi_schedule_prep(&tp->napi)) {
4634                 rtl_irq_disable(tp);
4635                 __napi_schedule(&tp->napi);
4636         }
4637 out:
4638         rtl_ack_events(tp, status);
4639
4640         return IRQ_HANDLED;
4641 }
4642
4643 static void rtl_task(struct work_struct *work)
4644 {
4645         struct rtl8169_private *tp =
4646                 container_of(work, struct rtl8169_private, wk.work);
4647         int ret;
4648
4649         rtnl_lock();
4650
4651         if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4652                 goto out_unlock;
4653
4654         if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4655                 /* if chip isn't accessible, reset bus to revive it */
4656                 if (RTL_R32(tp, TxConfig) == ~0) {
4657                         ret = pci_reset_bus(tp->pci_dev);
4658                         if (ret < 0) {
4659                                 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4660                                 netif_device_detach(tp->dev);
4661                                 goto out_unlock;
4662                         }
4663                 }
4664
4665                 /* ASPM compatibility issues are a typical reason for tx timeouts */
4666                 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4667                                                           PCIE_LINK_STATE_L0S);
4668                 if (!ret)
4669                         netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4670                 goto reset;
4671         }
4672
4673         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4674 reset:
4675                 rtl_reset_work(tp);
4676                 netif_wake_queue(tp->dev);
4677         } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4678                 rtl_reset_work(tp);
4679         }
4680 out_unlock:
4681         rtnl_unlock();
4682 }
4683
4684 static int rtl8169_poll(struct napi_struct *napi, int budget)
4685 {
4686         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4687         struct net_device *dev = tp->dev;
4688         int work_done;
4689
4690         rtl_tx(dev, tp, budget);
4691
4692         work_done = rtl_rx(dev, tp, budget);
4693
4694         if (work_done < budget && napi_complete_done(napi, work_done))
4695                 rtl_irq_enable(tp);
4696
4697         return work_done;
4698 }
4699
4700 static void r8169_phylink_handler(struct net_device *ndev)
4701 {
4702         struct rtl8169_private *tp = netdev_priv(ndev);
4703         struct device *d = tp_to_dev(tp);
4704
4705         if (netif_carrier_ok(ndev)) {
4706                 rtl_link_chg_patch(tp);
4707                 pm_request_resume(d);
4708                 netif_wake_queue(tp->dev);
4709         } else {
4710                 /* In few cases rx is broken after link-down otherwise */
4711                 if (rtl_is_8125(tp))
4712                         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4713                 pm_runtime_idle(d);
4714         }
4715
4716         phy_print_status(tp->phydev);
4717 }
4718
4719 static int r8169_phy_connect(struct rtl8169_private *tp)
4720 {
4721         struct phy_device *phydev = tp->phydev;
4722         phy_interface_t phy_mode;
4723         int ret;
4724
4725         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4726                    PHY_INTERFACE_MODE_MII;
4727
4728         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4729                                  phy_mode);
4730         if (ret)
4731                 return ret;
4732
4733         if (!tp->supports_gmii)
4734                 phy_set_max_speed(phydev, SPEED_100);
4735
4736         phy_attached_info(phydev);
4737
4738         return 0;
4739 }
4740
4741 static void rtl8169_down(struct rtl8169_private *tp)
4742 {
4743         /* Clear all task flags */
4744         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4745
4746         phy_stop(tp->phydev);
4747
4748         rtl8169_update_counters(tp);
4749
4750         pci_clear_master(tp->pci_dev);
4751         rtl_pci_commit(tp);
4752
4753         rtl8169_cleanup(tp);
4754         rtl_disable_exit_l1(tp);
4755         rtl_prepare_power_down(tp);
4756
4757         if (tp->dash_type != RTL_DASH_NONE)
4758                 rtl8168_driver_stop(tp);
4759 }
4760
4761 static void rtl8169_up(struct rtl8169_private *tp)
4762 {
4763         if (tp->dash_type != RTL_DASH_NONE)
4764                 rtl8168_driver_start(tp);
4765
4766         pci_set_master(tp->pci_dev);
4767         phy_init_hw(tp->phydev);
4768         phy_resume(tp->phydev);
4769         rtl8169_init_phy(tp);
4770         napi_enable(&tp->napi);
4771         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4772         rtl_reset_work(tp);
4773
4774         phy_start(tp->phydev);
4775 }
4776
4777 static int rtl8169_close(struct net_device *dev)
4778 {
4779         struct rtl8169_private *tp = netdev_priv(dev);
4780         struct pci_dev *pdev = tp->pci_dev;
4781
4782         pm_runtime_get_sync(&pdev->dev);
4783
4784         netif_stop_queue(dev);
4785         rtl8169_down(tp);
4786         rtl8169_rx_clear(tp);
4787
4788         cancel_work(&tp->wk.work);
4789
4790         free_irq(tp->irq, tp);
4791
4792         phy_disconnect(tp->phydev);
4793
4794         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4795                           tp->RxPhyAddr);
4796         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4797                           tp->TxPhyAddr);
4798         tp->TxDescArray = NULL;
4799         tp->RxDescArray = NULL;
4800
4801         pm_runtime_put_sync(&pdev->dev);
4802
4803         return 0;
4804 }
4805
4806 #ifdef CONFIG_NET_POLL_CONTROLLER
4807 static void rtl8169_netpoll(struct net_device *dev)
4808 {
4809         struct rtl8169_private *tp = netdev_priv(dev);
4810
4811         rtl8169_interrupt(tp->irq, tp);
4812 }
4813 #endif
4814
4815 static int rtl_open(struct net_device *dev)
4816 {
4817         struct rtl8169_private *tp = netdev_priv(dev);
4818         struct pci_dev *pdev = tp->pci_dev;
4819         unsigned long irqflags;
4820         int retval = -ENOMEM;
4821
4822         pm_runtime_get_sync(&pdev->dev);
4823
4824         /*
4825          * Rx and Tx descriptors needs 256 bytes alignment.
4826          * dma_alloc_coherent provides more.
4827          */
4828         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4829                                              &tp->TxPhyAddr, GFP_KERNEL);
4830         if (!tp->TxDescArray)
4831                 goto out;
4832
4833         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4834                                              &tp->RxPhyAddr, GFP_KERNEL);
4835         if (!tp->RxDescArray)
4836                 goto err_free_tx_0;
4837
4838         retval = rtl8169_init_ring(tp);
4839         if (retval < 0)
4840                 goto err_free_rx_1;
4841
4842         rtl_request_firmware(tp);
4843
4844         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4845         retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4846         if (retval < 0)
4847                 goto err_release_fw_2;
4848
4849         retval = r8169_phy_connect(tp);
4850         if (retval)
4851                 goto err_free_irq;
4852
4853         rtl8169_up(tp);
4854         rtl8169_init_counter_offsets(tp);
4855         netif_start_queue(dev);
4856 out:
4857         pm_runtime_put_sync(&pdev->dev);
4858
4859         return retval;
4860
4861 err_free_irq:
4862         free_irq(tp->irq, tp);
4863 err_release_fw_2:
4864         rtl_release_firmware(tp);
4865         rtl8169_rx_clear(tp);
4866 err_free_rx_1:
4867         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4868                           tp->RxPhyAddr);
4869         tp->RxDescArray = NULL;
4870 err_free_tx_0:
4871         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4872                           tp->TxPhyAddr);
4873         tp->TxDescArray = NULL;
4874         goto out;
4875 }
4876
4877 static void
4878 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4879 {
4880         struct rtl8169_private *tp = netdev_priv(dev);
4881         struct pci_dev *pdev = tp->pci_dev;
4882         struct rtl8169_counters *counters = tp->counters;
4883
4884         pm_runtime_get_noresume(&pdev->dev);
4885
4886         netdev_stats_to_stats64(stats, &dev->stats);
4887         dev_fetch_sw_netstats(stats, dev->tstats);
4888
4889         /*
4890          * Fetch additional counter values missing in stats collected by driver
4891          * from tally counters.
4892          */
4893         if (pm_runtime_active(&pdev->dev))
4894                 rtl8169_update_counters(tp);
4895
4896         /*
4897          * Subtract values fetched during initalization.
4898          * See rtl8169_init_counter_offsets for a description why we do that.
4899          */
4900         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4901                 le64_to_cpu(tp->tc_offset.tx_errors);
4902         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4903                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4904         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4905                 le16_to_cpu(tp->tc_offset.tx_aborted);
4906         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4907                 le16_to_cpu(tp->tc_offset.rx_missed);
4908
4909         pm_runtime_put_noidle(&pdev->dev);
4910 }
4911
4912 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4913 {
4914         netif_device_detach(tp->dev);
4915
4916         if (netif_running(tp->dev))
4917                 rtl8169_down(tp);
4918 }
4919
4920 static int rtl8169_runtime_resume(struct device *dev)
4921 {
4922         struct rtl8169_private *tp = dev_get_drvdata(dev);
4923
4924         rtl_rar_set(tp, tp->dev->dev_addr);
4925         __rtl8169_set_wol(tp, tp->saved_wolopts);
4926
4927         if (tp->TxDescArray)
4928                 rtl8169_up(tp);
4929
4930         netif_device_attach(tp->dev);
4931
4932         return 0;
4933 }
4934
4935 static int rtl8169_suspend(struct device *device)
4936 {
4937         struct rtl8169_private *tp = dev_get_drvdata(device);
4938
4939         rtnl_lock();
4940         rtl8169_net_suspend(tp);
4941         if (!device_may_wakeup(tp_to_dev(tp)))
4942                 clk_disable_unprepare(tp->clk);
4943         rtnl_unlock();
4944
4945         return 0;
4946 }
4947
4948 static int rtl8169_resume(struct device *device)
4949 {
4950         struct rtl8169_private *tp = dev_get_drvdata(device);
4951
4952         if (!device_may_wakeup(tp_to_dev(tp)))
4953                 clk_prepare_enable(tp->clk);
4954
4955         /* Reportedly at least Asus X453MA truncates packets otherwise */
4956         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4957                 rtl_init_rxcfg(tp);
4958
4959         return rtl8169_runtime_resume(device);
4960 }
4961
4962 static int rtl8169_runtime_suspend(struct device *device)
4963 {
4964         struct rtl8169_private *tp = dev_get_drvdata(device);
4965
4966         if (!tp->TxDescArray) {
4967                 netif_device_detach(tp->dev);
4968                 return 0;
4969         }
4970
4971         rtnl_lock();
4972         __rtl8169_set_wol(tp, WAKE_PHY);
4973         rtl8169_net_suspend(tp);
4974         rtnl_unlock();
4975
4976         return 0;
4977 }
4978
4979 static int rtl8169_runtime_idle(struct device *device)
4980 {
4981         struct rtl8169_private *tp = dev_get_drvdata(device);
4982
4983         if (tp->dash_enabled)
4984                 return -EBUSY;
4985
4986         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4987                 pm_schedule_suspend(device, 10000);
4988
4989         return -EBUSY;
4990 }
4991
4992 static const struct dev_pm_ops rtl8169_pm_ops = {
4993         SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4994         RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4995                        rtl8169_runtime_idle)
4996 };
4997
4998 static void rtl_shutdown(struct pci_dev *pdev)
4999 {
5000         struct rtl8169_private *tp = pci_get_drvdata(pdev);
5001
5002         rtnl_lock();
5003         rtl8169_net_suspend(tp);
5004         rtnl_unlock();
5005
5006         /* Restore original MAC address */
5007         rtl_rar_set(tp, tp->dev->perm_addr);
5008
5009         if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
5010                 pci_wake_from_d3(pdev, tp->saved_wolopts);
5011                 pci_set_power_state(pdev, PCI_D3hot);
5012         }
5013 }
5014
5015 static void rtl_remove_one(struct pci_dev *pdev)
5016 {
5017         struct rtl8169_private *tp = pci_get_drvdata(pdev);
5018
5019         if (pci_dev_run_wake(pdev))
5020                 pm_runtime_get_noresume(&pdev->dev);
5021
5022         cancel_work_sync(&tp->wk.work);
5023
5024         unregister_netdev(tp->dev);
5025
5026         if (tp->dash_type != RTL_DASH_NONE)
5027                 rtl8168_driver_stop(tp);
5028
5029         rtl_release_firmware(tp);
5030
5031         /* restore original MAC address */
5032         rtl_rar_set(tp, tp->dev->perm_addr);
5033 }
5034
5035 static const struct net_device_ops rtl_netdev_ops = {
5036         .ndo_open               = rtl_open,
5037         .ndo_stop               = rtl8169_close,
5038         .ndo_get_stats64        = rtl8169_get_stats64,
5039         .ndo_start_xmit         = rtl8169_start_xmit,
5040         .ndo_features_check     = rtl8169_features_check,
5041         .ndo_tx_timeout         = rtl8169_tx_timeout,
5042         .ndo_validate_addr      = eth_validate_addr,
5043         .ndo_change_mtu         = rtl8169_change_mtu,
5044         .ndo_fix_features       = rtl8169_fix_features,
5045         .ndo_set_features       = rtl8169_set_features,
5046         .ndo_set_mac_address    = rtl_set_mac_address,
5047         .ndo_eth_ioctl          = phy_do_ioctl_running,
5048         .ndo_set_rx_mode        = rtl_set_rx_mode,
5049 #ifdef CONFIG_NET_POLL_CONTROLLER
5050         .ndo_poll_controller    = rtl8169_netpoll,
5051 #endif
5052
5053 };
5054
5055 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5056 {
5057         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5058
5059         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5060                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5061         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5062                 /* special workaround needed */
5063                 tp->irq_mask |= RxFIFOOver;
5064         else
5065                 tp->irq_mask |= RxOverflow;
5066 }
5067
5068 static int rtl_alloc_irq(struct rtl8169_private *tp)
5069 {
5070         unsigned int flags;
5071
5072         switch (tp->mac_version) {
5073         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5074                 rtl_unlock_config_regs(tp);
5075                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5076                 rtl_lock_config_regs(tp);
5077                 fallthrough;
5078         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5079                 flags = PCI_IRQ_LEGACY;
5080                 break;
5081         default:
5082                 flags = PCI_IRQ_ALL_TYPES;
5083                 break;
5084         }
5085
5086         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5087 }
5088
5089 static void rtl_read_mac_address(struct rtl8169_private *tp,
5090                                  u8 mac_addr[ETH_ALEN])
5091 {
5092         /* Get MAC address */
5093         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5094                 u32 value;
5095
5096                 value = rtl_eri_read(tp, 0xe0);
5097                 put_unaligned_le32(value, mac_addr);
5098                 value = rtl_eri_read(tp, 0xe4);
5099                 put_unaligned_le16(value, mac_addr + 4);
5100         } else if (rtl_is_8125(tp)) {
5101                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5102         }
5103 }
5104
5105 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5106 {
5107         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5108 }
5109
5110 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5111 {
5112         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5113 }
5114
5115 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5116 {
5117         struct rtl8169_private *tp = mii_bus->priv;
5118
5119         if (phyaddr > 0)
5120                 return -ENODEV;
5121
5122         return rtl_readphy(tp, phyreg);
5123 }
5124
5125 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5126                                 int phyreg, u16 val)
5127 {
5128         struct rtl8169_private *tp = mii_bus->priv;
5129
5130         if (phyaddr > 0)
5131                 return -ENODEV;
5132
5133         rtl_writephy(tp, phyreg, val);
5134
5135         return 0;
5136 }
5137
5138 static int r8169_mdio_register(struct rtl8169_private *tp)
5139 {
5140         struct pci_dev *pdev = tp->pci_dev;
5141         struct mii_bus *new_bus;
5142         int ret;
5143
5144         new_bus = devm_mdiobus_alloc(&pdev->dev);
5145         if (!new_bus)
5146                 return -ENOMEM;
5147
5148         new_bus->name = "r8169";
5149         new_bus->priv = tp;
5150         new_bus->parent = &pdev->dev;
5151         new_bus->irq[0] = PHY_MAC_INTERRUPT;
5152         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5153                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5154
5155         new_bus->read = r8169_mdio_read_reg;
5156         new_bus->write = r8169_mdio_write_reg;
5157
5158         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5159         if (ret)
5160                 return ret;
5161
5162         tp->phydev = mdiobus_get_phy(new_bus, 0);
5163         if (!tp->phydev) {
5164                 return -ENODEV;
5165         } else if (!tp->phydev->drv) {
5166                 /* Most chip versions fail with the genphy driver.
5167                  * Therefore ensure that the dedicated PHY driver is loaded.
5168                  */
5169                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5170                         tp->phydev->phy_id);
5171                 return -EUNATCH;
5172         }
5173
5174         tp->phydev->mac_managed_pm = true;
5175         if (rtl_supports_eee(tp))
5176                 phy_support_eee(tp->phydev);
5177         phy_support_asym_pause(tp->phydev);
5178
5179         /* PHY will be woken up in rtl_open() */
5180         phy_suspend(tp->phydev);
5181
5182         return 0;
5183 }
5184
5185 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5186 {
5187         rtl_enable_rxdvgate(tp);
5188
5189         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5190         msleep(1);
5191         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5192
5193         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5194         r8168g_wait_ll_share_fifo_ready(tp);
5195
5196         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5197         r8168g_wait_ll_share_fifo_ready(tp);
5198 }
5199
5200 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5201 {
5202         rtl_enable_rxdvgate(tp);
5203
5204         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5205         msleep(1);
5206         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5207
5208         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5209         r8168g_wait_ll_share_fifo_ready(tp);
5210
5211         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5212         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5213         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5214         r8168g_wait_ll_share_fifo_ready(tp);
5215 }
5216
5217 static void rtl_hw_initialize(struct rtl8169_private *tp)
5218 {
5219         switch (tp->mac_version) {
5220         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5221                 rtl8168ep_stop_cmac(tp);
5222                 fallthrough;
5223         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5224                 rtl_hw_init_8168g(tp);
5225                 break;
5226         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
5227                 rtl_hw_init_8125(tp);
5228                 break;
5229         default:
5230                 break;
5231         }
5232 }
5233
5234 static int rtl_jumbo_max(struct rtl8169_private *tp)
5235 {
5236         /* Non-GBit versions don't support jumbo frames */
5237         if (!tp->supports_gmii)
5238                 return 0;
5239
5240         switch (tp->mac_version) {
5241         /* RTL8169 */
5242         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5243                 return JUMBO_7K;
5244         /* RTL8168b */
5245         case RTL_GIGA_MAC_VER_11:
5246         case RTL_GIGA_MAC_VER_17:
5247                 return JUMBO_4K;
5248         /* RTL8168c */
5249         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5250                 return JUMBO_6K;
5251         default:
5252                 return JUMBO_9K;
5253         }
5254 }
5255
5256 static void rtl_init_mac_address(struct rtl8169_private *tp)
5257 {
5258         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5259         struct net_device *dev = tp->dev;
5260         int rc;
5261
5262         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5263         if (!rc)
5264                 goto done;
5265
5266         rtl_read_mac_address(tp, mac_addr);
5267         if (is_valid_ether_addr(mac_addr))
5268                 goto done;
5269
5270         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5271         if (is_valid_ether_addr(mac_addr))
5272                 goto done;
5273
5274         eth_random_addr(mac_addr);
5275         dev->addr_assign_type = NET_ADDR_RANDOM;
5276         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5277 done:
5278         eth_hw_addr_set(dev, mac_addr);
5279         rtl_rar_set(tp, mac_addr);
5280 }
5281
5282 /* register is set if system vendor successfully tested ASPM 1.2 */
5283 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5284 {
5285         if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5286             r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5287                 return true;
5288
5289         return false;
5290 }
5291
5292 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5293 {
5294         struct rtl8169_private *tp;
5295         int jumbo_max, region, rc;
5296         enum mac_version chipset;
5297         struct net_device *dev;
5298         u32 txconfig;
5299         u16 xid;
5300
5301         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5302         if (!dev)
5303                 return -ENOMEM;
5304
5305         SET_NETDEV_DEV(dev, &pdev->dev);
5306         dev->netdev_ops = &rtl_netdev_ops;
5307         tp = netdev_priv(dev);
5308         tp->dev = dev;
5309         tp->pci_dev = pdev;
5310         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5311         tp->ocp_base = OCP_STD_PHY_BASE;
5312
5313         raw_spin_lock_init(&tp->cfg9346_usage_lock);
5314         raw_spin_lock_init(&tp->config25_lock);
5315         raw_spin_lock_init(&tp->mac_ocp_lock);
5316         mutex_init(&tp->led_lock);
5317
5318         /* Get the *optional* external "ether_clk" used on some boards */
5319         tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5320         if (IS_ERR(tp->clk))
5321                 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5322
5323         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5324         rc = pcim_enable_device(pdev);
5325         if (rc < 0)
5326                 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5327
5328         if (pcim_set_mwi(pdev) < 0)
5329                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5330
5331         /* use first MMIO region */
5332         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5333         if (region < 0)
5334                 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5335
5336         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5337         if (rc < 0)
5338                 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5339
5340         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5341
5342         txconfig = RTL_R32(tp, TxConfig);
5343         if (txconfig == ~0U)
5344                 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5345
5346         xid = (txconfig >> 20) & 0xfcf;
5347
5348         /* Identify chip attached to board */
5349         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5350         if (chipset == RTL_GIGA_MAC_NONE)
5351                 return dev_err_probe(&pdev->dev, -ENODEV,
5352                                      "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5353                                      xid);
5354         tp->mac_version = chipset;
5355
5356         /* Disable ASPM L1 as that cause random device stop working
5357          * problems as well as full system hangs for some PCIe devices users.
5358          */
5359         if (rtl_aspm_is_safe(tp))
5360                 rc = 0;
5361         else
5362                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5363         tp->aspm_manageable = !rc;
5364
5365         tp->dash_type = rtl_get_dash_type(tp);
5366         tp->dash_enabled = rtl_dash_is_enabled(tp);
5367
5368         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5369
5370         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5371             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5372                 dev->features |= NETIF_F_HIGHDMA;
5373
5374         rtl_init_rxcfg(tp);
5375
5376         rtl8169_irq_mask_and_ack(tp);
5377
5378         rtl_hw_initialize(tp);
5379
5380         rtl_hw_reset(tp);
5381
5382         rc = rtl_alloc_irq(tp);
5383         if (rc < 0)
5384                 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5385
5386         tp->irq = pci_irq_vector(pdev, 0);
5387
5388         INIT_WORK(&tp->wk.work, rtl_task);
5389
5390         rtl_init_mac_address(tp);
5391
5392         dev->ethtool_ops = &rtl8169_ethtool_ops;
5393
5394         netif_napi_add(dev, &tp->napi, rtl8169_poll);
5395
5396         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5397                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5398         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5399         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5400
5401         /*
5402          * Pretend we are using VLANs; This bypasses a nasty bug where
5403          * Interrupts stop flowing on high load on 8110SCd controllers.
5404          */
5405         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5406                 /* Disallow toggling */
5407                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5408
5409         if (rtl_chip_supports_csum_v2(tp))
5410                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5411
5412         dev->features |= dev->hw_features;
5413
5414         /* There has been a number of reports that using SG/TSO results in
5415          * tx timeouts. However for a lot of people SG/TSO works fine.
5416          * Therefore disable both features by default, but allow users to
5417          * enable them. Use at own risk!
5418          */
5419         if (rtl_chip_supports_csum_v2(tp)) {
5420                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5421                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5422                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5423         } else {
5424                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5425                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5426                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5427         }
5428
5429         dev->hw_features |= NETIF_F_RXALL;
5430         dev->hw_features |= NETIF_F_RXFCS;
5431
5432         dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5433
5434         netdev_sw_irq_coalesce_default_on(dev);
5435
5436         /* configure chip for default features */
5437         rtl8169_set_features(dev, dev->features);
5438
5439         if (!tp->dash_enabled) {
5440                 rtl_set_d3_pll_down(tp, true);
5441         } else {
5442                 rtl_set_d3_pll_down(tp, false);
5443                 dev->wol_enabled = 1;
5444         }
5445
5446         jumbo_max = rtl_jumbo_max(tp);
5447         if (jumbo_max)
5448                 dev->max_mtu = jumbo_max;
5449
5450         rtl_set_irq_mask(tp);
5451
5452         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5453
5454         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5455                                             &tp->counters_phys_addr,
5456                                             GFP_KERNEL);
5457         if (!tp->counters)
5458                 return -ENOMEM;
5459
5460         pci_set_drvdata(pdev, tp);
5461
5462         rc = r8169_mdio_register(tp);
5463         if (rc)
5464                 return rc;
5465
5466         rc = register_netdev(dev);
5467         if (rc)
5468                 return rc;
5469
5470         if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5471                 if (rtl_is_8125(tp))
5472                         rtl8125_init_leds(dev);
5473                 else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5474                         rtl8168_init_leds(dev);
5475         }
5476
5477         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5478                     rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5479
5480         if (jumbo_max)
5481                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5482                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5483                             "ok" : "ko");
5484
5485         if (tp->dash_type != RTL_DASH_NONE) {
5486                 netdev_info(dev, "DASH %s\n",
5487                             tp->dash_enabled ? "enabled" : "disabled");
5488                 rtl8168_driver_start(tp);
5489         }
5490
5491         if (pci_dev_run_wake(pdev))
5492                 pm_runtime_put_sync(&pdev->dev);
5493
5494         return 0;
5495 }
5496
5497 static struct pci_driver rtl8169_pci_driver = {
5498         .name           = KBUILD_MODNAME,
5499         .id_table       = rtl8169_pci_tbl,
5500         .probe          = rtl_init_one,
5501         .remove         = rtl_remove_one,
5502         .shutdown       = rtl_shutdown,
5503         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5504 };
5505
5506 module_pci_driver(rtl8169_pci_driver);