drivers/net/ethernet/cavium/liquidio/octeon_device.c

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: [email protected]
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2016 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17  ***********************************************************************/
  18 #include <linux/pci.h>
  19 #include <linux/netdevice.h>
  20 #include <linux/vmalloc.h>
  21 #include "liquidio_common.h"
  22 #include "octeon_droq.h"
  23 #include "octeon_iq.h"
  24 #include "response_manager.h"
  25 #include "octeon_device.h"
  26 #include "octeon_main.h"
  27 #include "octeon_network.h"
  28 #include "cn66xx_regs.h"
  29 #include "cn66xx_device.h"
  30 #include "cn23xx_pf_device.h"
  31 #include "cn23xx_vf_device.h"
  32
  33 /** Default configuration
  34  *  for CN66XX OCTEON Models.
  35  */
  36 static struct octeon_config default_cn66xx_conf = {
  37         .card_type                              = LIO_210SV,
  38         .card_name                              = LIO_210SV_NAME,
  39
  40         /** IQ attributes */
  41         .iq                                     = {
  42                 .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
  43                 .pending_list_size              =
  44                         (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
  45                 .instr_type                     = OCTEON_64BYTE_INSTR,
  46                 .db_min                         = CN6XXX_DB_MIN,
  47                 .db_timeout                     = CN6XXX_DB_TIMEOUT,
  48         }
  49         ,
  50
  51         /** OQ attributes */
  52         .oq                                     = {
  53                 .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
  54                 .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
  55                 .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
  56                 .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
  57                 .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
  58         }
  59         ,
  60
  61         .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_66XX,
  62         .num_def_rx_descs                       = CN6XXX_MAX_OQ_DESCRIPTORS,
  63         .num_def_tx_descs                       = CN6XXX_MAX_IQ_DESCRIPTORS,
  64         .def_rx_buf_size                        = CN6XXX_OQ_BUF_SIZE,
  65
  66         /* For ethernet interface 0:  Port cfg Attributes */
  67         .nic_if_cfg[0] = {
  68                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
  69                 .max_txqs                       = MAX_TXQS_PER_INTF,
  70
  71                 /* Actual configured value. Range could be: 1...max_txqs */
  72                 .num_txqs                       = DEF_TXQS_PER_INTF,
  73
  74                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
  75                 .max_rxqs                       = MAX_RXQS_PER_INTF,
  76
  77                 /* Actual configured value. Range could be: 1...max_rxqs */
  78                 .num_rxqs                       = DEF_RXQS_PER_INTF,
  79
  80                 /* Num of desc for rx rings */
  81                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
  82
  83                 /* Num of desc for tx rings */
  84                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
  85
  86                 /* SKB size, We need not change buf size even for Jumbo frames.
  87                  * Octeon can send jumbo frames in 4 consecutive descriptors,
  88                  */
  89                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
  90
  91                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
  92
  93                 .gmx_port_id                    = 0,
  94         },
  95
  96         .nic_if_cfg[1] = {
  97                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
  98                 .max_txqs                       = MAX_TXQS_PER_INTF,
  99
 100                 /* Actual configured value. Range could be: 1...max_txqs */
 101                 .num_txqs                       = DEF_TXQS_PER_INTF,
 102
 103                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 104                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 105
 106                 /* Actual configured value. Range could be: 1...max_rxqs */
 107                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 108
 109                 /* Num of desc for rx rings */
 110                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 111
 112                 /* Num of desc for tx rings */
 113                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 114
 115                 /* SKB size, We need not change buf size even for Jumbo frames.
 116                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 117                  */
 118                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 119
 120                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 121
 122                 .gmx_port_id                    = 1,
 123         },
 124
 125         /** Miscellaneous attributes */
 126         .misc                                   = {
 127                 /* Host driver link query interval */
 128                 .oct_link_query_interval        = 100,
 129
 130                 /* Octeon link query interval */
 131                 .host_link_query_interval       = 500,
 132
 133                 .enable_sli_oq_bp               = 0,
 134
 135                 /* Control queue group */
 136                 .ctrlq_grp                      = 1,
 137         }
 138         ,
 139 };
 140
 141 /** Default configuration
 142  *  for CN68XX OCTEON Model.
 143  */
 144
 145 static struct octeon_config default_cn68xx_conf = {
 146         .card_type                              = LIO_410NV,
 147         .card_name                              = LIO_410NV_NAME,
 148
 149         /** IQ attributes */
 150         .iq                                     = {
 151                 .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
 152                 .pending_list_size              =
 153                         (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
 154                 .instr_type                     = OCTEON_64BYTE_INSTR,
 155                 .db_min                         = CN6XXX_DB_MIN,
 156                 .db_timeout                     = CN6XXX_DB_TIMEOUT,
 157         }
 158         ,
 159
 160         /** OQ attributes */
 161         .oq                                     = {
 162                 .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
 163                 .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
 164                 .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
 165                 .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
 166                 .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
 167         }
 168         ,
 169
 170         .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_68XX,
 171         .num_def_rx_descs                       = CN6XXX_MAX_OQ_DESCRIPTORS,
 172         .num_def_tx_descs                       = CN6XXX_MAX_IQ_DESCRIPTORS,
 173         .def_rx_buf_size                        = CN6XXX_OQ_BUF_SIZE,
 174
 175         .nic_if_cfg[0] = {
 176                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 177                 .max_txqs                       = MAX_TXQS_PER_INTF,
 178
 179                 /* Actual configured value. Range could be: 1...max_txqs */
 180                 .num_txqs                       = DEF_TXQS_PER_INTF,
 181
 182                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 183                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 184
 185                 /* Actual configured value. Range could be: 1...max_rxqs */
 186                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 187
 188                 /* Num of desc for rx rings */
 189                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 190
 191                 /* Num of desc for tx rings */
 192                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 193
 194                 /* SKB size, We need not change buf size even for Jumbo frames.
 195                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 196                  */
 197                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 198
 199                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 200
 201                 .gmx_port_id                    = 0,
 202         },
 203
 204         .nic_if_cfg[1] = {
 205                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 206                 .max_txqs                       = MAX_TXQS_PER_INTF,
 207
 208                 /* Actual configured value. Range could be: 1...max_txqs */
 209                 .num_txqs                       = DEF_TXQS_PER_INTF,
 210
 211                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 212                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 213
 214                 /* Actual configured value. Range could be: 1...max_rxqs */
 215                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 216
 217                 /* Num of desc for rx rings */
 218                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 219
 220                 /* Num of desc for tx rings */
 221                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 222
 223                 /* SKB size, We need not change buf size even for Jumbo frames.
 224                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 225                  */
 226                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 227
 228                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 229
 230                 .gmx_port_id                    = 1,
 231         },
 232
 233         .nic_if_cfg[2] = {
 234                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 235                 .max_txqs                       = MAX_TXQS_PER_INTF,
 236
 237                 /* Actual configured value. Range could be: 1...max_txqs */
 238                 .num_txqs                       = DEF_TXQS_PER_INTF,
 239
 240                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 241                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 242
 243                 /* Actual configured value. Range could be: 1...max_rxqs */
 244                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 245
 246                 /* Num of desc for rx rings */
 247                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 248
 249                 /* Num of desc for tx rings */
 250                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 251
 252                 /* SKB size, We need not change buf size even for Jumbo frames.
 253                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 254                  */
 255                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 256
 257                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 258
 259                 .gmx_port_id                    = 2,
 260         },
 261
 262         .nic_if_cfg[3] = {
 263                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 264                 .max_txqs                       = MAX_TXQS_PER_INTF,
 265
 266                 /* Actual configured value. Range could be: 1...max_txqs */
 267                 .num_txqs                       = DEF_TXQS_PER_INTF,
 268
 269                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 270                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 271
 272                 /* Actual configured value. Range could be: 1...max_rxqs */
 273                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 274
 275                 /* Num of desc for rx rings */
 276                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 277
 278                 /* Num of desc for tx rings */
 279                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 280
 281                 /* SKB size, We need not change buf size even for Jumbo frames.
 282                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 283                  */
 284                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 285
 286                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 287
 288                 .gmx_port_id                    = 3,
 289         },
 290
 291         /** Miscellaneous attributes */
 292         .misc                                   = {
 293                 /* Host driver link query interval */
 294                 .oct_link_query_interval        = 100,
 295
 296                 /* Octeon link query interval */
 297                 .host_link_query_interval       = 500,
 298
 299                 .enable_sli_oq_bp               = 0,
 300
 301                 /* Control queue group */
 302                 .ctrlq_grp                      = 1,
 303         }
 304         ,
 305 };
 306
 307 /** Default configuration
 308  *  for CN68XX OCTEON Model.
 309  */
 310 static struct octeon_config default_cn68xx_210nv_conf = {
 311         .card_type                              = LIO_210NV,
 312         .card_name                              = LIO_210NV_NAME,
 313
 314         /** IQ attributes */
 315
 316         .iq                                     = {
 317                 .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
 318                 .pending_list_size              =
 319                         (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
 320                 .instr_type                     = OCTEON_64BYTE_INSTR,
 321                 .db_min                         = CN6XXX_DB_MIN,
 322                 .db_timeout                     = CN6XXX_DB_TIMEOUT,
 323         }
 324         ,
 325
 326         /** OQ attributes */
 327         .oq                                     = {
 328                 .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
 329                 .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
 330                 .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
 331                 .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
 332                 .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
 333         }
 334         ,
 335
 336         .num_nic_ports                  = DEFAULT_NUM_NIC_PORTS_68XX_210NV,
 337         .num_def_rx_descs               = CN6XXX_MAX_OQ_DESCRIPTORS,
 338         .num_def_tx_descs               = CN6XXX_MAX_IQ_DESCRIPTORS,
 339         .def_rx_buf_size                = CN6XXX_OQ_BUF_SIZE,
 340
 341         .nic_if_cfg[0] = {
 342                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 343                 .max_txqs                       = MAX_TXQS_PER_INTF,
 344
 345                 /* Actual configured value. Range could be: 1...max_txqs */
 346                 .num_txqs                       = DEF_TXQS_PER_INTF,
 347
 348                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 349                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 350
 351                 /* Actual configured value. Range could be: 1...max_rxqs */
 352                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 353
 354                 /* Num of desc for rx rings */
 355                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 356
 357                 /* Num of desc for tx rings */
 358                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 359
 360                 /* SKB size, We need not change buf size even for Jumbo frames.
 361                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 362                  */
 363                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 364
 365                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 366
 367                 .gmx_port_id                    = 0,
 368         },
 369
 370         .nic_if_cfg[1] = {
 371                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 372                 .max_txqs                       = MAX_TXQS_PER_INTF,
 373
 374                 /* Actual configured value. Range could be: 1...max_txqs */
 375                 .num_txqs                       = DEF_TXQS_PER_INTF,
 376
 377                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 378                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 379
 380                 /* Actual configured value. Range could be: 1...max_rxqs */
 381                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 382
 383                 /* Num of desc for rx rings */
 384                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 385
 386                 /* Num of desc for tx rings */
 387                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 388
 389                 /* SKB size, We need not change buf size even for Jumbo frames.
 390                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 391                  */
 392                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 393
 394                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 395
 396                 .gmx_port_id                    = 1,
 397         },
 398
 399         /** Miscellaneous attributes */
 400         .misc                                   = {
 401                 /* Host driver link query interval */
 402                 .oct_link_query_interval        = 100,
 403
 404                 /* Octeon link query interval */
 405                 .host_link_query_interval       = 500,
 406
 407                 .enable_sli_oq_bp               = 0,
 408
 409                 /* Control queue group */
 410                 .ctrlq_grp                      = 1,
 411         }
 412         ,
 413 };
 414
 415 static struct octeon_config default_cn23xx_conf = {
 416         .card_type                              = LIO_23XX,
 417         .card_name                              = LIO_23XX_NAME,
 418         /** IQ attributes */
 419         .iq = {
 420                 .max_iqs                = CN23XX_CFG_IO_QUEUES,
 421                 .pending_list_size      = (CN23XX_DEFAULT_IQ_DESCRIPTORS *
 422                                            CN23XX_CFG_IO_QUEUES),
 423                 .instr_type             = OCTEON_64BYTE_INSTR,
 424                 .db_min                 = CN23XX_DB_MIN,
 425                 .db_timeout             = CN23XX_DB_TIMEOUT,
 426                 .iq_intr_pkt            = CN23XX_DEF_IQ_INTR_THRESHOLD,
 427         },
 428
 429         /** OQ attributes */
 430         .oq = {
 431                 .max_oqs                = CN23XX_CFG_IO_QUEUES,
 432                 .pkts_per_intr  = CN23XX_OQ_PKTSPER_INTR,
 433                 .refill_threshold       = CN23XX_OQ_REFIL_THRESHOLD,
 434                 .oq_intr_pkt    = CN23XX_OQ_INTR_PKT,
 435                 .oq_intr_time   = CN23XX_OQ_INTR_TIME,
 436         },
 437
 438         .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_23XX,
 439         .num_def_rx_descs                       = CN23XX_DEFAULT_OQ_DESCRIPTORS,
 440         .num_def_tx_descs                       = CN23XX_DEFAULT_IQ_DESCRIPTORS,
 441         .def_rx_buf_size                        = CN23XX_OQ_BUF_SIZE,
 442
 443         /* For ethernet interface 0:  Port cfg Attributes */
 444         .nic_if_cfg[0] = {
 445                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 446                 .max_txqs                       = MAX_TXQS_PER_INTF,
 447
 448                 /* Actual configured value. Range could be: 1...max_txqs */
 449                 .num_txqs                       = DEF_TXQS_PER_INTF,
 450
 451                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 452                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 453
 454                 /* Actual configured value. Range could be: 1...max_rxqs */
 455                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 456
 457                 /* Num of desc for rx rings */
 458                 .num_rx_descs                   = CN23XX_DEFAULT_OQ_DESCRIPTORS,
 459
 460                 /* Num of desc for tx rings */
 461                 .num_tx_descs                   = CN23XX_DEFAULT_IQ_DESCRIPTORS,
 462
 463                 /* SKB size, We need not change buf size even for Jumbo frames.
 464                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 465                  */
 466                 .rx_buf_size                    = CN23XX_OQ_BUF_SIZE,
 467
 468                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 469
 470                 .gmx_port_id                    = 0,
 471         },
 472
 473         .nic_if_cfg[1] = {
 474                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 475                 .max_txqs                       = MAX_TXQS_PER_INTF,
 476
 477                 /* Actual configured value. Range could be: 1...max_txqs */
 478                 .num_txqs                       = DEF_TXQS_PER_INTF,
 479
 480                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 481                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 482
 483                 /* Actual configured value. Range could be: 1...max_rxqs */
 484                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 485
 486                 /* Num of desc for rx rings */
 487                 .num_rx_descs                   = CN23XX_DEFAULT_OQ_DESCRIPTORS,
 488
 489                 /* Num of desc for tx rings */
 490                 .num_tx_descs                   = CN23XX_DEFAULT_IQ_DESCRIPTORS,
 491
 492                 /* SKB size, We need not change buf size even for Jumbo frames.
 493                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 494                  */
 495                 .rx_buf_size                    = CN23XX_OQ_BUF_SIZE,
 496
 497                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 498
 499                 .gmx_port_id                    = 1,
 500         },
 501
 502         .misc                                   = {
 503                 /* Host driver link query interval */
 504                 .oct_link_query_interval        = 100,
 505
 506                 /* Octeon link query interval */
 507                 .host_link_query_interval       = 500,
 508
 509                 .enable_sli_oq_bp               = 0,
 510
 511                 /* Control queue group */
 512                 .ctrlq_grp                      = 1,
 513         }
 514 };
 515
 516 static struct octeon_config_ptr {
 517         u32 conf_type;
 518 } oct_conf_info[MAX_OCTEON_DEVICES] = {
 519         {
 520                 OCTEON_CONFIG_TYPE_DEFAULT,
 521         }, {
 522                 OCTEON_CONFIG_TYPE_DEFAULT,
 523         }, {
 524                 OCTEON_CONFIG_TYPE_DEFAULT,
 525         }, {
 526                 OCTEON_CONFIG_TYPE_DEFAULT,
 527         },
 528 };
 529
 530 static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = {
 531         "BEGIN", "PCI-ENABLE-DONE", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
 532         "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
 533         "DROQ-INIT-DONE", "MBOX-SETUP-DONE", "MSIX-ALLOC-VECTOR-DONE",
 534         "INTR-SET-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
 535         "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
 536         "INVALID"
 537 };
 538
 539 static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = {
 540         "BASE", "NIC", "UNKNOWN"};
 541
 542 static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES];
 543 static atomic_t adapter_refcounts[MAX_OCTEON_DEVICES];
 544 static atomic_t adapter_fw_states[MAX_OCTEON_DEVICES];
 545
 546 static u32 octeon_device_count;
 547 /* locks device array (i.e. octeon_device[]) */
 548 static DEFINE_SPINLOCK(octeon_devices_lock);
 549
 550 static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES];
 551
 552 static void oct_set_config_info(int oct_id, int conf_type)
 553 {
 554         if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1))
 555                 conf_type = OCTEON_CONFIG_TYPE_DEFAULT;
 556         oct_conf_info[oct_id].conf_type = conf_type;
 557 }
 558
 559 void octeon_init_device_list(int conf_type)
 560 {
 561         int i;
 562
 563         memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES));
 564         for (i = 0; i <  MAX_OCTEON_DEVICES; i++)
 565                 oct_set_config_info(i, conf_type);
 566 }
 567 EXPORT_SYMBOL_GPL(octeon_init_device_list);
 568
 569 static void *__retrieve_octeon_config_info(struct octeon_device *oct,
 570                                            u16 card_type)
 571 {
 572         u32 oct_id = oct->octeon_id;
 573         void *ret = NULL;
 574
 575         switch (oct_conf_info[oct_id].conf_type) {
 576         case OCTEON_CONFIG_TYPE_DEFAULT:
 577                 if (oct->chip_id == OCTEON_CN66XX) {
 578                         ret = &default_cn66xx_conf;
 579                 } else if ((oct->chip_id == OCTEON_CN68XX) &&
 580                            (card_type == LIO_210NV)) {
 581                         ret = &default_cn68xx_210nv_conf;
 582                 } else if ((oct->chip_id == OCTEON_CN68XX) &&
 583                            (card_type == LIO_410NV)) {
 584                         ret = &default_cn68xx_conf;
 585                 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 586                         ret = &default_cn23xx_conf;
 587                 } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
 588                         ret = &default_cn23xx_conf;
 589                 }
 590                 break;
 591         default:
 592                 break;
 593         }
 594         return ret;
 595 }
 596
 597 static int __verify_octeon_config_info(struct octeon_device *oct, void *conf)
 598 {
 599         switch (oct->chip_id) {
 600         case OCTEON_CN66XX:
 601         case OCTEON_CN68XX:
 602                 return lio_validate_cn6xxx_config_info(oct, conf);
 603         case OCTEON_CN23XX_PF_VID:
 604         case OCTEON_CN23XX_VF_VID:
 605                 return 0;
 606         default:
 607                 break;
 608         }
 609
 610         return 1;
 611 }
 612
 613 void *oct_get_config_info(struct octeon_device *oct, u16 card_type)
 614 {
 615         void *conf = NULL;
 616
 617         conf = __retrieve_octeon_config_info(oct, card_type);
 618         if (!conf)
 619                 return NULL;
 620
 621         if (__verify_octeon_config_info(oct, conf)) {
 622                 dev_err(&oct->pci_dev->dev, "Configuration verification failed\n");
 623                 return NULL;
 624         }
 625
 626         return conf;
 627 }
 628
 629 char *lio_get_state_string(atomic_t *state_ptr)
 630 {
 631         s32 istate = (s32)atomic_read(state_ptr);
 632
 633         if (istate > OCT_DEV_STATES || istate < 0)
 634                 return oct_dev_state_str[OCT_DEV_STATE_INVALID];
 635         return oct_dev_state_str[istate];
 636 }
 637 EXPORT_SYMBOL_GPL(lio_get_state_string);
 638
 639 static char *get_oct_app_string(u32 app_mode)
 640 {
 641         if (app_mode <= CVM_DRV_APP_END)
 642                 return oct_dev_app_str[app_mode - CVM_DRV_APP_START];
 643         return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START];
 644 }
 645
 646 void octeon_free_device_mem(struct octeon_device *oct)
 647 {
 648         int i;
 649
 650         for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
 651                 if (oct->io_qmask.oq & BIT_ULL(i))
 652                         vfree(oct->droq[i]);
 653         }
 654
 655         for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
 656                 if (oct->io_qmask.iq & BIT_ULL(i))
 657                         vfree(oct->instr_queue[i]);
 658         }
 659
 660         i = oct->octeon_id;
 661         vfree(oct);
 662
 663         octeon_device[i] = NULL;
 664         octeon_device_count--;
 665 }
 666 EXPORT_SYMBOL_GPL(octeon_free_device_mem);
 667
 668 static struct octeon_device *octeon_allocate_device_mem(u32 pci_id,
 669                                                         u32 priv_size)
 670 {
 671         struct octeon_device *oct;
 672         u8 *buf = NULL;
 673         u32 octdevsize = 0, configsize = 0, size;
 674
 675         switch (pci_id) {
 676         case OCTEON_CN68XX:
 677         case OCTEON_CN66XX:
 678                 configsize = sizeof(struct octeon_cn6xxx);
 679                 break;
 680
 681         case OCTEON_CN23XX_PF_VID:
 682                 configsize = sizeof(struct octeon_cn23xx_pf);
 683                 break;
 684         case OCTEON_CN23XX_VF_VID:
 685                 configsize = sizeof(struct octeon_cn23xx_vf);
 686                 break;
 687         default:
 688                 pr_err("%s: Unknown PCI Device: 0x%x\n",
 689                        __func__,
 690                        pci_id);
 691                 return NULL;
 692         }
 693
 694         if (configsize & 0x7)
 695                 configsize += (8 - (configsize & 0x7));
 696
 697         octdevsize = sizeof(struct octeon_device);
 698         if (octdevsize & 0x7)
 699                 octdevsize += (8 - (octdevsize & 0x7));
 700
 701         if (priv_size & 0x7)
 702                 priv_size += (8 - (priv_size & 0x7));
 703
 704         size = octdevsize + priv_size + configsize +
 705                 (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE);
 706
 707         buf = vzalloc(size);
 708         if (!buf)
 709                 return NULL;
 710
 711         oct = (struct octeon_device *)buf;
 712         oct->priv = (void *)(buf + octdevsize);
 713         oct->chip = (void *)(buf + octdevsize + priv_size);
 714         oct->dispatch.dlist = (struct octeon_dispatch *)
 715                 (buf + octdevsize + priv_size + configsize);
 716
 717         return oct;
 718 }
 719
 720 struct octeon_device *octeon_allocate_device(u32 pci_id,
 721                                              u32 priv_size)
 722 {
 723         u32 oct_idx = 0;
 724         struct octeon_device *oct = NULL;
 725
 726         spin_lock(&octeon_devices_lock);
 727
 728         for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++)
 729                 if (!octeon_device[oct_idx])
 730                         break;
 731
 732         if (oct_idx < MAX_OCTEON_DEVICES) {
 733                 oct = octeon_allocate_device_mem(pci_id, priv_size);
 734                 if (oct) {
 735                         octeon_device_count++;
 736                         octeon_device[oct_idx] = oct;
 737                 }
 738         }
 739
 740         spin_unlock(&octeon_devices_lock);
 741         if (!oct)
 742                 return NULL;
 743
 744         spin_lock_init(&oct->pci_win_lock);
 745         spin_lock_init(&oct->mem_access_lock);
 746
 747         oct->octeon_id = oct_idx;
 748         snprintf(oct->device_name, sizeof(oct->device_name),
 749                  "LiquidIO%d", (oct->octeon_id));
 750
 751         return oct;
 752 }
 753 EXPORT_SYMBOL_GPL(octeon_allocate_device);
 754
 755 /** Register a device's bus location at initialization time.
 756  *  @param octeon_dev - pointer to the octeon device structure.
 757  *  @param bus        - PCIe bus #
 758  *  @param dev        - PCIe device #
 759  *  @param func       - PCIe function #
 760  *  @param is_pf      - TRUE for PF, FALSE for VF
 761  *  @return reference count of device's adapter
 762  */
 763 int octeon_register_device(struct octeon_device *oct,
 764                            int bus, int dev, int func, int is_pf)
 765 {
 766         int idx, refcount;
 767
 768         oct->loc.bus = bus;
 769         oct->loc.dev = dev;
 770         oct->loc.func = func;
 771
 772         oct->adapter_refcount = &adapter_refcounts[oct->octeon_id];
 773         atomic_set(oct->adapter_refcount, 0);
 774
 775         /* Like the reference count, the f/w state is shared 'per-adapter' */
 776         oct->adapter_fw_state = &adapter_fw_states[oct->octeon_id];
 777         atomic_set(oct->adapter_fw_state, FW_NEEDS_TO_BE_LOADED);
 778
 779         spin_lock(&octeon_devices_lock);
 780         for (idx = (int)oct->octeon_id - 1; idx >= 0; idx--) {
 781                 if (!octeon_device[idx]) {
 782                         dev_err(&oct->pci_dev->dev,
 783                                 "%s: Internal driver error, missing dev",
 784                                 __func__);
 785                         spin_unlock(&octeon_devices_lock);
 786                         atomic_inc(oct->adapter_refcount);
 787                         return 1; /* here, refcount is guaranteed to be 1 */
 788                 }
 789                 /* If another device is at same bus/dev, use its refcounter
 790                  * (and f/w state variable).
 791                  */
 792                 if ((octeon_device[idx]->loc.bus == bus) &&
 793                     (octeon_device[idx]->loc.dev == dev)) {
 794                         oct->adapter_refcount =
 795                                 octeon_device[idx]->adapter_refcount;
 796                         oct->adapter_fw_state =
 797                                 octeon_device[idx]->adapter_fw_state;
 798                         break;
 799                 }
 800         }
 801         spin_unlock(&octeon_devices_lock);
 802
 803         atomic_inc(oct->adapter_refcount);
 804         refcount = atomic_read(oct->adapter_refcount);
 805
 806         dev_dbg(&oct->pci_dev->dev, "%s: %02x:%02x:%d refcount %u", __func__,
 807                 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
 808
 809         return refcount;
 810 }
 811 EXPORT_SYMBOL_GPL(octeon_register_device);
 812
 813 /** Deregister a device at de-initialization time.
 814  *  @param octeon_dev - pointer to the octeon device structure.
 815  *  @return reference count of device's adapter
 816  */
 817 int octeon_deregister_device(struct octeon_device *oct)
 818 {
 819         int refcount;
 820
 821         atomic_dec(oct->adapter_refcount);
 822         refcount = atomic_read(oct->adapter_refcount);
 823
 824         dev_dbg(&oct->pci_dev->dev, "%s: %04d:%02d:%d refcount %u", __func__,
 825                 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
 826
 827         return refcount;
 828 }
 829 EXPORT_SYMBOL_GPL(octeon_deregister_device);
 830
 831 int
 832 octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs)
 833 {
 834         struct octeon_ioq_vector *ioq_vector;
 835         int cpu_num;
 836         int size;
 837         int i;
 838
 839         size = sizeof(struct octeon_ioq_vector) * num_ioqs;
 840
 841         oct->ioq_vector = vzalloc(size);
 842         if (!oct->ioq_vector)
 843                 return -1;
 844         for (i = 0; i < num_ioqs; i++) {
 845                 ioq_vector              = &oct->ioq_vector[i];
 846                 ioq_vector->oct_dev     = oct;
 847                 ioq_vector->iq_index    = i;
 848                 ioq_vector->droq_index  = i;
 849                 ioq_vector->mbox        = oct->mbox[i];
 850
 851                 cpu_num = i % num_online_cpus();
 852                 cpumask_set_cpu(cpu_num, &ioq_vector->affinity_mask);
 853
 854                 if (oct->chip_id == OCTEON_CN23XX_PF_VID)
 855                         ioq_vector->ioq_num     = i + oct->sriov_info.pf_srn;
 856                 else
 857                         ioq_vector->ioq_num     = i;
 858         }
 859
 860         return 0;
 861 }
 862 EXPORT_SYMBOL_GPL(octeon_allocate_ioq_vector);
 863
 864 void
 865 octeon_free_ioq_vector(struct octeon_device *oct)
 866 {
 867         vfree(oct->ioq_vector);
 868 }
 869 EXPORT_SYMBOL_GPL(octeon_free_ioq_vector);
 870
 871 /* this function is only for setting up the first queue */
 872 int octeon_setup_instr_queues(struct octeon_device *oct)
 873 {
 874         u32 num_descs = 0;
 875         u32 iq_no = 0;
 876         union oct_txpciq txpciq;
 877         int numa_node = dev_to_node(&oct->pci_dev->dev);
 878
 879         if (OCTEON_CN6XXX(oct))
 880                 num_descs =
 881                         CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
 882         else if (OCTEON_CN23XX_PF(oct))
 883                 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
 884         else if (OCTEON_CN23XX_VF(oct))
 885                 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_vf));
 886
 887         oct->num_iqs = 0;
 888
 889         oct->instr_queue[0] = vzalloc_node(sizeof(*oct->instr_queue[0]),
 890                                 numa_node);
 891         if (!oct->instr_queue[0])
 892                 oct->instr_queue[0] =
 893                         vzalloc(sizeof(struct octeon_instr_queue));
 894         if (!oct->instr_queue[0])
 895                 return 1;
 896         memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue));
 897         oct->instr_queue[0]->q_index = 0;
 898         oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
 899         oct->instr_queue[0]->ifidx = 0;
 900         txpciq.u64 = 0;
 901         txpciq.s.q_no = iq_no;
 902         txpciq.s.pkind = oct->pfvf_hsword.pkind;
 903         txpciq.s.use_qpg = 0;
 904         txpciq.s.qpg = 0;
 905         if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
 906                 /* prevent memory leak */
 907                 vfree(oct->instr_queue[0]);
 908                 oct->instr_queue[0] = NULL;
 909                 return 1;
 910         }
 911
 912         oct->num_iqs++;
 913         return 0;
 914 }
 915 EXPORT_SYMBOL_GPL(octeon_setup_instr_queues);
 916
 917 int octeon_setup_output_queues(struct octeon_device *oct)
 918 {
 919         u32 num_descs = 0;
 920         u32 desc_size = 0;
 921         u32 oq_no = 0;
 922         int numa_node = dev_to_node(&oct->pci_dev->dev);
 923
 924         if (OCTEON_CN6XXX(oct)) {
 925                 num_descs =
 926                         CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx));
 927                 desc_size =
 928                         CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx));
 929         } else if (OCTEON_CN23XX_PF(oct)) {
 930                 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
 931                 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
 932         } else if (OCTEON_CN23XX_VF(oct)) {
 933                 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_vf));
 934                 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_vf));
 935         }
 936         oct->num_oqs = 0;
 937         oct->droq[0] = vzalloc_node(sizeof(*oct->droq[0]), numa_node);
 938         if (!oct->droq[0])
 939                 oct->droq[0] = vzalloc(sizeof(*oct->droq[0]));
 940         if (!oct->droq[0])
 941                 return 1;
 942
 943         if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) {
 944                 vfree(oct->droq[oq_no]);
 945                 oct->droq[oq_no] = NULL;
 946                 return 1;
 947         }
 948         oct->num_oqs++;
 949
 950         return 0;
 951 }
 952 EXPORT_SYMBOL_GPL(octeon_setup_output_queues);
 953
 954 int octeon_set_io_queues_off(struct octeon_device *oct)
 955 {
 956         int loop = BUSY_READING_REG_VF_LOOP_COUNT;
 957
 958         if (OCTEON_CN6XXX(oct)) {
 959                 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
 960                 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
 961         } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
 962                 u32 q_no;
 963
 964                 /* IOQs will already be in reset.
 965                  * If RST bit is set, wait for quiet bit to be set.
 966                  * Once quiet bit is set, clear the RST bit.
 967                  */
 968                 for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
 969                         u64 reg_val = octeon_read_csr64(
 970                                 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
 971
 972                         while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
 973                                !(reg_val &  CN23XX_PKT_INPUT_CTL_QUIET) &&
 974                                loop) {
 975                                 reg_val = octeon_read_csr64(
 976                                         oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 977                                 loop--;
 978                         }
 979                         if (!loop) {
 980                                 dev_err(&oct->pci_dev->dev,
 981                                         "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
 982                                         q_no);
 983                                 return -1;
 984                         }
 985
 986                         reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
 987                         octeon_write_csr64(oct,
 988                                            CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
 989                                            reg_val);
 990
 991                         reg_val = octeon_read_csr64(
 992                                         oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 993                         if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
 994                                 dev_err(&oct->pci_dev->dev,
 995                                         "unable to reset qno %u\n", q_no);
 996                                 return -1;
 997                         }
 998                 }
 999         }
1000         return 0;
1001 }
1002 EXPORT_SYMBOL_GPL(octeon_set_io_queues_off);
1003
1004 void octeon_set_droq_pkt_op(struct octeon_device *oct,
1005                             u32 q_no,
1006                             u32 enable)
1007 {
1008         u32 reg_val = 0;
1009
1010         /* Disable the i/p and o/p queues for this Octeon. */
1011         if (OCTEON_CN6XXX(oct)) {
1012                 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);
1013
1014                 if (enable)
1015                         reg_val = reg_val | (1 << q_no);
1016                 else
1017                         reg_val = reg_val & (~(1 << q_no));
1018
1019                 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);
1020         }
1021 }
1022
1023 int octeon_init_dispatch_list(struct octeon_device *oct)
1024 {
1025         u32 i;
1026
1027         oct->dispatch.count = 0;
1028
1029         for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1030                 oct->dispatch.dlist[i].opcode = 0;
1031                 INIT_LIST_HEAD(&oct->dispatch.dlist[i].list);
1032         }
1033
1034         for (i = 0; i <= REQTYPE_LAST; i++)
1035                 octeon_register_reqtype_free_fn(oct, i, NULL);
1036
1037         spin_lock_init(&oct->dispatch.lock);
1038
1039         return 0;
1040 }
1041 EXPORT_SYMBOL_GPL(octeon_init_dispatch_list);
1042
1043 void octeon_delete_dispatch_list(struct octeon_device *oct)
1044 {
1045         u32 i;
1046         struct list_head freelist, *temp, *tmp2;
1047
1048         INIT_LIST_HEAD(&freelist);
1049
1050         spin_lock_bh(&oct->dispatch.lock);
1051
1052         for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1053                 struct list_head *dispatch;
1054
1055                 dispatch = &oct->dispatch.dlist[i].list;
1056                 while (dispatch->next != dispatch) {
1057                         temp = dispatch->next;
1058                         list_move_tail(temp, &freelist);
1059                 }
1060
1061                 oct->dispatch.dlist[i].opcode = 0;
1062         }
1063
1064         oct->dispatch.count = 0;
1065
1066         spin_unlock_bh(&oct->dispatch.lock);
1067
1068         list_for_each_safe(temp, tmp2, &freelist) {
1069                 list_del(temp);
1070                 kfree(temp);
1071         }
1072 }
1073 EXPORT_SYMBOL_GPL(octeon_delete_dispatch_list);
1074
1075 octeon_dispatch_fn_t
1076 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
1077                     u16 subcode)
1078 {
1079         u32 idx;
1080         struct list_head *dispatch;
1081         octeon_dispatch_fn_t fn = NULL;
1082         u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1083
1084         idx = combined_opcode & OCTEON_OPCODE_MASK;
1085
1086         spin_lock_bh(&octeon_dev->dispatch.lock);
1087
1088         if (octeon_dev->dispatch.count == 0) {
1089                 spin_unlock_bh(&octeon_dev->dispatch.lock);
1090                 return NULL;
1091         }
1092
1093         if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
1094                 spin_unlock_bh(&octeon_dev->dispatch.lock);
1095                 return NULL;
1096         }
1097
1098         if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
1099                 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
1100         } else {
1101                 list_for_each(dispatch,
1102                               &octeon_dev->dispatch.dlist[idx].list) {
1103                         if (((struct octeon_dispatch *)dispatch)->opcode ==
1104                             combined_opcode) {
1105                                 fn = ((struct octeon_dispatch *)
1106                                       dispatch)->dispatch_fn;
1107                                 break;
1108                         }
1109                 }
1110         }
1111
1112         spin_unlock_bh(&octeon_dev->dispatch.lock);
1113         return fn;
1114 }
1115
1116 /* octeon_register_dispatch_fn
1117  * Parameters:
1118  *   octeon_id - id of the octeon device.
1119  *   opcode    - opcode for which driver should call the registered function
1120  *   subcode   - subcode for which driver should call the registered function
1121  *   fn        - The function to call when a packet with "opcode" arrives in
1122  *                octeon output queues.
1123  *   fn_arg    - The argument to be passed when calling function "fn".
1124  * Description:
1125  *   Registers a function and its argument to be called when a packet
1126  *   arrives in Octeon output queues with "opcode".
1127  * Returns:
1128  *   Success: 0
1129  *   Failure: 1
1130  * Locks:
1131  *   No locks are held.
1132  */
1133 int
1134 octeon_register_dispatch_fn(struct octeon_device *oct,
1135                             u16 opcode,
1136                             u16 subcode,
1137                             octeon_dispatch_fn_t fn, void *fn_arg)
1138 {
1139         u32 idx;
1140         octeon_dispatch_fn_t pfn;
1141         u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1142
1143         idx = combined_opcode & OCTEON_OPCODE_MASK;
1144
1145         spin_lock_bh(&oct->dispatch.lock);
1146         /* Add dispatch function to first level of lookup table */
1147         if (oct->dispatch.dlist[idx].opcode == 0) {
1148                 oct->dispatch.dlist[idx].opcode = combined_opcode;
1149                 oct->dispatch.dlist[idx].dispatch_fn = fn;
1150                 oct->dispatch.dlist[idx].arg = fn_arg;
1151                 oct->dispatch.count++;
1152                 spin_unlock_bh(&oct->dispatch.lock);
1153                 return 0;
1154         }
1155
1156         spin_unlock_bh(&oct->dispatch.lock);
1157
1158         /* Check if there was a function already registered for this
1159          * opcode/subcode.
1160          */
1161         pfn = octeon_get_dispatch(oct, opcode, subcode);
1162         if (!pfn) {
1163                 struct octeon_dispatch *dispatch;
1164
1165                 dev_dbg(&oct->pci_dev->dev,
1166                         "Adding opcode to dispatch list linked list\n");
1167                 dispatch = kmalloc(sizeof(*dispatch), GFP_KERNEL);
1168                 if (!dispatch)
1169                         return 1;
1170
1171                 dispatch->opcode = combined_opcode;
1172                 dispatch->dispatch_fn = fn;
1173                 dispatch->arg = fn_arg;
1174
1175                 /* Add dispatch function to linked list of fn ptrs
1176                  * at the hashed index.
1177                  */
1178                 spin_lock_bh(&oct->dispatch.lock);
1179                 list_add(&dispatch->list, &oct->dispatch.dlist[idx].list);
1180                 oct->dispatch.count++;
1181                 spin_unlock_bh(&oct->dispatch.lock);
1182
1183         } else {
1184                 if (pfn == fn &&
1185                     octeon_get_dispatch_arg(oct, opcode, subcode) == fn_arg)
1186                         return 0;
1187
1188                 dev_err(&oct->pci_dev->dev,
1189                         "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
1190                         opcode, subcode);
1191                 return 1;
1192         }
1193
1194         return 0;
1195 }
1196 EXPORT_SYMBOL_GPL(octeon_register_dispatch_fn);
1197
1198 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf)
1199 {
1200         u32 i;
1201         char app_name[16];
1202         struct octeon_device *oct = (struct octeon_device *)buf;
1203         struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
1204         struct octeon_core_setup *cs = NULL;
1205         u32 num_nic_ports = 0;
1206
1207         if (OCTEON_CN6XXX(oct))
1208                 num_nic_ports =
1209                         CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx));
1210         else if (OCTEON_CN23XX_PF(oct))
1211                 num_nic_ports =
1212                         CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn23xx_pf));
1213
1214         if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) {
1215                 dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n",
1216                         atomic_read(&oct->status));
1217                 goto core_drv_init_err;
1218         }
1219
1220         strscpy(app_name,
1221                 get_oct_app_string(
1222                 (u32)recv_pkt->rh.r_core_drv_init.app_mode),
1223                 sizeof(app_name));
1224         oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1225         if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) {
1226                 oct->fw_info.max_nic_ports =
1227                         (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports;
1228                 oct->fw_info.num_gmx_ports =
1229                         (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
1230         }
1231
1232         if (oct->fw_info.max_nic_ports < num_nic_ports) {
1233                 dev_err(&oct->pci_dev->dev,
1234                         "Config has more ports than firmware allows (%d > %d).\n",
1235                         num_nic_ports, oct->fw_info.max_nic_ports);
1236                 goto core_drv_init_err;
1237         }
1238         oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
1239         oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1240         oct->pfvf_hsword.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1241
1242         oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind;
1243
1244         for (i = 0; i < oct->num_iqs; i++)
1245                 oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
1246
1247         atomic_set(&oct->status, OCT_DEV_CORE_OK);
1248
1249         cs = &core_setup[oct->octeon_id];
1250
1251         if (recv_pkt->buffer_size[0] != (sizeof(*cs) + OCT_DROQ_INFO_SIZE)) {
1252                 dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n",
1253                         (u32)sizeof(*cs),
1254                         recv_pkt->buffer_size[0]);
1255         }
1256
1257         memcpy(cs, get_rbd(
1258                recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE, sizeof(*cs));
1259
1260         strscpy(oct->boardinfo.name, cs->boardname,
1261                     sizeof(oct->boardinfo.name));
1262         strscpy(oct->boardinfo.serial_number, cs->board_serial_number,
1263                     sizeof(oct->boardinfo.serial_number));
1264
1265         octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3));
1266
1267         oct->boardinfo.major = cs->board_rev_major;
1268         oct->boardinfo.minor = cs->board_rev_minor;
1269
1270         dev_info(&oct->pci_dev->dev,
1271                  "Running %s (%llu Hz)\n",
1272                  app_name, CVM_CAST64(cs->corefreq));
1273
1274 core_drv_init_err:
1275         for (i = 0; i < recv_pkt->buffer_count; i++)
1276                 recv_buffer_free(recv_pkt->buffer_ptr[i]);
1277         octeon_free_recv_info(recv_info);
1278         return 0;
1279 }
1280 EXPORT_SYMBOL_GPL(octeon_core_drv_init);
1281
1282 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no)
1283
1284 {
1285         if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) &&
1286             (oct->io_qmask.iq & BIT_ULL(q_no)))
1287                 return oct->instr_queue[q_no]->max_count;
1288
1289         return -1;
1290 }
1291 EXPORT_SYMBOL_GPL(octeon_get_tx_qsize);
1292
1293 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no)
1294 {
1295         if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) &&
1296             (oct->io_qmask.oq & BIT_ULL(q_no)))
1297                 return oct->droq[q_no]->max_count;
1298         return -1;
1299 }
1300 EXPORT_SYMBOL_GPL(octeon_get_rx_qsize);
1301
1302 /* Retruns the host firmware handshake OCTEON specific configuration */
1303 struct octeon_config *octeon_get_conf(struct octeon_device *oct)
1304 {
1305         struct octeon_config *default_oct_conf = NULL;
1306
1307         /* check the OCTEON Device model & return the corresponding octeon
1308          * configuration
1309          */
1310
1311         if (OCTEON_CN6XXX(oct)) {
1312                 default_oct_conf =
1313                         (struct octeon_config *)(CHIP_CONF(oct, cn6xxx));
1314         } else if (OCTEON_CN23XX_PF(oct)) {
1315                 default_oct_conf = (struct octeon_config *)
1316                         (CHIP_CONF(oct, cn23xx_pf));
1317         } else if (OCTEON_CN23XX_VF(oct)) {
1318                 default_oct_conf = (struct octeon_config *)
1319                         (CHIP_CONF(oct, cn23xx_vf));
1320         }
1321         return default_oct_conf;
1322 }
1323 EXPORT_SYMBOL_GPL(octeon_get_conf);
1324
1325 /* scratch register address is same in all the OCT-II and CN70XX models */
1326 #define CNXX_SLI_SCRATCH1   0x3C0
1327
1328 /* Get the octeon device pointer.
1329  *  @param octeon_id  - The id for which the octeon device pointer is required.
1330  *  @return Success: Octeon device pointer.
1331  *  @return Failure: NULL.
1332  */
1333 struct octeon_device *lio_get_device(u32 octeon_id)
1334 {
1335         if (octeon_id >= MAX_OCTEON_DEVICES)
1336                 return NULL;
1337         else
1338                 return octeon_device[octeon_id];
1339 }
1340 EXPORT_SYMBOL_GPL(lio_get_device);
1341
1342 u64 lio_pci_readq(struct octeon_device *oct, u64 addr)
1343 {
1344         u64 val64;
1345         unsigned long flags;
1346         u32 addrhi;
1347
1348         spin_lock_irqsave(&oct->pci_win_lock, flags);
1349
1350         /* The windowed read happens when the LSB of the addr is written.
1351          * So write MSB first
1352          */
1353         addrhi = (addr >> 32);
1354         if ((oct->chip_id == OCTEON_CN66XX) ||
1355             (oct->chip_id == OCTEON_CN68XX) ||
1356             (oct->chip_id == OCTEON_CN23XX_PF_VID))
1357                 addrhi |= 0x00060000;
1358         writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
1359
1360         /* Read back to preserve ordering of writes */
1361         readl(oct->reg_list.pci_win_rd_addr_hi);
1362
1363         writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
1364         readl(oct->reg_list.pci_win_rd_addr_lo);
1365
1366         val64 = readq(oct->reg_list.pci_win_rd_data);
1367
1368         spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1369
1370         return val64;
1371 }
1372 EXPORT_SYMBOL_GPL(lio_pci_readq);
1373
1374 void lio_pci_writeq(struct octeon_device *oct,
1375                     u64 val,
1376                     u64 addr)
1377 {
1378         unsigned long flags;
1379
1380         spin_lock_irqsave(&oct->pci_win_lock, flags);
1381
1382         writeq(addr, oct->reg_list.pci_win_wr_addr);
1383
1384         /* The write happens when the LSB is written. So write MSB first. */
1385         writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
1386         /* Read the MSB to ensure ordering of writes. */
1387         readl(oct->reg_list.pci_win_wr_data_hi);
1388
1389         writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
1390
1391         spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1392 }
1393 EXPORT_SYMBOL_GPL(lio_pci_writeq);
1394
1395 int octeon_mem_access_ok(struct octeon_device *oct)
1396 {
1397         u64 access_okay = 0;
1398         u64 lmc0_reset_ctl;
1399
1400         /* Check to make sure a DDR interface is enabled */
1401         if (OCTEON_CN23XX_PF(oct)) {
1402                 lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL);
1403                 access_okay =
1404                         (lmc0_reset_ctl & CN23XX_LMC0_RESET_CTL_DDR3RST_MASK);
1405         } else {
1406                 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
1407                 access_okay =
1408                         (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK);
1409         }
1410
1411         return access_okay ? 0 : 1;
1412 }
1413 EXPORT_SYMBOL_GPL(octeon_mem_access_ok);
1414
1415 int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout)
1416 {
1417         int ret = 1;
1418         u32 ms;
1419
1420         if (!timeout)
1421                 return ret;
1422
1423         for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout));
1424              ms += HZ / 10) {
1425                 ret = octeon_mem_access_ok(oct);
1426
1427                 /* wait 100 ms */
1428                 if (ret)
1429                         schedule_timeout_uninterruptible(HZ / 10);
1430         }
1431
1432         return ret;
1433 }
1434 EXPORT_SYMBOL_GPL(octeon_wait_for_ddr_init);
1435
1436 /* Get the octeon id assigned to the octeon device passed as argument.
1437  *  This function is exported to other modules.
1438  *  @param dev - octeon device pointer passed as a void *.
1439  *  @return octeon device id
1440  */
1441 int lio_get_device_id(void *dev)
1442 {
1443         struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1444         u32 i;
1445
1446         for (i = 0; i < MAX_OCTEON_DEVICES; i++)
1447                 if (octeon_device[i] == octeon_dev)
1448                         return octeon_dev->octeon_id;
1449         return -1;
1450 }
1451
1452 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq)
1453 {
1454         u64 instr_cnt;
1455         u32 pkts_pend;
1456         struct octeon_device *oct = NULL;
1457
1458         /* the whole thing needs to be atomic, ideally */
1459         if (droq) {
1460                 pkts_pend = (u32)atomic_read(&droq->pkts_pending);
1461                 writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg);
1462                 droq->pkt_count = pkts_pend;
1463                 oct = droq->oct_dev;
1464         }
1465         if (iq) {
1466                 spin_lock_bh(&iq->lock);
1467                 writel(iq->pkts_processed, iq->inst_cnt_reg);
1468                 iq->pkt_in_done -= iq->pkts_processed;
1469                 iq->pkts_processed = 0;
1470                 /* this write needs to be flushed before we release the lock */
1471                 spin_unlock_bh(&iq->lock);
1472                 oct = iq->oct_dev;
1473         }
1474         /*write resend. Writing RESEND in SLI_PKTX_CNTS should be enough
1475          *to trigger tx interrupts as well, if they are pending.
1476          */
1477         if (oct && (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))) {
1478                 if (droq)
1479                         writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg);
1480                 /*we race with firmrware here. read and write the IN_DONE_CNTS*/
1481                 else if (iq) {
1482                         instr_cnt =  readq(iq->inst_cnt_reg);
1483                         writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) |
1484                                 CN23XX_INTR_RESEND),
1485                                iq->inst_cnt_reg);
1486                 }
1487         }
1488 }
1489 EXPORT_SYMBOL_GPL(lio_enable_irq);