drivers/gpu/drm/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31
  32 #include <drm/drm_device.h>
  33 #include <drm/drm_file.h>
  34
  35 #include "atom.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "rv515_reg_safe.h"
  39 #include "rv515d.h"
  40
  41 /* This files gather functions specifics to: rv515 */
  42 static void rv515_gpu_init(struct radeon_device *rdev);
  43 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  44
  45 static const u32 crtc_offsets[2] = {
  46         0,
  47         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  48 };
  49
  50 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
  51 {
  52         int r;
  53
  54         r = radeon_ring_lock(rdev, ring, 64);
  55         if (r) {
  56                 return;
  57         }
  58         radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
  59         radeon_ring_write(ring,
  60                           ISYNC_ANY2D_IDLE3D |
  61                           ISYNC_ANY3D_IDLE2D |
  62                           ISYNC_WAIT_IDLEGUI |
  63                           ISYNC_CPSCRATCH_IDLEGUI);
  64         radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  65         radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  66         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
  67         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
  68         radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
  69         radeon_ring_write(ring, 0);
  70         radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
  71         radeon_ring_write(ring, 0);
  72         radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
  73         radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
  74         radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
  75         radeon_ring_write(ring, 0);
  76         radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  77         radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  78         radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  79         radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  80         radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  81         radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  82         radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
  83         radeon_ring_write(ring, 0);
  84         radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  85         radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  86         radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  87         radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  88         radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
  89         radeon_ring_write(ring,
  90                           ((6 << MS_X0_SHIFT) |
  91                            (6 << MS_Y0_SHIFT) |
  92                            (6 << MS_X1_SHIFT) |
  93                            (6 << MS_Y1_SHIFT) |
  94                            (6 << MS_X2_SHIFT) |
  95                            (6 << MS_Y2_SHIFT) |
  96                            (6 << MSBD0_Y_SHIFT) |
  97                            (6 << MSBD0_X_SHIFT)));
  98         radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
  99         radeon_ring_write(ring,
 100                           ((6 << MS_X3_SHIFT) |
 101                            (6 << MS_Y3_SHIFT) |
 102                            (6 << MS_X4_SHIFT) |
 103                            (6 << MS_Y4_SHIFT) |
 104                            (6 << MS_X5_SHIFT) |
 105                            (6 << MS_Y5_SHIFT) |
 106                            (6 << MSBD1_SHIFT)));
 107         radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
 108         radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 109         radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
 110         radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 111         radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
 112         radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 113         radeon_ring_write(ring, PACKET0(0x20C8, 0));
 114         radeon_ring_write(ring, 0);
 115         radeon_ring_unlock_commit(rdev, ring, false);
 116 }
 117
 118 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 119 {
 120         unsigned i;
 121         uint32_t tmp;
 122
 123         for (i = 0; i < rdev->usec_timeout; i++) {
 124                 /* read MC_STATUS */
 125                 tmp = RREG32_MC(MC_STATUS);
 126                 if (tmp & MC_STATUS_IDLE) {
 127                         return 0;
 128                 }
 129                 udelay(1);
 130         }
 131         return -1;
 132 }
 133
 134 void rv515_vga_render_disable(struct radeon_device *rdev)
 135 {
 136         WREG32(R_000300_VGA_RENDER_CONTROL,
 137                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 138 }
 139
 140 static void rv515_gpu_init(struct radeon_device *rdev)
 141 {
 142         unsigned pipe_select_current, gb_pipe_select, tmp;
 143
 144         if (r100_gui_wait_for_idle(rdev)) {
 145                 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
 146         }
 147         rv515_vga_render_disable(rdev);
 148         r420_pipes_init(rdev);
 149         gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
 150         tmp = RREG32(R300_DST_PIPE_CONFIG);
 151         pipe_select_current = (tmp >> 2) & 3;
 152         tmp = (1 << pipe_select_current) |
 153               (((gb_pipe_select >> 8) & 0xF) << 4);
 154         WREG32_PLL(0x000D, tmp);
 155         if (r100_gui_wait_for_idle(rdev)) {
 156                 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
 157         }
 158         if (rv515_mc_wait_for_idle(rdev)) {
 159                 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
 160         }
 161 }
 162
 163 static void rv515_vram_get_type(struct radeon_device *rdev)
 164 {
 165         uint32_t tmp;
 166
 167         rdev->mc.vram_width = 128;
 168         rdev->mc.vram_is_ddr = true;
 169         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 170         switch (tmp) {
 171         case 0:
 172                 rdev->mc.vram_width = 64;
 173                 break;
 174         case 1:
 175                 rdev->mc.vram_width = 128;
 176                 break;
 177         default:
 178                 rdev->mc.vram_width = 128;
 179                 break;
 180         }
 181 }
 182
 183 static void rv515_mc_init(struct radeon_device *rdev)
 184 {
 185
 186         rv515_vram_get_type(rdev);
 187         r100_vram_init_sizes(rdev);
 188         radeon_vram_location(rdev, &rdev->mc, 0);
 189         rdev->mc.gtt_base_align = 0;
 190         if (!(rdev->flags & RADEON_IS_AGP))
 191                 radeon_gtt_location(rdev, &rdev->mc);
 192         radeon_update_bandwidth_info(rdev);
 193 }
 194
 195 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 196 {
 197         unsigned long flags;
 198         uint32_t r;
 199
 200         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 201         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 202         r = RREG32(MC_IND_DATA);
 203         WREG32(MC_IND_INDEX, 0);
 204         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 205
 206         return r;
 207 }
 208
 209 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 210 {
 211         unsigned long flags;
 212
 213         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 214         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 215         WREG32(MC_IND_DATA, (v));
 216         WREG32(MC_IND_INDEX, 0);
 217         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 218 }
 219
 220 #if defined(CONFIG_DEBUG_FS)
 221 static int rv515_debugfs_pipes_info_show(struct seq_file *m, void *unused)
 222 {
 223         struct radeon_device *rdev = m->private;
 224         uint32_t tmp;
 225
 226         tmp = RREG32(GB_PIPE_SELECT);
 227         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 228         tmp = RREG32(SU_REG_DEST);
 229         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 230         tmp = RREG32(GB_TILE_CONFIG);
 231         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 232         tmp = RREG32(DST_PIPE_CONFIG);
 233         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 234         return 0;
 235 }
 236
 237 static int rv515_debugfs_ga_info_show(struct seq_file *m, void *unused)
 238 {
 239         struct radeon_device *rdev = m->private;
 240         uint32_t tmp;
 241
 242         tmp = RREG32(0x2140);
 243         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 244         radeon_asic_reset(rdev);
 245         tmp = RREG32(0x425C);
 246         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 247         return 0;
 248 }
 249
 250 DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_pipes_info);
 251 DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_ga_info);
 252 #endif
 253
 254 void rv515_debugfs(struct radeon_device *rdev)
 255 {
 256 #if defined(CONFIG_DEBUG_FS)
 257         struct dentry *root = rdev->ddev->primary->debugfs_root;
 258
 259         debugfs_create_file("rv515_pipes_info", 0444, root, rdev,
 260                             &rv515_debugfs_pipes_info_fops);
 261         debugfs_create_file("rv515_ga_info", 0444, root, rdev,
 262                             &rv515_debugfs_ga_info_fops);
 263 #endif
 264         r100_debugfs_rbbm_init(rdev);
 265 }
 266
 267 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
 268 {
 269         u32 crtc_enabled, tmp, frame_count, blackout;
 270         int i, j;
 271
 272         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
 273         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
 274
 275         /* disable VGA render */
 276         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
 277         /* blank the display controllers */
 278         for (i = 0; i < rdev->num_crtc; i++) {
 279                 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
 280                 if (crtc_enabled) {
 281                         save->crtc_enabled[i] = true;
 282                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 283                         if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
 284                                 radeon_wait_for_vblank(rdev, i);
 285                                 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 286                                 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 287                                 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 288                                 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 289                         }
 290                         /* wait for the next frame */
 291                         frame_count = radeon_get_vblank_counter(rdev, i);
 292                         for (j = 0; j < rdev->usec_timeout; j++) {
 293                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
 294                                         break;
 295                                 udelay(1);
 296                         }
 297
 298                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 299                         WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 300                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 301                         tmp &= ~AVIVO_CRTC_EN;
 302                         WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 303                         WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 304                         save->crtc_enabled[i] = false;
 305                         /* ***** */
 306                 } else {
 307                         save->crtc_enabled[i] = false;
 308                 }
 309         }
 310
 311         radeon_mc_wait_for_idle(rdev);
 312
 313         if (rdev->family >= CHIP_R600) {
 314                 if (rdev->family >= CHIP_RV770)
 315                         blackout = RREG32(R700_MC_CITF_CNTL);
 316                 else
 317                         blackout = RREG32(R600_CITF_CNTL);
 318                 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
 319                         /* Block CPU access */
 320                         WREG32(R600_BIF_FB_EN, 0);
 321                         /* blackout the MC */
 322                         blackout |= R600_BLACKOUT_MASK;
 323                         if (rdev->family >= CHIP_RV770)
 324                                 WREG32(R700_MC_CITF_CNTL, blackout);
 325                         else
 326                                 WREG32(R600_CITF_CNTL, blackout);
 327                 }
 328         }
 329         /* wait for the MC to settle */
 330         udelay(100);
 331
 332         /* lock double buffered regs */
 333         for (i = 0; i < rdev->num_crtc; i++) {
 334                 if (save->crtc_enabled[i]) {
 335                         tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 336                         if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
 337                                 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 338                                 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
 339                         }
 340                         tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 341                         if (!(tmp & 1)) {
 342                                 tmp |= 1;
 343                                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 344                         }
 345                 }
 346         }
 347 }
 348
 349 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 350 {
 351         u32 tmp, frame_count;
 352         int i, j;
 353
 354         /* update crtc base addresses */
 355         for (i = 0; i < rdev->num_crtc; i++) {
 356                 if (rdev->family >= CHIP_RV770) {
 357                         if (i == 0) {
 358                                 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
 359                                        upper_32_bits(rdev->mc.vram_start));
 360                                 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
 361                                        upper_32_bits(rdev->mc.vram_start));
 362                         } else {
 363                                 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
 364                                        upper_32_bits(rdev->mc.vram_start));
 365                                 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
 366                                        upper_32_bits(rdev->mc.vram_start));
 367                         }
 368                 }
 369                 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 370                        (u32)rdev->mc.vram_start);
 371                 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 372                        (u32)rdev->mc.vram_start);
 373         }
 374         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 375
 376         /* unlock regs and wait for update */
 377         for (i = 0; i < rdev->num_crtc; i++) {
 378                 if (save->crtc_enabled[i]) {
 379                         tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
 380                         if ((tmp & 0x7) != 3) {
 381                                 tmp &= ~0x7;
 382                                 tmp |= 0x3;
 383                                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 384                         }
 385                         tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 386                         if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
 387                                 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 388                                 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
 389                         }
 390                         tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 391                         if (tmp & 1) {
 392                                 tmp &= ~1;
 393                                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 394                         }
 395                         for (j = 0; j < rdev->usec_timeout; j++) {
 396                                 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 397                                 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
 398                                         break;
 399                                 udelay(1);
 400                         }
 401                 }
 402         }
 403
 404         if (rdev->family >= CHIP_R600) {
 405                 /* unblackout the MC */
 406                 if (rdev->family >= CHIP_RV770)
 407                         tmp = RREG32(R700_MC_CITF_CNTL);
 408                 else
 409                         tmp = RREG32(R600_CITF_CNTL);
 410                 tmp &= ~R600_BLACKOUT_MASK;
 411                 if (rdev->family >= CHIP_RV770)
 412                         WREG32(R700_MC_CITF_CNTL, tmp);
 413                 else
 414                         WREG32(R600_CITF_CNTL, tmp);
 415                 /* allow CPU access */
 416                 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
 417         }
 418
 419         for (i = 0; i < rdev->num_crtc; i++) {
 420                 if (save->crtc_enabled[i]) {
 421                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 422                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 423                         WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 424                         /* wait for the next frame */
 425                         frame_count = radeon_get_vblank_counter(rdev, i);
 426                         for (j = 0; j < rdev->usec_timeout; j++) {
 427                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
 428                                         break;
 429                                 udelay(1);
 430                         }
 431                 }
 432         }
 433         /* Unlock vga access */
 434         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
 435         mdelay(1);
 436         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 437 }
 438
 439 static void rv515_mc_program(struct radeon_device *rdev)
 440 {
 441         struct rv515_mc_save save;
 442
 443         /* Stops all mc clients */
 444         rv515_mc_stop(rdev, &save);
 445
 446         /* Wait for mc idle */
 447         if (rv515_mc_wait_for_idle(rdev))
 448                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 449         /* Write VRAM size in case we are limiting it */
 450         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 451         /* Program MC, should be a 32bits limited address space */
 452         WREG32_MC(R_000001_MC_FB_LOCATION,
 453                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
 454                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
 455         WREG32(R_000134_HDP_FB_LOCATION,
 456                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 457         if (rdev->flags & RADEON_IS_AGP) {
 458                 WREG32_MC(R_000002_MC_AGP_LOCATION,
 459                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 460                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 461                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 462                 WREG32_MC(R_000004_MC_AGP_BASE_2,
 463                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
 464         } else {
 465                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
 466                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
 467                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
 468         }
 469
 470         rv515_mc_resume(rdev, &save);
 471 }
 472
 473 void rv515_clock_startup(struct radeon_device *rdev)
 474 {
 475         if (radeon_dynclks != -1 && radeon_dynclks)
 476                 radeon_atom_set_clock_gating(rdev, 1);
 477         /* We need to force on some of the block */
 478         WREG32_PLL(R_00000F_CP_DYN_CNTL,
 479                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
 480         WREG32_PLL(R_000011_E2_DYN_CNTL,
 481                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
 482         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
 483                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
 484 }
 485
 486 static int rv515_startup(struct radeon_device *rdev)
 487 {
 488         int r;
 489
 490         rv515_mc_program(rdev);
 491         /* Resume clock */
 492         rv515_clock_startup(rdev);
 493         /* Initialize GPU configuration (# pipes, ...) */
 494         rv515_gpu_init(rdev);
 495         /* Initialize GART (initialize after TTM so we can allocate
 496          * memory through TTM but finalize after TTM) */
 497         if (rdev->flags & RADEON_IS_PCIE) {
 498                 r = rv370_pcie_gart_enable(rdev);
 499                 if (r)
 500                         return r;
 501         }
 502
 503         /* allocate wb buffer */
 504         r = radeon_wb_init(rdev);
 505         if (r)
 506                 return r;
 507
 508         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 509         if (r) {
 510                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 511                 return r;
 512         }
 513
 514         /* Enable IRQ */
 515         if (!rdev->irq.installed) {
 516                 r = radeon_irq_kms_init(rdev);
 517                 if (r)
 518                         return r;
 519         }
 520
 521         rs600_irq_set(rdev);
 522         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 523         /* 1M ring buffer */
 524         r = r100_cp_init(rdev, 1024 * 1024);
 525         if (r) {
 526                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 527                 return r;
 528         }
 529
 530         r = radeon_ib_pool_init(rdev);
 531         if (r) {
 532                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 533                 return r;
 534         }
 535
 536         return 0;
 537 }
 538
 539 int rv515_resume(struct radeon_device *rdev)
 540 {
 541         int r;
 542
 543         /* Make sur GART are not working */
 544         if (rdev->flags & RADEON_IS_PCIE)
 545                 rv370_pcie_gart_disable(rdev);
 546         /* Resume clock before doing reset */
 547         rv515_clock_startup(rdev);
 548         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 549         if (radeon_asic_reset(rdev)) {
 550                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 551                         RREG32(R_000E40_RBBM_STATUS),
 552                         RREG32(R_0007C0_CP_STAT));
 553         }
 554         /* post */
 555         atom_asic_init(rdev->mode_info.atom_context);
 556         /* Resume clock after posting */
 557         rv515_clock_startup(rdev);
 558         /* Initialize surface registers */
 559         radeon_surface_init(rdev);
 560
 561         rdev->accel_working = true;
 562         r =  rv515_startup(rdev);
 563         if (r) {
 564                 rdev->accel_working = false;
 565         }
 566         return r;
 567 }
 568
 569 int rv515_suspend(struct radeon_device *rdev)
 570 {
 571         radeon_pm_suspend(rdev);
 572         r100_cp_disable(rdev);
 573         radeon_wb_disable(rdev);
 574         rs600_irq_disable(rdev);
 575         if (rdev->flags & RADEON_IS_PCIE)
 576                 rv370_pcie_gart_disable(rdev);
 577         return 0;
 578 }
 579
 580 void rv515_set_safe_registers(struct radeon_device *rdev)
 581 {
 582         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 583         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 584 }
 585
 586 void rv515_fini(struct radeon_device *rdev)
 587 {
 588         radeon_pm_fini(rdev);
 589         r100_cp_fini(rdev);
 590         radeon_wb_fini(rdev);
 591         radeon_ib_pool_fini(rdev);
 592         radeon_gem_fini(rdev);
 593         rv370_pcie_gart_fini(rdev);
 594         radeon_agp_fini(rdev);
 595         radeon_irq_kms_fini(rdev);
 596         radeon_fence_driver_fini(rdev);
 597         radeon_bo_fini(rdev);
 598         radeon_atombios_fini(rdev);
 599         kfree(rdev->bios);
 600         rdev->bios = NULL;
 601 }
 602
 603 int rv515_init(struct radeon_device *rdev)
 604 {
 605         int r;
 606
 607         /* Initialize scratch registers */
 608         radeon_scratch_init(rdev);
 609         /* Initialize surface registers */
 610         radeon_surface_init(rdev);
 611         /* TODO: disable VGA need to use VGA request */
 612         /* restore some register to sane defaults */
 613         r100_restore_sanity(rdev);
 614         /* BIOS*/
 615         if (!radeon_get_bios(rdev)) {
 616                 if (ASIC_IS_AVIVO(rdev))
 617                         return -EINVAL;
 618         }
 619         if (rdev->is_atom_bios) {
 620                 r = radeon_atombios_init(rdev);
 621                 if (r)
 622                         return r;
 623         } else {
 624                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 625                 return -EINVAL;
 626         }
 627         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 628         if (radeon_asic_reset(rdev)) {
 629                 dev_warn(rdev->dev,
 630                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 631                         RREG32(R_000E40_RBBM_STATUS),
 632                         RREG32(R_0007C0_CP_STAT));
 633         }
 634         /* check if cards are posted or not */
 635         if (radeon_boot_test_post_card(rdev) == false)
 636                 return -EINVAL;
 637         /* Initialize clocks */
 638         radeon_get_clock_info(rdev->ddev);
 639         /* initialize AGP */
 640         if (rdev->flags & RADEON_IS_AGP) {
 641                 r = radeon_agp_init(rdev);
 642                 if (r) {
 643                         radeon_agp_disable(rdev);
 644                 }
 645         }
 646         /* initialize memory controller */
 647         rv515_mc_init(rdev);
 648         rv515_debugfs(rdev);
 649         /* Fence driver */
 650         radeon_fence_driver_init(rdev);
 651         /* Memory manager */
 652         r = radeon_bo_init(rdev);
 653         if (r)
 654                 return r;
 655         r = rv370_pcie_gart_init(rdev);
 656         if (r)
 657                 return r;
 658         rv515_set_safe_registers(rdev);
 659
 660         /* Initialize power management */
 661         radeon_pm_init(rdev);
 662
 663         rdev->accel_working = true;
 664         r = rv515_startup(rdev);
 665         if (r) {
 666                 /* Somethings want wront with the accel init stop accel */
 667                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 668                 r100_cp_fini(rdev);
 669                 radeon_wb_fini(rdev);
 670                 radeon_ib_pool_fini(rdev);
 671                 radeon_irq_kms_fini(rdev);
 672                 rv370_pcie_gart_fini(rdev);
 673                 radeon_agp_fini(rdev);
 674                 rdev->accel_working = false;
 675         }
 676         return 0;
 677 }
 678
 679 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 680 {
 681         int index_reg = 0x6578 + crtc->crtc_offset;
 682         int data_reg = 0x657c + crtc->crtc_offset;
 683
 684         WREG32(0x659C + crtc->crtc_offset, 0x0);
 685         WREG32(0x6594 + crtc->crtc_offset, 0x705);
 686         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
 687         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
 688         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
 689         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
 690         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
 691         WREG32(index_reg, 0x0);
 692         WREG32(data_reg, 0x841880A8);
 693         WREG32(index_reg, 0x1);
 694         WREG32(data_reg, 0x84208680);
 695         WREG32(index_reg, 0x2);
 696         WREG32(data_reg, 0xBFF880B0);
 697         WREG32(index_reg, 0x100);
 698         WREG32(data_reg, 0x83D88088);
 699         WREG32(index_reg, 0x101);
 700         WREG32(data_reg, 0x84608680);
 701         WREG32(index_reg, 0x102);
 702         WREG32(data_reg, 0xBFF080D0);
 703         WREG32(index_reg, 0x200);
 704         WREG32(data_reg, 0x83988068);
 705         WREG32(index_reg, 0x201);
 706         WREG32(data_reg, 0x84A08680);
 707         WREG32(index_reg, 0x202);
 708         WREG32(data_reg, 0xBFF080F8);
 709         WREG32(index_reg, 0x300);
 710         WREG32(data_reg, 0x83588058);
 711         WREG32(index_reg, 0x301);
 712         WREG32(data_reg, 0x84E08660);
 713         WREG32(index_reg, 0x302);
 714         WREG32(data_reg, 0xBFF88120);
 715         WREG32(index_reg, 0x400);
 716         WREG32(data_reg, 0x83188040);
 717         WREG32(index_reg, 0x401);
 718         WREG32(data_reg, 0x85008660);
 719         WREG32(index_reg, 0x402);
 720         WREG32(data_reg, 0xBFF88150);
 721         WREG32(index_reg, 0x500);
 722         WREG32(data_reg, 0x82D88030);
 723         WREG32(index_reg, 0x501);
 724         WREG32(data_reg, 0x85408640);
 725         WREG32(index_reg, 0x502);
 726         WREG32(data_reg, 0xBFF88180);
 727         WREG32(index_reg, 0x600);
 728         WREG32(data_reg, 0x82A08018);
 729         WREG32(index_reg, 0x601);
 730         WREG32(data_reg, 0x85808620);
 731         WREG32(index_reg, 0x602);
 732         WREG32(data_reg, 0xBFF081B8);
 733         WREG32(index_reg, 0x700);
 734         WREG32(data_reg, 0x82608010);
 735         WREG32(index_reg, 0x701);
 736         WREG32(data_reg, 0x85A08600);
 737         WREG32(index_reg, 0x702);
 738         WREG32(data_reg, 0x800081F0);
 739         WREG32(index_reg, 0x800);
 740         WREG32(data_reg, 0x8228BFF8);
 741         WREG32(index_reg, 0x801);
 742         WREG32(data_reg, 0x85E085E0);
 743         WREG32(index_reg, 0x802);
 744         WREG32(data_reg, 0xBFF88228);
 745         WREG32(index_reg, 0x10000);
 746         WREG32(data_reg, 0x82A8BF00);
 747         WREG32(index_reg, 0x10001);
 748         WREG32(data_reg, 0x82A08CC0);
 749         WREG32(index_reg, 0x10002);
 750         WREG32(data_reg, 0x8008BEF8);
 751         WREG32(index_reg, 0x10100);
 752         WREG32(data_reg, 0x81F0BF28);
 753         WREG32(index_reg, 0x10101);
 754         WREG32(data_reg, 0x83608CA0);
 755         WREG32(index_reg, 0x10102);
 756         WREG32(data_reg, 0x8018BED0);
 757         WREG32(index_reg, 0x10200);
 758         WREG32(data_reg, 0x8148BF38);
 759         WREG32(index_reg, 0x10201);
 760         WREG32(data_reg, 0x84408C80);
 761         WREG32(index_reg, 0x10202);
 762         WREG32(data_reg, 0x8008BEB8);
 763         WREG32(index_reg, 0x10300);
 764         WREG32(data_reg, 0x80B0BF78);
 765         WREG32(index_reg, 0x10301);
 766         WREG32(data_reg, 0x85008C20);
 767         WREG32(index_reg, 0x10302);
 768         WREG32(data_reg, 0x8020BEA0);
 769         WREG32(index_reg, 0x10400);
 770         WREG32(data_reg, 0x8028BF90);
 771         WREG32(index_reg, 0x10401);
 772         WREG32(data_reg, 0x85E08BC0);
 773         WREG32(index_reg, 0x10402);
 774         WREG32(data_reg, 0x8018BE90);
 775         WREG32(index_reg, 0x10500);
 776         WREG32(data_reg, 0xBFB8BFB0);
 777         WREG32(index_reg, 0x10501);
 778         WREG32(data_reg, 0x86C08B40);
 779         WREG32(index_reg, 0x10502);
 780         WREG32(data_reg, 0x8010BE90);
 781         WREG32(index_reg, 0x10600);
 782         WREG32(data_reg, 0xBF58BFC8);
 783         WREG32(index_reg, 0x10601);
 784         WREG32(data_reg, 0x87A08AA0);
 785         WREG32(index_reg, 0x10602);
 786         WREG32(data_reg, 0x8010BE98);
 787         WREG32(index_reg, 0x10700);
 788         WREG32(data_reg, 0xBF10BFF0);
 789         WREG32(index_reg, 0x10701);
 790         WREG32(data_reg, 0x886089E0);
 791         WREG32(index_reg, 0x10702);
 792         WREG32(data_reg, 0x8018BEB0);
 793         WREG32(index_reg, 0x10800);
 794         WREG32(data_reg, 0xBED8BFE8);
 795         WREG32(index_reg, 0x10801);
 796         WREG32(data_reg, 0x89408940);
 797         WREG32(index_reg, 0x10802);
 798         WREG32(data_reg, 0xBFE8BED8);
 799         WREG32(index_reg, 0x20000);
 800         WREG32(data_reg, 0x80008000);
 801         WREG32(index_reg, 0x20001);
 802         WREG32(data_reg, 0x90008000);
 803         WREG32(index_reg, 0x20002);
 804         WREG32(data_reg, 0x80008000);
 805         WREG32(index_reg, 0x20003);
 806         WREG32(data_reg, 0x80008000);
 807         WREG32(index_reg, 0x20100);
 808         WREG32(data_reg, 0x80108000);
 809         WREG32(index_reg, 0x20101);
 810         WREG32(data_reg, 0x8FE0BF70);
 811         WREG32(index_reg, 0x20102);
 812         WREG32(data_reg, 0xBFE880C0);
 813         WREG32(index_reg, 0x20103);
 814         WREG32(data_reg, 0x80008000);
 815         WREG32(index_reg, 0x20200);
 816         WREG32(data_reg, 0x8018BFF8);
 817         WREG32(index_reg, 0x20201);
 818         WREG32(data_reg, 0x8F80BF08);
 819         WREG32(index_reg, 0x20202);
 820         WREG32(data_reg, 0xBFD081A0);
 821         WREG32(index_reg, 0x20203);
 822         WREG32(data_reg, 0xBFF88000);
 823         WREG32(index_reg, 0x20300);
 824         WREG32(data_reg, 0x80188000);
 825         WREG32(index_reg, 0x20301);
 826         WREG32(data_reg, 0x8EE0BEC0);
 827         WREG32(index_reg, 0x20302);
 828         WREG32(data_reg, 0xBFB082A0);
 829         WREG32(index_reg, 0x20303);
 830         WREG32(data_reg, 0x80008000);
 831         WREG32(index_reg, 0x20400);
 832         WREG32(data_reg, 0x80188000);
 833         WREG32(index_reg, 0x20401);
 834         WREG32(data_reg, 0x8E00BEA0);
 835         WREG32(index_reg, 0x20402);
 836         WREG32(data_reg, 0xBF8883C0);
 837         WREG32(index_reg, 0x20403);
 838         WREG32(data_reg, 0x80008000);
 839         WREG32(index_reg, 0x20500);
 840         WREG32(data_reg, 0x80188000);
 841         WREG32(index_reg, 0x20501);
 842         WREG32(data_reg, 0x8D00BE90);
 843         WREG32(index_reg, 0x20502);
 844         WREG32(data_reg, 0xBF588500);
 845         WREG32(index_reg, 0x20503);
 846         WREG32(data_reg, 0x80008008);
 847         WREG32(index_reg, 0x20600);
 848         WREG32(data_reg, 0x80188000);
 849         WREG32(index_reg, 0x20601);
 850         WREG32(data_reg, 0x8BC0BE98);
 851         WREG32(index_reg, 0x20602);
 852         WREG32(data_reg, 0xBF308660);
 853         WREG32(index_reg, 0x20603);
 854         WREG32(data_reg, 0x80008008);
 855         WREG32(index_reg, 0x20700);
 856         WREG32(data_reg, 0x80108000);
 857         WREG32(index_reg, 0x20701);
 858         WREG32(data_reg, 0x8A80BEB0);
 859         WREG32(index_reg, 0x20702);
 860         WREG32(data_reg, 0xBF0087C0);
 861         WREG32(index_reg, 0x20703);
 862         WREG32(data_reg, 0x80008008);
 863         WREG32(index_reg, 0x20800);
 864         WREG32(data_reg, 0x80108000);
 865         WREG32(index_reg, 0x20801);
 866         WREG32(data_reg, 0x8920BED0);
 867         WREG32(index_reg, 0x20802);
 868         WREG32(data_reg, 0xBED08920);
 869         WREG32(index_reg, 0x20803);
 870         WREG32(data_reg, 0x80008010);
 871         WREG32(index_reg, 0x30000);
 872         WREG32(data_reg, 0x90008000);
 873         WREG32(index_reg, 0x30001);
 874         WREG32(data_reg, 0x80008000);
 875         WREG32(index_reg, 0x30100);
 876         WREG32(data_reg, 0x8FE0BF90);
 877         WREG32(index_reg, 0x30101);
 878         WREG32(data_reg, 0xBFF880A0);
 879         WREG32(index_reg, 0x30200);
 880         WREG32(data_reg, 0x8F60BF40);
 881         WREG32(index_reg, 0x30201);
 882         WREG32(data_reg, 0xBFE88180);
 883         WREG32(index_reg, 0x30300);
 884         WREG32(data_reg, 0x8EC0BF00);
 885         WREG32(index_reg, 0x30301);
 886         WREG32(data_reg, 0xBFC88280);
 887         WREG32(index_reg, 0x30400);
 888         WREG32(data_reg, 0x8DE0BEE0);
 889         WREG32(index_reg, 0x30401);
 890         WREG32(data_reg, 0xBFA083A0);
 891         WREG32(index_reg, 0x30500);
 892         WREG32(data_reg, 0x8CE0BED0);
 893         WREG32(index_reg, 0x30501);
 894         WREG32(data_reg, 0xBF7884E0);
 895         WREG32(index_reg, 0x30600);
 896         WREG32(data_reg, 0x8BA0BED8);
 897         WREG32(index_reg, 0x30601);
 898         WREG32(data_reg, 0xBF508640);
 899         WREG32(index_reg, 0x30700);
 900         WREG32(data_reg, 0x8A60BEE8);
 901         WREG32(index_reg, 0x30701);
 902         WREG32(data_reg, 0xBF2087A0);
 903         WREG32(index_reg, 0x30800);
 904         WREG32(data_reg, 0x8900BF00);
 905         WREG32(index_reg, 0x30801);
 906         WREG32(data_reg, 0xBF008900);
 907 }
 908
 909 struct rv515_watermark {
 910         u32        lb_request_fifo_depth;
 911         fixed20_12 num_line_pair;
 912         fixed20_12 estimated_width;
 913         fixed20_12 worst_case_latency;
 914         fixed20_12 consumption_rate;
 915         fixed20_12 active_time;
 916         fixed20_12 dbpp;
 917         fixed20_12 priority_mark_max;
 918         fixed20_12 priority_mark;
 919         fixed20_12 sclk;
 920 };
 921
 922 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 923                                          struct radeon_crtc *crtc,
 924                                          struct rv515_watermark *wm,
 925                                          bool low)
 926 {
 927         struct drm_display_mode *mode = &crtc->base.mode;
 928         fixed20_12 a, b, c;
 929         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 930         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 931         fixed20_12 sclk;
 932         u32 selected_sclk;
 933
 934         if (!crtc->base.enabled) {
 935                 /* FIXME: wouldn't it better to set priority mark to maximum */
 936                 wm->lb_request_fifo_depth = 4;
 937                 return;
 938         }
 939
 940         /* rv6xx, rv7xx */
 941         if ((rdev->family >= CHIP_RV610) &&
 942             (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
 943                 selected_sclk = radeon_dpm_get_sclk(rdev, low);
 944         else
 945                 selected_sclk = rdev->pm.current_sclk;
 946
 947         /* sclk in Mhz */
 948         a.full = dfixed_const(100);
 949         sclk.full = dfixed_const(selected_sclk);
 950         sclk.full = dfixed_div(sclk, a);
 951
 952         if (crtc->vsc.full > dfixed_const(2))
 953                 wm->num_line_pair.full = dfixed_const(2);
 954         else
 955                 wm->num_line_pair.full = dfixed_const(1);
 956
 957         b.full = dfixed_const(mode->crtc_hdisplay);
 958         c.full = dfixed_const(256);
 959         a.full = dfixed_div(b, c);
 960         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 961         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 962         if (a.full < dfixed_const(4)) {
 963                 wm->lb_request_fifo_depth = 4;
 964         } else {
 965                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 966         }
 967
 968         /* Determine consumption rate
 969          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 970          *  vtaps = number of vertical taps,
 971          *  vsc = vertical scaling ratio, defined as source/destination
 972          *  hsc = horizontal scaling ration, defined as source/destination
 973          */
 974         a.full = dfixed_const(mode->clock);
 975         b.full = dfixed_const(1000);
 976         a.full = dfixed_div(a, b);
 977         pclk.full = dfixed_div(b, a);
 978         if (crtc->rmx_type != RMX_OFF) {
 979                 b.full = dfixed_const(2);
 980                 if (crtc->vsc.full > b.full)
 981                         b.full = crtc->vsc.full;
 982                 b.full = dfixed_mul(b, crtc->hsc);
 983                 c.full = dfixed_const(2);
 984                 b.full = dfixed_div(b, c);
 985                 consumption_time.full = dfixed_div(pclk, b);
 986         } else {
 987                 consumption_time.full = pclk.full;
 988         }
 989         a.full = dfixed_const(1);
 990         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 991
 992
 993         /* Determine line time
 994          *  LineTime = total time for one line of displayhtotal
 995          *  LineTime = total number of horizontal pixels
 996          *  pclk = pixel clock period(ns)
 997          */
 998         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 999         line_time.full = dfixed_mul(a, pclk);
1000
1001         /* Determine active time
1002          *  ActiveTime = time of active region of display within one line,
1003          *  hactive = total number of horizontal active pixels
1004          *  htotal = total number of horizontal pixels
1005          */
1006         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1007         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1008         wm->active_time.full = dfixed_mul(line_time, b);
1009         wm->active_time.full = dfixed_div(wm->active_time, a);
1010
1011         /* Determine chunk time
1012          * ChunkTime = the time it takes the DCP to send one chunk of data
1013          * to the LB which consists of pipeline delay and inter chunk gap
1014          * sclk = system clock(Mhz)
1015          */
1016         a.full = dfixed_const(600 * 1000);
1017         chunk_time.full = dfixed_div(a, sclk);
1018         read_delay_latency.full = dfixed_const(1000);
1019
1020         /* Determine the worst case latency
1021          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1022          * WorstCaseLatency = worst case time from urgent to when the MC starts
1023          *                    to return data
1024          * READ_DELAY_IDLE_MAX = constant of 1us
1025          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1026          *             which consists of pipeline delay and inter chunk gap
1027          */
1028         if (dfixed_trunc(wm->num_line_pair) > 1) {
1029                 a.full = dfixed_const(3);
1030                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1031                 wm->worst_case_latency.full += read_delay_latency.full;
1032         } else {
1033                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1034         }
1035
1036         /* Determine the tolerable latency
1037          * TolerableLatency = Any given request has only 1 line time
1038          *                    for the data to be returned
1039          * LBRequestFifoDepth = Number of chunk requests the LB can
1040          *                      put into the request FIFO for a display
1041          *  LineTime = total time for one line of display
1042          *  ChunkTime = the time it takes the DCP to send one chunk
1043          *              of data to the LB which consists of
1044          *  pipeline delay and inter chunk gap
1045          */
1046         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1047                 tolerable_latency.full = line_time.full;
1048         } else {
1049                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1050                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1051                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1052                 tolerable_latency.full = line_time.full - tolerable_latency.full;
1053         }
1054         /* We assume worst case 32bits (4 bytes) */
1055         wm->dbpp.full = dfixed_const(2 * 16);
1056
1057         /* Determine the maximum priority mark
1058          *  width = viewport width in pixels
1059          */
1060         a.full = dfixed_const(16);
1061         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1062         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1063         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1064
1065         /* Determine estimated width */
1066         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1067         estimated_width.full = dfixed_div(estimated_width, consumption_time);
1068         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1069                 wm->priority_mark.full = wm->priority_mark_max.full;
1070         } else {
1071                 a.full = dfixed_const(16);
1072                 wm->priority_mark.full = dfixed_div(estimated_width, a);
1073                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1074                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1075         }
1076 }
1077
1078 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1079                                         struct rv515_watermark *wm0,
1080                                         struct rv515_watermark *wm1,
1081                                         struct drm_display_mode *mode0,
1082                                         struct drm_display_mode *mode1,
1083                                         u32 *d1mode_priority_a_cnt,
1084                                         u32 *d2mode_priority_a_cnt)
1085 {
1086         fixed20_12 priority_mark02, priority_mark12, fill_rate;
1087         fixed20_12 a, b;
1088
1089         *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1090         *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1091
1092         if (mode0 && mode1) {
1093                 if (dfixed_trunc(wm0->dbpp) > 64)
1094                         a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1095                 else
1096                         a.full = wm0->num_line_pair.full;
1097                 if (dfixed_trunc(wm1->dbpp) > 64)
1098                         b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1099                 else
1100                         b.full = wm1->num_line_pair.full;
1101                 a.full += b.full;
1102                 fill_rate.full = dfixed_div(wm0->sclk, a);
1103                 if (wm0->consumption_rate.full > fill_rate.full) {
1104                         b.full = wm0->consumption_rate.full - fill_rate.full;
1105                         b.full = dfixed_mul(b, wm0->active_time);
1106                         a.full = dfixed_const(16);
1107                         b.full = dfixed_div(b, a);
1108                         a.full = dfixed_mul(wm0->worst_case_latency,
1109                                                 wm0->consumption_rate);
1110                         priority_mark02.full = a.full + b.full;
1111                 } else {
1112                         a.full = dfixed_mul(wm0->worst_case_latency,
1113                                                 wm0->consumption_rate);
1114                         b.full = dfixed_const(16 * 1000);
1115                         priority_mark02.full = dfixed_div(a, b);
1116                 }
1117                 if (wm1->consumption_rate.full > fill_rate.full) {
1118                         b.full = wm1->consumption_rate.full - fill_rate.full;
1119                         b.full = dfixed_mul(b, wm1->active_time);
1120                         a.full = dfixed_const(16);
1121                         b.full = dfixed_div(b, a);
1122                         a.full = dfixed_mul(wm1->worst_case_latency,
1123                                                 wm1->consumption_rate);
1124                         priority_mark12.full = a.full + b.full;
1125                 } else {
1126                         a.full = dfixed_mul(wm1->worst_case_latency,
1127                                                 wm1->consumption_rate);
1128                         b.full = dfixed_const(16 * 1000);
1129                         priority_mark12.full = dfixed_div(a, b);
1130                 }
1131                 if (wm0->priority_mark.full > priority_mark02.full)
1132                         priority_mark02.full = wm0->priority_mark.full;
1133                 if (wm0->priority_mark_max.full > priority_mark02.full)
1134                         priority_mark02.full = wm0->priority_mark_max.full;
1135                 if (wm1->priority_mark.full > priority_mark12.full)
1136                         priority_mark12.full = wm1->priority_mark.full;
1137                 if (wm1->priority_mark_max.full > priority_mark12.full)
1138                         priority_mark12.full = wm1->priority_mark_max.full;
1139                 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1140                 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1141                 if (rdev->disp_priority == 2) {
1142                         *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1143                         *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1144                 }
1145         } else if (mode0) {
1146                 if (dfixed_trunc(wm0->dbpp) > 64)
1147                         a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1148                 else
1149                         a.full = wm0->num_line_pair.full;
1150                 fill_rate.full = dfixed_div(wm0->sclk, a);
1151                 if (wm0->consumption_rate.full > fill_rate.full) {
1152                         b.full = wm0->consumption_rate.full - fill_rate.full;
1153                         b.full = dfixed_mul(b, wm0->active_time);
1154                         a.full = dfixed_const(16);
1155                         b.full = dfixed_div(b, a);
1156                         a.full = dfixed_mul(wm0->worst_case_latency,
1157                                                 wm0->consumption_rate);
1158                         priority_mark02.full = a.full + b.full;
1159                 } else {
1160                         a.full = dfixed_mul(wm0->worst_case_latency,
1161                                                 wm0->consumption_rate);
1162                         b.full = dfixed_const(16);
1163                         priority_mark02.full = dfixed_div(a, b);
1164                 }
1165                 if (wm0->priority_mark.full > priority_mark02.full)
1166                         priority_mark02.full = wm0->priority_mark.full;
1167                 if (wm0->priority_mark_max.full > priority_mark02.full)
1168                         priority_mark02.full = wm0->priority_mark_max.full;
1169                 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1170                 if (rdev->disp_priority == 2)
1171                         *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1172         } else if (mode1) {
1173                 if (dfixed_trunc(wm1->dbpp) > 64)
1174                         a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1175                 else
1176                         a.full = wm1->num_line_pair.full;
1177                 fill_rate.full = dfixed_div(wm1->sclk, a);
1178                 if (wm1->consumption_rate.full > fill_rate.full) {
1179                         b.full = wm1->consumption_rate.full - fill_rate.full;
1180                         b.full = dfixed_mul(b, wm1->active_time);
1181                         a.full = dfixed_const(16);
1182                         b.full = dfixed_div(b, a);
1183                         a.full = dfixed_mul(wm1->worst_case_latency,
1184                                                 wm1->consumption_rate);
1185                         priority_mark12.full = a.full + b.full;
1186                 } else {
1187                         a.full = dfixed_mul(wm1->worst_case_latency,
1188                                                 wm1->consumption_rate);
1189                         b.full = dfixed_const(16 * 1000);
1190                         priority_mark12.full = dfixed_div(a, b);
1191                 }
1192                 if (wm1->priority_mark.full > priority_mark12.full)
1193                         priority_mark12.full = wm1->priority_mark.full;
1194                 if (wm1->priority_mark_max.full > priority_mark12.full)
1195                         priority_mark12.full = wm1->priority_mark_max.full;
1196                 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1197                 if (rdev->disp_priority == 2)
1198                         *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1199         }
1200 }
1201
1202 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1203 {
1204         struct drm_display_mode *mode0 = NULL;
1205         struct drm_display_mode *mode1 = NULL;
1206         struct rv515_watermark wm0_high, wm0_low;
1207         struct rv515_watermark wm1_high, wm1_low;
1208         u32 tmp;
1209         u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1210         u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1211
1212         if (rdev->mode_info.crtcs[0]->base.enabled)
1213                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1214         if (rdev->mode_info.crtcs[1]->base.enabled)
1215                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1216         rs690_line_buffer_adjust(rdev, mode0, mode1);
1217
1218         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1219         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1220
1221         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1222         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1223
1224         tmp = wm0_high.lb_request_fifo_depth;
1225         tmp |= wm1_high.lb_request_fifo_depth << 16;
1226         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1227
1228         rv515_compute_mode_priority(rdev,
1229                                     &wm0_high, &wm1_high,
1230                                     mode0, mode1,
1231                                     &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1232         rv515_compute_mode_priority(rdev,
1233                                     &wm0_low, &wm1_low,
1234                                     mode0, mode1,
1235                                     &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1236
1237         WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1238         WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1239         WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1240         WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1241 }
1242
1243 void rv515_bandwidth_update(struct radeon_device *rdev)
1244 {
1245         uint32_t tmp;
1246         struct drm_display_mode *mode0 = NULL;
1247         struct drm_display_mode *mode1 = NULL;
1248
1249         if (!rdev->mode_info.mode_config_initialized)
1250                 return;
1251
1252         radeon_update_display_priority(rdev);
1253
1254         if (rdev->mode_info.crtcs[0]->base.enabled)
1255                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1256         if (rdev->mode_info.crtcs[1]->base.enabled)
1257                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1258         /*
1259          * Set display0/1 priority up in the memory controller for
1260          * modes if the user specifies HIGH for displaypriority
1261          * option.
1262          */
1263         if ((rdev->disp_priority == 2) &&
1264             (rdev->family == CHIP_RV515)) {
1265                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1266                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1267                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1268                 if (mode1)
1269                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1270                 if (mode0)
1271                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1272                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1273         }
1274         rv515_bandwidth_avivo_update(rdev);
1275 }