drivers/gpu/drm/radeon/dce6_afmt.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/hdmi.h>
  24 #include <drm/drm_edid.h>
  25
  26 #include "dce6_afmt.h"
  27 #include "radeon.h"
  28 #include "radeon_audio.h"
  29 #include "sid.h"
  30
  31 #define DCE8_DCCG_AUDIO_DTO1_PHASE      0x05b8
  32 #define DCE8_DCCG_AUDIO_DTO1_MODULE     0x05bc
  33
  34 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
  35                               u32 block_offset, u32 reg)
  36 {
  37         unsigned long flags;
  38         u32 r;
  39
  40         spin_lock_irqsave(&rdev->end_idx_lock, flags);
  41         WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  42         r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
  43         spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
  44
  45         return r;
  46 }
  47
  48 void dce6_endpoint_wreg(struct radeon_device *rdev,
  49                                u32 block_offset, u32 reg, u32 v)
  50 {
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rdev->end_idx_lock, flags);
  54         if (ASIC_IS_DCE8(rdev))
  55                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  56         else
  57                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
  58                        AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
  59         WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
  60         spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
  61 }
  62
  63 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
  64 {
  65         int i;
  66         u32 offset, tmp;
  67
  68         for (i = 0; i < rdev->audio.num_pins; i++) {
  69                 offset = rdev->audio.pin[i].offset;
  70                 tmp = RREG32_ENDPOINT(offset,
  71                                       AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
  72                 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
  73                         rdev->audio.pin[i].connected = false;
  74                 else
  75                         rdev->audio.pin[i].connected = true;
  76         }
  77 }
  78
  79 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
  80 {
  81         struct drm_encoder *encoder;
  82         struct radeon_encoder *radeon_encoder;
  83         struct radeon_encoder_atom_dig *dig;
  84         struct r600_audio_pin *pin = NULL;
  85         int i, pin_count;
  86
  87         dce6_afmt_get_connected_pins(rdev);
  88
  89         for (i = 0; i < rdev->audio.num_pins; i++) {
  90                 if (rdev->audio.pin[i].connected) {
  91                         pin = &rdev->audio.pin[i];
  92                         pin_count = 0;
  93
  94                         list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) {
  95                                 if (radeon_encoder_is_digital(encoder)) {
  96                                         radeon_encoder = to_radeon_encoder(encoder);
  97                                         dig = radeon_encoder->enc_priv;
  98                                         if (dig->pin == pin)
  99                                                 pin_count++;
 100                                 }
 101                         }
 102
 103                         if (pin_count == 0)
 104                                 return pin;
 105                 }
 106         }
 107         if (!pin)
 108                 DRM_ERROR("No connected audio pins found!\n");
 109         return pin;
 110 }
 111
 112 void dce6_afmt_select_pin(struct drm_encoder *encoder)
 113 {
 114         struct radeon_device *rdev = encoder->dev->dev_private;
 115         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 116         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 117
 118         if (!dig || !dig->afmt || !dig->pin)
 119                 return;
 120
 121         WREG32(AFMT_AUDIO_SRC_CONTROL +  dig->afmt->offset,
 122                AFMT_AUDIO_SRC_SELECT(dig->pin->id));
 123 }
 124
 125 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
 126                                     struct drm_connector *connector,
 127                                     struct drm_display_mode *mode)
 128 {
 129         struct radeon_device *rdev = encoder->dev->dev_private;
 130         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 131         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 132         u32 tmp = 0;
 133
 134         if (!dig || !dig->afmt || !dig->pin)
 135                 return;
 136
 137         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 138                 if (connector->latency_present[1])
 139                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
 140                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
 141                 else
 142                         tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
 143         } else {
 144                 if (connector->latency_present[0])
 145                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
 146                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
 147                 else
 148                         tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
 149         }
 150         WREG32_ENDPOINT(dig->pin->offset,
 151                         AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
 152 }
 153
 154 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
 155                                              u8 *sadb, int sad_count)
 156 {
 157         struct radeon_device *rdev = encoder->dev->dev_private;
 158         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 159         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 160         u32 tmp;
 161
 162         if (!dig || !dig->afmt || !dig->pin)
 163                 return;
 164
 165         /* program the speaker allocation */
 166         tmp = RREG32_ENDPOINT(dig->pin->offset,
 167                               AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 168         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 169         /* set HDMI mode */
 170         tmp |= HDMI_CONNECTION;
 171         if (sad_count)
 172                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 173         else
 174                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 175         WREG32_ENDPOINT(dig->pin->offset,
 176                         AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
 177 }
 178
 179 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
 180                                            u8 *sadb, int sad_count)
 181 {
 182         struct radeon_device *rdev = encoder->dev->dev_private;
 183         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 184         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 185         u32 tmp;
 186
 187         if (!dig || !dig->afmt || !dig->pin)
 188                 return;
 189
 190         /* program the speaker allocation */
 191         tmp = RREG32_ENDPOINT(dig->pin->offset,
 192                               AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 193         tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
 194         /* set DP mode */
 195         tmp |= DP_CONNECTION;
 196         if (sad_count)
 197                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 198         else
 199                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 200         WREG32_ENDPOINT(dig->pin->offset,
 201                         AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
 202 }
 203
 204 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
 205                               struct cea_sad *sads, int sad_count)
 206 {
 207         int i;
 208         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 209         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 210         struct radeon_device *rdev = encoder->dev->dev_private;
 211         static const u16 eld_reg_to_type[][2] = {
 212                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 213                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 214                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 215                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 216                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 217                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 218                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 219                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 220                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 221                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 222                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 223                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 224         };
 225
 226         if (!dig || !dig->afmt || !dig->pin)
 227                 return;
 228
 229         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 230                 u32 value = 0;
 231                 u8 stereo_freqs = 0;
 232                 int max_channels = -1;
 233                 int j;
 234
 235                 for (j = 0; j < sad_count; j++) {
 236                         struct cea_sad *sad = &sads[j];
 237
 238                         if (sad->format == eld_reg_to_type[i][1]) {
 239                                 if (sad->channels > max_channels) {
 240                                         value = MAX_CHANNELS(sad->channels) |
 241                                                 DESCRIPTOR_BYTE_2(sad->byte2) |
 242                                                 SUPPORTED_FREQUENCIES(sad->freq);
 243                                         max_channels = sad->channels;
 244                                 }
 245
 246                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 247                                         stereo_freqs |= sad->freq;
 248                                 else
 249                                         break;
 250                         }
 251                 }
 252
 253                 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
 254
 255                 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
 256         }
 257 }
 258
 259 void dce6_audio_enable(struct radeon_device *rdev,
 260                        struct r600_audio_pin *pin,
 261                        u8 enable_mask)
 262 {
 263         if (!pin)
 264                 return;
 265
 266         WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 267                         enable_mask ? AUDIO_ENABLED : 0);
 268 }
 269
 270 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
 271                              struct radeon_crtc *crtc, unsigned int clock)
 272 {
 273         /* Two dtos; generally use dto0 for HDMI */
 274         u32 value = 0;
 275
 276         if (crtc)
 277                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
 278
 279         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
 280
 281         /* Express [24MHz / target pixel clock] as an exact rational
 282          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 283          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 284          */
 285         WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
 286         WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
 287 }
 288
 289 void dce6_dp_audio_set_dto(struct radeon_device *rdev,
 290                            struct radeon_crtc *crtc, unsigned int clock)
 291 {
 292         /* Two dtos; generally use dto1 for DP */
 293         u32 value = 0;
 294         value |= DCCG_AUDIO_DTO_SEL;
 295
 296         if (crtc)
 297                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
 298
 299         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
 300
 301         /* Express [24MHz / target pixel clock] as an exact rational
 302          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 303          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 304          */
 305         if (ASIC_IS_DCE8(rdev)) {
 306                 unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
 307                         DENTIST_DPREFCLK_WDIVIDER_MASK) >>
 308                         DENTIST_DPREFCLK_WDIVIDER_SHIFT;
 309                 div = radeon_audio_decode_dfs_div(div);
 310
 311                 if (div)
 312                         clock = clock * 100 / div;
 313
 314                 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
 315                 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
 316         } else {
 317                 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
 318                 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
 319         }
 320 }