drivers/gpu/drm/i915/gt/intel_engine_cs.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2016 Intel Corporation
   4  */
   5
   6 #include <linux/string_helpers.h>
   7
   8 #include <drm/drm_print.h>
   9
  10 #include "gem/i915_gem_context.h"
  11 #include "gem/i915_gem_internal.h"
  12 #include "gt/intel_gt_print.h"
  13 #include "gt/intel_gt_regs.h"
  14
  15 #include "i915_cmd_parser.h"
  16 #include "i915_drv.h"
  17 #include "i915_irq.h"
  18 #include "i915_reg.h"
  19 #include "intel_breadcrumbs.h"
  20 #include "intel_context.h"
  21 #include "intel_engine.h"
  22 #include "intel_engine_pm.h"
  23 #include "intel_engine_regs.h"
  24 #include "intel_engine_user.h"
  25 #include "intel_execlists_submission.h"
  26 #include "intel_gt.h"
  27 #include "intel_gt_mcr.h"
  28 #include "intel_gt_pm.h"
  29 #include "intel_gt_requests.h"
  30 #include "intel_lrc.h"
  31 #include "intel_lrc_reg.h"
  32 #include "intel_reset.h"
  33 #include "intel_ring.h"
  34 #include "uc/intel_guc_submission.h"
  35
  36 /* Haswell does have the CXT_SIZE register however it does not appear to be
  37  * valid. Now, docs explain in dwords what is in the context object. The full
  38  * size is 70720 bytes, however, the power context and execlist context will
  39  * never be saved (power context is stored elsewhere, and execlists don't work
  40  * on HSW) - so the final size, including the extra state required for the
  41  * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
  42  */
  43 #define HSW_CXT_TOTAL_SIZE              (17 * PAGE_SIZE)
  44
  45 #define DEFAULT_LR_CONTEXT_RENDER_SIZE  (22 * PAGE_SIZE)
  46 #define GEN8_LR_CONTEXT_RENDER_SIZE     (20 * PAGE_SIZE)
  47 #define GEN9_LR_CONTEXT_RENDER_SIZE     (22 * PAGE_SIZE)
  48 #define GEN11_LR_CONTEXT_RENDER_SIZE    (14 * PAGE_SIZE)
  49
  50 #define GEN8_LR_CONTEXT_OTHER_SIZE      (2 * PAGE_SIZE)
  51
  52 #define MAX_MMIO_BASES 3
  53 struct engine_info {
  54         u8 class;
  55         u8 instance;
  56         /* mmio bases table *must* be sorted in reverse graphics_ver order */
  57         struct engine_mmio_base {
  58                 u32 graphics_ver : 8;
  59                 u32 base : 24;
  60         } mmio_bases[MAX_MMIO_BASES];
  61 };
  62
  63 static const struct engine_info intel_engines[] = {
  64         [RCS0] = {
  65                 .class = RENDER_CLASS,
  66                 .instance = 0,
  67                 .mmio_bases = {
  68                         { .graphics_ver = 1, .base = RENDER_RING_BASE }
  69                 },
  70         },
  71         [BCS0] = {
  72                 .class = COPY_ENGINE_CLASS,
  73                 .instance = 0,
  74                 .mmio_bases = {
  75                         { .graphics_ver = 6, .base = BLT_RING_BASE }
  76                 },
  77         },
  78         [BCS1] = {
  79                 .class = COPY_ENGINE_CLASS,
  80                 .instance = 1,
  81                 .mmio_bases = {
  82                         { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
  83                 },
  84         },
  85         [BCS2] = {
  86                 .class = COPY_ENGINE_CLASS,
  87                 .instance = 2,
  88                 .mmio_bases = {
  89                         { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
  90                 },
  91         },
  92         [BCS3] = {
  93                 .class = COPY_ENGINE_CLASS,
  94                 .instance = 3,
  95                 .mmio_bases = {
  96                         { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
  97                 },
  98         },
  99         [BCS4] = {
 100                 .class = COPY_ENGINE_CLASS,
 101                 .instance = 4,
 102                 .mmio_bases = {
 103                         { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
 104                 },
 105         },
 106         [BCS5] = {
 107                 .class = COPY_ENGINE_CLASS,
 108                 .instance = 5,
 109                 .mmio_bases = {
 110                         { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
 111                 },
 112         },
 113         [BCS6] = {
 114                 .class = COPY_ENGINE_CLASS,
 115                 .instance = 6,
 116                 .mmio_bases = {
 117                         { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
 118                 },
 119         },
 120         [BCS7] = {
 121                 .class = COPY_ENGINE_CLASS,
 122                 .instance = 7,
 123                 .mmio_bases = {
 124                         { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
 125                 },
 126         },
 127         [BCS8] = {
 128                 .class = COPY_ENGINE_CLASS,
 129                 .instance = 8,
 130                 .mmio_bases = {
 131                         { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
 132                 },
 133         },
 134         [VCS0] = {
 135                 .class = VIDEO_DECODE_CLASS,
 136                 .instance = 0,
 137                 .mmio_bases = {
 138                         { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
 139                         { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
 140                         { .graphics_ver = 4, .base = BSD_RING_BASE }
 141                 },
 142         },
 143         [VCS1] = {
 144                 .class = VIDEO_DECODE_CLASS,
 145                 .instance = 1,
 146                 .mmio_bases = {
 147                         { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
 148                         { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
 149                 },
 150         },
 151         [VCS2] = {
 152                 .class = VIDEO_DECODE_CLASS,
 153                 .instance = 2,
 154                 .mmio_bases = {
 155                         { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
 156                 },
 157         },
 158         [VCS3] = {
 159                 .class = VIDEO_DECODE_CLASS,
 160                 .instance = 3,
 161                 .mmio_bases = {
 162                         { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
 163                 },
 164         },
 165         [VCS4] = {
 166                 .class = VIDEO_DECODE_CLASS,
 167                 .instance = 4,
 168                 .mmio_bases = {
 169                         { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
 170                 },
 171         },
 172         [VCS5] = {
 173                 .class = VIDEO_DECODE_CLASS,
 174                 .instance = 5,
 175                 .mmio_bases = {
 176                         { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
 177                 },
 178         },
 179         [VCS6] = {
 180                 .class = VIDEO_DECODE_CLASS,
 181                 .instance = 6,
 182                 .mmio_bases = {
 183                         { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
 184                 },
 185         },
 186         [VCS7] = {
 187                 .class = VIDEO_DECODE_CLASS,
 188                 .instance = 7,
 189                 .mmio_bases = {
 190                         { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
 191                 },
 192         },
 193         [VECS0] = {
 194                 .class = VIDEO_ENHANCEMENT_CLASS,
 195                 .instance = 0,
 196                 .mmio_bases = {
 197                         { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
 198                         { .graphics_ver = 7, .base = VEBOX_RING_BASE }
 199                 },
 200         },
 201         [VECS1] = {
 202                 .class = VIDEO_ENHANCEMENT_CLASS,
 203                 .instance = 1,
 204                 .mmio_bases = {
 205                         { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
 206                 },
 207         },
 208         [VECS2] = {
 209                 .class = VIDEO_ENHANCEMENT_CLASS,
 210                 .instance = 2,
 211                 .mmio_bases = {
 212                         { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
 213                 },
 214         },
 215         [VECS3] = {
 216                 .class = VIDEO_ENHANCEMENT_CLASS,
 217                 .instance = 3,
 218                 .mmio_bases = {
 219                         { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
 220                 },
 221         },
 222         [CCS0] = {
 223                 .class = COMPUTE_CLASS,
 224                 .instance = 0,
 225                 .mmio_bases = {
 226                         { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
 227                 }
 228         },
 229         [CCS1] = {
 230                 .class = COMPUTE_CLASS,
 231                 .instance = 1,
 232                 .mmio_bases = {
 233                         { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
 234                 }
 235         },
 236         [CCS2] = {
 237                 .class = COMPUTE_CLASS,
 238                 .instance = 2,
 239                 .mmio_bases = {
 240                         { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
 241                 }
 242         },
 243         [CCS3] = {
 244                 .class = COMPUTE_CLASS,
 245                 .instance = 3,
 246                 .mmio_bases = {
 247                         { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
 248                 }
 249         },
 250         [GSC0] = {
 251                 .class = OTHER_CLASS,
 252                 .instance = OTHER_GSC_INSTANCE,
 253                 .mmio_bases = {
 254                         { .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
 255                 }
 256         },
 257 };
 258
 259 /**
 260  * intel_engine_context_size() - return the size of the context for an engine
 261  * @gt: the gt
 262  * @class: engine class
 263  *
 264  * Each engine class may require a different amount of space for a context
 265  * image.
 266  *
 267  * Return: size (in bytes) of an engine class specific context image
 268  *
 269  * Note: this size includes the HWSP, which is part of the context image
 270  * in LRC mode, but does not include the "shared data page" used with
 271  * GuC submission. The caller should account for this if using the GuC.
 272  */
 273 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 274 {
 275         struct intel_uncore *uncore = gt->uncore;
 276         u32 cxt_size;
 277
 278         BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
 279
 280         switch (class) {
 281         case COMPUTE_CLASS:
 282                 fallthrough;
 283         case RENDER_CLASS:
 284                 switch (GRAPHICS_VER(gt->i915)) {
 285                 default:
 286                         MISSING_CASE(GRAPHICS_VER(gt->i915));
 287                         return DEFAULT_LR_CONTEXT_RENDER_SIZE;
 288                 case 12:
 289                 case 11:
 290                         return GEN11_LR_CONTEXT_RENDER_SIZE;
 291                 case 9:
 292                         return GEN9_LR_CONTEXT_RENDER_SIZE;
 293                 case 8:
 294                         return GEN8_LR_CONTEXT_RENDER_SIZE;
 295                 case 7:
 296                         if (IS_HASWELL(gt->i915))
 297                                 return HSW_CXT_TOTAL_SIZE;
 298
 299                         cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
 300                         return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
 301                                         PAGE_SIZE);
 302                 case 6:
 303                         cxt_size = intel_uncore_read(uncore, CXT_SIZE);
 304                         return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
 305                                         PAGE_SIZE);
 306                 case 5:
 307                 case 4:
 308                         /*
 309                          * There is a discrepancy here between the size reported
 310                          * by the register and the size of the context layout
 311                          * in the docs. Both are described as authorative!
 312                          *
 313                          * The discrepancy is on the order of a few cachelines,
 314                          * but the total is under one page (4k), which is our
 315                          * minimum allocation anyway so it should all come
 316                          * out in the wash.
 317                          */
 318                         cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
 319                         gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
 320                                GRAPHICS_VER(gt->i915), cxt_size * 64,
 321                                cxt_size - 1);
 322                         return round_up(cxt_size * 64, PAGE_SIZE);
 323                 case 3:
 324                 case 2:
 325                 /* For the special day when i810 gets merged. */
 326                 case 1:
 327                         return 0;
 328                 }
 329                 break;
 330         default:
 331                 MISSING_CASE(class);
 332                 fallthrough;
 333         case VIDEO_DECODE_CLASS:
 334         case VIDEO_ENHANCEMENT_CLASS:
 335         case COPY_ENGINE_CLASS:
 336         case OTHER_CLASS:
 337                 if (GRAPHICS_VER(gt->i915) < 8)
 338                         return 0;
 339                 return GEN8_LR_CONTEXT_OTHER_SIZE;
 340         }
 341 }
 342
 343 static u32 __engine_mmio_base(struct drm_i915_private *i915,
 344                               const struct engine_mmio_base *bases)
 345 {
 346         int i;
 347
 348         for (i = 0; i < MAX_MMIO_BASES; i++)
 349                 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
 350                         break;
 351
 352         GEM_BUG_ON(i == MAX_MMIO_BASES);
 353         GEM_BUG_ON(!bases[i].base);
 354
 355         return bases[i].base;
 356 }
 357
 358 static void __sprint_engine_name(struct intel_engine_cs *engine)
 359 {
 360         /*
 361          * Before we know what the uABI name for this engine will be,
 362          * we still would like to keep track of this engine in the debug logs.
 363          * We throw in a ' here as a reminder that this isn't its final name.
 364          */
 365         GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
 366                              intel_engine_class_repr(engine->class),
 367                              engine->instance) >= sizeof(engine->name));
 368 }
 369
 370 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
 371 {
 372         /*
 373          * Though they added more rings on g4x/ilk, they did not add
 374          * per-engine HWSTAM until gen6.
 375          */
 376         if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
 377                 return;
 378
 379         if (GRAPHICS_VER(engine->i915) >= 3)
 380                 ENGINE_WRITE(engine, RING_HWSTAM, mask);
 381         else
 382                 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
 383 }
 384
 385 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
 386 {
 387         /* Mask off all writes into the unknown HWSP */
 388         intel_engine_set_hwsp_writemask(engine, ~0u);
 389 }
 390
 391 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
 392 {
 393         GEM_DEBUG_WARN_ON(iir);
 394 }
 395
 396 static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
 397 {
 398         u32 reset_domain;
 399
 400         if (ver >= 11) {
 401                 static const u32 engine_reset_domains[] = {
 402                         [RCS0]  = GEN11_GRDOM_RENDER,
 403                         [BCS0]  = GEN11_GRDOM_BLT,
 404                         [BCS1]  = XEHPC_GRDOM_BLT1,
 405                         [BCS2]  = XEHPC_GRDOM_BLT2,
 406                         [BCS3]  = XEHPC_GRDOM_BLT3,
 407                         [BCS4]  = XEHPC_GRDOM_BLT4,
 408                         [BCS5]  = XEHPC_GRDOM_BLT5,
 409                         [BCS6]  = XEHPC_GRDOM_BLT6,
 410                         [BCS7]  = XEHPC_GRDOM_BLT7,
 411                         [BCS8]  = XEHPC_GRDOM_BLT8,
 412                         [VCS0]  = GEN11_GRDOM_MEDIA,
 413                         [VCS1]  = GEN11_GRDOM_MEDIA2,
 414                         [VCS2]  = GEN11_GRDOM_MEDIA3,
 415                         [VCS3]  = GEN11_GRDOM_MEDIA4,
 416                         [VCS4]  = GEN11_GRDOM_MEDIA5,
 417                         [VCS5]  = GEN11_GRDOM_MEDIA6,
 418                         [VCS6]  = GEN11_GRDOM_MEDIA7,
 419                         [VCS7]  = GEN11_GRDOM_MEDIA8,
 420                         [VECS0] = GEN11_GRDOM_VECS,
 421                         [VECS1] = GEN11_GRDOM_VECS2,
 422                         [VECS2] = GEN11_GRDOM_VECS3,
 423                         [VECS3] = GEN11_GRDOM_VECS4,
 424                         [CCS0]  = GEN11_GRDOM_RENDER,
 425                         [CCS1]  = GEN11_GRDOM_RENDER,
 426                         [CCS2]  = GEN11_GRDOM_RENDER,
 427                         [CCS3]  = GEN11_GRDOM_RENDER,
 428                         [GSC0]  = GEN12_GRDOM_GSC,
 429                 };
 430                 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
 431                            !engine_reset_domains[id]);
 432                 reset_domain = engine_reset_domains[id];
 433         } else {
 434                 static const u32 engine_reset_domains[] = {
 435                         [RCS0]  = GEN6_GRDOM_RENDER,
 436                         [BCS0]  = GEN6_GRDOM_BLT,
 437                         [VCS0]  = GEN6_GRDOM_MEDIA,
 438                         [VCS1]  = GEN8_GRDOM_MEDIA2,
 439                         [VECS0] = GEN6_GRDOM_VECS,
 440                 };
 441                 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
 442                            !engine_reset_domains[id]);
 443                 reset_domain = engine_reset_domains[id];
 444         }
 445
 446         return reset_domain;
 447 }
 448
 449 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
 450                               u8 logical_instance)
 451 {
 452         const struct engine_info *info = &intel_engines[id];
 453         struct drm_i915_private *i915 = gt->i915;
 454         struct intel_engine_cs *engine;
 455         u8 guc_class;
 456
 457         BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
 458         BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
 459         BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
 460         BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
 461
 462         if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
 463                 return -EINVAL;
 464
 465         if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
 466                 return -EINVAL;
 467
 468         if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
 469                 return -EINVAL;
 470
 471         if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
 472                 return -EINVAL;
 473
 474         engine = kzalloc(sizeof(*engine), GFP_KERNEL);
 475         if (!engine)
 476                 return -ENOMEM;
 477
 478         BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
 479
 480         INIT_LIST_HEAD(&engine->pinned_contexts_list);
 481         engine->id = id;
 482         engine->legacy_idx = INVALID_ENGINE;
 483         engine->mask = BIT(id);
 484         engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
 485                                                 id);
 486         engine->i915 = i915;
 487         engine->gt = gt;
 488         engine->uncore = gt->uncore;
 489         guc_class = engine_class_to_guc_class(info->class);
 490         engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
 491         engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
 492
 493         engine->irq_handler = nop_irq_handler;
 494
 495         engine->class = info->class;
 496         engine->instance = info->instance;
 497         engine->logical_mask = BIT(logical_instance);
 498         __sprint_engine_name(engine);
 499
 500         if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
 501              __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
 502              engine->class == RENDER_CLASS)
 503                 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
 504
 505         /* features common between engines sharing EUs */
 506         if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
 507                 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
 508                 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
 509         }
 510
 511         engine->props.heartbeat_interval_ms =
 512                 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
 513         engine->props.max_busywait_duration_ns =
 514                 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
 515         engine->props.preempt_timeout_ms =
 516                 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
 517         engine->props.stop_timeout_ms =
 518                 CONFIG_DRM_I915_STOP_TIMEOUT;
 519         engine->props.timeslice_duration_ms =
 520                 CONFIG_DRM_I915_TIMESLICE_DURATION;
 521
 522         /*
 523          * Mid-thread pre-emption is not available in Gen12. Unfortunately,
 524          * some compute workloads run quite long threads. That means they get
 525          * reset due to not pre-empting in a timely manner. So, bump the
 526          * pre-emption timeout value to be much higher for compute engines.
 527          */
 528         if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
 529                 engine->props.preempt_timeout_ms = CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE;
 530
 531         /* Cap properties according to any system limits */
 532 #define CLAMP_PROP(field) \
 533         do { \
 534                 u64 clamp = intel_clamp_##field(engine, engine->props.field); \
 535                 if (clamp != engine->props.field) { \
 536                         drm_notice(&engine->i915->drm, \
 537                                    "Warning, clamping %s to %lld to prevent overflow\n", \
 538                                    #field, clamp); \
 539                         engine->props.field = clamp; \
 540                 } \
 541         } while (0)
 542
 543         CLAMP_PROP(heartbeat_interval_ms);
 544         CLAMP_PROP(max_busywait_duration_ns);
 545         CLAMP_PROP(preempt_timeout_ms);
 546         CLAMP_PROP(stop_timeout_ms);
 547         CLAMP_PROP(timeslice_duration_ms);
 548
 549 #undef CLAMP_PROP
 550
 551         engine->defaults = engine->props; /* never to change again */
 552
 553         engine->context_size = intel_engine_context_size(gt, engine->class);
 554         if (WARN_ON(engine->context_size > BIT(20)))
 555                 engine->context_size = 0;
 556         if (engine->context_size)
 557                 DRIVER_CAPS(i915)->has_logical_contexts = true;
 558
 559         ewma__engine_latency_init(&engine->latency);
 560
 561         ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 562
 563         /* Scrub mmio state on takeover */
 564         intel_engine_sanitize_mmio(engine);
 565
 566         gt->engine_class[info->class][info->instance] = engine;
 567         gt->engine[id] = engine;
 568
 569         return 0;
 570 }
 571
 572 u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)
 573 {
 574         value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
 575
 576         return value;
 577 }
 578
 579 u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)
 580 {
 581         value = min(value, jiffies_to_nsecs(2));
 582
 583         return value;
 584 }
 585
 586 u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)
 587 {
 588         /*
 589          * NB: The GuC API only supports 32bit values. However, the limit is further
 590          * reduced due to internal calculations which would otherwise overflow.
 591          */
 592         if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
 593                 value = min_t(u64, value, guc_policy_max_preempt_timeout_ms());
 594
 595         value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
 596
 597         return value;
 598 }
 599
 600 u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)
 601 {
 602         value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
 603
 604         return value;
 605 }
 606
 607 u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)
 608 {
 609         /*
 610          * NB: The GuC API only supports 32bit values. However, the limit is further
 611          * reduced due to internal calculations which would otherwise overflow.
 612          */
 613         if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
 614                 value = min_t(u64, value, guc_policy_max_exec_quantum_ms());
 615
 616         value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
 617
 618         return value;
 619 }
 620
 621 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 622 {
 623         struct drm_i915_private *i915 = engine->i915;
 624
 625         if (engine->class == VIDEO_DECODE_CLASS) {
 626                 /*
 627                  * HEVC support is present on first engine instance
 628                  * before Gen11 and on all instances afterwards.
 629                  */
 630                 if (GRAPHICS_VER(i915) >= 11 ||
 631                     (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
 632                         engine->uabi_capabilities |=
 633                                 I915_VIDEO_CLASS_CAPABILITY_HEVC;
 634
 635                 /*
 636                  * SFC block is present only on even logical engine
 637                  * instances.
 638                  */
 639                 if ((GRAPHICS_VER(i915) >= 11 &&
 640                      (engine->gt->info.vdbox_sfc_access &
 641                       BIT(engine->instance))) ||
 642                     (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
 643                         engine->uabi_capabilities |=
 644                                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 645         } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
 646                 if (GRAPHICS_VER(i915) >= 9 &&
 647                     engine->gt->info.sfc_mask & BIT(engine->instance))
 648                         engine->uabi_capabilities |=
 649                                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 650         }
 651 }
 652
 653 static void intel_setup_engine_capabilities(struct intel_gt *gt)
 654 {
 655         struct intel_engine_cs *engine;
 656         enum intel_engine_id id;
 657
 658         for_each_engine(engine, gt, id)
 659                 __setup_engine_capabilities(engine);
 660 }
 661
 662 /**
 663  * intel_engines_release() - free the resources allocated for Command Streamers
 664  * @gt: pointer to struct intel_gt
 665  */
 666 void intel_engines_release(struct intel_gt *gt)
 667 {
 668         struct intel_engine_cs *engine;
 669         enum intel_engine_id id;
 670
 671         /*
 672          * Before we release the resources held by engine, we must be certain
 673          * that the HW is no longer accessing them -- having the GPU scribble
 674          * to or read from a page being used for something else causes no end
 675          * of fun.
 676          *
 677          * The GPU should be reset by this point, but assume the worst just
 678          * in case we aborted before completely initialising the engines.
 679          */
 680         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 681         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 682                 __intel_gt_reset(gt, ALL_ENGINES);
 683
 684         /* Decouple the backend; but keep the layout for late GPU resets */
 685         for_each_engine(engine, gt, id) {
 686                 if (!engine->release)
 687                         continue;
 688
 689                 intel_wakeref_wait_for_idle(&engine->wakeref);
 690                 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
 691
 692                 engine->release(engine);
 693                 engine->release = NULL;
 694
 695                 memset(&engine->reset, 0, sizeof(engine->reset));
 696         }
 697 }
 698
 699 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
 700 {
 701         if (!engine->request_pool)
 702                 return;
 703
 704         kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
 705 }
 706
 707 void intel_engines_free(struct intel_gt *gt)
 708 {
 709         struct intel_engine_cs *engine;
 710         enum intel_engine_id id;
 711
 712         /* Free the requests! dma-resv keeps fences around for an eternity */
 713         rcu_barrier();
 714
 715         for_each_engine(engine, gt, id) {
 716                 intel_engine_free_request_pool(engine);
 717                 kfree(engine);
 718                 gt->engine[id] = NULL;
 719         }
 720 }
 721
 722 static
 723 bool gen11_vdbox_has_sfc(struct intel_gt *gt,
 724                          unsigned int physical_vdbox,
 725                          unsigned int logical_vdbox, u16 vdbox_mask)
 726 {
 727         struct drm_i915_private *i915 = gt->i915;
 728
 729         /*
 730          * In Gen11, only even numbered logical VDBOXes are hooked
 731          * up to an SFC (Scaler & Format Converter) unit.
 732          * In Gen12, Even numbered physical instance always are connected
 733          * to an SFC. Odd numbered physical instances have SFC only if
 734          * previous even instance is fused off.
 735          *
 736          * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
 737          * in the fuse register that tells us whether a specific SFC is present.
 738          */
 739         if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
 740                 return false;
 741         else if (MEDIA_VER(i915) >= 12)
 742                 return (physical_vdbox % 2 == 0) ||
 743                         !(BIT(physical_vdbox - 1) & vdbox_mask);
 744         else if (MEDIA_VER(i915) == 11)
 745                 return logical_vdbox % 2 == 0;
 746
 747         return false;
 748 }
 749
 750 static void engine_mask_apply_media_fuses(struct intel_gt *gt)
 751 {
 752         struct drm_i915_private *i915 = gt->i915;
 753         unsigned int logical_vdbox = 0;
 754         unsigned int i;
 755         u32 media_fuse, fuse1;
 756         u16 vdbox_mask;
 757         u16 vebox_mask;
 758
 759         if (MEDIA_VER(gt->i915) < 11)
 760                 return;
 761
 762         /*
 763          * On newer platforms the fusing register is called 'enable' and has
 764          * enable semantics, while on older platforms it is called 'disable'
 765          * and bits have disable semantices.
 766          */
 767         media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
 768         if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
 769                 media_fuse = ~media_fuse;
 770
 771         vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
 772         vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
 773                       GEN11_GT_VEBOX_DISABLE_SHIFT;
 774
 775         if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
 776                 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
 777                 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
 778         } else {
 779                 gt->info.sfc_mask = ~0;
 780         }
 781
 782         for (i = 0; i < I915_MAX_VCS; i++) {
 783                 if (!HAS_ENGINE(gt, _VCS(i))) {
 784                         vdbox_mask &= ~BIT(i);
 785                         continue;
 786                 }
 787
 788                 if (!(BIT(i) & vdbox_mask)) {
 789                         gt->info.engine_mask &= ~BIT(_VCS(i));
 790                         gt_dbg(gt, "vcs%u fused off\n", i);
 791                         continue;
 792                 }
 793
 794                 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
 795                         gt->info.vdbox_sfc_access |= BIT(i);
 796                 logical_vdbox++;
 797         }
 798         gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));
 799         GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
 800
 801         for (i = 0; i < I915_MAX_VECS; i++) {
 802                 if (!HAS_ENGINE(gt, _VECS(i))) {
 803                         vebox_mask &= ~BIT(i);
 804                         continue;
 805                 }
 806
 807                 if (!(BIT(i) & vebox_mask)) {
 808                         gt->info.engine_mask &= ~BIT(_VECS(i));
 809                         gt_dbg(gt, "vecs%u fused off\n", i);
 810                 }
 811         }
 812         gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));
 813         GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
 814 }
 815
 816 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
 817 {
 818         struct drm_i915_private *i915 = gt->i915;
 819         struct intel_gt_info *info = &gt->info;
 820         int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
 821         unsigned long ccs_mask;
 822         unsigned int i;
 823
 824         if (GRAPHICS_VER(i915) < 11)
 825                 return;
 826
 827         if (hweight32(CCS_MASK(gt)) <= 1)
 828                 return;
 829
 830         ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
 831                                                      ss_per_ccs);
 832         /*
 833          * If all DSS in a quadrant are fused off, the corresponding CCS
 834          * engine is not available for use.
 835          */
 836         for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
 837                 info->engine_mask &= ~BIT(_CCS(i));
 838                 gt_dbg(gt, "ccs%u fused off\n", i);
 839         }
 840 }
 841
 842 static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
 843 {
 844         struct drm_i915_private *i915 = gt->i915;
 845         struct intel_gt_info *info = &gt->info;
 846         unsigned long meml3_mask;
 847         unsigned long quad;
 848
 849         if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
 850               GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
 851                 return;
 852
 853         meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
 854         meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
 855
 856         /*
 857          * Link Copy engines may be fused off according to meml3_mask. Each
 858          * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
 859          */
 860         for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
 861                 unsigned int instance = quad * 2 + 1;
 862                 intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
 863                                                    _BCS(instance));
 864
 865                 if (mask & info->engine_mask) {
 866                         gt_dbg(gt, "bcs%u fused off\n", instance);
 867                         gt_dbg(gt, "bcs%u fused off\n", instance + 1);
 868
 869                         info->engine_mask &= ~mask;
 870                 }
 871         }
 872 }
 873
 874 /*
 875  * Determine which engines are fused off in our particular hardware.
 876  * Note that we have a catch-22 situation where we need to be able to access
 877  * the blitter forcewake domain to read the engine fuses, but at the same time
 878  * we need to know which engines are available on the system to know which
 879  * forcewake domains are present. We solve this by intializing the forcewake
 880  * domains based on the full engine mask in the platform capabilities before
 881  * calling this function and pruning the domains for fused-off engines
 882  * afterwards.
 883  */
 884 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 885 {
 886         struct intel_gt_info *info = &gt->info;
 887
 888         GEM_BUG_ON(!info->engine_mask);
 889
 890         engine_mask_apply_media_fuses(gt);
 891         engine_mask_apply_compute_fuses(gt);
 892         engine_mask_apply_copy_fuses(gt);
 893
 894         /*
 895          * The only use of the GSC CS is to load and communicate with the GSC
 896          * FW, so we have no use for it if we don't have the FW.
 897          *
 898          * IMPORTANT: in cases where we don't have the GSC FW, we have a
 899          * catch-22 situation that breaks media C6 due to 2 requirements:
 900          * 1) once turned on, the GSC power well will not go to sleep unless the
 901          *    GSC FW is loaded.
 902          * 2) to enable idling (which is required for media C6) we need to
 903          *    initialize the IDLE_MSG register for the GSC CS and do at least 1
 904          *    submission, which will wake up the GSC power well.
 905          */
 906         if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(&gt->uc)) {
 907                 gt_notice(gt, "No GSC FW selected, disabling GSC CS and media C6\n");
 908                 info->engine_mask &= ~BIT(GSC0);
 909         }
 910
 911         return info->engine_mask;
 912 }
 913
 914 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
 915                                  u8 class, const u8 *map, u8 num_instances)
 916 {
 917         int i, j;
 918         u8 current_logical_id = 0;
 919
 920         for (j = 0; j < num_instances; ++j) {
 921                 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
 922                         if (!HAS_ENGINE(gt, i) ||
 923                             intel_engines[i].class != class)
 924                                 continue;
 925
 926                         if (intel_engines[i].instance == map[j]) {
 927                                 logical_ids[intel_engines[i].instance] =
 928                                         current_logical_id++;
 929                                 break;
 930                         }
 931                 }
 932         }
 933 }
 934
 935 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
 936 {
 937         /*
 938          * Logical to physical mapping is needed for proper support
 939          * to split-frame feature.
 940          */
 941         if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
 942                 const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
 943
 944                 populate_logical_ids(gt, logical_ids, class,
 945                                      map, ARRAY_SIZE(map));
 946         } else {
 947                 int i;
 948                 u8 map[MAX_ENGINE_INSTANCE + 1];
 949
 950                 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
 951                         map[i] = i;
 952                 populate_logical_ids(gt, logical_ids, class,
 953                                      map, ARRAY_SIZE(map));
 954         }
 955 }
 956
 957 /**
 958  * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
 959  * @gt: pointer to struct intel_gt
 960  *
 961  * Return: non-zero if the initialization failed.
 962  */
 963 int intel_engines_init_mmio(struct intel_gt *gt)
 964 {
 965         struct drm_i915_private *i915 = gt->i915;
 966         const unsigned int engine_mask = init_engine_mask(gt);
 967         unsigned int mask = 0;
 968         unsigned int i, class;
 969         u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
 970         int err;
 971
 972         drm_WARN_ON(&i915->drm, engine_mask == 0);
 973         drm_WARN_ON(&i915->drm, engine_mask &
 974                     GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
 975
 976         if (i915_inject_probe_failure(i915))
 977                 return -ENODEV;
 978
 979         for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
 980                 setup_logical_ids(gt, logical_ids, class);
 981
 982                 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
 983                         u8 instance = intel_engines[i].instance;
 984
 985                         if (intel_engines[i].class != class ||
 986                             !HAS_ENGINE(gt, i))
 987                                 continue;
 988
 989                         err = intel_engine_setup(gt, i,
 990                                                  logical_ids[instance]);
 991                         if (err)
 992                                 goto cleanup;
 993
 994                         mask |= BIT(i);
 995                 }
 996         }
 997
 998         /*
 999          * Catch failures to update intel_engines table when the new engines
1000          * are added to the driver by a warning and disabling the forgotten
1001          * engines.
1002          */
1003         if (drm_WARN_ON(&i915->drm, mask != engine_mask))
1004                 gt->info.engine_mask = mask;
1005
1006         gt->info.num_engines = hweight32(mask);
1007
1008         intel_gt_check_and_clear_faults(gt);
1009
1010         intel_setup_engine_capabilities(gt);
1011
1012         intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
1013
1014         return 0;
1015
1016 cleanup:
1017         intel_engines_free(gt);
1018         return err;
1019 }
1020
1021 void intel_engine_init_execlists(struct intel_engine_cs *engine)
1022 {
1023         struct intel_engine_execlists * const execlists = &engine->execlists;
1024
1025         execlists->port_mask = 1;
1026         GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
1027         GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
1028
1029         memset(execlists->pending, 0, sizeof(execlists->pending));
1030         execlists->active =
1031                 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1032 }
1033
1034 static void cleanup_status_page(struct intel_engine_cs *engine)
1035 {
1036         struct i915_vma *vma;
1037
1038         /* Prevent writes into HWSP after returning the page to the system */
1039         intel_engine_set_hwsp_writemask(engine, ~0u);
1040
1041         vma = fetch_and_zero(&engine->status_page.vma);
1042         if (!vma)
1043                 return;
1044
1045         if (!HWS_NEEDS_PHYSICAL(engine->i915))
1046                 i915_vma_unpin(vma);
1047
1048         i915_gem_object_unpin_map(vma->obj);
1049         i915_gem_object_put(vma->obj);
1050 }
1051
1052 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
1053                                 struct i915_gem_ww_ctx *ww,
1054                                 struct i915_vma *vma)
1055 {
1056         unsigned int flags;
1057
1058         if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
1059                 /*
1060                  * On g33, we cannot place HWS above 256MiB, so
1061                  * restrict its pinning to the low mappable arena.
1062                  * Though this restriction is not documented for
1063                  * gen4, gen5, or byt, they also behave similarly
1064                  * and hang if the HWS is placed at the top of the
1065                  * GTT. To generalise, it appears that all !llc
1066                  * platforms have issues with us placing the HWS
1067                  * above the mappable region (even though we never
1068                  * actually map it).
1069                  */
1070                 flags = PIN_MAPPABLE;
1071         else
1072                 flags = PIN_HIGH;
1073
1074         return i915_ggtt_pin(vma, ww, 0, flags);
1075 }
1076
1077 static int init_status_page(struct intel_engine_cs *engine)
1078 {
1079         struct drm_i915_gem_object *obj;
1080         struct i915_gem_ww_ctx ww;
1081         struct i915_vma *vma;
1082         void *vaddr;
1083         int ret;
1084
1085         INIT_LIST_HEAD(&engine->status_page.timelines);
1086
1087         /*
1088          * Though the HWS register does support 36bit addresses, historically
1089          * we have had hangs and corruption reported due to wild writes if
1090          * the HWS is placed above 4G. We only allow objects to be allocated
1091          * in GFP_DMA32 for i965, and no earlier physical address users had
1092          * access to more than 4G.
1093          */
1094         obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
1095         if (IS_ERR(obj)) {
1096                 gt_err(engine->gt, "Failed to allocate status page\n");
1097                 return PTR_ERR(obj);
1098         }
1099
1100         i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1101
1102         vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1103         if (IS_ERR(vma)) {
1104                 ret = PTR_ERR(vma);
1105                 goto err_put;
1106         }
1107
1108         i915_gem_ww_ctx_init(&ww, true);
1109 retry:
1110         ret = i915_gem_object_lock(obj, &ww);
1111         if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1112                 ret = pin_ggtt_status_page(engine, &ww, vma);
1113         if (ret)
1114                 goto err;
1115
1116         vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1117         if (IS_ERR(vaddr)) {
1118                 ret = PTR_ERR(vaddr);
1119                 goto err_unpin;
1120         }
1121
1122         engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1123         engine->status_page.vma = vma;
1124
1125 err_unpin:
1126         if (ret)
1127                 i915_vma_unpin(vma);
1128 err:
1129         if (ret == -EDEADLK) {
1130                 ret = i915_gem_ww_ctx_backoff(&ww);
1131                 if (!ret)
1132                         goto retry;
1133         }
1134         i915_gem_ww_ctx_fini(&ww);
1135 err_put:
1136         if (ret)
1137                 i915_gem_object_put(obj);
1138         return ret;
1139 }
1140
1141 static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
1142 {
1143         static const union intel_engine_tlb_inv_reg gen8_regs[] = {
1144                 [RENDER_CLASS].reg              = GEN8_RTCR,
1145                 [VIDEO_DECODE_CLASS].reg        = GEN8_M1TCR, /* , GEN8_M2TCR */
1146                 [VIDEO_ENHANCEMENT_CLASS].reg   = GEN8_VTCR,
1147                 [COPY_ENGINE_CLASS].reg         = GEN8_BTCR,
1148         };
1149         static const union intel_engine_tlb_inv_reg gen12_regs[] = {
1150                 [RENDER_CLASS].reg              = GEN12_GFX_TLB_INV_CR,
1151                 [VIDEO_DECODE_CLASS].reg        = GEN12_VD_TLB_INV_CR,
1152                 [VIDEO_ENHANCEMENT_CLASS].reg   = GEN12_VE_TLB_INV_CR,
1153                 [COPY_ENGINE_CLASS].reg         = GEN12_BLT_TLB_INV_CR,
1154                 [COMPUTE_CLASS].reg             = GEN12_COMPCTX_TLB_INV_CR,
1155         };
1156         static const union intel_engine_tlb_inv_reg xehp_regs[] = {
1157                 [RENDER_CLASS].mcr_reg            = XEHP_GFX_TLB_INV_CR,
1158                 [VIDEO_DECODE_CLASS].mcr_reg      = XEHP_VD_TLB_INV_CR,
1159                 [VIDEO_ENHANCEMENT_CLASS].mcr_reg = XEHP_VE_TLB_INV_CR,
1160                 [COPY_ENGINE_CLASS].mcr_reg       = XEHP_BLT_TLB_INV_CR,
1161                 [COMPUTE_CLASS].mcr_reg           = XEHP_COMPCTX_TLB_INV_CR,
1162         };
1163         static const union intel_engine_tlb_inv_reg xelpmp_regs[] = {
1164                 [VIDEO_DECODE_CLASS].reg          = GEN12_VD_TLB_INV_CR,
1165                 [VIDEO_ENHANCEMENT_CLASS].reg     = GEN12_VE_TLB_INV_CR,
1166                 [OTHER_CLASS].reg                 = XELPMP_GSC_TLB_INV_CR,
1167         };
1168         struct drm_i915_private *i915 = engine->i915;
1169         const unsigned int instance = engine->instance;
1170         const unsigned int class = engine->class;
1171         const union intel_engine_tlb_inv_reg *regs;
1172         union intel_engine_tlb_inv_reg reg;
1173         unsigned int num = 0;
1174         u32 val;
1175
1176         /*
1177          * New platforms should not be added with catch-all-newer (>=)
1178          * condition so that any later platform added triggers the below warning
1179          * and in turn mandates a human cross-check of whether the invalidation
1180          * flows have compatible semantics.
1181          *
1182          * For instance with the 11.00 -> 12.00 transition three out of five
1183          * respective engine registers were moved to masked type. Then after the
1184          * 12.00 -> 12.50 transition multi cast handling is required too.
1185          */
1186
1187         if (engine->gt->type == GT_MEDIA) {
1188                 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
1189                         regs = xelpmp_regs;
1190                         num = ARRAY_SIZE(xelpmp_regs);
1191                 }
1192         } else {
1193                 if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
1194                     GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
1195                     GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
1196                     GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
1197                     GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
1198                         regs = xehp_regs;
1199                         num = ARRAY_SIZE(xehp_regs);
1200                 } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) ||
1201                            GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) {
1202                         regs = gen12_regs;
1203                         num = ARRAY_SIZE(gen12_regs);
1204                 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
1205                         regs = gen8_regs;
1206                         num = ARRAY_SIZE(gen8_regs);
1207                 } else if (GRAPHICS_VER(i915) < 8) {
1208                         return 0;
1209                 }
1210         }
1211
1212         if (gt_WARN_ONCE(engine->gt, !num,
1213                          "Platform does not implement TLB invalidation!"))
1214                 return -ENODEV;
1215
1216         if (gt_WARN_ON_ONCE(engine->gt,
1217                             class >= num ||
1218                             (!regs[class].reg.reg &&
1219                              !regs[class].mcr_reg.reg)))
1220                 return -ERANGE;
1221
1222         reg = regs[class];
1223
1224         if (regs == xelpmp_regs && class == OTHER_CLASS) {
1225                 /*
1226                  * There's only a single GSC instance, but it uses register bit
1227                  * 1 instead of either 0 or OTHER_GSC_INSTANCE.
1228                  */
1229                 GEM_WARN_ON(instance != OTHER_GSC_INSTANCE);
1230                 val = 1;
1231         } else if (regs == gen8_regs && class == VIDEO_DECODE_CLASS && instance == 1) {
1232                 reg.reg = GEN8_M2TCR;
1233                 val = 0;
1234         } else {
1235                 val = instance;
1236         }
1237
1238         val = BIT(val);
1239
1240         engine->tlb_inv.mcr = regs == xehp_regs;
1241         engine->tlb_inv.reg = reg;
1242         engine->tlb_inv.done = val;
1243
1244         if (GRAPHICS_VER(i915) >= 12 &&
1245             (engine->class == VIDEO_DECODE_CLASS ||
1246              engine->class == VIDEO_ENHANCEMENT_CLASS ||
1247              engine->class == COMPUTE_CLASS ||
1248              engine->class == OTHER_CLASS))
1249                 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);
1250         else
1251                 engine->tlb_inv.request = val;
1252
1253         return 0;
1254 }
1255
1256 static int engine_setup_common(struct intel_engine_cs *engine)
1257 {
1258         int err;
1259
1260         init_llist_head(&engine->barrier_tasks);
1261
1262         err = intel_engine_init_tlb_invalidation(engine);
1263         if (err)
1264                 return err;
1265
1266         err = init_status_page(engine);
1267         if (err)
1268                 return err;
1269
1270         engine->breadcrumbs = intel_breadcrumbs_create(engine);
1271         if (!engine->breadcrumbs) {
1272                 err = -ENOMEM;
1273                 goto err_status;
1274         }
1275
1276         engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1277         if (!engine->sched_engine) {
1278                 err = -ENOMEM;
1279                 goto err_sched_engine;
1280         }
1281         engine->sched_engine->private_data = engine;
1282
1283         err = intel_engine_init_cmd_parser(engine);
1284         if (err)
1285                 goto err_cmd_parser;
1286
1287         intel_engine_init_execlists(engine);
1288         intel_engine_init__pm(engine);
1289         intel_engine_init_retire(engine);
1290
1291         /* Use the whole device by default */
1292         engine->sseu =
1293                 intel_sseu_from_device_info(&engine->gt->info.sseu);
1294
1295         intel_engine_init_workarounds(engine);
1296         intel_engine_init_whitelist(engine);
1297         intel_engine_init_ctx_wa(engine);
1298
1299         if (GRAPHICS_VER(engine->i915) >= 12)
1300                 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1301
1302         return 0;
1303
1304 err_cmd_parser:
1305         i915_sched_engine_put(engine->sched_engine);
1306 err_sched_engine:
1307         intel_breadcrumbs_put(engine->breadcrumbs);
1308 err_status:
1309         cleanup_status_page(engine);
1310         return err;
1311 }
1312
1313 struct measure_breadcrumb {
1314         struct i915_request rq;
1315         struct intel_ring ring;
1316         u32 cs[2048];
1317 };
1318
1319 static int measure_breadcrumb_dw(struct intel_context *ce)
1320 {
1321         struct intel_engine_cs *engine = ce->engine;
1322         struct measure_breadcrumb *frame;
1323         int dw;
1324
1325         GEM_BUG_ON(!engine->gt->scratch);
1326
1327         frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1328         if (!frame)
1329                 return -ENOMEM;
1330
1331         frame->rq.i915 = engine->i915;
1332         frame->rq.engine = engine;
1333         frame->rq.context = ce;
1334         rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1335         frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1336
1337         frame->ring.vaddr = frame->cs;
1338         frame->ring.size = sizeof(frame->cs);
1339         frame->ring.wrap =
1340                 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1341         frame->ring.effective_size = frame->ring.size;
1342         intel_ring_update_space(&frame->ring);
1343         frame->rq.ring = &frame->ring;
1344
1345         mutex_lock(&ce->timeline->mutex);
1346         spin_lock_irq(&engine->sched_engine->lock);
1347
1348         dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1349
1350         spin_unlock_irq(&engine->sched_engine->lock);
1351         mutex_unlock(&ce->timeline->mutex);
1352
1353         GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1354
1355         kfree(frame);
1356         return dw;
1357 }
1358
1359 struct intel_context *
1360 intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1361                                    struct i915_address_space *vm,
1362                                    unsigned int ring_size,
1363                                    unsigned int hwsp,
1364                                    struct lock_class_key *key,
1365                                    const char *name)
1366 {
1367         struct intel_context *ce;
1368         int err;
1369
1370         ce = intel_context_create(engine);
1371         if (IS_ERR(ce))
1372                 return ce;
1373
1374         __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1375         ce->timeline = page_pack_bits(NULL, hwsp);
1376         ce->ring = NULL;
1377         ce->ring_size = ring_size;
1378
1379         i915_vm_put(ce->vm);
1380         ce->vm = i915_vm_get(vm);
1381
1382         err = intel_context_pin(ce); /* perma-pin so it is always available */
1383         if (err) {
1384                 intel_context_put(ce);
1385                 return ERR_PTR(err);
1386         }
1387
1388         list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1389
1390         /*
1391          * Give our perma-pinned kernel timelines a separate lockdep class,
1392          * so that we can use them from within the normal user timelines
1393          * should we need to inject GPU operations during their request
1394          * construction.
1395          */
1396         lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1397
1398         return ce;
1399 }
1400
1401 void intel_engine_destroy_pinned_context(struct intel_context *ce)
1402 {
1403         struct intel_engine_cs *engine = ce->engine;
1404         struct i915_vma *hwsp = engine->status_page.vma;
1405
1406         GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1407
1408         mutex_lock(&hwsp->vm->mutex);
1409         list_del(&ce->timeline->engine_link);
1410         mutex_unlock(&hwsp->vm->mutex);
1411
1412         list_del(&ce->pinned_contexts_link);
1413         intel_context_unpin(ce);
1414         intel_context_put(ce);
1415 }
1416
1417 static struct intel_context *
1418 create_ggtt_bind_context(struct intel_engine_cs *engine)
1419 {
1420         static struct lock_class_key kernel;
1421
1422         /*
1423          * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple
1424          * bind requets at a time so get a bigger ring.
1425          */
1426         return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,
1427                                                   I915_GEM_HWS_GGTT_BIND_ADDR,
1428                                                   &kernel, "ggtt_bind_context");
1429 }
1430
1431 static struct intel_context *
1432 create_kernel_context(struct intel_engine_cs *engine)
1433 {
1434         static struct lock_class_key kernel;
1435
1436         return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1437                                                   I915_GEM_HWS_SEQNO_ADDR,
1438                                                   &kernel, "kernel_context");
1439 }
1440
1441 /*
1442  * engine_init_common - initialize engine state which might require hw access
1443  * @engine: Engine to initialize.
1444  *
1445  * Initializes @engine@ structure members shared between legacy and execlists
1446  * submission modes which do require hardware access.
1447  *
1448  * Typcally done at later stages of submission mode specific engine setup.
1449  *
1450  * Returns zero on success or an error code on failure.
1451  */
1452 static int engine_init_common(struct intel_engine_cs *engine)
1453 {
1454         struct intel_context *ce, *bce = NULL;
1455         int ret;
1456
1457         engine->set_default_submission(engine);
1458
1459         /*
1460          * We may need to do things with the shrinker which
1461          * require us to immediately switch back to the default
1462          * context. This can cause a problem as pinning the
1463          * default context also requires GTT space which may not
1464          * be available. To avoid this we always pin the default
1465          * context.
1466          */
1467         ce = create_kernel_context(engine);
1468         if (IS_ERR(ce))
1469                 return PTR_ERR(ce);
1470         /*
1471          * Create a separate pinned context for GGTT update with blitter engine
1472          * if a platform require such service. MI_UPDATE_GTT works on other
1473          * engines as well but BCS should be less busy engine so pick that for
1474          * GGTT updates.
1475          */
1476         if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
1477                 bce = create_ggtt_bind_context(engine);
1478                 if (IS_ERR(bce)) {
1479                         ret = PTR_ERR(bce);
1480                         goto err_ce_context;
1481                 }
1482         }
1483
1484         ret = measure_breadcrumb_dw(ce);
1485         if (ret < 0)
1486                 goto err_bce_context;
1487
1488         engine->emit_fini_breadcrumb_dw = ret;
1489         engine->kernel_context = ce;
1490         engine->bind_context = bce;
1491
1492         return 0;
1493
1494 err_bce_context:
1495         if (bce)
1496                 intel_engine_destroy_pinned_context(bce);
1497 err_ce_context:
1498         intel_engine_destroy_pinned_context(ce);
1499         return ret;
1500 }
1501
1502 int intel_engines_init(struct intel_gt *gt)
1503 {
1504         int (*setup)(struct intel_engine_cs *engine);
1505         struct intel_engine_cs *engine;
1506         enum intel_engine_id id;
1507         int err;
1508
1509         if (intel_uc_uses_guc_submission(&gt->uc)) {
1510                 gt->submission_method = INTEL_SUBMISSION_GUC;
1511                 setup = intel_guc_submission_setup;
1512         } else if (HAS_EXECLISTS(gt->i915)) {
1513                 gt->submission_method = INTEL_SUBMISSION_ELSP;
1514                 setup = intel_execlists_submission_setup;
1515         } else {
1516                 gt->submission_method = INTEL_SUBMISSION_RING;
1517                 setup = intel_ring_submission_setup;
1518         }
1519
1520         for_each_engine(engine, gt, id) {
1521                 err = engine_setup_common(engine);
1522                 if (err)
1523                         return err;
1524
1525                 err = setup(engine);
1526                 if (err) {
1527                         intel_engine_cleanup_common(engine);
1528                         return err;
1529                 }
1530
1531                 /* The backend should now be responsible for cleanup */
1532                 GEM_BUG_ON(engine->release == NULL);
1533
1534                 err = engine_init_common(engine);
1535                 if (err)
1536                         return err;
1537
1538                 intel_engine_add_user(engine);
1539         }
1540
1541         return 0;
1542 }
1543
1544 /**
1545  * intel_engine_cleanup_common - cleans up the engine state created by
1546  *                                the common initiailizers.
1547  * @engine: Engine to cleanup.
1548  *
1549  * This cleans up everything created by the common helpers.
1550  */
1551 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1552 {
1553         GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1554
1555         i915_sched_engine_put(engine->sched_engine);
1556         intel_breadcrumbs_put(engine->breadcrumbs);
1557
1558         intel_engine_fini_retire(engine);
1559         intel_engine_cleanup_cmd_parser(engine);
1560
1561         if (engine->default_state)
1562                 fput(engine->default_state);
1563
1564         if (engine->kernel_context)
1565                 intel_engine_destroy_pinned_context(engine->kernel_context);
1566
1567         if (engine->bind_context)
1568                 intel_engine_destroy_pinned_context(engine->bind_context);
1569
1570
1571         GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1572         cleanup_status_page(engine);
1573
1574         intel_wa_list_free(&engine->ctx_wa_list);
1575         intel_wa_list_free(&engine->wa_list);
1576         intel_wa_list_free(&engine->whitelist);
1577 }
1578
1579 /**
1580  * intel_engine_resume - re-initializes the HW state of the engine
1581  * @engine: Engine to resume.
1582  *
1583  * Returns zero on success or an error code on failure.
1584  */
1585 int intel_engine_resume(struct intel_engine_cs *engine)
1586 {
1587         intel_engine_apply_workarounds(engine);
1588         intel_engine_apply_whitelist(engine);
1589
1590         return engine->resume(engine);
1591 }
1592
1593 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1594 {
1595         struct drm_i915_private *i915 = engine->i915;
1596
1597         u64 acthd;
1598
1599         if (GRAPHICS_VER(i915) >= 8)
1600                 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1601         else if (GRAPHICS_VER(i915) >= 4)
1602                 acthd = ENGINE_READ(engine, RING_ACTHD);
1603         else
1604                 acthd = ENGINE_READ(engine, ACTHD);
1605
1606         return acthd;
1607 }
1608
1609 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1610 {
1611         u64 bbaddr;
1612
1613         if (GRAPHICS_VER(engine->i915) >= 8)
1614                 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1615         else
1616                 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1617
1618         return bbaddr;
1619 }
1620
1621 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1622 {
1623         if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1624                 return 0;
1625
1626         /*
1627          * If we are doing a normal GPU reset, we can take our time and allow
1628          * the engine to quiesce. We've stopped submission to the engine, and
1629          * if we wait long enough an innocent context should complete and
1630          * leave the engine idle. So they should not be caught unaware by
1631          * the forthcoming GPU reset (which usually follows the stop_cs)!
1632          */
1633         return READ_ONCE(engine->props.stop_timeout_ms);
1634 }
1635
1636 static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1637                                   int fast_timeout_us,
1638                                   int slow_timeout_ms)
1639 {
1640         struct intel_uncore *uncore = engine->uncore;
1641         const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1642         int err;
1643
1644         intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1645
1646         /*
1647          * Wa_22011802037: Prior to doing a reset, ensure CS is
1648          * stopped, set ring stop bit and prefetch disable bit to halt CS
1649          */
1650         if (intel_engine_reset_needs_wa_22011802037(engine->gt))
1651                 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1652                                       _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1653
1654         err = __intel_wait_for_register_fw(engine->uncore, mode,
1655                                            MODE_IDLE, MODE_IDLE,
1656                                            fast_timeout_us,
1657                                            slow_timeout_ms,
1658                                            NULL);
1659
1660         /* A final mmio read to let GPU writes be hopefully flushed to memory */
1661         intel_uncore_posting_read_fw(uncore, mode);
1662         return err;
1663 }
1664
1665 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1666 {
1667         int err = 0;
1668
1669         if (GRAPHICS_VER(engine->i915) < 3)
1670                 return -ENODEV;
1671
1672         ENGINE_TRACE(engine, "\n");
1673         /*
1674          * TODO: Find out why occasionally stopping the CS times out. Seen
1675          * especially with gem_eio tests.
1676          *
1677          * Occasionally trying to stop the cs times out, but does not adversely
1678          * affect functionality. The timeout is set as a config parameter that
1679          * defaults to 100ms. In most cases the follow up operation is to wait
1680          * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1681          * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1682          * caused, the caller must check and handle the return from this
1683          * function.
1684          */
1685         if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1686                 ENGINE_TRACE(engine,
1687                              "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1688                              ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1689                              ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1690
1691                 /*
1692                  * Sometimes we observe that the idle flag is not
1693                  * set even though the ring is empty. So double
1694                  * check before giving up.
1695                  */
1696                 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1697                     (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1698                         err = -ETIMEDOUT;
1699         }
1700
1701         return err;
1702 }
1703
1704 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1705 {
1706         ENGINE_TRACE(engine, "\n");
1707
1708         ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1709 }
1710
1711 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1712 {
1713         static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1714                 [RCS0] = MSG_IDLE_CS,
1715                 [BCS0] = MSG_IDLE_BCS,
1716                 [VCS0] = MSG_IDLE_VCS0,
1717                 [VCS1] = MSG_IDLE_VCS1,
1718                 [VCS2] = MSG_IDLE_VCS2,
1719                 [VCS3] = MSG_IDLE_VCS3,
1720                 [VCS4] = MSG_IDLE_VCS4,
1721                 [VCS5] = MSG_IDLE_VCS5,
1722                 [VCS6] = MSG_IDLE_VCS6,
1723                 [VCS7] = MSG_IDLE_VCS7,
1724                 [VECS0] = MSG_IDLE_VECS0,
1725                 [VECS1] = MSG_IDLE_VECS1,
1726                 [VECS2] = MSG_IDLE_VECS2,
1727                 [VECS3] = MSG_IDLE_VECS3,
1728                 [CCS0] = MSG_IDLE_CS,
1729                 [CCS1] = MSG_IDLE_CS,
1730                 [CCS2] = MSG_IDLE_CS,
1731                 [CCS3] = MSG_IDLE_CS,
1732         };
1733         u32 val;
1734
1735         if (!_reg[engine->id].reg)
1736                 return 0;
1737
1738         val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1739
1740         /* bits[29:25] & bits[13:9] >> shift */
1741         return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1742 }
1743
1744 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1745 {
1746         int ret;
1747
1748         /* Ensure GPM receives fw up/down after CS is stopped */
1749         udelay(1);
1750
1751         /* Wait for forcewake request to complete in GPM */
1752         ret =  __intel_wait_for_register_fw(gt->uncore,
1753                                             GEN9_PWRGT_DOMAIN_STATUS,
1754                                             fw_mask, fw_mask, 5000, 0, NULL);
1755
1756         /* Ensure CS receives fw ack from GPM */
1757         udelay(1);
1758
1759         if (ret)
1760                 GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1761 }
1762
1763 /*
1764  * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1765  * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1766  * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1767  * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1768  * are concerned only with the gt reset here, we use a logical OR of pending
1769  * forcewakeups from all reset domains and then wait for them to complete by
1770  * querying PWRGT_DOMAIN_STATUS.
1771  */
1772 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1773 {
1774         u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1775
1776         if (fw_pending)
1777                 __gpm_wait_for_fw_complete(engine->gt, fw_pending);
1778 }
1779
1780 /* NB: please notice the memset */
1781 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1782                                struct intel_instdone *instdone)
1783 {
1784         struct drm_i915_private *i915 = engine->i915;
1785         struct intel_uncore *uncore = engine->uncore;
1786         u32 mmio_base = engine->mmio_base;
1787         int slice;
1788         int subslice;
1789         int iter;
1790
1791         memset(instdone, 0, sizeof(*instdone));
1792
1793         if (GRAPHICS_VER(i915) >= 8) {
1794                 instdone->instdone =
1795                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1796
1797                 if (engine->id != RCS0)
1798                         return;
1799
1800                 instdone->slice_common =
1801                         intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1802                 if (GRAPHICS_VER(i915) >= 12) {
1803                         instdone->slice_common_extra[0] =
1804                                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1805                         instdone->slice_common_extra[1] =
1806                                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1807                 }
1808
1809                 for_each_ss_steering(iter, engine->gt, slice, subslice) {
1810                         instdone->sampler[slice][subslice] =
1811                                 intel_gt_mcr_read(engine->gt,
1812                                                   GEN8_SAMPLER_INSTDONE,
1813                                                   slice, subslice);
1814                         instdone->row[slice][subslice] =
1815                                 intel_gt_mcr_read(engine->gt,
1816                                                   GEN8_ROW_INSTDONE,
1817                                                   slice, subslice);
1818                 }
1819
1820                 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1821                         for_each_ss_steering(iter, engine->gt, slice, subslice)
1822                                 instdone->geom_svg[slice][subslice] =
1823                                         intel_gt_mcr_read(engine->gt,
1824                                                           XEHPG_INSTDONE_GEOM_SVG,
1825                                                           slice, subslice);
1826                 }
1827         } else if (GRAPHICS_VER(i915) >= 7) {
1828                 instdone->instdone =
1829                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1830
1831                 if (engine->id != RCS0)
1832                         return;
1833
1834                 instdone->slice_common =
1835                         intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1836                 instdone->sampler[0][0] =
1837                         intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1838                 instdone->row[0][0] =
1839                         intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1840         } else if (GRAPHICS_VER(i915) >= 4) {
1841                 instdone->instdone =
1842                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1843                 if (engine->id == RCS0)
1844                         /* HACK: Using the wrong struct member */
1845                         instdone->slice_common =
1846                                 intel_uncore_read(uncore, GEN4_INSTDONE1);
1847         } else {
1848                 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1849         }
1850 }
1851
1852 static bool ring_is_idle(struct intel_engine_cs *engine)
1853 {
1854         bool idle = true;
1855
1856         if (I915_SELFTEST_ONLY(!engine->mmio_base))
1857                 return true;
1858
1859         if (!intel_engine_pm_get_if_awake(engine))
1860                 return true;
1861
1862         /* First check that no commands are left in the ring */
1863         if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1864             (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1865                 idle = false;
1866
1867         /* No bit for gen2, so assume the CS parser is idle */
1868         if (GRAPHICS_VER(engine->i915) > 2 &&
1869             !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1870                 idle = false;
1871
1872         intel_engine_pm_put(engine);
1873
1874         return idle;
1875 }
1876
1877 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1878 {
1879         struct tasklet_struct *t = &engine->sched_engine->tasklet;
1880
1881         if (!t->callback)
1882                 return;
1883
1884         local_bh_disable();
1885         if (tasklet_trylock(t)) {
1886                 /* Must wait for any GPU reset in progress. */
1887                 if (__tasklet_is_enabled(t))
1888                         t->callback(t);
1889                 tasklet_unlock(t);
1890         }
1891         local_bh_enable();
1892
1893         /* Synchronise and wait for the tasklet on another CPU */
1894         if (sync)
1895                 tasklet_unlock_wait(t);
1896 }
1897
1898 /**
1899  * intel_engine_is_idle() - Report if the engine has finished process all work
1900  * @engine: the intel_engine_cs
1901  *
1902  * Return true if there are no requests pending, nothing left to be submitted
1903  * to hardware, and that the engine is idle.
1904  */
1905 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1906 {
1907         /* More white lies, if wedged, hw state is inconsistent */
1908         if (intel_gt_is_wedged(engine->gt))
1909                 return true;
1910
1911         if (!intel_engine_pm_is_awake(engine))
1912                 return true;
1913
1914         /* Waiting to drain ELSP? */
1915         intel_synchronize_hardirq(engine->i915);
1916         intel_engine_flush_submission(engine);
1917
1918         /* ELSP is empty, but there are ready requests? E.g. after reset */
1919         if (!i915_sched_engine_is_empty(engine->sched_engine))
1920                 return false;
1921
1922         /* Ring stopped? */
1923         return ring_is_idle(engine);
1924 }
1925
1926 bool intel_engines_are_idle(struct intel_gt *gt)
1927 {
1928         struct intel_engine_cs *engine;
1929         enum intel_engine_id id;
1930
1931         /*
1932          * If the driver is wedged, HW state may be very inconsistent and
1933          * report that it is still busy, even though we have stopped using it.
1934          */
1935         if (intel_gt_is_wedged(gt))
1936                 return true;
1937
1938         /* Already parked (and passed an idleness test); must still be idle */
1939         if (!READ_ONCE(gt->awake))
1940                 return true;
1941
1942         for_each_engine(engine, gt, id) {
1943                 if (!intel_engine_is_idle(engine))
1944                         return false;
1945         }
1946
1947         return true;
1948 }
1949
1950 bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1951 {
1952         if (!engine->irq_enable)
1953                 return false;
1954
1955         /* Caller disables interrupts */
1956         spin_lock(engine->gt->irq_lock);
1957         engine->irq_enable(engine);
1958         spin_unlock(engine->gt->irq_lock);
1959
1960         return true;
1961 }
1962
1963 void intel_engine_irq_disable(struct intel_engine_cs *engine)
1964 {
1965         if (!engine->irq_disable)
1966                 return;
1967
1968         /* Caller disables interrupts */
1969         spin_lock(engine->gt->irq_lock);
1970         engine->irq_disable(engine);
1971         spin_unlock(engine->gt->irq_lock);
1972 }
1973
1974 void intel_engines_reset_default_submission(struct intel_gt *gt)
1975 {
1976         struct intel_engine_cs *engine;
1977         enum intel_engine_id id;
1978
1979         for_each_engine(engine, gt, id) {
1980                 if (engine->sanitize)
1981                         engine->sanitize(engine);
1982
1983                 engine->set_default_submission(engine);
1984         }
1985 }
1986
1987 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1988 {
1989         switch (GRAPHICS_VER(engine->i915)) {
1990         case 2:
1991                 return false; /* uses physical not virtual addresses */
1992         case 3:
1993                 /* maybe only uses physical not virtual addresses */
1994                 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1995         case 4:
1996                 return !IS_I965G(engine->i915); /* who knows! */
1997         case 6:
1998                 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1999         default:
2000                 return true;
2001         }
2002 }
2003
2004 static struct intel_timeline *get_timeline(struct i915_request *rq)
2005 {
2006         struct intel_timeline *tl;
2007
2008         /*
2009          * Even though we are holding the engine->sched_engine->lock here, there
2010          * is no control over the submission queue per-se and we are
2011          * inspecting the active state at a random point in time, with an
2012          * unknown queue. Play safe and make sure the timeline remains valid.
2013          * (Only being used for pretty printing, one extra kref shouldn't
2014          * cause a camel stampede!)
2015          */
2016         rcu_read_lock();
2017         tl = rcu_dereference(rq->timeline);
2018         if (!kref_get_unless_zero(&tl->kref))
2019                 tl = NULL;
2020         rcu_read_unlock();
2021
2022         return tl;
2023 }
2024
2025 static int print_ring(char *buf, int sz, struct i915_request *rq)
2026 {
2027         int len = 0;
2028
2029         if (!i915_request_signaled(rq)) {
2030                 struct intel_timeline *tl = get_timeline(rq);
2031
2032                 len = scnprintf(buf, sz,
2033                                 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
2034                                 i915_ggtt_offset(rq->ring->vma),
2035                                 tl ? tl->hwsp_offset : 0,
2036                                 hwsp_seqno(rq),
2037                                 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
2038                                                       1000 * 1000));
2039
2040                 if (tl)
2041                         intel_timeline_put(tl);
2042         }
2043
2044         return len;
2045 }
2046
2047 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
2048 {
2049         const size_t rowsize = 8 * sizeof(u32);
2050         const void *prev = NULL;
2051         bool skip = false;
2052         size_t pos;
2053
2054         for (pos = 0; pos < len; pos += rowsize) {
2055                 char line[128];
2056
2057                 if (prev && !memcmp(prev, buf + pos, rowsize)) {
2058                         if (!skip) {
2059                                 drm_printf(m, "*\n");
2060                                 skip = true;
2061                         }
2062                         continue;
2063                 }
2064
2065                 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
2066                                                 rowsize, sizeof(u32),
2067                                                 line, sizeof(line),
2068                                                 false) >= sizeof(line));
2069                 drm_printf(m, "[%04zx] %s\n", pos, line);
2070
2071                 prev = buf + pos;
2072                 skip = false;
2073         }
2074 }
2075
2076 static const char *repr_timer(const struct timer_list *t)
2077 {
2078         if (!READ_ONCE(t->expires))
2079                 return "inactive";
2080
2081         if (timer_pending(t))
2082                 return "active";
2083
2084         return "expired";
2085 }
2086
2087 static void intel_engine_print_registers(struct intel_engine_cs *engine,
2088                                          struct drm_printer *m)
2089 {
2090         struct drm_i915_private *i915 = engine->i915;
2091         struct intel_engine_execlists * const execlists = &engine->execlists;
2092         u64 addr;
2093
2094         if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(i915, 4, 7))
2095                 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
2096         if (HAS_EXECLISTS(i915)) {
2097                 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
2098                            ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
2099                 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
2100                            ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
2101         }
2102         drm_printf(m, "\tRING_START: 0x%08x\n",
2103                    ENGINE_READ(engine, RING_START));
2104         drm_printf(m, "\tRING_HEAD:  0x%08x\n",
2105                    ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
2106         drm_printf(m, "\tRING_TAIL:  0x%08x\n",
2107                    ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
2108         drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
2109                    ENGINE_READ(engine, RING_CTL),
2110                    ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
2111         if (GRAPHICS_VER(engine->i915) > 2) {
2112                 drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
2113                            ENGINE_READ(engine, RING_MI_MODE),
2114                            ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
2115         }
2116
2117         if (GRAPHICS_VER(i915) >= 6) {
2118                 drm_printf(m, "\tRING_IMR:   0x%08x\n",
2119                            ENGINE_READ(engine, RING_IMR));
2120                 drm_printf(m, "\tRING_ESR:   0x%08x\n",
2121                            ENGINE_READ(engine, RING_ESR));
2122                 drm_printf(m, "\tRING_EMR:   0x%08x\n",
2123                            ENGINE_READ(engine, RING_EMR));
2124                 drm_printf(m, "\tRING_EIR:   0x%08x\n",
2125                            ENGINE_READ(engine, RING_EIR));
2126         }
2127
2128         addr = intel_engine_get_active_head(engine);
2129         drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
2130                    upper_32_bits(addr), lower_32_bits(addr));
2131         addr = intel_engine_get_last_batch_head(engine);
2132         drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
2133                    upper_32_bits(addr), lower_32_bits(addr));
2134         if (GRAPHICS_VER(i915) >= 8)
2135                 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
2136         else if (GRAPHICS_VER(i915) >= 4)
2137                 addr = ENGINE_READ(engine, RING_DMA_FADD);
2138         else
2139                 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
2140         drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
2141                    upper_32_bits(addr), lower_32_bits(addr));
2142         if (GRAPHICS_VER(i915) >= 4) {
2143                 drm_printf(m, "\tIPEIR: 0x%08x\n",
2144                            ENGINE_READ(engine, RING_IPEIR));
2145                 drm_printf(m, "\tIPEHR: 0x%08x\n",
2146                            ENGINE_READ(engine, RING_IPEHR));
2147         } else {
2148                 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
2149                 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
2150         }
2151
2152         if (HAS_EXECLISTS(i915) && !intel_engine_uses_guc(engine)) {
2153                 struct i915_request * const *port, *rq;
2154                 const u32 *hws =
2155                         &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2156                 const u8 num_entries = execlists->csb_size;
2157                 unsigned int idx;
2158                 u8 read, write;
2159
2160                 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
2161                            str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
2162                            str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
2163                            repr_timer(&engine->execlists.preempt),
2164                            repr_timer(&engine->execlists.timer));
2165
2166                 read = execlists->csb_head;
2167                 write = READ_ONCE(*execlists->csb_write);
2168
2169                 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
2170                            ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
2171                            ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
2172                            read, write, num_entries);
2173
2174                 if (read >= num_entries)
2175                         read = 0;
2176                 if (write >= num_entries)
2177                         write = 0;
2178                 if (read > write)
2179                         write += num_entries;
2180                 while (read < write) {
2181                         idx = ++read % num_entries;
2182                         drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
2183                                    idx, hws[idx * 2], hws[idx * 2 + 1]);
2184                 }
2185
2186                 i915_sched_engine_active_lock_bh(engine->sched_engine);
2187                 rcu_read_lock();
2188                 for (port = execlists->active; (rq = *port); port++) {
2189                         char hdr[160];
2190                         int len;
2191
2192                         len = scnprintf(hdr, sizeof(hdr),
2193                                         "\t\tActive[%d]:  ccid:%08x%s%s, ",
2194                                         (int)(port - execlists->active),
2195                                         rq->context->lrc.ccid,
2196                                         intel_context_is_closed(rq->context) ? "!" : "",
2197                                         intel_context_is_banned(rq->context) ? "*" : "");
2198                         len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2199                         scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2200                         i915_request_show(m, rq, hdr, 0);
2201                 }
2202                 for (port = execlists->pending; (rq = *port); port++) {
2203                         char hdr[160];
2204                         int len;
2205
2206                         len = scnprintf(hdr, sizeof(hdr),
2207                                         "\t\tPending[%d]: ccid:%08x%s%s, ",
2208                                         (int)(port - execlists->pending),
2209                                         rq->context->lrc.ccid,
2210                                         intel_context_is_closed(rq->context) ? "!" : "",
2211                                         intel_context_is_banned(rq->context) ? "*" : "");
2212                         len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2213                         scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2214                         i915_request_show(m, rq, hdr, 0);
2215                 }
2216                 rcu_read_unlock();
2217                 i915_sched_engine_active_unlock_bh(engine->sched_engine);
2218         } else if (GRAPHICS_VER(i915) > 6) {
2219                 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
2220                            ENGINE_READ(engine, RING_PP_DIR_BASE));
2221                 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
2222                            ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
2223                 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
2224                            ENGINE_READ(engine, RING_PP_DIR_DCLV));
2225         }
2226 }
2227
2228 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
2229 {
2230         struct i915_vma_resource *vma_res = rq->batch_res;
2231         void *ring;
2232         int size;
2233
2234         drm_printf(m,
2235                    "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
2236                    rq->head, rq->postfix, rq->tail,
2237                    vma_res ? upper_32_bits(vma_res->start) : ~0u,
2238                    vma_res ? lower_32_bits(vma_res->start) : ~0u);
2239
2240         size = rq->tail - rq->head;
2241         if (rq->tail < rq->head)
2242                 size += rq->ring->size;
2243
2244         ring = kmalloc(size, GFP_ATOMIC);
2245         if (ring) {
2246                 const void *vaddr = rq->ring->vaddr;
2247                 unsigned int head = rq->head;
2248                 unsigned int len = 0;
2249
2250                 if (rq->tail < head) {
2251                         len = rq->ring->size - head;
2252                         memcpy(ring, vaddr + head, len);
2253                         head = 0;
2254                 }
2255                 memcpy(ring + len, vaddr + head, size - len);
2256
2257                 hexdump(m, ring, size);
2258                 kfree(ring);
2259         }
2260 }
2261
2262 static unsigned long read_ul(void *p, size_t x)
2263 {
2264         return *(unsigned long *)(p + x);
2265 }
2266
2267 static void print_properties(struct intel_engine_cs *engine,
2268                              struct drm_printer *m)
2269 {
2270         static const struct pmap {
2271                 size_t offset;
2272                 const char *name;
2273         } props[] = {
2274 #define P(x) { \
2275         .offset = offsetof(typeof(engine->props), x), \
2276         .name = #x \
2277 }
2278                 P(heartbeat_interval_ms),
2279                 P(max_busywait_duration_ns),
2280                 P(preempt_timeout_ms),
2281                 P(stop_timeout_ms),
2282                 P(timeslice_duration_ms),
2283
2284                 {},
2285 #undef P
2286         };
2287         const struct pmap *p;
2288
2289         drm_printf(m, "\tProperties:\n");
2290         for (p = props; p->name; p++)
2291                 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2292                            p->name,
2293                            read_ul(&engine->props, p->offset),
2294                            read_ul(&engine->defaults, p->offset));
2295 }
2296
2297 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2298 {
2299         struct intel_timeline *tl = get_timeline(rq);
2300
2301         i915_request_show(m, rq, msg, 0);
2302
2303         drm_printf(m, "\t\tring->start:  0x%08x\n",
2304                    i915_ggtt_offset(rq->ring->vma));
2305         drm_printf(m, "\t\tring->head:   0x%08x\n",
2306                    rq->ring->head);
2307         drm_printf(m, "\t\tring->tail:   0x%08x\n",
2308                    rq->ring->tail);
2309         drm_printf(m, "\t\tring->emit:   0x%08x\n",
2310                    rq->ring->emit);
2311         drm_printf(m, "\t\tring->space:  0x%08x\n",
2312                    rq->ring->space);
2313
2314         if (tl) {
2315                 drm_printf(m, "\t\tring->hwsp:   0x%08x\n",
2316                            tl->hwsp_offset);
2317                 intel_timeline_put(tl);
2318         }
2319
2320         print_request_ring(m, rq);
2321
2322         if (rq->context->lrc_reg_state) {
2323                 drm_printf(m, "Logical Ring Context:\n");
2324                 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2325         }
2326 }
2327
2328 void intel_engine_dump_active_requests(struct list_head *requests,
2329                                        struct i915_request *hung_rq,
2330                                        struct drm_printer *m)
2331 {
2332         struct i915_request *rq;
2333         const char *msg;
2334         enum i915_request_state state;
2335
2336         list_for_each_entry(rq, requests, sched.link) {
2337                 if (rq == hung_rq)
2338                         continue;
2339
2340                 state = i915_test_request_state(rq);
2341                 if (state < I915_REQUEST_QUEUED)
2342                         continue;
2343
2344                 if (state == I915_REQUEST_ACTIVE)
2345                         msg = "\t\tactive on engine";
2346                 else
2347                         msg = "\t\tactive in queue";
2348
2349                 engine_dump_request(rq, m, msg);
2350         }
2351 }
2352
2353 static void engine_dump_active_requests(struct intel_engine_cs *engine,
2354                                         struct drm_printer *m)
2355 {
2356         struct intel_context *hung_ce = NULL;
2357         struct i915_request *hung_rq = NULL;
2358
2359         /*
2360          * No need for an engine->irq_seqno_barrier() before the seqno reads.
2361          * The GPU is still running so requests are still executing and any
2362          * hardware reads will be out of date by the time they are reported.
2363          * But the intention here is just to report an instantaneous snapshot
2364          * so that's fine.
2365          */
2366         intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq);
2367
2368         drm_printf(m, "\tRequests:\n");
2369
2370         if (hung_rq)
2371                 engine_dump_request(hung_rq, m, "\t\thung");
2372         else if (hung_ce)
2373                 drm_printf(m, "\t\tGot hung ce but no hung rq!\n");
2374
2375         if (intel_uc_uses_guc_submission(&engine->gt->uc))
2376                 intel_guc_dump_active_requests(engine, hung_rq, m);
2377         else
2378                 intel_execlists_dump_active_requests(engine, hung_rq, m);
2379
2380         if (hung_rq)
2381                 i915_request_put(hung_rq);
2382 }
2383
2384 void intel_engine_dump(struct intel_engine_cs *engine,
2385                        struct drm_printer *m,
2386                        const char *header, ...)
2387 {
2388         struct i915_gpu_error * const error = &engine->i915->gpu_error;
2389         struct i915_request *rq;
2390         intel_wakeref_t wakeref;
2391         ktime_t dummy;
2392
2393         if (header) {
2394                 va_list ap;
2395
2396                 va_start(ap, header);
2397                 drm_vprintf(m, header, &ap);
2398                 va_end(ap);
2399         }
2400
2401         if (intel_gt_is_wedged(engine->gt))
2402                 drm_printf(m, "*** WEDGED ***\n");
2403
2404         drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2405         drm_printf(m, "\tBarriers?: %s\n",
2406                    str_yes_no(!llist_empty(&engine->barrier_tasks)));
2407         drm_printf(m, "\tLatency: %luus\n",
2408                    ewma__engine_latency_read(&engine->latency));
2409         if (intel_engine_supports_stats(engine))
2410                 drm_printf(m, "\tRuntime: %llums\n",
2411                            ktime_to_ms(intel_engine_get_busy_time(engine,
2412                                                                   &dummy)));
2413         drm_printf(m, "\tForcewake: %x domains, %d active\n",
2414                    engine->fw_domain, READ_ONCE(engine->fw_active));
2415
2416         rcu_read_lock();
2417         rq = READ_ONCE(engine->heartbeat.systole);
2418         if (rq)
2419                 drm_printf(m, "\tHeartbeat: %d ms ago\n",
2420                            jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2421         rcu_read_unlock();
2422         drm_printf(m, "\tReset count: %d (global %d)\n",
2423                    i915_reset_engine_count(error, engine),
2424                    i915_reset_count(error));
2425         print_properties(engine, m);
2426
2427         engine_dump_active_requests(engine, m);
2428
2429         drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
2430         wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2431         if (wakeref) {
2432                 intel_engine_print_registers(engine, m);
2433                 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2434         } else {
2435                 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2436         }
2437
2438         intel_execlists_show_requests(engine, m, i915_request_show, 8);
2439
2440         drm_printf(m, "HWSP:\n");
2441         hexdump(m, engine->status_page.addr, PAGE_SIZE);
2442
2443         drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2444
2445         intel_engine_print_breadcrumbs(engine, m);
2446 }
2447
2448 /**
2449  * intel_engine_get_busy_time() - Return current accumulated engine busyness
2450  * @engine: engine to report on
2451  * @now: monotonic timestamp of sampling
2452  *
2453  * Returns accumulated time @engine was busy since engine stats were enabled.
2454  */
2455 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2456 {
2457         return engine->busyness(engine, now);
2458 }
2459
2460 struct intel_context *
2461 intel_engine_create_virtual(struct intel_engine_cs **siblings,
2462                             unsigned int count, unsigned long flags)
2463 {
2464         if (count == 0)
2465                 return ERR_PTR(-EINVAL);
2466
2467         if (count == 1 && !(flags & FORCE_VIRTUAL))
2468                 return intel_context_create(siblings[0]);
2469
2470         GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2471         return siblings[0]->cops->create_virtual(siblings, count, flags);
2472 }
2473
2474 static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2475 {
2476         struct i915_request *request, *active = NULL;
2477
2478         /*
2479          * This search does not work in GuC submission mode. However, the GuC
2480          * will report the hanging context directly to the driver itself. So
2481          * the driver should never get here when in GuC mode.
2482          */
2483         GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2484
2485         /*
2486          * We are called by the error capture, reset and to dump engine
2487          * state at random points in time. In particular, note that neither is
2488          * crucially ordered with an interrupt. After a hang, the GPU is dead
2489          * and we assume that no more writes can happen (we waited long enough
2490          * for all writes that were in transaction to be flushed) - adding an
2491          * extra delay for a recent interrupt is pointless. Hence, we do
2492          * not need an engine->irq_seqno_barrier() before the seqno reads.
2493          * At all other times, we must assume the GPU is still running, but
2494          * we only care about the snapshot of this moment.
2495          */
2496         lockdep_assert_held(&engine->sched_engine->lock);
2497
2498         rcu_read_lock();
2499         request = execlists_active(&engine->execlists);
2500         if (request) {
2501                 struct intel_timeline *tl = request->context->timeline;
2502
2503                 list_for_each_entry_from_reverse(request, &tl->requests, link) {
2504                         if (__i915_request_is_complete(request))
2505                                 break;
2506
2507                         active = request;
2508                 }
2509         }
2510         rcu_read_unlock();
2511         if (active)
2512                 return active;
2513
2514         list_for_each_entry(request, &engine->sched_engine->requests,
2515                             sched.link) {
2516                 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2517                         continue;
2518
2519                 active = request;
2520                 break;
2521         }
2522
2523         return active;
2524 }
2525
2526 void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
2527                                   struct intel_context **ce, struct i915_request **rq)
2528 {
2529         unsigned long flags;
2530
2531         *ce = intel_engine_get_hung_context(engine);
2532         if (*ce) {
2533                 intel_engine_clear_hung_context(engine);
2534
2535                 *rq = intel_context_get_active_request(*ce);
2536                 return;
2537         }
2538
2539         /*
2540          * Getting here with GuC enabled means it is a forced error capture
2541          * with no actual hang. So, no need to attempt the execlist search.
2542          */
2543         if (intel_uc_uses_guc_submission(&engine->gt->uc))
2544                 return;
2545
2546         spin_lock_irqsave(&engine->sched_engine->lock, flags);
2547         *rq = engine_execlist_find_hung_request(engine);
2548         if (*rq)
2549                 *rq = i915_request_get_rcu(*rq);
2550         spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2551 }
2552
2553 void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2554 {
2555         /*
2556          * If there are any non-fused-off CCS engines, we need to enable CCS
2557          * support in the RCU_MODE register.  This only needs to be done once,
2558          * so for simplicity we'll take care of this in the RCS engine's
2559          * resume handler; since the RCS and all CCS engines belong to the
2560          * same reset domain and are reset together, this will also take care
2561          * of re-applying the setting after i915-triggered resets.
2562          */
2563         if (!CCS_MASK(engine->gt))
2564                 return;
2565
2566         intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2567                            _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2568 }
2569
2570 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2571 #include "mock_engine.c"
2572 #include "selftest_engine.c"
2573 #include "selftest_engine_cs.c"
2574 #endif