1 // SPDX-License-Identifier: GPL-2.0
3 * Low-level direct PCI config space access via ECAM - common code between
7 * - known chipset handling
8 * - ACPI decoding and validation
10 * Per-architecture code takes care of the mappings and accesses
14 #define pr_fmt(fmt) "PCI: " fmt
16 #include <linux/acpi.h>
17 #include <linux/efi.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/bitmap.h>
21 #include <linux/dmi.h>
22 #include <linux/slab.h>
23 #include <linux/mutex.h>
24 #include <linux/rculist.h>
25 #include <asm/e820/api.h>
26 #include <asm/pci_x86.h>
29 /* Indicate if the ECAM resources have been placed into the resource table */
30 static bool pci_mmcfg_running_state;
31 static bool pci_mmcfg_arch_init_failed;
32 static DEFINE_MUTEX(pci_mmcfg_lock);
33 #define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map)
35 LIST_HEAD(pci_mmcfg_list);
37 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
40 release_resource(&cfg->res);
45 static void __init free_all_mmcfg(void)
47 struct pci_mmcfg_region *cfg, *tmp;
49 pci_mmcfg_arch_free();
50 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
51 pci_mmconfig_remove(cfg);
54 static void list_add_sorted(struct pci_mmcfg_region *new)
56 struct pci_mmcfg_region *cfg;
58 /* keep list sorted by segment and starting bus number */
59 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) {
60 if (cfg->segment > new->segment ||
61 (cfg->segment == new->segment &&
62 cfg->start_bus >= new->start_bus)) {
63 list_add_tail_rcu(&new->list, &cfg->list);
67 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
70 static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
73 struct pci_mmcfg_region *new;
79 new = kzalloc(sizeof(*new), GFP_KERNEL);
84 new->segment = segment;
85 new->start_bus = start;
89 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
90 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
91 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
92 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
93 "PCI ECAM %04x [bus %02x-%02x]", segment, start, end);
94 res->name = new->name;
99 struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
102 struct pci_mmcfg_region *new;
104 new = pci_mmconfig_alloc(segment, start, end, addr);
108 mutex_lock(&pci_mmcfg_lock);
109 list_add_sorted(new);
110 mutex_unlock(&pci_mmcfg_lock);
112 pr_info("ECAM %pR (base %#lx) for domain %04x [bus %02x-%02x]\n",
113 &new->res, (unsigned long)addr, segment, start, end);
118 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
120 struct pci_mmcfg_region *cfg;
122 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held())
123 if (cfg->segment == segment &&
124 cfg->start_bus <= bus && bus <= cfg->end_bus)
130 static const char *__init pci_mmcfg_e7520(void)
133 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
136 if (win == 0x0000 || win == 0xf000)
139 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
142 return "Intel Corporation E7520 Memory Controller Hub";
145 static const char *__init pci_mmcfg_intel_945(void)
147 u32 pciexbar, mask = 0, len = 0;
149 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
156 switch ((pciexbar >> 1) & 3) {
173 /* Errata #2, things break when not aligned on a 256Mb boundary */
174 /* Can only happen in 64M/128M mode */
176 if ((pciexbar & mask) & 0x0fffffffU)
179 /* Don't hit the APIC registers and their friends */
180 if ((pciexbar & mask) >= 0xf0000000U)
183 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
186 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
189 static const char *__init pci_mmcfg_amd_fam10h(void)
191 u32 low, high, address;
194 unsigned segnbits = 0, busnbits, end_bus;
196 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
199 address = MSR_FAM10H_MMIO_CONF_BASE;
200 if (rdmsr_safe(address, &low, &high))
207 /* ECAM is not enabled */
208 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
211 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
213 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
214 FAM10H_MMIO_CONF_BUSRANGE_MASK;
217 * only handle bus 0 ?
224 segnbits = busnbits - 8;
228 end_bus = (1 << busnbits) - 1;
229 for (i = 0; i < (1 << segnbits); i++)
230 if (pci_mmconfig_add(i, 0, end_bus,
231 base + (1<<28) * i) == NULL) {
236 return "AMD Family 10h NB";
239 static bool __initdata mcp55_checked;
240 static const char *__init pci_mmcfg_nvidia_mcp55(void)
243 int mcp55_mmconf_found = 0;
245 static const u32 extcfg_regnum __initconst = 0x90;
246 static const u32 extcfg_regsize __initconst = 4;
247 static const u32 extcfg_enable_mask __initconst = 1 << 31;
248 static const u32 extcfg_start_mask __initconst = 0xff << 16;
249 static const int extcfg_start_shift __initconst = 16;
250 static const u32 extcfg_size_mask __initconst = 0x3 << 28;
251 static const int extcfg_size_shift __initconst = 28;
252 static const int extcfg_sizebus[] __initconst = {
253 0x100, 0x80, 0x40, 0x20
255 static const u32 extcfg_base_mask[] __initconst = {
256 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
258 static const int extcfg_base_lshift __initconst = 25;
261 * do check if amd fam10h already took over
263 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
266 mcp55_checked = true;
267 for (bus = 0; bus < 256; bus++) {
271 int start, size_index, end;
273 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
275 device = (l >> 16) & 0xffff;
277 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
280 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
281 extcfg_regsize, &extcfg);
283 if (!(extcfg & extcfg_enable_mask))
286 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
287 base = extcfg & extcfg_base_mask[size_index];
288 /* base could > 4G */
289 base <<= extcfg_base_lshift;
290 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
291 end = start + extcfg_sizebus[size_index] - 1;
292 if (pci_mmconfig_add(0, start, end, base) == NULL)
294 mcp55_mmconf_found++;
297 if (!mcp55_mmconf_found)
300 return "nVidia MCP55";
303 struct pci_mmcfg_hostbridge_probe {
308 const char *(*probe)(void);
311 static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
312 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
313 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
314 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
315 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
316 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
317 0x1200, pci_mmcfg_amd_fam10h },
318 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
319 0x1200, pci_mmcfg_amd_fam10h },
320 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
321 0x0369, pci_mmcfg_nvidia_mcp55 },
324 static void __init pci_mmcfg_check_end_bus_number(void)
326 struct pci_mmcfg_region *cfg, *cfgx;
329 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
330 if (cfg->end_bus < cfg->start_bus)
333 /* Don't access the list head ! */
334 if (cfg->list.next == &pci_mmcfg_list)
337 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
338 if (cfg->end_bus >= cfgx->start_bus)
339 cfg->end_bus = cfgx->start_bus - 1;
343 static int __init pci_mmcfg_check_hostbridge(void)
356 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
357 bus = pci_mmcfg_probes[i].bus;
358 devfn = pci_mmcfg_probes[i].devfn;
359 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
361 device = (l >> 16) & 0xffff;
364 if (pci_mmcfg_probes[i].vendor == vendor &&
365 pci_mmcfg_probes[i].device == device)
366 name = pci_mmcfg_probes[i].probe();
369 pr_info("%s with ECAM support\n", name);
372 /* some end_bus_number is crazy, fix it */
373 pci_mmcfg_check_end_bus_number();
375 return !list_empty(&pci_mmcfg_list);
378 static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
380 struct resource *mcfg_res = data;
381 struct acpi_resource_address64 address;
384 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
385 struct acpi_resource_fixed_memory32 *fixmem32 =
386 &res->data.fixed_memory32;
389 if ((mcfg_res->start >= fixmem32->address) &&
390 (mcfg_res->end < (fixmem32->address +
391 fixmem32->address_length))) {
393 return AE_CTRL_TERMINATE;
396 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
397 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
400 status = acpi_resource_to_address64(res, &address);
401 if (ACPI_FAILURE(status) ||
402 (address.address.address_length <= 0) ||
403 (address.resource_type != ACPI_MEMORY_RANGE))
406 if ((mcfg_res->start >= address.address.minimum) &&
407 (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
409 return AE_CTRL_TERMINATE;
414 static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
415 void *context, void **rv)
417 struct resource *mcfg_res = context;
419 acpi_walk_resources(handle, METHOD_NAME__CRS,
420 check_mcfg_resource, context);
423 return AE_CTRL_TERMINATE;
428 static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used)
430 struct resource mcfg_res;
432 mcfg_res.start = start;
433 mcfg_res.end = end - 1;
436 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
439 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
442 return mcfg_res.flags;
445 static bool is_efi_mmio(struct resource *res)
448 u64 start = res->start;
449 u64 end = res->start + resource_size(res);
450 efi_memory_desc_t *md;
451 u64 size, mmio_start, mmio_end;
453 for_each_efi_memory_desc(md) {
454 if (md->type == EFI_MEMORY_MAPPED_IO) {
455 size = md->num_pages << EFI_PAGE_SHIFT;
456 mmio_start = md->phys_addr;
457 mmio_end = mmio_start + size;
459 if (mmio_start <= start && end <= mmio_end)
468 typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type);
470 static bool __ref is_mmconf_reserved(check_reserved_t is_reserved,
471 struct pci_mmcfg_region *cfg,
472 struct device *dev, const char *method)
474 u64 addr = cfg->res.start;
475 u64 size = resource_size(&cfg->res);
479 while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) {
481 if (size < (16UL<<20))
485 if (size < (16UL<<20) && size != old_size)
489 dev_info(dev, "ECAM %pR reserved as %s\n",
492 pr_info("ECAM %pR reserved as %s\n", &cfg->res, method);
494 if (old_size != size) {
496 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
497 num_buses = cfg->end_bus - cfg->start_bus + 1;
498 cfg->res.end = cfg->res.start +
499 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
500 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
501 "PCI ECAM %04x [bus %02x-%02x]",
502 cfg->segment, cfg->start_bus, cfg->end_bus);
505 dev_info(dev, "ECAM %pR (base %#lx) (size reduced!)\n",
506 &cfg->res, (unsigned long) cfg->address);
508 pr_info("ECAM %pR (base %#lx) for %04x [bus%02x-%02x] (size reduced!)\n",
509 &cfg->res, (unsigned long) cfg->address,
510 cfg->segment, cfg->start_bus, cfg->end_bus);
516 static bool __ref pci_mmcfg_reserved(struct device *dev,
517 struct pci_mmcfg_region *cfg, int early)
519 struct resource *conflict;
521 if (!early && !acpi_disabled) {
522 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev,
523 "ACPI motherboard resource"))
527 dev_info(dev, FW_INFO "ECAM %pR not reserved in ACPI motherboard resources\n",
530 pr_info(FW_INFO "ECAM %pR not reserved in ACPI motherboard resources\n",
533 if (is_efi_mmio(&cfg->res)) {
534 pr_info("ECAM %pR is EfiMemoryMappedIO; assuming valid\n",
536 conflict = insert_resource_conflict(&iomem_resource,
539 pr_warn("ECAM %pR conflicts with %s %pR\n",
540 &cfg->res, conflict->name, conflict);
542 pr_info("ECAM %pR reserved to work around lack of ACPI motherboard _CRS\n",
549 * e820__mapped_all() is marked as __init.
550 * All entries from ACPI MCFG table have been checked at boot time.
551 * For MCFG information constructed from hotpluggable host bridge's
552 * _CBA method, just assume it's reserved.
554 if (pci_mmcfg_running_state)
557 /* Don't try to do this check unless configuration
558 type 1 is available. how about type 2 ?*/
560 return is_mmconf_reserved(e820__mapped_all, cfg, dev,
566 static void __init pci_mmcfg_reject_broken(int early)
568 struct pci_mmcfg_region *cfg;
570 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
571 if (!pci_mmcfg_reserved(NULL, cfg, early)) {
572 pr_info("not using ECAM (%pR not reserved)\n",
580 static bool __init acpi_mcfg_valid_entry(struct acpi_table_mcfg *mcfg,
581 struct acpi_mcfg_allocation *cfg)
583 if (cfg->address < 0xFFFFFFFF)
586 if (!strncmp(mcfg->header.oem_id, "SGI", 3))
589 if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010))
592 pr_err("ECAM at %#llx for %04x [bus %02x-%02x] is above 4GB, ignored\n",
593 cfg->address, cfg->pci_segment, cfg->start_bus_number,
594 cfg->end_bus_number);
598 static int __init pci_parse_mcfg(struct acpi_table_header *header)
600 struct acpi_table_mcfg *mcfg;
601 struct acpi_mcfg_allocation *cfg_table, *cfg;
608 mcfg = (struct acpi_table_mcfg *)header;
610 /* how many config structures do we have */
613 i = header->length - sizeof(struct acpi_table_mcfg);
614 while (i >= sizeof(struct acpi_mcfg_allocation)) {
616 i -= sizeof(struct acpi_mcfg_allocation);
619 pr_err("MCFG has no entries\n");
623 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
624 for (i = 0; i < entries; i++) {
626 if (!acpi_mcfg_valid_entry(mcfg, cfg)) {
631 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
632 cfg->end_bus_number, cfg->address) == NULL) {
633 pr_warn("no memory for MCFG entries\n");
642 #ifdef CONFIG_ACPI_APEI
643 extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
644 void *data), void *data);
646 static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
647 void *data), void *data)
649 struct pci_mmcfg_region *cfg;
652 if (list_empty(&pci_mmcfg_list))
655 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
656 rc = func(cfg->res.start, resource_size(&cfg->res), data);
663 #define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
665 #define set_apei_filter()
668 static void __init __pci_mmcfg_init(int early)
670 pr_debug("%s(%s)\n", __func__, early ? "early" : "late");
672 pci_mmcfg_reject_broken(early);
673 if (list_empty(&pci_mmcfg_list))
676 if (pcibios_last_bus < 0) {
677 const struct pci_mmcfg_region *cfg;
679 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
682 pcibios_last_bus = cfg->end_bus;
686 if (pci_mmcfg_arch_init())
687 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
690 pci_mmcfg_arch_init_failed = true;
694 static int __initdata known_bridge;
696 void __init pci_mmcfg_early_init(void)
698 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe);
700 if (pci_probe & PCI_PROBE_MMCONF) {
701 if (pci_mmcfg_check_hostbridge())
704 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
711 void __init pci_mmcfg_late_init(void)
713 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe);
716 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
722 /* ECAM hasn't been enabled yet, try again */
723 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
724 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
729 static int __init pci_mmcfg_late_insert_resources(void)
731 struct pci_mmcfg_region *cfg;
733 pci_mmcfg_running_state = true;
735 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe);
737 /* If we are not using ECAM, don't insert the resources. */
738 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
742 * Attempt to insert the mmcfg resources but not with the busy flag
743 * marked so it won't cause request errors when __request_region is
746 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
747 if (!cfg->res.parent) {
748 pr_debug("%s() insert %pR\n", __func__, &cfg->res);
749 insert_resource(&iomem_resource, &cfg->res);
757 * Perform ECAM resource insertion after PCI initialization to allow for
758 * misprogrammed MCFG tables that state larger sizes but actually conflict
759 * with other system resources.
761 late_initcall(pci_mmcfg_late_insert_resources);
763 /* Add ECAM information for host bridges */
764 int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
768 struct resource *tmp = NULL;
769 struct pci_mmcfg_region *cfg;
771 dev_dbg(dev, "%s(%04x [bus %02x-%02x])\n", __func__, seg, start, end);
773 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
779 mutex_lock(&pci_mmcfg_lock);
780 cfg = pci_mmconfig_lookup(seg, start);
782 if (cfg->end_bus < end)
783 dev_info(dev, FW_INFO "ECAM %pR for domain %04x [bus %02x-%02x] only partially covers this bridge\n",
784 &cfg->res, cfg->segment, cfg->start_bus,
786 mutex_unlock(&pci_mmcfg_lock);
791 * Don't move earlier; we must return -EEXIST, not -EINVAL, if
792 * pci_mmconfig_lookup() finds something
795 mutex_unlock(&pci_mmcfg_lock);
800 cfg = pci_mmconfig_alloc(seg, start, end, addr);
802 dev_warn(dev, "fail to add ECAM (out of memory)\n");
804 } else if (!pci_mmcfg_reserved(dev, cfg, 0)) {
805 dev_warn(dev, FW_BUG "ECAM %pR isn't reserved\n",
808 /* Insert resource if it's not in boot stage */
809 if (pci_mmcfg_running_state)
810 tmp = insert_resource_conflict(&iomem_resource,
814 dev_warn(dev, "ECAM %pR conflicts with %s %pR\n",
815 &cfg->res, tmp->name, tmp);
816 } else if (pci_mmcfg_arch_map(cfg)) {
817 dev_warn(dev, "fail to map ECAM %pR\n", &cfg->res);
819 list_add_sorted(cfg);
820 dev_info(dev, "ECAM %pR (base %#lx)\n",
821 &cfg->res, (unsigned long)addr);
829 release_resource(&cfg->res);
833 mutex_unlock(&pci_mmcfg_lock);
838 /* Delete ECAM information for host bridges */
839 int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
841 struct pci_mmcfg_region *cfg;
843 mutex_lock(&pci_mmcfg_lock);
844 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
845 if (cfg->segment == seg && cfg->start_bus == start &&
846 cfg->end_bus == end) {
847 list_del_rcu(&cfg->list);
849 pci_mmcfg_arch_unmap(cfg);
851 release_resource(&cfg->res);
852 mutex_unlock(&pci_mmcfg_lock);
856 mutex_unlock(&pci_mmcfg_lock);