drivers/gpu/drm/vc4/vc4_hdmi.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /**
  21  * DOC: VC4 Falcon HDMI module
  22  *
  23  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  24  * the unit operates off of the HSM clock from CPRMAN.  It also
  25  * internally uses the PLLH_PIX clock for the PHY.
  26  *
  27  * HDMI infoframes are kept within a small packet ram, where each
  28  * packet can be individually enabled for including in a frame.
  29  *
  30  * HDMI audio is implemented entirely within the HDMI IP block.  A
  31  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  32  * and transfers them over an internal MAI (multi-channel audio
  33  * interconnect) bus to the encoder side for insertion into the video
  34  * blank regions.
  35  *
  36  * The driver's HDMI encoder does not yet support power management.
  37  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  38  * continuously running, and only the HDMI logic and packet ram are
  39  * powered off/on at disable/enable time.
  40  *
  41  * The driver does not yet support CEC control, though the HDMI
  42  * encoder block has CEC support.
  43  */
  44
  45 #include <drm/drm_atomic_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_edid.h>
  48 #include <linux/clk.h>
  49 #include <linux/component.h>
  50 #include <linux/i2c.h>
  51 #include <linux/of_address.h>
  52 #include <linux/of_gpio.h>
  53 #include <linux/of_platform.h>
  54 #include <linux/pm_runtime.h>
  55 #include <linux/rational.h>
  56 #include <sound/dmaengine_pcm.h>
  57 #include <sound/pcm_drm_eld.h>
  58 #include <sound/pcm_params.h>
  59 #include <sound/soc.h>
  60 #include "media/cec.h"
  61 #include "vc4_drv.h"
  62 #include "vc4_regs.h"
  63
  64 #define HSM_CLOCK_FREQ 163682864
  65 #define CEC_CLOCK_FREQ 40000
  66 #define CEC_CLOCK_DIV  (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
  67
  68 /* HDMI audio information */
  69 struct vc4_hdmi_audio {
  70         struct snd_soc_card card;
  71         struct snd_soc_dai_link link;
  72         int samplerate;
  73         int channels;
  74         struct snd_dmaengine_dai_dma_data dma_data;
  75         struct snd_pcm_substream *substream;
  76 };
  77
  78 /* General HDMI hardware state. */
  79 struct vc4_hdmi {
  80         struct platform_device *pdev;
  81
  82         struct drm_encoder *encoder;
  83         struct drm_connector *connector;
  84
  85         struct vc4_hdmi_audio audio;
  86
  87         struct i2c_adapter *ddc;
  88         void __iomem *hdmicore_regs;
  89         void __iomem *hd_regs;
  90         int hpd_gpio;
  91         bool hpd_active_low;
  92
  93         struct cec_adapter *cec_adap;
  94         struct cec_msg cec_rx_msg;
  95         bool cec_tx_ok;
  96         bool cec_irq_was_rx;
  97
  98         struct clk *pixel_clock;
  99         struct clk *hsm_clock;
 100 };
 101
 102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
 103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
 104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
 105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
 106
 107 /* VC4 HDMI encoder KMS struct */
 108 struct vc4_hdmi_encoder {
 109         struct vc4_encoder base;
 110         bool hdmi_monitor;
 111         bool limited_rgb_range;
 112         bool rgb_range_selectable;
 113 };
 114
 115 static inline struct vc4_hdmi_encoder *
 116 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
 117 {
 118         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
 119 }
 120
 121 /* VC4 HDMI connector KMS struct */
 122 struct vc4_hdmi_connector {
 123         struct drm_connector base;
 124
 125         /* Since the connector is attached to just the one encoder,
 126          * this is the reference to it so we can do the best_encoder()
 127          * hook.
 128          */
 129         struct drm_encoder *encoder;
 130 };
 131
 132 static inline struct vc4_hdmi_connector *
 133 to_vc4_hdmi_connector(struct drm_connector *connector)
 134 {
 135         return container_of(connector, struct vc4_hdmi_connector, base);
 136 }
 137
 138 #define HDMI_REG(reg) { reg, #reg }
 139 static const struct {
 140         u32 reg;
 141         const char *name;
 142 } hdmi_regs[] = {
 143         HDMI_REG(VC4_HDMI_CORE_REV),
 144         HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
 145         HDMI_REG(VC4_HDMI_HOTPLUG_INT),
 146         HDMI_REG(VC4_HDMI_HOTPLUG),
 147         HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
 148         HDMI_REG(VC4_HDMI_MAI_CONFIG),
 149         HDMI_REG(VC4_HDMI_MAI_FORMAT),
 150         HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
 151         HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
 152         HDMI_REG(VC4_HDMI_HORZA),
 153         HDMI_REG(VC4_HDMI_HORZB),
 154         HDMI_REG(VC4_HDMI_FIFO_CTL),
 155         HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
 156         HDMI_REG(VC4_HDMI_VERTA0),
 157         HDMI_REG(VC4_HDMI_VERTA1),
 158         HDMI_REG(VC4_HDMI_VERTB0),
 159         HDMI_REG(VC4_HDMI_VERTB1),
 160         HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
 161         HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
 162
 163         HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
 164         HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
 165         HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
 166         HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
 167         HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
 168         HDMI_REG(VC4_HDMI_CPU_STATUS),
 169         HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
 170
 171         HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
 172         HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
 173         HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
 174         HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
 175         HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
 176         HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
 177         HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
 178         HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
 179 };
 180
 181 static const struct {
 182         u32 reg;
 183         const char *name;
 184 } hd_regs[] = {
 185         HDMI_REG(VC4_HD_M_CTL),
 186         HDMI_REG(VC4_HD_MAI_CTL),
 187         HDMI_REG(VC4_HD_MAI_THR),
 188         HDMI_REG(VC4_HD_MAI_FMT),
 189         HDMI_REG(VC4_HD_MAI_SMP),
 190         HDMI_REG(VC4_HD_VID_CTL),
 191         HDMI_REG(VC4_HD_CSC_CTL),
 192         HDMI_REG(VC4_HD_FRAME_COUNT),
 193 };
 194
 195 #ifdef CONFIG_DEBUG_FS
 196 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 197 {
 198         struct drm_info_node *node = (struct drm_info_node *)m->private;
 199         struct drm_device *dev = node->minor->dev;
 200         struct vc4_dev *vc4 = to_vc4_dev(dev);
 201         int i;
 202
 203         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 204                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 205                            hdmi_regs[i].name, hdmi_regs[i].reg,
 206                            HDMI_READ(hdmi_regs[i].reg));
 207         }
 208
 209         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 210                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 211                            hd_regs[i].name, hd_regs[i].reg,
 212                            HD_READ(hd_regs[i].reg));
 213         }
 214
 215         return 0;
 216 }
 217 #endif /* CONFIG_DEBUG_FS */
 218
 219 static void vc4_hdmi_dump_regs(struct drm_device *dev)
 220 {
 221         struct vc4_dev *vc4 = to_vc4_dev(dev);
 222         int i;
 223
 224         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 225                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 226                          hdmi_regs[i].reg, hdmi_regs[i].name,
 227                          HDMI_READ(hdmi_regs[i].reg));
 228         }
 229         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 230                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 231                          hd_regs[i].reg, hd_regs[i].name,
 232                          HD_READ(hd_regs[i].reg));
 233         }
 234 }
 235
 236 static enum drm_connector_status
 237 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 238 {
 239         struct drm_device *dev = connector->dev;
 240         struct vc4_dev *vc4 = to_vc4_dev(dev);
 241
 242         if (vc4->hdmi->hpd_gpio) {
 243                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 244                     vc4->hdmi->hpd_active_low)
 245                         return connector_status_connected;
 246                 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 247                 return connector_status_disconnected;
 248         }
 249
 250         if (drm_probe_ddc(vc4->hdmi->ddc))
 251                 return connector_status_connected;
 252
 253         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 254                 return connector_status_connected;
 255         cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 256         return connector_status_disconnected;
 257 }
 258
 259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 260 {
 261         drm_connector_unregister(connector);
 262         drm_connector_cleanup(connector);
 263 }
 264
 265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 266 {
 267         struct vc4_hdmi_connector *vc4_connector =
 268                 to_vc4_hdmi_connector(connector);
 269         struct drm_encoder *encoder = vc4_connector->encoder;
 270         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 271         struct drm_device *dev = connector->dev;
 272         struct vc4_dev *vc4 = to_vc4_dev(dev);
 273         int ret = 0;
 274         struct edid *edid;
 275
 276         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 277         cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
 278         if (!edid)
 279                 return -ENODEV;
 280
 281         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 282
 283         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
 284                 vc4_encoder->rgb_range_selectable =
 285                         drm_rgb_quant_range_selectable(edid);
 286         }
 287
 288         drm_connector_update_edid_property(connector, edid);
 289         ret = drm_add_edid_modes(connector, edid);
 290         kfree(edid);
 291
 292         return ret;
 293 }
 294
 295 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 296         .detect = vc4_hdmi_connector_detect,
 297         .fill_modes = drm_helper_probe_single_connector_modes,
 298         .destroy = vc4_hdmi_connector_destroy,
 299         .reset = drm_atomic_helper_connector_reset,
 300         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 301         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 302 };
 303
 304 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 305         .get_modes = vc4_hdmi_connector_get_modes,
 306 };
 307
 308 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 309                                                      struct drm_encoder *encoder)
 310 {
 311         struct drm_connector *connector;
 312         struct vc4_hdmi_connector *hdmi_connector;
 313         int ret;
 314
 315         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 316                                       GFP_KERNEL);
 317         if (!hdmi_connector)
 318                 return ERR_PTR(-ENOMEM);
 319         connector = &hdmi_connector->base;
 320
 321         hdmi_connector->encoder = encoder;
 322
 323         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 324                            DRM_MODE_CONNECTOR_HDMIA);
 325         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 326
 327         /* Create and attach TV margin props to this connector. */
 328         ret = drm_mode_create_tv_margin_properties(dev);
 329         if (ret)
 330                 return ERR_PTR(ret);
 331
 332         drm_connector_attach_tv_margin_properties(connector);
 333
 334         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 335                              DRM_CONNECTOR_POLL_DISCONNECT);
 336
 337         connector->interlace_allowed = 1;
 338         connector->doublescan_allowed = 0;
 339
 340         drm_connector_attach_encoder(connector, encoder);
 341
 342         return connector;
 343 }
 344
 345 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 346 {
 347         drm_encoder_cleanup(encoder);
 348 }
 349
 350 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 351         .destroy = vc4_hdmi_encoder_destroy,
 352 };
 353
 354 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 355                                 enum hdmi_infoframe_type type)
 356 {
 357         struct drm_device *dev = encoder->dev;
 358         struct vc4_dev *vc4 = to_vc4_dev(dev);
 359         u32 packet_id = type - 0x80;
 360
 361         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 362                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 363
 364         return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 365                           BIT(packet_id)), 100);
 366 }
 367
 368 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 369                                      union hdmi_infoframe *frame)
 370 {
 371         struct drm_device *dev = encoder->dev;
 372         struct vc4_dev *vc4 = to_vc4_dev(dev);
 373         u32 packet_id = frame->any.type - 0x80;
 374         u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
 375         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 376         ssize_t len, i;
 377         int ret;
 378
 379         WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 380                     VC4_HDMI_RAM_PACKET_ENABLE),
 381                   "Packet RAM has to be on to store the packet.");
 382
 383         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 384         if (len < 0)
 385                 return;
 386
 387         ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
 388         if (ret) {
 389                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 390                 return;
 391         }
 392
 393         for (i = 0; i < len; i += 7) {
 394                 HDMI_WRITE(packet_reg,
 395                            buffer[i + 0] << 0 |
 396                            buffer[i + 1] << 8 |
 397                            buffer[i + 2] << 16);
 398                 packet_reg += 4;
 399
 400                 HDMI_WRITE(packet_reg,
 401                            buffer[i + 3] << 0 |
 402                            buffer[i + 4] << 8 |
 403                            buffer[i + 5] << 16 |
 404                            buffer[i + 6] << 24);
 405                 packet_reg += 4;
 406         }
 407
 408         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 409                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 410         ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 411                         BIT(packet_id)), 100);
 412         if (ret)
 413                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 414 }
 415
 416 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 417 {
 418         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 419         struct vc4_dev *vc4 = encoder->dev->dev_private;
 420         struct vc4_hdmi *hdmi = vc4->hdmi;
 421         struct drm_connector_state *cstate = hdmi->connector->state;
 422         struct drm_crtc *crtc = encoder->crtc;
 423         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 424         union hdmi_infoframe frame;
 425         int ret;
 426
 427         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
 428         if (ret < 0) {
 429                 DRM_ERROR("couldn't fill AVI infoframe\n");
 430                 return;
 431         }
 432
 433         drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
 434                                            vc4_encoder->limited_rgb_range ?
 435                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 436                                            HDMI_QUANTIZATION_RANGE_FULL,
 437                                            vc4_encoder->rgb_range_selectable,
 438                                            false);
 439
 440         frame.avi.right_bar = cstate->tv.margins.right;
 441         frame.avi.left_bar = cstate->tv.margins.left;
 442         frame.avi.top_bar = cstate->tv.margins.top;
 443         frame.avi.bottom_bar = cstate->tv.margins.bottom;
 444
 445         vc4_hdmi_write_infoframe(encoder, &frame);
 446 }
 447
 448 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 449 {
 450         union hdmi_infoframe frame;
 451         int ret;
 452
 453         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 454         if (ret < 0) {
 455                 DRM_ERROR("couldn't fill SPD infoframe\n");
 456                 return;
 457         }
 458
 459         frame.spd.sdi = HDMI_SPD_SDI_PC;
 460
 461         vc4_hdmi_write_infoframe(encoder, &frame);
 462 }
 463
 464 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 465 {
 466         struct drm_device *drm = encoder->dev;
 467         struct vc4_dev *vc4 = drm->dev_private;
 468         struct vc4_hdmi *hdmi = vc4->hdmi;
 469         union hdmi_infoframe frame;
 470         int ret;
 471
 472         ret = hdmi_audio_infoframe_init(&frame.audio);
 473
 474         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 475         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 476         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 477         frame.audio.channels = hdmi->audio.channels;
 478
 479         vc4_hdmi_write_infoframe(encoder, &frame);
 480 }
 481
 482 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 483 {
 484         vc4_hdmi_set_avi_infoframe(encoder);
 485         vc4_hdmi_set_spd_infoframe(encoder);
 486 }
 487
 488 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 489 {
 490         struct drm_device *dev = encoder->dev;
 491         struct vc4_dev *vc4 = to_vc4_dev(dev);
 492         struct vc4_hdmi *hdmi = vc4->hdmi;
 493         int ret;
 494
 495         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
 496
 497         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 498         HD_WRITE(VC4_HD_VID_CTL,
 499                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 500
 501         clk_disable_unprepare(hdmi->pixel_clock);
 502
 503         ret = pm_runtime_put(&hdmi->pdev->dev);
 504         if (ret < 0)
 505                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 506 }
 507
 508 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 509 {
 510         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 511         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 512         struct drm_device *dev = encoder->dev;
 513         struct vc4_dev *vc4 = to_vc4_dev(dev);
 514         struct vc4_hdmi *hdmi = vc4->hdmi;
 515         bool debug_dump_regs = false;
 516         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 517         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 518         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 519         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 520         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 521                                    VC4_HDMI_VERTA_VSP) |
 522                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 523                                    VC4_HDMI_VERTA_VFP) |
 524                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 525         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 526                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 527                                    VC4_HDMI_VERTB_VBP));
 528         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 529                           VC4_SET_FIELD(mode->crtc_vtotal -
 530                                         mode->crtc_vsync_end -
 531                                         interlaced,
 532                                         VC4_HDMI_VERTB_VBP));
 533         u32 csc_ctl;
 534         int ret;
 535
 536         ret = pm_runtime_get_sync(&hdmi->pdev->dev);
 537         if (ret < 0) {
 538                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 539                 return;
 540         }
 541
 542         ret = clk_set_rate(hdmi->pixel_clock,
 543                            mode->clock * 1000 *
 544                            ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
 545         if (ret) {
 546                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 547                 return;
 548         }
 549
 550         ret = clk_prepare_enable(hdmi->pixel_clock);
 551         if (ret) {
 552                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 553                 return;
 554         }
 555
 556         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 557                    VC4_HDMI_SW_RESET_HDMI |
 558                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 559
 560         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 561
 562         /* PHY should be in reset, like
 563          * vc4_hdmi_encoder_disable() does.
 564          */
 565         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 566
 567         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 568
 569         if (debug_dump_regs) {
 570                 DRM_INFO("HDMI regs before:\n");
 571                 vc4_hdmi_dump_regs(dev);
 572         }
 573
 574         HD_WRITE(VC4_HD_VID_CTL, 0);
 575
 576         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 577                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 578                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 579                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 580
 581         HDMI_WRITE(VC4_HDMI_HORZA,
 582                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 583                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 584                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 585                                  VC4_HDMI_HORZA_HAP));
 586
 587         HDMI_WRITE(VC4_HDMI_HORZB,
 588                    VC4_SET_FIELD((mode->htotal -
 589                                   mode->hsync_end) * pixel_rep,
 590                                  VC4_HDMI_HORZB_HBP) |
 591                    VC4_SET_FIELD((mode->hsync_end -
 592                                   mode->hsync_start) * pixel_rep,
 593                                  VC4_HDMI_HORZB_HSP) |
 594                    VC4_SET_FIELD((mode->hsync_start -
 595                                   mode->hdisplay) * pixel_rep,
 596                                  VC4_HDMI_HORZB_HFP));
 597
 598         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 599         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 600
 601         HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
 602         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 603
 604         HD_WRITE(VC4_HD_VID_CTL,
 605                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 606                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 607
 608         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 609                                 VC4_HD_CSC_CTL_ORDER);
 610
 611         if (vc4_encoder->hdmi_monitor &&
 612             drm_default_rgb_quant_range(mode) ==
 613             HDMI_QUANTIZATION_RANGE_LIMITED) {
 614                 /* CEA VICs other than #1 requre limited range RGB
 615                  * output unless overridden by an AVI infoframe.
 616                  * Apply a colorspace conversion to squash 0-255 down
 617                  * to 16-235.  The matrix here is:
 618                  *
 619                  * [ 0      0      0.8594 16]
 620                  * [ 0      0.8594 0      16]
 621                  * [ 0.8594 0      0      16]
 622                  * [ 0      0      0       1]
 623                  */
 624                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 625                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 626                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 627                                          VC4_HD_CSC_CTL_MODE);
 628
 629                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 630                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 631                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 632                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 633                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 634                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 635                 vc4_encoder->limited_rgb_range = true;
 636         } else {
 637                 vc4_encoder->limited_rgb_range = false;
 638         }
 639
 640         /* The RGB order applies even when CSC is disabled. */
 641         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 642
 643         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 644
 645         if (debug_dump_regs) {
 646                 DRM_INFO("HDMI regs after:\n");
 647                 vc4_hdmi_dump_regs(dev);
 648         }
 649
 650         HD_WRITE(VC4_HD_VID_CTL,
 651                  HD_READ(VC4_HD_VID_CTL) |
 652                  VC4_HD_VID_CTL_ENABLE |
 653                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 654                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 655
 656         if (vc4_encoder->hdmi_monitor) {
 657                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 658                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 659                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 660
 661                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 662                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 663                 WARN_ONCE(ret, "Timeout waiting for "
 664                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 665         } else {
 666                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 667                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 668                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 669                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 670                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 671                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 672
 673                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 674                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 675                 WARN_ONCE(ret, "Timeout waiting for "
 676                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 677         }
 678
 679         if (vc4_encoder->hdmi_monitor) {
 680                 u32 drift;
 681
 682                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 683                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 684                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 685                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 686                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 687
 688                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 689                            VC4_HDMI_RAM_PACKET_ENABLE);
 690
 691                 vc4_hdmi_set_infoframes(encoder);
 692
 693                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 694                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 695
 696                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 697                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 698                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 699                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 700                 usleep_range(1000, 1100);
 701                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 702                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 703                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 704                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 705
 706                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 707                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 708                 WARN_ONCE(ret, "Timeout waiting for "
 709                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 710         }
 711 }
 712
 713 static enum drm_mode_status
 714 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
 715                             const struct drm_display_mode *mode)
 716 {
 717         /* HSM clock must be 108% of the pixel clock.  Additionally,
 718          * the AXI clock needs to be at least 25% of pixel clock, but
 719          * HSM ends up being the limiting factor.
 720          */
 721         if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
 722                 return MODE_CLOCK_HIGH;
 723
 724         return MODE_OK;
 725 }
 726
 727 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 728         .mode_valid = vc4_hdmi_encoder_mode_valid,
 729         .disable = vc4_hdmi_encoder_disable,
 730         .enable = vc4_hdmi_encoder_enable,
 731 };
 732
 733 /* HDMI audio codec callbacks */
 734 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
 735 {
 736         struct drm_device *drm = hdmi->encoder->dev;
 737         struct vc4_dev *vc4 = to_vc4_dev(drm);
 738         u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
 739         unsigned long n, m;
 740
 741         rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
 742                                     VC4_HD_MAI_SMP_N_MASK >>
 743                                     VC4_HD_MAI_SMP_N_SHIFT,
 744                                     (VC4_HD_MAI_SMP_M_MASK >>
 745                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 746                                     &n, &m);
 747
 748         HD_WRITE(VC4_HD_MAI_SMP,
 749                  VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 750                  VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 751 }
 752
 753 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
 754 {
 755         struct drm_encoder *encoder = hdmi->encoder;
 756         struct drm_crtc *crtc = encoder->crtc;
 757         struct drm_device *drm = encoder->dev;
 758         struct vc4_dev *vc4 = to_vc4_dev(drm);
 759         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 760         u32 samplerate = hdmi->audio.samplerate;
 761         u32 n, cts;
 762         u64 tmp;
 763
 764         n = 128 * samplerate / 1000;
 765         tmp = (u64)(mode->clock * 1000) * n;
 766         do_div(tmp, 128 * samplerate);
 767         cts = tmp;
 768
 769         HDMI_WRITE(VC4_HDMI_CRP_CFG,
 770                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 771                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 772
 773         /*
 774          * We could get slightly more accurate clocks in some cases by
 775          * providing a CTS_1 value.  The two CTS values are alternated
 776          * between based on the period fields
 777          */
 778         HDMI_WRITE(VC4_HDMI_CTS_0, cts);
 779         HDMI_WRITE(VC4_HDMI_CTS_1, cts);
 780 }
 781
 782 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 783 {
 784         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 785
 786         return snd_soc_card_get_drvdata(card);
 787 }
 788
 789 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 790                                   struct snd_soc_dai *dai)
 791 {
 792         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 793         struct drm_encoder *encoder = hdmi->encoder;
 794         struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
 795         int ret;
 796
 797         if (hdmi->audio.substream && hdmi->audio.substream != substream)
 798                 return -EINVAL;
 799
 800         hdmi->audio.substream = substream;
 801
 802         /*
 803          * If the HDMI encoder hasn't probed, or the encoder is
 804          * currently in DVI mode, treat the codec dai as missing.
 805          */
 806         if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 807                                 VC4_HDMI_RAM_PACKET_ENABLE))
 808                 return -ENODEV;
 809
 810         ret = snd_pcm_hw_constraint_eld(substream->runtime,
 811                                         hdmi->connector->eld);
 812         if (ret)
 813                 return ret;
 814
 815         return 0;
 816 }
 817
 818 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 819 {
 820         return 0;
 821 }
 822
 823 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
 824 {
 825         struct drm_encoder *encoder = hdmi->encoder;
 826         struct drm_device *drm = encoder->dev;
 827         struct device *dev = &hdmi->pdev->dev;
 828         struct vc4_dev *vc4 = to_vc4_dev(drm);
 829         int ret;
 830
 831         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
 832         if (ret)
 833                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
 834
 835         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
 836         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
 837         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
 838 }
 839
 840 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
 841                                     struct snd_soc_dai *dai)
 842 {
 843         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 844
 845         if (substream != hdmi->audio.substream)
 846                 return;
 847
 848         vc4_hdmi_audio_reset(hdmi);
 849
 850         hdmi->audio.substream = NULL;
 851 }
 852
 853 /* HDMI audio codec callbacks */
 854 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 855                                     struct snd_pcm_hw_params *params,
 856                                     struct snd_soc_dai *dai)
 857 {
 858         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 859         struct drm_encoder *encoder = hdmi->encoder;
 860         struct drm_device *drm = encoder->dev;
 861         struct device *dev = &hdmi->pdev->dev;
 862         struct vc4_dev *vc4 = to_vc4_dev(drm);
 863         u32 audio_packet_config, channel_mask;
 864         u32 channel_map, i;
 865
 866         if (substream != hdmi->audio.substream)
 867                 return -EINVAL;
 868
 869         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
 870                 params_rate(params), params_width(params),
 871                 params_channels(params));
 872
 873         hdmi->audio.channels = params_channels(params);
 874         hdmi->audio.samplerate = params_rate(params);
 875
 876         HD_WRITE(VC4_HD_MAI_CTL,
 877                  VC4_HD_MAI_CTL_RESET |
 878                  VC4_HD_MAI_CTL_FLUSH |
 879                  VC4_HD_MAI_CTL_DLATE |
 880                  VC4_HD_MAI_CTL_ERRORE |
 881                  VC4_HD_MAI_CTL_ERRORF);
 882
 883         vc4_hdmi_audio_set_mai_clock(hdmi);
 884
 885         audio_packet_config =
 886                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
 887                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
 888                 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
 889
 890         channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
 891         audio_packet_config |= VC4_SET_FIELD(channel_mask,
 892                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 893
 894         /* Set the MAI threshold.  This logic mimics the firmware's. */
 895         if (hdmi->audio.samplerate > 96000) {
 896                 HD_WRITE(VC4_HD_MAI_THR,
 897                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
 898                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 899         } else if (hdmi->audio.samplerate > 48000) {
 900                 HD_WRITE(VC4_HD_MAI_THR,
 901                          VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
 902                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 903         } else {
 904                 HD_WRITE(VC4_HD_MAI_THR,
 905                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
 906                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
 907                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
 908                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
 909         }
 910
 911         HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
 912                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
 913                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
 914
 915         channel_map = 0;
 916         for (i = 0; i < 8; i++) {
 917                 if (channel_mask & BIT(i))
 918                         channel_map |= i << (3 * i);
 919         }
 920
 921         HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
 922         HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
 923         vc4_hdmi_set_n_cts(hdmi);
 924
 925         return 0;
 926 }
 927
 928 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
 929                                   struct snd_soc_dai *dai)
 930 {
 931         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 932         struct drm_encoder *encoder = hdmi->encoder;
 933         struct drm_device *drm = encoder->dev;
 934         struct vc4_dev *vc4 = to_vc4_dev(drm);
 935
 936         switch (cmd) {
 937         case SNDRV_PCM_TRIGGER_START:
 938                 vc4_hdmi_set_audio_infoframe(encoder);
 939                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 940                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
 941                            ~VC4_HDMI_TX_PHY_RNG_PWRDN);
 942                 HD_WRITE(VC4_HD_MAI_CTL,
 943                          VC4_SET_FIELD(hdmi->audio.channels,
 944                                        VC4_HD_MAI_CTL_CHNUM) |
 945                          VC4_HD_MAI_CTL_ENABLE);
 946                 break;
 947         case SNDRV_PCM_TRIGGER_STOP:
 948                 HD_WRITE(VC4_HD_MAI_CTL,
 949                          VC4_HD_MAI_CTL_DLATE |
 950                          VC4_HD_MAI_CTL_ERRORE |
 951                          VC4_HD_MAI_CTL_ERRORF);
 952                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 953                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
 954                            VC4_HDMI_TX_PHY_RNG_PWRDN);
 955                 break;
 956         default:
 957                 break;
 958         }
 959
 960         return 0;
 961 }
 962
 963 static inline struct vc4_hdmi *
 964 snd_component_to_hdmi(struct snd_soc_component *component)
 965 {
 966         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
 967
 968         return snd_soc_card_get_drvdata(card);
 969 }
 970
 971 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
 972                                        struct snd_ctl_elem_info *uinfo)
 973 {
 974         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 975         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 976
 977         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 978         uinfo->count = sizeof(hdmi->connector->eld);
 979
 980         return 0;
 981 }
 982
 983 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
 984                                       struct snd_ctl_elem_value *ucontrol)
 985 {
 986         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 987         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 988
 989         memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
 990                sizeof(hdmi->connector->eld));
 991
 992         return 0;
 993 }
 994
 995 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
 996         {
 997                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
 998                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 999                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1000                 .name = "ELD",
1001                 .info = vc4_hdmi_audio_eld_ctl_info,
1002                 .get = vc4_hdmi_audio_eld_ctl_get,
1003         },
1004 };
1005
1006 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1007         SND_SOC_DAPM_OUTPUT("TX"),
1008 };
1009
1010 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1011         { "TX", NULL, "Playback" },
1012 };
1013
1014 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1015         .controls               = vc4_hdmi_audio_controls,
1016         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
1017         .dapm_widgets           = vc4_hdmi_audio_widgets,
1018         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1019         .dapm_routes            = vc4_hdmi_audio_routes,
1020         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1021         .idle_bias_on           = 1,
1022         .use_pmdown_time        = 1,
1023         .endianness             = 1,
1024         .non_legacy_dai_naming  = 1,
1025 };
1026
1027 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1028         .startup = vc4_hdmi_audio_startup,
1029         .shutdown = vc4_hdmi_audio_shutdown,
1030         .hw_params = vc4_hdmi_audio_hw_params,
1031         .set_fmt = vc4_hdmi_audio_set_fmt,
1032         .trigger = vc4_hdmi_audio_trigger,
1033 };
1034
1035 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1036         .name = "vc4-hdmi-hifi",
1037         .playback = {
1038                 .stream_name = "Playback",
1039                 .channels_min = 2,
1040                 .channels_max = 8,
1041                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1042                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1043                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1044                          SNDRV_PCM_RATE_192000,
1045                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1046         },
1047 };
1048
1049 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1050         .name = "vc4-hdmi-cpu-dai-component",
1051 };
1052
1053 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1054 {
1055         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1056
1057         snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1058
1059         return 0;
1060 }
1061
1062 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1063         .name = "vc4-hdmi-cpu-dai",
1064         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1065         .playback = {
1066                 .stream_name = "Playback",
1067                 .channels_min = 1,
1068                 .channels_max = 8,
1069                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1070                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1071                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1072                          SNDRV_PCM_RATE_192000,
1073                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1074         },
1075         .ops = &vc4_hdmi_audio_dai_ops,
1076 };
1077
1078 static const struct snd_dmaengine_pcm_config pcm_conf = {
1079         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1080         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1081 };
1082
1083 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1084 {
1085         struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1086         struct snd_soc_card *card = &hdmi->audio.card;
1087         struct device *dev = &hdmi->pdev->dev;
1088         const __be32 *addr;
1089         int ret;
1090
1091         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1092                 dev_warn(dev,
1093                          "'dmas' DT property is missing, no HDMI audio\n");
1094                 return 0;
1095         }
1096
1097         /*
1098          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1099          * the bus address specified in the DT, because the physical address
1100          * (the one returned by platform_get_resource()) is not appropriate
1101          * for DMA transfers.
1102          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1103          */
1104         addr = of_get_address(dev->of_node, 1, NULL, NULL);
1105         hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1106         hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1107         hdmi->audio.dma_data.maxburst = 2;
1108
1109         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1110         if (ret) {
1111                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1112                 return ret;
1113         }
1114
1115         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1116                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1117         if (ret) {
1118                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1119                 return ret;
1120         }
1121
1122         /* register component and codec dai */
1123         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1124                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1125         if (ret) {
1126                 dev_err(dev, "Could not register component: %d\n", ret);
1127                 return ret;
1128         }
1129
1130         dai_link->name = "MAI";
1131         dai_link->stream_name = "MAI PCM";
1132         dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1133         dai_link->cpu_dai_name = dev_name(dev);
1134         dai_link->codec_name = dev_name(dev);
1135         dai_link->platform_name = dev_name(dev);
1136
1137         card->dai_link = dai_link;
1138         card->num_links = 1;
1139         card->name = "vc4-hdmi";
1140         card->dev = dev;
1141
1142         /*
1143          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1144          * stores a pointer to the snd card object in dev->driver_data. This
1145          * means we cannot use it for something else. The hdmi back-pointer is
1146          * now stored in card->drvdata and should be retrieved with
1147          * snd_soc_card_get_drvdata() if needed.
1148          */
1149         snd_soc_card_set_drvdata(card, hdmi);
1150         ret = devm_snd_soc_register_card(dev, card);
1151         if (ret)
1152                 dev_err(dev, "Could not register sound card: %d\n", ret);
1153
1154         return ret;
1155
1156 }
1157
1158 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1159 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1160 {
1161         struct vc4_dev *vc4 = priv;
1162         struct vc4_hdmi *hdmi = vc4->hdmi;
1163
1164         if (hdmi->cec_irq_was_rx) {
1165                 if (hdmi->cec_rx_msg.len)
1166                         cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1167         } else if (hdmi->cec_tx_ok) {
1168                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1169                                   0, 0, 0, 0);
1170         } else {
1171                 /*
1172                  * This CEC implementation makes 1 retry, so if we
1173                  * get a NACK, then that means it made 2 attempts.
1174                  */
1175                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1176                                   0, 2, 0, 0);
1177         }
1178         return IRQ_HANDLED;
1179 }
1180
1181 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1182 {
1183         struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1184         unsigned int i;
1185
1186         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1187                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1188         for (i = 0; i < msg->len; i += 4) {
1189                 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1190
1191                 msg->msg[i] = val & 0xff;
1192                 msg->msg[i + 1] = (val >> 8) & 0xff;
1193                 msg->msg[i + 2] = (val >> 16) & 0xff;
1194                 msg->msg[i + 3] = (val >> 24) & 0xff;
1195         }
1196 }
1197
1198 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1199 {
1200         struct vc4_dev *vc4 = priv;
1201         struct vc4_hdmi *hdmi = vc4->hdmi;
1202         u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1203         u32 cntrl1, cntrl5;
1204
1205         if (!(stat & VC4_HDMI_CPU_CEC))
1206                 return IRQ_NONE;
1207         hdmi->cec_rx_msg.len = 0;
1208         cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1209         cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1210         hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1211         if (hdmi->cec_irq_was_rx) {
1212                 vc4_cec_read_msg(vc4, cntrl1);
1213                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1214                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1215                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1216         } else {
1217                 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1218                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1219         }
1220         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1221         HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1222
1223         return IRQ_WAKE_THREAD;
1224 }
1225
1226 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1227 {
1228         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1229         /* clock period in microseconds */
1230         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1231         u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1232
1233         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1234                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1235                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1236         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1237                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1238
1239         if (enable) {
1240                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1241                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1242                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1243                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1244                          ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1245                          ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1246                          ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1247                          ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1248                          ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1249                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1250                          ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1251                          ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1252                          ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1253                          ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1254                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1255                          ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1256                          ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1257                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1258                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1259
1260                 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1261         } else {
1262                 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1263                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1264                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1265         }
1266         return 0;
1267 }
1268
1269 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1270 {
1271         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1272
1273         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1274                    (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1275                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1276         return 0;
1277 }
1278
1279 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1280                                       u32 signal_free_time, struct cec_msg *msg)
1281 {
1282         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1283         u32 val;
1284         unsigned int i;
1285
1286         for (i = 0; i < msg->len; i += 4)
1287                 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1288                            (msg->msg[i]) |
1289                            (msg->msg[i + 1] << 8) |
1290                            (msg->msg[i + 2] << 16) |
1291                            (msg->msg[i + 3] << 24));
1292
1293         val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1294         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1295         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1296         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1297         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1298         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1299
1300         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1301         return 0;
1302 }
1303
1304 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1305         .adap_enable = vc4_hdmi_cec_adap_enable,
1306         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1307         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1308 };
1309 #endif
1310
1311 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1312 {
1313         struct platform_device *pdev = to_platform_device(dev);
1314         struct drm_device *drm = dev_get_drvdata(master);
1315         struct vc4_dev *vc4 = drm->dev_private;
1316         struct vc4_hdmi *hdmi;
1317         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1318         struct device_node *ddc_node;
1319         u32 value;
1320         int ret;
1321
1322         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1323         if (!hdmi)
1324                 return -ENOMEM;
1325
1326         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1327                                         GFP_KERNEL);
1328         if (!vc4_hdmi_encoder)
1329                 return -ENOMEM;
1330         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1331         hdmi->encoder = &vc4_hdmi_encoder->base.base;
1332
1333         hdmi->pdev = pdev;
1334         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1335         if (IS_ERR(hdmi->hdmicore_regs))
1336                 return PTR_ERR(hdmi->hdmicore_regs);
1337
1338         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1339         if (IS_ERR(hdmi->hd_regs))
1340                 return PTR_ERR(hdmi->hd_regs);
1341
1342         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1343         if (IS_ERR(hdmi->pixel_clock)) {
1344                 DRM_ERROR("Failed to get pixel clock\n");
1345                 return PTR_ERR(hdmi->pixel_clock);
1346         }
1347         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1348         if (IS_ERR(hdmi->hsm_clock)) {
1349                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1350                 return PTR_ERR(hdmi->hsm_clock);
1351         }
1352
1353         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1354         if (!ddc_node) {
1355                 DRM_ERROR("Failed to find ddc node in device tree\n");
1356                 return -ENODEV;
1357         }
1358
1359         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1360         of_node_put(ddc_node);
1361         if (!hdmi->ddc) {
1362                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1363                 return -EPROBE_DEFER;
1364         }
1365
1366         /* This is the rate that is set by the firmware.  The number
1367          * needs to be a bit higher than the pixel clock rate
1368          * (generally 148.5Mhz).
1369          */
1370         ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1371         if (ret) {
1372                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1373                 goto err_put_i2c;
1374         }
1375
1376         ret = clk_prepare_enable(hdmi->hsm_clock);
1377         if (ret) {
1378                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1379                           ret);
1380                 goto err_put_i2c;
1381         }
1382
1383         /* Only use the GPIO HPD pin if present in the DT, otherwise
1384          * we'll use the HDMI core's register.
1385          */
1386         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1387                 enum of_gpio_flags hpd_gpio_flags;
1388
1389                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1390                                                          "hpd-gpios", 0,
1391                                                          &hpd_gpio_flags);
1392                 if (hdmi->hpd_gpio < 0) {
1393                         ret = hdmi->hpd_gpio;
1394                         goto err_unprepare_hsm;
1395                 }
1396
1397                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1398         }
1399
1400         vc4->hdmi = hdmi;
1401
1402         /* HDMI core must be enabled. */
1403         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1404                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1405                 udelay(1);
1406                 HD_WRITE(VC4_HD_M_CTL, 0);
1407
1408                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1409         }
1410         pm_runtime_enable(dev);
1411
1412         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1413                          DRM_MODE_ENCODER_TMDS, NULL);
1414         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1415
1416         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1417         if (IS_ERR(hdmi->connector)) {
1418                 ret = PTR_ERR(hdmi->connector);
1419                 goto err_destroy_encoder;
1420         }
1421 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1422         hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1423                                               vc4, "vc4",
1424                                               CEC_CAP_TRANSMIT |
1425                                               CEC_CAP_LOG_ADDRS |
1426                                               CEC_CAP_PASSTHROUGH |
1427                                               CEC_CAP_RC, 1);
1428         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1429         if (ret < 0)
1430                 goto err_destroy_conn;
1431         HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1432         value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1433         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1434         /*
1435          * Set the logical address to Unregistered and set the clock
1436          * divider: the hsm_clock rate and this divider setting will
1437          * give a 40 kHz CEC clock.
1438          */
1439         value |= VC4_HDMI_CEC_ADDR_MASK |
1440                  (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1441         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1442         ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1443                                         vc4_cec_irq_handler,
1444                                         vc4_cec_irq_handler_thread, 0,
1445                                         "vc4 hdmi cec", vc4);
1446         if (ret)
1447                 goto err_delete_cec_adap;
1448         ret = cec_register_adapter(hdmi->cec_adap, dev);
1449         if (ret < 0)
1450                 goto err_delete_cec_adap;
1451 #endif
1452
1453         ret = vc4_hdmi_audio_init(hdmi);
1454         if (ret)
1455                 goto err_destroy_encoder;
1456
1457         return 0;
1458
1459 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1460 err_delete_cec_adap:
1461         cec_delete_adapter(hdmi->cec_adap);
1462 err_destroy_conn:
1463         vc4_hdmi_connector_destroy(hdmi->connector);
1464 #endif
1465 err_destroy_encoder:
1466         vc4_hdmi_encoder_destroy(hdmi->encoder);
1467 err_unprepare_hsm:
1468         clk_disable_unprepare(hdmi->hsm_clock);
1469         pm_runtime_disable(dev);
1470 err_put_i2c:
1471         put_device(&hdmi->ddc->dev);
1472
1473         return ret;
1474 }
1475
1476 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1477                             void *data)
1478 {
1479         struct drm_device *drm = dev_get_drvdata(master);
1480         struct vc4_dev *vc4 = drm->dev_private;
1481         struct vc4_hdmi *hdmi = vc4->hdmi;
1482
1483         cec_unregister_adapter(hdmi->cec_adap);
1484         vc4_hdmi_connector_destroy(hdmi->connector);
1485         vc4_hdmi_encoder_destroy(hdmi->encoder);
1486
1487         clk_disable_unprepare(hdmi->hsm_clock);
1488         pm_runtime_disable(dev);
1489
1490         put_device(&hdmi->ddc->dev);
1491
1492         vc4->hdmi = NULL;
1493 }
1494
1495 static const struct component_ops vc4_hdmi_ops = {
1496         .bind   = vc4_hdmi_bind,
1497         .unbind = vc4_hdmi_unbind,
1498 };
1499
1500 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1501 {
1502         return component_add(&pdev->dev, &vc4_hdmi_ops);
1503 }
1504
1505 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1506 {
1507         component_del(&pdev->dev, &vc4_hdmi_ops);
1508         return 0;
1509 }
1510
1511 static const struct of_device_id vc4_hdmi_dt_match[] = {
1512         { .compatible = "brcm,bcm2835-hdmi" },
1513         {}
1514 };
1515
1516 struct platform_driver vc4_hdmi_driver = {
1517         .probe = vc4_hdmi_dev_probe,
1518         .remove = vc4_hdmi_dev_remove,
1519         .driver = {
1520                 .name = "vc4_hdmi",
1521                 .of_match_table = vc4_hdmi_dt_match,
1522         },
1523 };