drivers/gpu/drm/meson/meson_crtc.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <[email protected]>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  * Copyright (C) 2014 Endless Mobile
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of the
  10  * License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  * Written by:
  21  *     Jasper St. Pierre <[email protected]>
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/bitfield.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_flip_work.h>
  33 #include <drm/drm_crtc_helper.h>
  34
  35 #include "meson_crtc.h"
  36 #include "meson_plane.h"
  37 #include "meson_venc.h"
  38 #include "meson_vpp.h"
  39 #include "meson_viu.h"
  40 #include "meson_canvas.h"
  41 #include "meson_registers.h"
  42
  43 /* CRTC definition */
  44
  45 struct meson_crtc {
  46         struct drm_crtc base;
  47         struct drm_pending_vblank_event *event;
  48         struct meson_drm *priv;
  49 };
  50 #define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
  51
  52 /* CRTC */
  53
  54 static int meson_crtc_enable_vblank(struct drm_crtc *crtc)
  55 {
  56         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  57         struct meson_drm *priv = meson_crtc->priv;
  58
  59         meson_venc_enable_vsync(priv);
  60
  61         return 0;
  62 }
  63
  64 static void meson_crtc_disable_vblank(struct drm_crtc *crtc)
  65 {
  66         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  67         struct meson_drm *priv = meson_crtc->priv;
  68
  69         meson_venc_disable_vsync(priv);
  70 }
  71
  72 static const struct drm_crtc_funcs meson_crtc_funcs = {
  73         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
  74         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  75         .destroy                = drm_crtc_cleanup,
  76         .page_flip              = drm_atomic_helper_page_flip,
  77         .reset                  = drm_atomic_helper_crtc_reset,
  78         .set_config             = drm_atomic_helper_set_config,
  79         .enable_vblank          = meson_crtc_enable_vblank,
  80         .disable_vblank         = meson_crtc_disable_vblank,
  81
  82 };
  83
  84 static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
  85                                      struct drm_crtc_state *old_state)
  86 {
  87         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
  88         struct drm_crtc_state *crtc_state = crtc->state;
  89         struct meson_drm *priv = meson_crtc->priv;
  90
  91         DRM_DEBUG_DRIVER("\n");
  92
  93         if (!crtc_state) {
  94                 DRM_ERROR("Invalid crtc_state\n");
  95                 return;
  96         }
  97
  98         /* Enable VPP Postblend */
  99         writel(crtc_state->mode.hdisplay,
 100                priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
 101
 102         /* VD1 Preblend vertical start/end */
 103         writel(FIELD_PREP(GENMASK(11, 0), 2303),
 104                         priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
 105
 106         writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
 107                             priv->io_base + _REG(VPP_MISC));
 108
 109         priv->viu.osd1_enabled = true;
 110 }
 111
 112 static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
 113                                       struct drm_crtc_state *old_state)
 114 {
 115         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
 116         struct meson_drm *priv = meson_crtc->priv;
 117
 118         DRM_DEBUG_DRIVER("\n");
 119
 120         priv->viu.osd1_enabled = false;
 121         priv->viu.osd1_commit = false;
 122
 123         priv->viu.vd1_enabled = false;
 124         priv->viu.vd1_commit = false;
 125
 126         /* Disable VPP Postblend */
 127         writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |
 128                             VPP_VD1_PREBLEND | VPP_POSTBLEND_ENABLE, 0,
 129                             priv->io_base + _REG(VPP_MISC));
 130
 131         if (crtc->state->event && !crtc->state->active) {
 132                 spin_lock_irq(&crtc->dev->event_lock);
 133                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 134                 spin_unlock_irq(&crtc->dev->event_lock);
 135
 136                 crtc->state->event = NULL;
 137         }
 138 }
 139
 140 static void meson_crtc_atomic_begin(struct drm_crtc *crtc,
 141                                     struct drm_crtc_state *state)
 142 {
 143         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
 144         unsigned long flags;
 145
 146         if (crtc->state->event) {
 147                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 148
 149                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 150                 meson_crtc->event = crtc->state->event;
 151                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 152                 crtc->state->event = NULL;
 153         }
 154 }
 155
 156 static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
 157                                     struct drm_crtc_state *old_crtc_state)
 158 {
 159         struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
 160         struct meson_drm *priv = meson_crtc->priv;
 161
 162         priv->viu.osd1_commit = true;
 163         priv->viu.vd1_commit = true;
 164 }
 165
 166 static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
 167         .atomic_begin   = meson_crtc_atomic_begin,
 168         .atomic_flush   = meson_crtc_atomic_flush,
 169         .atomic_enable  = meson_crtc_atomic_enable,
 170         .atomic_disable = meson_crtc_atomic_disable,
 171 };
 172
 173 void meson_crtc_irq(struct meson_drm *priv)
 174 {
 175         struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
 176         unsigned long flags;
 177
 178         /* Update the OSD registers */
 179         if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
 180                 writel_relaxed(priv->viu.osd1_ctrl_stat,
 181                                 priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
 182                 writel_relaxed(priv->viu.osd1_blk0_cfg[0],
 183                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
 184                 writel_relaxed(priv->viu.osd1_blk0_cfg[1],
 185                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
 186                 writel_relaxed(priv->viu.osd1_blk0_cfg[2],
 187                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
 188                 writel_relaxed(priv->viu.osd1_blk0_cfg[3],
 189                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
 190                 writel_relaxed(priv->viu.osd1_blk0_cfg[4],
 191                                 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
 192                 writel_relaxed(priv->viu.osd_sc_ctrl0,
 193                                 priv->io_base + _REG(VPP_OSD_SC_CTRL0));
 194                 writel_relaxed(priv->viu.osd_sc_i_wh_m1,
 195                                 priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
 196                 writel_relaxed(priv->viu.osd_sc_o_h_start_end,
 197                                 priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
 198                 writel_relaxed(priv->viu.osd_sc_o_v_start_end,
 199                                 priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
 200                 writel_relaxed(priv->viu.osd_sc_v_ini_phase,
 201                                 priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
 202                 writel_relaxed(priv->viu.osd_sc_v_phase_step,
 203                                 priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
 204                 writel_relaxed(priv->viu.osd_sc_h_ini_phase,
 205                                 priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE));
 206                 writel_relaxed(priv->viu.osd_sc_h_phase_step,
 207                                 priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP));
 208                 writel_relaxed(priv->viu.osd_sc_h_ctrl0,
 209                                 priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
 210                 writel_relaxed(priv->viu.osd_sc_v_ctrl0,
 211                                 priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
 212
 213                 if (priv->canvas)
 214                         meson_canvas_config(priv->canvas, priv->canvas_id_osd1,
 215                                 priv->viu.osd1_addr, priv->viu.osd1_stride,
 216                                 priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
 217                                 MESON_CANVAS_BLKMODE_LINEAR, 0);
 218                 else
 219                         meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
 220                                 priv->viu.osd1_addr, priv->viu.osd1_stride,
 221                                 priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
 222                                 MESON_CANVAS_BLKMODE_LINEAR, 0);
 223
 224                 /* Enable OSD1 */
 225                 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
 226                                     priv->io_base + _REG(VPP_MISC));
 227
 228                 priv->viu.osd1_commit = false;
 229         }
 230
 231         /* Update the VD1 registers */
 232         if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
 233
 234                 switch (priv->viu.vd1_planes) {
 235                 case 3:
 236                         if (priv->canvas)
 237                                 meson_canvas_config(priv->canvas,
 238                                                     priv->canvas_id_vd1_2,
 239                                                     priv->viu.vd1_addr2,
 240                                                     priv->viu.vd1_stride2,
 241                                                     priv->viu.vd1_height2,
 242                                                     MESON_CANVAS_WRAP_NONE,
 243                                                     MESON_CANVAS_BLKMODE_LINEAR,
 244                                                     MESON_CANVAS_ENDIAN_SWAP64);
 245                         else
 246                                 meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_2,
 247                                                    priv->viu.vd1_addr2,
 248                                                    priv->viu.vd1_stride2,
 249                                                    priv->viu.vd1_height2,
 250                                                    MESON_CANVAS_WRAP_NONE,
 251                                                    MESON_CANVAS_BLKMODE_LINEAR,
 252                                                    MESON_CANVAS_ENDIAN_SWAP64);
 253                 /* fallthrough */
 254                 case 2:
 255                         if (priv->canvas)
 256                                 meson_canvas_config(priv->canvas,
 257                                                     priv->canvas_id_vd1_1,
 258                                                     priv->viu.vd1_addr1,
 259                                                     priv->viu.vd1_stride1,
 260                                                     priv->viu.vd1_height1,
 261                                                     MESON_CANVAS_WRAP_NONE,
 262                                                     MESON_CANVAS_BLKMODE_LINEAR,
 263                                                     MESON_CANVAS_ENDIAN_SWAP64);
 264                         else
 265                                 meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_1,
 266                                                    priv->viu.vd1_addr2,
 267                                                    priv->viu.vd1_stride2,
 268                                                    priv->viu.vd1_height2,
 269                                                    MESON_CANVAS_WRAP_NONE,
 270                                                    MESON_CANVAS_BLKMODE_LINEAR,
 271                                                    MESON_CANVAS_ENDIAN_SWAP64);
 272                 /* fallthrough */
 273                 case 1:
 274                         if (priv->canvas)
 275                                 meson_canvas_config(priv->canvas,
 276                                                     priv->canvas_id_vd1_0,
 277                                                     priv->viu.vd1_addr0,
 278                                                     priv->viu.vd1_stride0,
 279                                                     priv->viu.vd1_height0,
 280                                                     MESON_CANVAS_WRAP_NONE,
 281                                                     MESON_CANVAS_BLKMODE_LINEAR,
 282                                                     MESON_CANVAS_ENDIAN_SWAP64);
 283                         else
 284                                 meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_0,
 285                                                    priv->viu.vd1_addr2,
 286                                                    priv->viu.vd1_stride2,
 287                                                    priv->viu.vd1_height2,
 288                                                    MESON_CANVAS_WRAP_NONE,
 289                                                    MESON_CANVAS_BLKMODE_LINEAR,
 290                                                    MESON_CANVAS_ENDIAN_SWAP64);
 291                 };
 292
 293                 writel_relaxed(priv->viu.vd1_if0_gen_reg,
 294                                 priv->io_base + _REG(VD1_IF0_GEN_REG));
 295                 writel_relaxed(priv->viu.vd1_if0_gen_reg,
 296                                 priv->io_base + _REG(VD2_IF0_GEN_REG));
 297                 writel_relaxed(priv->viu.vd1_if0_gen_reg2,
 298                                 priv->io_base + _REG(VD1_IF0_GEN_REG2));
 299                 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
 300                                 priv->io_base + _REG(VIU_VD1_FMT_CTRL));
 301                 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
 302                                 priv->io_base + _REG(VIU_VD2_FMT_CTRL));
 303                 writel_relaxed(priv->viu.viu_vd1_fmt_w,
 304                                 priv->io_base + _REG(VIU_VD1_FMT_W));
 305                 writel_relaxed(priv->viu.viu_vd1_fmt_w,
 306                                 priv->io_base + _REG(VIU_VD2_FMT_W));
 307                 writel_relaxed(priv->viu.vd1_if0_canvas0,
 308                                 priv->io_base + _REG(VD1_IF0_CANVAS0));
 309                 writel_relaxed(priv->viu.vd1_if0_canvas0,
 310                                 priv->io_base + _REG(VD1_IF0_CANVAS1));
 311                 writel_relaxed(priv->viu.vd1_if0_canvas0,
 312                                 priv->io_base + _REG(VD2_IF0_CANVAS0));
 313                 writel_relaxed(priv->viu.vd1_if0_canvas0,
 314                                 priv->io_base + _REG(VD2_IF0_CANVAS1));
 315                 writel_relaxed(priv->viu.vd1_if0_luma_x0,
 316                                 priv->io_base + _REG(VD1_IF0_LUMA_X0));
 317                 writel_relaxed(priv->viu.vd1_if0_luma_x0,
 318                                 priv->io_base + _REG(VD1_IF0_LUMA_X1));
 319                 writel_relaxed(priv->viu.vd1_if0_luma_x0,
 320                                 priv->io_base + _REG(VD2_IF0_LUMA_X0));
 321                 writel_relaxed(priv->viu.vd1_if0_luma_x0,
 322                                 priv->io_base + _REG(VD2_IF0_LUMA_X1));
 323                 writel_relaxed(priv->viu.vd1_if0_luma_y0,
 324                                 priv->io_base + _REG(VD1_IF0_LUMA_Y0));
 325                 writel_relaxed(priv->viu.vd1_if0_luma_y0,
 326                                 priv->io_base + _REG(VD1_IF0_LUMA_Y1));
 327                 writel_relaxed(priv->viu.vd1_if0_luma_y0,
 328                                 priv->io_base + _REG(VD2_IF0_LUMA_Y0));
 329                 writel_relaxed(priv->viu.vd1_if0_luma_y0,
 330                                 priv->io_base + _REG(VD2_IF0_LUMA_Y1));
 331                 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
 332                                 priv->io_base + _REG(VD1_IF0_CHROMA_X0));
 333                 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
 334                                 priv->io_base + _REG(VD1_IF0_CHROMA_X1));
 335                 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
 336                                 priv->io_base + _REG(VD2_IF0_CHROMA_X0));
 337                 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
 338                                 priv->io_base + _REG(VD2_IF0_CHROMA_X1));
 339                 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
 340                                 priv->io_base + _REG(VD1_IF0_CHROMA_Y0));
 341                 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
 342                                 priv->io_base + _REG(VD1_IF0_CHROMA_Y1));
 343                 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
 344                                 priv->io_base + _REG(VD2_IF0_CHROMA_Y0));
 345                 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
 346                                 priv->io_base + _REG(VD2_IF0_CHROMA_Y1));
 347                 writel_relaxed(priv->viu.vd1_if0_repeat_loop,
 348                                 priv->io_base + _REG(VD1_IF0_RPT_LOOP));
 349                 writel_relaxed(priv->viu.vd1_if0_repeat_loop,
 350                                 priv->io_base + _REG(VD2_IF0_RPT_LOOP));
 351                 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
 352                                 priv->io_base + _REG(VD1_IF0_LUMA0_RPT_PAT));
 353                 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
 354                                 priv->io_base + _REG(VD2_IF0_LUMA0_RPT_PAT));
 355                 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
 356                                 priv->io_base + _REG(VD1_IF0_LUMA1_RPT_PAT));
 357                 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
 358                                 priv->io_base + _REG(VD2_IF0_LUMA1_RPT_PAT));
 359                 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
 360                                 priv->io_base + _REG(VD1_IF0_CHROMA0_RPT_PAT));
 361                 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
 362                                 priv->io_base + _REG(VD2_IF0_CHROMA0_RPT_PAT));
 363                 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
 364                                 priv->io_base + _REG(VD1_IF0_CHROMA1_RPT_PAT));
 365                 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
 366                                 priv->io_base + _REG(VD2_IF0_CHROMA1_RPT_PAT));
 367                 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_LUMA_PSEL));
 368                 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_CHROMA_PSEL));
 369                 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_LUMA_PSEL));
 370                 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_CHROMA_PSEL));
 371                 writel_relaxed(priv->viu.vd1_range_map_y,
 372                                 priv->io_base + _REG(VD1_IF0_RANGE_MAP_Y));
 373                 writel_relaxed(priv->viu.vd1_range_map_cb,
 374                                 priv->io_base + _REG(VD1_IF0_RANGE_MAP_CB));
 375                 writel_relaxed(priv->viu.vd1_range_map_cr,
 376                                 priv->io_base + _REG(VD1_IF0_RANGE_MAP_CR));
 377                 writel_relaxed(0x78404,
 378                                 priv->io_base + _REG(VPP_SC_MISC));
 379                 writel_relaxed(priv->viu.vpp_pic_in_height,
 380                                 priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
 381                 writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
 382                         priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
 383                 writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
 384                         priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
 385                 writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
 386                         priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
 387                 writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
 388                         priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
 389                 writel_relaxed(priv->viu.vpp_hsc_region12_startp,
 390                                 priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
 391                 writel_relaxed(priv->viu.vpp_hsc_region34_startp,
 392                                 priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
 393                 writel_relaxed(priv->viu.vpp_hsc_region4_endp,
 394                                 priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
 395                 writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
 396                                 priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
 397                 writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
 398                         priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
 399                 writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
 400                         priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
 401                 writel_relaxed(priv->viu.vpp_line_in_length,
 402                                 priv->io_base + _REG(VPP_LINE_IN_LENGTH));
 403                 writel_relaxed(priv->viu.vpp_preblend_h_size,
 404                                 priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
 405                 writel_relaxed(priv->viu.vpp_vsc_region12_startp,
 406                                 priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
 407                 writel_relaxed(priv->viu.vpp_vsc_region34_startp,
 408                                 priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
 409                 writel_relaxed(priv->viu.vpp_vsc_region4_endp,
 410                                 priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
 411                 writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
 412                                 priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
 413                 writel_relaxed(priv->viu.vpp_vsc_ini_phase,
 414                                 priv->io_base + _REG(VPP_VSC_INI_PHASE));
 415                 writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
 416                                 priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
 417                 writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
 418                                 priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
 419                 writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
 420
 421                 /* Enable VD1 */
 422                 writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
 423                                     VPP_COLOR_MNG_ENABLE,
 424                                     VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
 425                                     VPP_COLOR_MNG_ENABLE,
 426                                     priv->io_base + _REG(VPP_MISC));
 427
 428                 priv->viu.vd1_commit = false;
 429         }
 430
 431         drm_crtc_handle_vblank(priv->crtc);
 432
 433         spin_lock_irqsave(&priv->drm->event_lock, flags);
 434         if (meson_crtc->event) {
 435                 drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
 436                 drm_crtc_vblank_put(priv->crtc);
 437                 meson_crtc->event = NULL;
 438         }
 439         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 440 }
 441
 442 int meson_crtc_create(struct meson_drm *priv)
 443 {
 444         struct meson_crtc *meson_crtc;
 445         struct drm_crtc *crtc;
 446         int ret;
 447
 448         meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
 449                                   GFP_KERNEL);
 450         if (!meson_crtc)
 451                 return -ENOMEM;
 452
 453         meson_crtc->priv = priv;
 454         crtc = &meson_crtc->base;
 455         ret = drm_crtc_init_with_planes(priv->drm, crtc,
 456                                         priv->primary_plane, NULL,
 457                                         &meson_crtc_funcs, "meson_crtc");
 458         if (ret) {
 459                 dev_err(priv->drm->dev, "Failed to init CRTC\n");
 460                 return ret;
 461         }
 462
 463         drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs);
 464
 465         priv->crtc = crtc;
 466
 467         return 0;
 468 }