drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 struct ddi_buf_trans {
  33         u32 trans1;     /* balance leg enable, de-emph level */
  34         u32 trans2;     /* vref sel, vswing */
  35         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  36 };
  37
  38 static const u8 index_to_dp_signal_levels[] = {
  39         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  40         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  41         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  42         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  43         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  44         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  45         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  46         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  47         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  48         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  49 };
  50
  51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  52  * them for both DP and FDI transports, allowing those ports to
  53  * automatically adapt to HDMI connections as well
  54  */
  55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  56         { 0x00FFFFFF, 0x0006000E, 0x0 },
  57         { 0x00D75FFF, 0x0005000A, 0x0 },
  58         { 0x00C30FFF, 0x00040006, 0x0 },
  59         { 0x80AAAFFF, 0x000B0000, 0x0 },
  60         { 0x00FFFFFF, 0x0005000A, 0x0 },
  61         { 0x00D75FFF, 0x000C0004, 0x0 },
  62         { 0x80C30FFF, 0x000B0000, 0x0 },
  63         { 0x00FFFFFF, 0x00040006, 0x0 },
  64         { 0x80D75FFF, 0x000B0000, 0x0 },
  65 };
  66
  67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  68         { 0x00FFFFFF, 0x0007000E, 0x0 },
  69         { 0x00D75FFF, 0x000F000A, 0x0 },
  70         { 0x00C30FFF, 0x00060006, 0x0 },
  71         { 0x00AAAFFF, 0x001E0000, 0x0 },
  72         { 0x00FFFFFF, 0x000F000A, 0x0 },
  73         { 0x00D75FFF, 0x00160004, 0x0 },
  74         { 0x00C30FFF, 0x001E0000, 0x0 },
  75         { 0x00FFFFFF, 0x00060006, 0x0 },
  76         { 0x00D75FFF, 0x001E0000, 0x0 },
  77 };
  78
  79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  80                                         /* Idx  NT mV d T mV d  db      */
  81         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  82         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  83         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  84         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  85         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  86         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  87         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  88         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  89         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  90         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  91         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  92         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  93 };
  94
  95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  96         { 0x00FFFFFF, 0x00000012, 0x0 },
  97         { 0x00EBAFFF, 0x00020011, 0x0 },
  98         { 0x00C71FFF, 0x0006000F, 0x0 },
  99         { 0x00AAAFFF, 0x000E000A, 0x0 },
 100         { 0x00FFFFFF, 0x00020011, 0x0 },
 101         { 0x00DB6FFF, 0x0005000F, 0x0 },
 102         { 0x00BEEFFF, 0x000A000C, 0x0 },
 103         { 0x00FFFFFF, 0x0005000F, 0x0 },
 104         { 0x00DB6FFF, 0x000A000C, 0x0 },
 105 };
 106
 107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 108         { 0x00FFFFFF, 0x0007000E, 0x0 },
 109         { 0x00D75FFF, 0x000E000A, 0x0 },
 110         { 0x00BEFFFF, 0x00140006, 0x0 },
 111         { 0x80B2CFFF, 0x001B0002, 0x0 },
 112         { 0x00FFFFFF, 0x000E000A, 0x0 },
 113         { 0x00DB6FFF, 0x00160005, 0x0 },
 114         { 0x80C71FFF, 0x001A0002, 0x0 },
 115         { 0x00F7DFFF, 0x00180004, 0x0 },
 116         { 0x80D75FFF, 0x001B0002, 0x0 },
 117 };
 118
 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 120         { 0x00FFFFFF, 0x0001000E, 0x0 },
 121         { 0x00D75FFF, 0x0004000A, 0x0 },
 122         { 0x00C30FFF, 0x00070006, 0x0 },
 123         { 0x00AAAFFF, 0x000C0000, 0x0 },
 124         { 0x00FFFFFF, 0x0004000A, 0x0 },
 125         { 0x00D75FFF, 0x00090004, 0x0 },
 126         { 0x00C30FFF, 0x000C0000, 0x0 },
 127         { 0x00FFFFFF, 0x00070006, 0x0 },
 128         { 0x00D75FFF, 0x000C0000, 0x0 },
 129 };
 130
 131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 132                                         /* Idx  NT mV d T mV df db      */
 133         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 134         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 135         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 136         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 137         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 138         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 139         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 140         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 141         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 142         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 143 };
 144
 145 /* Skylake H and S */
 146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 147         { 0x00002016, 0x000000A0, 0x0 },
 148         { 0x00005012, 0x0000009B, 0x0 },
 149         { 0x00007011, 0x00000088, 0x0 },
 150         { 0x80009010, 0x000000C0, 0x1 },
 151         { 0x00002016, 0x0000009B, 0x0 },
 152         { 0x00005012, 0x00000088, 0x0 },
 153         { 0x80007011, 0x000000C0, 0x1 },
 154         { 0x00002016, 0x000000DF, 0x0 },
 155         { 0x80005012, 0x000000C0, 0x1 },
 156 };
 157
 158 /* Skylake U */
 159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 160         { 0x0000201B, 0x000000A2, 0x0 },
 161         { 0x00005012, 0x00000088, 0x0 },
 162         { 0x80007011, 0x000000CD, 0x1 },
 163         { 0x80009010, 0x000000C0, 0x1 },
 164         { 0x0000201B, 0x0000009D, 0x0 },
 165         { 0x80005012, 0x000000C0, 0x1 },
 166         { 0x80007011, 0x000000C0, 0x1 },
 167         { 0x00002016, 0x00000088, 0x0 },
 168         { 0x80005012, 0x000000C0, 0x1 },
 169 };
 170
 171 /* Skylake Y */
 172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 173         { 0x00000018, 0x000000A2, 0x0 },
 174         { 0x00005012, 0x00000088, 0x0 },
 175         { 0x80007011, 0x000000CD, 0x3 },
 176         { 0x80009010, 0x000000C0, 0x3 },
 177         { 0x00000018, 0x0000009D, 0x0 },
 178         { 0x80005012, 0x000000C0, 0x3 },
 179         { 0x80007011, 0x000000C0, 0x3 },
 180         { 0x00000018, 0x00000088, 0x0 },
 181         { 0x80005012, 0x000000C0, 0x3 },
 182 };
 183
 184 /* Kabylake H and S */
 185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 186         { 0x00002016, 0x000000A0, 0x0 },
 187         { 0x00005012, 0x0000009B, 0x0 },
 188         { 0x00007011, 0x00000088, 0x0 },
 189         { 0x80009010, 0x000000C0, 0x1 },
 190         { 0x00002016, 0x0000009B, 0x0 },
 191         { 0x00005012, 0x00000088, 0x0 },
 192         { 0x80007011, 0x000000C0, 0x1 },
 193         { 0x00002016, 0x00000097, 0x0 },
 194         { 0x80005012, 0x000000C0, 0x1 },
 195 };
 196
 197 /* Kabylake U */
 198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 199         { 0x0000201B, 0x000000A1, 0x0 },
 200         { 0x00005012, 0x00000088, 0x0 },
 201         { 0x80007011, 0x000000CD, 0x3 },
 202         { 0x80009010, 0x000000C0, 0x3 },
 203         { 0x0000201B, 0x0000009D, 0x0 },
 204         { 0x80005012, 0x000000C0, 0x3 },
 205         { 0x80007011, 0x000000C0, 0x3 },
 206         { 0x00002016, 0x0000004F, 0x0 },
 207         { 0x80005012, 0x000000C0, 0x3 },
 208 };
 209
 210 /* Kabylake Y */
 211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 212         { 0x00001017, 0x000000A1, 0x0 },
 213         { 0x00005012, 0x00000088, 0x0 },
 214         { 0x80007011, 0x000000CD, 0x3 },
 215         { 0x8000800F, 0x000000C0, 0x3 },
 216         { 0x00001017, 0x0000009D, 0x0 },
 217         { 0x80005012, 0x000000C0, 0x3 },
 218         { 0x80007011, 0x000000C0, 0x3 },
 219         { 0x00001017, 0x0000004C, 0x0 },
 220         { 0x80005012, 0x000000C0, 0x3 },
 221 };
 222
 223 /*
 224  * Skylake/Kabylake H and S
 225  * eDP 1.4 low vswing translation parameters
 226  */
 227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 228         { 0x00000018, 0x000000A8, 0x0 },
 229         { 0x00004013, 0x000000A9, 0x0 },
 230         { 0x00007011, 0x000000A2, 0x0 },
 231         { 0x00009010, 0x0000009C, 0x0 },
 232         { 0x00000018, 0x000000A9, 0x0 },
 233         { 0x00006013, 0x000000A2, 0x0 },
 234         { 0x00007011, 0x000000A6, 0x0 },
 235         { 0x00000018, 0x000000AB, 0x0 },
 236         { 0x00007013, 0x0000009F, 0x0 },
 237         { 0x00000018, 0x000000DF, 0x0 },
 238 };
 239
 240 /*
 241  * Skylake/Kabylake U
 242  * eDP 1.4 low vswing translation parameters
 243  */
 244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 245         { 0x00000018, 0x000000A8, 0x0 },
 246         { 0x00004013, 0x000000A9, 0x0 },
 247         { 0x00007011, 0x000000A2, 0x0 },
 248         { 0x00009010, 0x0000009C, 0x0 },
 249         { 0x00000018, 0x000000A9, 0x0 },
 250         { 0x00006013, 0x000000A2, 0x0 },
 251         { 0x00007011, 0x000000A6, 0x0 },
 252         { 0x00002016, 0x000000AB, 0x0 },
 253         { 0x00005013, 0x0000009F, 0x0 },
 254         { 0x00000018, 0x000000DF, 0x0 },
 255 };
 256
 257 /*
 258  * Skylake/Kabylake Y
 259  * eDP 1.4 low vswing translation parameters
 260  */
 261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 262         { 0x00000018, 0x000000A8, 0x0 },
 263         { 0x00004013, 0x000000AB, 0x0 },
 264         { 0x00007011, 0x000000A4, 0x0 },
 265         { 0x00009010, 0x000000DF, 0x0 },
 266         { 0x00000018, 0x000000AA, 0x0 },
 267         { 0x00006013, 0x000000A4, 0x0 },
 268         { 0x00007011, 0x0000009D, 0x0 },
 269         { 0x00000018, 0x000000A0, 0x0 },
 270         { 0x00006012, 0x000000DF, 0x0 },
 271         { 0x00000018, 0x0000008A, 0x0 },
 272 };
 273
 274 /* Skylake/Kabylake U, H and S */
 275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 276         { 0x00000018, 0x000000AC, 0x0 },
 277         { 0x00005012, 0x0000009D, 0x0 },
 278         { 0x00007011, 0x00000088, 0x0 },
 279         { 0x00000018, 0x000000A1, 0x0 },
 280         { 0x00000018, 0x00000098, 0x0 },
 281         { 0x00004013, 0x00000088, 0x0 },
 282         { 0x80006012, 0x000000CD, 0x1 },
 283         { 0x00000018, 0x000000DF, 0x0 },
 284         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 285         { 0x80003015, 0x000000C0, 0x1 },
 286         { 0x80000018, 0x000000C0, 0x1 },
 287 };
 288
 289 /* Skylake/Kabylake Y */
 290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 291         { 0x00000018, 0x000000A1, 0x0 },
 292         { 0x00005012, 0x000000DF, 0x0 },
 293         { 0x80007011, 0x000000CB, 0x3 },
 294         { 0x00000018, 0x000000A4, 0x0 },
 295         { 0x00000018, 0x0000009D, 0x0 },
 296         { 0x00004013, 0x00000080, 0x0 },
 297         { 0x80006013, 0x000000C0, 0x3 },
 298         { 0x00000018, 0x0000008A, 0x0 },
 299         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 300         { 0x80003015, 0x000000C0, 0x3 },
 301         { 0x80000018, 0x000000C0, 0x3 },
 302 };
 303
 304 struct bxt_ddi_buf_trans {
 305         u8 margin;      /* swing value */
 306         u8 scale;       /* scale value */
 307         u8 enable;      /* scale enable */
 308         u8 deemphasis;
 309 };
 310
 311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 312                                         /* Idx  NT mV diff      db  */
 313         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 314         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 315         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 316         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 317         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 318         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 319         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 320         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 321         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 322         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 323 };
 324
 325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 326                                         /* Idx  NT mV diff      db  */
 327         { 26, 0, 0, 128, },     /* 0:   200             0   */
 328         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 329         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 330         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 331         { 32, 0, 0, 128, },     /* 4:   250             0   */
 332         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 333         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 334         { 43, 0, 0, 128, },     /* 7:   300             0   */
 335         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 336         { 48, 0, 0, 128, },     /* 9:   300             0   */
 337 };
 338
 339 /* BSpec has 2 recommended values - entries 0 and 8.
 340  * Using the entry with higher vswing.
 341  */
 342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 343                                         /* Idx  NT mV diff      db  */
 344         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 345         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 346         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 347         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 348         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 349         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 350         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 351         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 352         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 353         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 354 };
 355
 356 struct cnl_ddi_buf_trans {
 357         u8 dw2_swing_sel;
 358         u8 dw7_n_scalar;
 359         u8 dw4_cursor_coeff;
 360         u8 dw4_post_cursor_2;
 361         u8 dw4_post_cursor_1;
 362 };
 363
 364 /* Voltage Swing Programming for VccIO 0.85V for DP */
 365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 366                                                 /* NT mV Trans mV db    */
 367         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 368         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 369         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 370         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 371         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 372         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 373         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 374         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 375         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 376         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 377 };
 378
 379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 381                                                 /* NT mV Trans mV db    */
 382         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 383         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 384         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 385         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 386         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 387         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 388         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 389 };
 390
 391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 393                                                 /* NT mV Trans mV db    */
 394         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 395         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 396         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 397         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 398         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 399         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 400         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 401         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 402         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 403 };
 404
 405 /* Voltage Swing Programming for VccIO 0.95V for DP */
 406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 407                                                 /* NT mV Trans mV db    */
 408         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 409         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 410         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 411         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 412         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 413         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 414         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 415         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 416         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 417         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 418 };
 419
 420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 422                                                 /* NT mV Trans mV db    */
 423         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 425         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 426         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 427         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 428         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 429         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 430         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 431         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 432         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 433         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 434 };
 435
 436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 438                                                 /* NT mV Trans mV db    */
 439         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 440         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 441         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 442         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 443         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 444         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 445         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 446         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 447         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 448         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 449 };
 450
 451 /* Voltage Swing Programming for VccIO 1.05V for DP */
 452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 453                                                 /* NT mV Trans mV db    */
 454         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 455         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 456         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 457         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 458         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 459         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 460         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 461         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 462         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 463         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 464 };
 465
 466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 468                                                 /* NT mV Trans mV db    */
 469         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 471         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 472         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 473         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 474         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 475         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 476         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 477         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 478         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 479         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 480 };
 481
 482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 484                                                 /* NT mV Trans mV db    */
 485         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 486         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 487         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 488         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 489         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 490         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 491         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 492         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 493         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 494 };
 495
 496 struct icl_combo_phy_ddi_buf_trans {
 497         u32 dw2_swing_select;
 498         u32 dw2_swing_scalar;
 499         u32 dw4_scaling;
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 0.85V for DP */
 503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 504                                 /* Voltage mV  db    */
 505         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 506         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 507         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 508         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 509         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 510         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 511         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 512         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 513         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 514         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 515 };
 516
 517 /* FIXME - After table is updated in Bspec */
 518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 520                                 /* Voltage mV  db    */
 521         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 522         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 523         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 524         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 525         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 527         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 528         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 530         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 531 };
 532
 533 /* Voltage Swing Programming for VccIO 0.95V for DP */
 534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 535                                 /* Voltage mV  db    */
 536         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 537         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 538         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 539         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 540         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 541         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 542         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 543         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 544         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 545         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 546 };
 547
 548 /* FIXME - After table is updated in Bspec */
 549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 551                                 /* Voltage mV  db    */
 552         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 553         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 554         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 555         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 556         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 558         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 559         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 561         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 562 };
 563
 564 /* Voltage Swing Programming for VccIO 1.05V for DP */
 565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 566                                 /* Voltage mV  db    */
 567         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 568         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 569         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 570         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 571         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 572         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 573         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 574         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 575         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 576         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 577 };
 578
 579 /* FIXME - After table is updated in Bspec */
 580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 582                                 /* Voltage mV  db    */
 583         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 584         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 585         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 586         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 587         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 589         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 590         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 592         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 593 };
 594
 595 struct icl_mg_phy_ddi_buf_trans {
 596         u32 cri_txdeemph_override_5_0;
 597         u32 cri_txdeemph_override_11_6;
 598         u32 cri_txdeemph_override_17_12;
 599 };
 600
 601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 602                                 /* Voltage swing  pre-emphasis */
 603         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 604         { 0x0, 0x23, 0x08 },    /* 0              1   */
 605         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 606         { 0x0, 0x00, 0x00 },    /* 0              3   */
 607         { 0x0, 0x23, 0x00 },    /* 1              0   */
 608         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 609         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 610         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 611         { 0x0, 0x33, 0x0C },    /* 2              1   */
 612         { 0x0, 0x00, 0x00 },    /* 3              0   */
 613 };
 614
 615 static const struct ddi_buf_trans *
 616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 617 {
 618         if (dev_priv->vbt.edp.low_vswing) {
 619                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 620                 return bdw_ddi_translations_edp;
 621         } else {
 622                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 623                 return bdw_ddi_translations_dp;
 624         }
 625 }
 626
 627 static const struct ddi_buf_trans *
 628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 629 {
 630         if (IS_SKL_ULX(dev_priv)) {
 631                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 632                 return skl_y_ddi_translations_dp;
 633         } else if (IS_SKL_ULT(dev_priv)) {
 634                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 635                 return skl_u_ddi_translations_dp;
 636         } else {
 637                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 638                 return skl_ddi_translations_dp;
 639         }
 640 }
 641
 642 static const struct ddi_buf_trans *
 643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 644 {
 645         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 646                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 647                 return kbl_y_ddi_translations_dp;
 648         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 649                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 650                 return kbl_u_ddi_translations_dp;
 651         } else {
 652                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 653                 return kbl_ddi_translations_dp;
 654         }
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 659 {
 660         if (dev_priv->vbt.edp.low_vswing) {
 661                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 663                         return skl_y_ddi_translations_edp;
 664                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 665                            IS_CFL_ULT(dev_priv)) {
 666                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 667                         return skl_u_ddi_translations_edp;
 668                 } else {
 669                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 670                         return skl_ddi_translations_edp;
 671                 }
 672         }
 673
 674         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 675                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 676         else
 677                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 678 }
 679
 680 static const struct ddi_buf_trans *
 681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 682 {
 683         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 684                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 685                 return skl_y_ddi_translations_hdmi;
 686         } else {
 687                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 688                 return skl_ddi_translations_hdmi;
 689         }
 690 }
 691
 692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 693 {
 694         /* Only DDIA and DDIE can select the 10th register with DP */
 695         if (port == PORT_A || port == PORT_E)
 696                 return min(n_entries, 10);
 697         else
 698                 return min(n_entries, 9);
 699 }
 700
 701 static const struct ddi_buf_trans *
 702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 703                            enum port port, int *n_entries)
 704 {
 705         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 706                 const struct ddi_buf_trans *ddi_translations =
 707                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 708                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 709                 return ddi_translations;
 710         } else if (IS_SKYLAKE(dev_priv)) {
 711                 const struct ddi_buf_trans *ddi_translations =
 712                         skl_get_buf_trans_dp(dev_priv, n_entries);
 713                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 714                 return ddi_translations;
 715         } else if (IS_BROADWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 717                 return  bdw_ddi_translations_dp;
 718         } else if (IS_HASWELL(dev_priv)) {
 719                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 720                 return hsw_ddi_translations_dp;
 721         }
 722
 723         *n_entries = 0;
 724         return NULL;
 725 }
 726
 727 static const struct ddi_buf_trans *
 728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 729                             enum port port, int *n_entries)
 730 {
 731         if (IS_GEN9_BC(dev_priv)) {
 732                 const struct ddi_buf_trans *ddi_translations =
 733                         skl_get_buf_trans_edp(dev_priv, n_entries);
 734                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 735                 return ddi_translations;
 736         } else if (IS_BROADWELL(dev_priv)) {
 737                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 738         } else if (IS_HASWELL(dev_priv)) {
 739                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 740                 return hsw_ddi_translations_dp;
 741         }
 742
 743         *n_entries = 0;
 744         return NULL;
 745 }
 746
 747 static const struct ddi_buf_trans *
 748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 749                             int *n_entries)
 750 {
 751         if (IS_BROADWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 753                 return bdw_ddi_translations_fdi;
 754         } else if (IS_HASWELL(dev_priv)) {
 755                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 756                 return hsw_ddi_translations_fdi;
 757         }
 758
 759         *n_entries = 0;
 760         return NULL;
 761 }
 762
 763 static const struct ddi_buf_trans *
 764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 765                              int *n_entries)
 766 {
 767         if (IS_GEN9_BC(dev_priv)) {
 768                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 769         } else if (IS_BROADWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 771                 return bdw_ddi_translations_hdmi;
 772         } else if (IS_HASWELL(dev_priv)) {
 773                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 774                 return hsw_ddi_translations_hdmi;
 775         }
 776
 777         *n_entries = 0;
 778         return NULL;
 779 }
 780
 781 static const struct bxt_ddi_buf_trans *
 782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 783 {
 784         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 785         return bxt_ddi_translations_dp;
 786 }
 787
 788 static const struct bxt_ddi_buf_trans *
 789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 790 {
 791         if (dev_priv->vbt.edp.low_vswing) {
 792                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 793                 return bxt_ddi_translations_edp;
 794         }
 795
 796         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 803         return bxt_ddi_translations_hdmi;
 804 }
 805
 806 static const struct cnl_ddi_buf_trans *
 807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 808 {
 809         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 810
 811         if (voltage == VOLTAGE_INFO_0_85V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 813                 return cnl_ddi_translations_hdmi_0_85V;
 814         } else if (voltage == VOLTAGE_INFO_0_95V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 816                 return cnl_ddi_translations_hdmi_0_95V;
 817         } else if (voltage == VOLTAGE_INFO_1_05V) {
 818                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 819                 return cnl_ddi_translations_hdmi_1_05V;
 820         } else {
 821                 *n_entries = 1; /* shut up gcc */
 822                 MISSING_CASE(voltage);
 823         }
 824         return NULL;
 825 }
 826
 827 static const struct cnl_ddi_buf_trans *
 828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 829 {
 830         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 831
 832         if (voltage == VOLTAGE_INFO_0_85V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 834                 return cnl_ddi_translations_dp_0_85V;
 835         } else if (voltage == VOLTAGE_INFO_0_95V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 837                 return cnl_ddi_translations_dp_0_95V;
 838         } else if (voltage == VOLTAGE_INFO_1_05V) {
 839                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 840                 return cnl_ddi_translations_dp_1_05V;
 841         } else {
 842                 *n_entries = 1; /* shut up gcc */
 843                 MISSING_CASE(voltage);
 844         }
 845         return NULL;
 846 }
 847
 848 static const struct cnl_ddi_buf_trans *
 849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 850 {
 851         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 852
 853         if (dev_priv->vbt.edp.low_vswing) {
 854                 if (voltage == VOLTAGE_INFO_0_85V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 856                         return cnl_ddi_translations_edp_0_85V;
 857                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 859                         return cnl_ddi_translations_edp_0_95V;
 860                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 861                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 862                         return cnl_ddi_translations_edp_1_05V;
 863                 } else {
 864                         *n_entries = 1; /* shut up gcc */
 865                         MISSING_CASE(voltage);
 866                 }
 867                 return NULL;
 868         } else {
 869                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 870         }
 871 }
 872
 873 static const struct icl_combo_phy_ddi_buf_trans *
 874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 875                         int type, int *n_entries)
 876 {
 877         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 878
 879         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 880                 switch (voltage) {
 881                 case VOLTAGE_INFO_0_85V:
 882                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 883                         return icl_combo_phy_ddi_translations_edp_0_85V;
 884                 case VOLTAGE_INFO_0_95V:
 885                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 886                         return icl_combo_phy_ddi_translations_edp_0_95V;
 887                 case VOLTAGE_INFO_1_05V:
 888                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 889                         return icl_combo_phy_ddi_translations_edp_1_05V;
 890                 default:
 891                         MISSING_CASE(voltage);
 892                         return NULL;
 893                 }
 894         } else {
 895                 switch (voltage) {
 896                 case VOLTAGE_INFO_0_85V:
 897                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 898                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 899                 case VOLTAGE_INFO_0_95V:
 900                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 901                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 902                 case VOLTAGE_INFO_1_05V:
 903                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 904                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 905                 default:
 906                         MISSING_CASE(voltage);
 907                         return NULL;
 908                 }
 909         }
 910 }
 911
 912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 913 {
 914         int n_entries, level, default_entry;
 915
 916         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 917
 918         if (IS_ICELAKE(dev_priv)) {
 919                 if (intel_port_is_combophy(dev_priv, port))
 920                         icl_get_combo_buf_trans(dev_priv, port,
 921                                                 INTEL_OUTPUT_HDMI, &n_entries);
 922                 else
 923                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 924                 default_entry = n_entries - 1;
 925         } else if (IS_CANNONLAKE(dev_priv)) {
 926                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 927                 default_entry = n_entries - 1;
 928         } else if (IS_GEN9_LP(dev_priv)) {
 929                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 930                 default_entry = n_entries - 1;
 931         } else if (IS_GEN9_BC(dev_priv)) {
 932                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 933                 default_entry = 8;
 934         } else if (IS_BROADWELL(dev_priv)) {
 935                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 936                 default_entry = 7;
 937         } else if (IS_HASWELL(dev_priv)) {
 938                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 939                 default_entry = 6;
 940         } else {
 941                 WARN(1, "ddi translation table missing\n");
 942                 return 0;
 943         }
 944
 945         /* Choose a good default if VBT is badly populated */
 946         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 947                 level = default_entry;
 948
 949         if (WARN_ON_ONCE(n_entries == 0))
 950                 return 0;
 951         if (WARN_ON_ONCE(level >= n_entries))
 952                 level = n_entries - 1;
 953
 954         return level;
 955 }
 956
 957 /*
 958  * Starting with Haswell, DDI port buffers must be programmed with correct
 959  * values in advance. This function programs the correct values for
 960  * DP/eDP/FDI use cases.
 961  */
 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 966         u32 iboost_bit = 0;
 967         int i, n_entries;
 968         enum port port = encoder->port;
 969         const struct ddi_buf_trans *ddi_translations;
 970
 971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 972                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 973                                                                &n_entries);
 974         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 975                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 976                                                                &n_entries);
 977         else
 978                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 979                                                               &n_entries);
 980
 981         /* If we're boosting the current, set bit 31 of trans1 */
 982         if (IS_GEN9_BC(dev_priv) &&
 983             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 984                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 985
 986         for (i = 0; i < n_entries; i++) {
 987                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 988                            ddi_translations[i].trans1 | iboost_bit);
 989                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 990                            ddi_translations[i].trans2);
 991         }
 992 }
 993
 994 /*
 995  * Starting with Haswell, DDI port buffers must be programmed with correct
 996  * values in advance. This function programs the correct values for
 997  * HDMI/DVI use cases.
 998  */
 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000                                            int level)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003         u32 iboost_bit = 0;
1004         int n_entries;
1005         enum port port = encoder->port;
1006         const struct ddi_buf_trans *ddi_translations;
1007
1008         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010         if (WARN_ON_ONCE(!ddi_translations))
1011                 return;
1012         if (WARN_ON_ONCE(level >= n_entries))
1013                 level = n_entries - 1;
1014
1015         /* If we're boosting the current, set bit 31 of trans1 */
1016         if (IS_GEN9_BC(dev_priv) &&
1017             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020         /* Entry 9 is for HDMI: */
1021         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022                    ddi_translations[level].trans1 | iboost_bit);
1023         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024                    ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028                                     enum port port)
1029 {
1030         i915_reg_t reg = DDI_BUF_CTL(port);
1031         int i;
1032
1033         for (i = 0; i < 16; i++) {
1034                 udelay(1);
1035                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036                         return;
1037         }
1038         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043         switch (pll->info->id) {
1044         case DPLL_ID_WRPLL1:
1045                 return PORT_CLK_SEL_WRPLL1;
1046         case DPLL_ID_WRPLL2:
1047                 return PORT_CLK_SEL_WRPLL2;
1048         case DPLL_ID_SPLL:
1049                 return PORT_CLK_SEL_SPLL;
1050         case DPLL_ID_LCPLL_810:
1051                 return PORT_CLK_SEL_LCPLL_810;
1052         case DPLL_ID_LCPLL_1350:
1053                 return PORT_CLK_SEL_LCPLL_1350;
1054         case DPLL_ID_LCPLL_2700:
1055                 return PORT_CLK_SEL_LCPLL_2700;
1056         default:
1057                 MISSING_CASE(pll->info->id);
1058                 return PORT_CLK_SEL_NONE;
1059         }
1060 }
1061
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063                                        const struct intel_crtc_state *crtc_state)
1064 {
1065         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1066         int clock = crtc_state->port_clock;
1067         const enum intel_dpll_id id = pll->info->id;
1068
1069         switch (id) {
1070         default:
1071                 MISSING_CASE(id);
1072                 /* fall through */
1073         case DPLL_ID_ICL_DPLL0:
1074         case DPLL_ID_ICL_DPLL1:
1075                 return DDI_CLK_SEL_NONE;
1076         case DPLL_ID_ICL_TBTPLL:
1077                 switch (clock) {
1078                 case 162000:
1079                         return DDI_CLK_SEL_TBT_162;
1080                 case 270000:
1081                         return DDI_CLK_SEL_TBT_270;
1082                 case 540000:
1083                         return DDI_CLK_SEL_TBT_540;
1084                 case 810000:
1085                         return DDI_CLK_SEL_TBT_810;
1086                 default:
1087                         MISSING_CASE(clock);
1088                         break;
1089                 }
1090         case DPLL_ID_ICL_MGPLL1:
1091         case DPLL_ID_ICL_MGPLL2:
1092         case DPLL_ID_ICL_MGPLL3:
1093         case DPLL_ID_ICL_MGPLL4:
1094                 return DDI_CLK_SEL_MG;
1095         }
1096 }
1097
1098 /* Starting with Haswell, different DDI ports can work in FDI mode for
1099  * connection to the PCH-located connectors. For this, it is necessary to train
1100  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1101  *
1102  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104  * DDI A (which is used for eDP)
1105  */
1106
1107 void hsw_fdi_link_train(struct intel_crtc *crtc,
1108                         const struct intel_crtc_state *crtc_state)
1109 {
1110         struct drm_device *dev = crtc->base.dev;
1111         struct drm_i915_private *dev_priv = to_i915(dev);
1112         struct intel_encoder *encoder;
1113         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1114
1115         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1116                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1117                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1118         }
1119
1120         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121          * mode set "sequence for CRT port" document:
1122          * - TP1 to TP2 time with the default value
1123          * - FDI delay to 90h
1124          *
1125          * WaFDIAutoLinkSetTimingOverrride:hsw
1126          */
1127         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1128                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1129                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1130
1131         /* Enable the PCH Receiver FDI PLL */
1132         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1133                      FDI_RX_PLL_ENABLE |
1134                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1135         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136         POSTING_READ(FDI_RX_CTL(PIPE_A));
1137         udelay(220);
1138
1139         /* Switch from Rawclk to PCDclk */
1140         rx_ctl_val |= FDI_PCDCLK;
1141         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1142
1143         /* Configure Port Clock Select */
1144         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1145         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1147
1148         /* Start the training iterating through available voltages and emphasis,
1149          * testing each value twice. */
1150         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1151                 /* Configure DP_TP_CTL with auto-training */
1152                 I915_WRITE(DP_TP_CTL(PORT_E),
1153                                         DP_TP_CTL_FDI_AUTOTRAIN |
1154                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1156                                         DP_TP_CTL_ENABLE);
1157
1158                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159                  * DDI E does not support port reversal, the functionality is
1160                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161                  * port reversal bit */
1162                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1163                            DDI_BUF_CTL_ENABLE |
1164                            ((crtc_state->fdi_lanes - 1) << 1) |
1165                            DDI_BUF_TRANS_SELECT(i / 2));
1166                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1167
1168                 udelay(600);
1169
1170                 /* Program PCH FDI Receiver TU */
1171                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1172
1173                 /* Enable PCH FDI Receiver with auto-training */
1174                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1175                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1177
1178                 /* Wait for FDI receiver lane calibration */
1179                 udelay(30);
1180
1181                 /* Unset FDI_RX_MISC pwrdn lanes */
1182                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1186
1187                 /* Wait for FDI auto training time */
1188                 udelay(5);
1189
1190                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1192                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1193                         break;
1194                 }
1195
1196                 /*
1197                  * Leave things enabled even if we failed to train FDI.
1198                  * Results in less fireworks from the state checker.
1199                  */
1200                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201                         DRM_ERROR("FDI link training failed!\n");
1202                         break;
1203                 }
1204
1205                 rx_ctl_val &= ~FDI_RX_ENABLE;
1206                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1208
1209                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210                 temp &= ~DDI_BUF_CTL_ENABLE;
1211                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1213
1214                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1215                 temp = I915_READ(DP_TP_CTL(PORT_E));
1216                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219                 POSTING_READ(DP_TP_CTL(PORT_E));
1220
1221                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1222
1223                 /* Reset FDI_RX_MISC pwrdn lanes */
1224                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1225                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1227                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1229         }
1230
1231         /* Enable normal pixel sending for FDI */
1232         I915_WRITE(DP_TP_CTL(PORT_E),
1233                    DP_TP_CTL_FDI_AUTOTRAIN |
1234                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1235                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1236                    DP_TP_CTL_ENABLE);
1237 }
1238
1239 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1240 {
1241         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242         struct intel_digital_port *intel_dig_port =
1243                 enc_to_dig_port(&encoder->base);
1244
1245         intel_dp->DP = intel_dig_port->saved_port_bits |
1246                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1247         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1248 }
1249
1250 static struct intel_encoder *
1251 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1252 {
1253         struct drm_device *dev = crtc->base.dev;
1254         struct intel_encoder *encoder, *ret = NULL;
1255         int num_encoders = 0;
1256
1257         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1258                 ret = encoder;
1259                 num_encoders++;
1260         }
1261
1262         if (num_encoders != 1)
1263                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1264                      pipe_name(crtc->pipe));
1265
1266         BUG_ON(ret == NULL);
1267         return ret;
1268 }
1269
1270 #define LC_FREQ 2700
1271
1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1273                                    i915_reg_t reg)
1274 {
1275         int refclk = LC_FREQ;
1276         int n, p, r;
1277         u32 wrpll;
1278
1279         wrpll = I915_READ(reg);
1280         switch (wrpll & WRPLL_PLL_REF_MASK) {
1281         case WRPLL_PLL_SSC:
1282         case WRPLL_PLL_NON_SSC:
1283                 /*
1284                  * We could calculate spread here, but our checking
1285                  * code only cares about 5% accuracy, and spread is a max of
1286                  * 0.5% downspread.
1287                  */
1288                 refclk = 135;
1289                 break;
1290         case WRPLL_PLL_LCPLL:
1291                 refclk = LC_FREQ;
1292                 break;
1293         default:
1294                 WARN(1, "bad wrpll refclk\n");
1295                 return 0;
1296         }
1297
1298         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1301
1302         /* Convert to KHz, p & r have a fixed point portion */
1303         return (refclk * n * 100) / (p * r);
1304 }
1305
1306 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307                                enum intel_dpll_id pll_id)
1308 {
1309         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1310         uint32_t cfgcr1_val, cfgcr2_val;
1311         uint32_t p0, p1, p2, dco_freq;
1312
1313         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1315
1316         cfgcr1_val = I915_READ(cfgcr1_reg);
1317         cfgcr2_val = I915_READ(cfgcr2_reg);
1318
1319         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1321
1322         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1323                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1324         else
1325                 p1 = 1;
1326
1327
1328         switch (p0) {
1329         case DPLL_CFGCR2_PDIV_1:
1330                 p0 = 1;
1331                 break;
1332         case DPLL_CFGCR2_PDIV_2:
1333                 p0 = 2;
1334                 break;
1335         case DPLL_CFGCR2_PDIV_3:
1336                 p0 = 3;
1337                 break;
1338         case DPLL_CFGCR2_PDIV_7:
1339                 p0 = 7;
1340                 break;
1341         }
1342
1343         switch (p2) {
1344         case DPLL_CFGCR2_KDIV_5:
1345                 p2 = 5;
1346                 break;
1347         case DPLL_CFGCR2_KDIV_2:
1348                 p2 = 2;
1349                 break;
1350         case DPLL_CFGCR2_KDIV_3:
1351                 p2 = 3;
1352                 break;
1353         case DPLL_CFGCR2_KDIV_1:
1354                 p2 = 1;
1355                 break;
1356         }
1357
1358         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1359
1360         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1361                 1000) / 0x8000;
1362
1363         return dco_freq / (p0 * p1 * p2 * 5);
1364 }
1365
1366 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1367                                enum intel_dpll_id pll_id)
1368 {
1369         uint32_t cfgcr0, cfgcr1;
1370         uint32_t p0, p1, p2, dco_freq, ref_clock;
1371
1372         if (INTEL_GEN(dev_priv) >= 11) {
1373                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1375         } else {
1376                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1378         }
1379
1380         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386         else
1387                 p1 = 1;
1388
1389
1390         switch (p0) {
1391         case DPLL_CFGCR1_PDIV_2:
1392                 p0 = 2;
1393                 break;
1394         case DPLL_CFGCR1_PDIV_3:
1395                 p0 = 3;
1396                 break;
1397         case DPLL_CFGCR1_PDIV_5:
1398                 p0 = 5;
1399                 break;
1400         case DPLL_CFGCR1_PDIV_7:
1401                 p0 = 7;
1402                 break;
1403         }
1404
1405         switch (p2) {
1406         case DPLL_CFGCR1_KDIV_1:
1407                 p2 = 1;
1408                 break;
1409         case DPLL_CFGCR1_KDIV_2:
1410                 p2 = 2;
1411                 break;
1412         case DPLL_CFGCR1_KDIV_4:
1413                 p2 = 4;
1414                 break;
1415         }
1416
1417         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1418
1419         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1420
1421         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1423
1424         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1425                 return 0;
1426
1427         return dco_freq / (p0 * p1 * p2 * 5);
1428 }
1429
1430 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1431                                  enum port port)
1432 {
1433         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1434
1435         switch (val) {
1436         case DDI_CLK_SEL_NONE:
1437                 return 0;
1438         case DDI_CLK_SEL_TBT_162:
1439                 return 162000;
1440         case DDI_CLK_SEL_TBT_270:
1441                 return 270000;
1442         case DDI_CLK_SEL_TBT_540:
1443                 return 540000;
1444         case DDI_CLK_SEL_TBT_810:
1445                 return 810000;
1446         default:
1447                 MISSING_CASE(val);
1448                 return 0;
1449         }
1450 }
1451
1452 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1453                                 enum port port)
1454 {
1455         u32 mg_pll_div0, mg_clktop_hsclkctl;
1456         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1457         u64 tmp;
1458
1459         refclk = dev_priv->cdclk.hw.ref;
1460
1461         mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1463
1464         m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1469
1470         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1472                 div1 = 2;
1473                 break;
1474         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1475                 div1 = 3;
1476                 break;
1477         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1478                 div1 = 5;
1479                 break;
1480         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1481                 div1 = 7;
1482                 break;
1483         default:
1484                 MISSING_CASE(mg_clktop_hsclkctl);
1485                 return 0;
1486         }
1487
1488         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490         /* div2 value of 0 is same as 1 means no div */
1491         if (div2 == 0)
1492                 div2 = 1;
1493
1494         /*
1495          * Adjust the original formula to delay the division by 2^22 in order to
1496          * minimize possible rounding errors.
1497          */
1498         tmp = (u64)m1 * m2_int * refclk +
1499               (((u64)m1 * m2_frac * refclk) >> 22);
1500         tmp = div_u64(tmp, 5 * div1 * div2);
1501
1502         return tmp;
1503 }
1504
1505 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1506 {
1507         int dotclock;
1508
1509         if (pipe_config->has_pch_encoder)
1510                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1511                                                     &pipe_config->fdi_m_n);
1512         else if (intel_crtc_has_dp_encoder(pipe_config))
1513                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514                                                     &pipe_config->dp_m_n);
1515         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1516                 dotclock = pipe_config->port_clock * 2 / 3;
1517         else
1518                 dotclock = pipe_config->port_clock;
1519
1520         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1521                 dotclock *= 2;
1522
1523         if (pipe_config->pixel_multiplier)
1524                 dotclock /= pipe_config->pixel_multiplier;
1525
1526         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1527 }
1528
1529 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1530                               struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533         enum port port = encoder->port;
1534         int link_clock = 0;
1535         uint32_t pll_id;
1536
1537         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538         if (intel_port_is_combophy(dev_priv, port)) {
1539                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1541                 else
1542                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1543                                                                 pll_id);
1544         } else {
1545                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1546                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1547                 else
1548                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1549         }
1550
1551         pipe_config->port_clock = link_clock;
1552         ddi_dotclock_get(pipe_config);
1553 }
1554
1555 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1556                               struct intel_crtc_state *pipe_config)
1557 {
1558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1559         int link_clock = 0;
1560         uint32_t cfgcr0;
1561         enum intel_dpll_id pll_id;
1562
1563         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1564
1565         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1566
1567         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1569         } else {
1570                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572                 switch (link_clock) {
1573                 case DPLL_CFGCR0_LINK_RATE_810:
1574                         link_clock = 81000;
1575                         break;
1576                 case DPLL_CFGCR0_LINK_RATE_1080:
1577                         link_clock = 108000;
1578                         break;
1579                 case DPLL_CFGCR0_LINK_RATE_1350:
1580                         link_clock = 135000;
1581                         break;
1582                 case DPLL_CFGCR0_LINK_RATE_1620:
1583                         link_clock = 162000;
1584                         break;
1585                 case DPLL_CFGCR0_LINK_RATE_2160:
1586                         link_clock = 216000;
1587                         break;
1588                 case DPLL_CFGCR0_LINK_RATE_2700:
1589                         link_clock = 270000;
1590                         break;
1591                 case DPLL_CFGCR0_LINK_RATE_3240:
1592                         link_clock = 324000;
1593                         break;
1594                 case DPLL_CFGCR0_LINK_RATE_4050:
1595                         link_clock = 405000;
1596                         break;
1597                 default:
1598                         WARN(1, "Unsupported link rate\n");
1599                         break;
1600                 }
1601                 link_clock *= 2;
1602         }
1603
1604         pipe_config->port_clock = link_clock;
1605
1606         ddi_dotclock_get(pipe_config);
1607 }
1608
1609 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1610                                 struct intel_crtc_state *pipe_config)
1611 {
1612         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1613         int link_clock = 0;
1614         uint32_t dpll_ctl1;
1615         enum intel_dpll_id pll_id;
1616
1617         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1618
1619         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1620
1621         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1622                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1623         } else {
1624                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1625                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1626
1627                 switch (link_clock) {
1628                 case DPLL_CTRL1_LINK_RATE_810:
1629                         link_clock = 81000;
1630                         break;
1631                 case DPLL_CTRL1_LINK_RATE_1080:
1632                         link_clock = 108000;
1633                         break;
1634                 case DPLL_CTRL1_LINK_RATE_1350:
1635                         link_clock = 135000;
1636                         break;
1637                 case DPLL_CTRL1_LINK_RATE_1620:
1638                         link_clock = 162000;
1639                         break;
1640                 case DPLL_CTRL1_LINK_RATE_2160:
1641                         link_clock = 216000;
1642                         break;
1643                 case DPLL_CTRL1_LINK_RATE_2700:
1644                         link_clock = 270000;
1645                         break;
1646                 default:
1647                         WARN(1, "Unsupported link rate\n");
1648                         break;
1649                 }
1650                 link_clock *= 2;
1651         }
1652
1653         pipe_config->port_clock = link_clock;
1654
1655         ddi_dotclock_get(pipe_config);
1656 }
1657
1658 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1659                               struct intel_crtc_state *pipe_config)
1660 {
1661         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1662         int link_clock = 0;
1663         u32 val, pll;
1664
1665         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1666         switch (val & PORT_CLK_SEL_MASK) {
1667         case PORT_CLK_SEL_LCPLL_810:
1668                 link_clock = 81000;
1669                 break;
1670         case PORT_CLK_SEL_LCPLL_1350:
1671                 link_clock = 135000;
1672                 break;
1673         case PORT_CLK_SEL_LCPLL_2700:
1674                 link_clock = 270000;
1675                 break;
1676         case PORT_CLK_SEL_WRPLL1:
1677                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1678                 break;
1679         case PORT_CLK_SEL_WRPLL2:
1680                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1681                 break;
1682         case PORT_CLK_SEL_SPLL:
1683                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1684                 if (pll == SPLL_PLL_FREQ_810MHz)
1685                         link_clock = 81000;
1686                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1687                         link_clock = 135000;
1688                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1689                         link_clock = 270000;
1690                 else {
1691                         WARN(1, "bad spll freq\n");
1692                         return;
1693                 }
1694                 break;
1695         default:
1696                 WARN(1, "bad port clock sel\n");
1697                 return;
1698         }
1699
1700         pipe_config->port_clock = link_clock * 2;
1701
1702         ddi_dotclock_get(pipe_config);
1703 }
1704
1705 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1706 {
1707         struct intel_dpll_hw_state *state;
1708         struct dpll clock;
1709
1710         /* For DDI ports we always use a shared PLL. */
1711         if (WARN_ON(!crtc_state->shared_dpll))
1712                 return 0;
1713
1714         state = &crtc_state->dpll_hw_state;
1715
1716         clock.m1 = 2;
1717         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1718         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1719                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1720         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1721         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1722         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1723
1724         return chv_calc_dpll_params(100000, &clock);
1725 }
1726
1727 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1728                               struct intel_crtc_state *pipe_config)
1729 {
1730         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1731
1732         ddi_dotclock_get(pipe_config);
1733 }
1734
1735 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1736                                 struct intel_crtc_state *pipe_config)
1737 {
1738         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1739
1740         if (IS_ICELAKE(dev_priv))
1741                 icl_ddi_clock_get(encoder, pipe_config);
1742         else if (IS_CANNONLAKE(dev_priv))
1743                 cnl_ddi_clock_get(encoder, pipe_config);
1744         else if (IS_GEN9_LP(dev_priv))
1745                 bxt_ddi_clock_get(encoder, pipe_config);
1746         else if (IS_GEN9_BC(dev_priv))
1747                 skl_ddi_clock_get(encoder, pipe_config);
1748         else if (INTEL_GEN(dev_priv) <= 8)
1749                 hsw_ddi_clock_get(encoder, pipe_config);
1750 }
1751
1752 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1753 {
1754         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1755         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1756         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1757         u32 temp;
1758
1759         if (!intel_crtc_has_dp_encoder(crtc_state))
1760                 return;
1761
1762         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1763
1764         temp = TRANS_MSA_SYNC_CLK;
1765
1766         if (crtc_state->limited_color_range)
1767                 temp |= TRANS_MSA_CEA_RANGE;
1768
1769         switch (crtc_state->pipe_bpp) {
1770         case 18:
1771                 temp |= TRANS_MSA_6_BPC;
1772                 break;
1773         case 24:
1774                 temp |= TRANS_MSA_8_BPC;
1775                 break;
1776         case 30:
1777                 temp |= TRANS_MSA_10_BPC;
1778                 break;
1779         case 36:
1780                 temp |= TRANS_MSA_12_BPC;
1781                 break;
1782         default:
1783                 MISSING_CASE(crtc_state->pipe_bpp);
1784                 break;
1785         }
1786
1787         /*
1788          * As per DP 1.2 spec section 2.3.4.3 while sending
1789          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1790          * colorspace information. The output colorspace encoding is BT601.
1791          */
1792         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1793                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1794         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1795 }
1796
1797 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1798                                     bool state)
1799 {
1800         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1801         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1803         uint32_t temp;
1804
1805         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1806         if (state == true)
1807                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1808         else
1809                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1810         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1811 }
1812
1813 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1814 {
1815         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1816         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1818         enum pipe pipe = crtc->pipe;
1819         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1820         enum port port = encoder->port;
1821         uint32_t temp;
1822
1823         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1824         temp = TRANS_DDI_FUNC_ENABLE;
1825         temp |= TRANS_DDI_SELECT_PORT(port);
1826
1827         switch (crtc_state->pipe_bpp) {
1828         case 18:
1829                 temp |= TRANS_DDI_BPC_6;
1830                 break;
1831         case 24:
1832                 temp |= TRANS_DDI_BPC_8;
1833                 break;
1834         case 30:
1835                 temp |= TRANS_DDI_BPC_10;
1836                 break;
1837         case 36:
1838                 temp |= TRANS_DDI_BPC_12;
1839                 break;
1840         default:
1841                 BUG();
1842         }
1843
1844         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1845                 temp |= TRANS_DDI_PVSYNC;
1846         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1847                 temp |= TRANS_DDI_PHSYNC;
1848
1849         if (cpu_transcoder == TRANSCODER_EDP) {
1850                 switch (pipe) {
1851                 case PIPE_A:
1852                         /* On Haswell, can only use the always-on power well for
1853                          * eDP when not using the panel fitter, and when not
1854                          * using motion blur mitigation (which we don't
1855                          * support). */
1856                         if (IS_HASWELL(dev_priv) &&
1857                             (crtc_state->pch_pfit.enabled ||
1858                              crtc_state->pch_pfit.force_thru))
1859                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1860                         else
1861                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1862                         break;
1863                 case PIPE_B:
1864                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1865                         break;
1866                 case PIPE_C:
1867                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1868                         break;
1869                 default:
1870                         BUG();
1871                         break;
1872                 }
1873         }
1874
1875         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1876                 if (crtc_state->has_hdmi_sink)
1877                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1878                 else
1879                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1880
1881                 if (crtc_state->hdmi_scrambling)
1882                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1883                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1884                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1885         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1886                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1887                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1888         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1889                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1890                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1891         } else {
1892                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1893                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1894         }
1895
1896         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1897 }
1898
1899 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1900 {
1901         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1902         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1903         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1904         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1905         uint32_t val = I915_READ(reg);
1906
1907         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1908         val |= TRANS_DDI_PORT_NONE;
1909         I915_WRITE(reg, val);
1910
1911         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1912             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1913                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1914                 /* Quirk time at 100ms for reliable operation */
1915                 msleep(100);
1916         }
1917 }
1918
1919 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1920                                      bool enable)
1921 {
1922         struct drm_device *dev = intel_encoder->base.dev;
1923         struct drm_i915_private *dev_priv = to_i915(dev);
1924         enum pipe pipe = 0;
1925         int ret = 0;
1926         uint32_t tmp;
1927
1928         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1929                                                 intel_encoder->power_domain)))
1930                 return -ENXIO;
1931
1932         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1933                 ret = -EIO;
1934                 goto out;
1935         }
1936
1937         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1938         if (enable)
1939                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1940         else
1941                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1942         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1943 out:
1944         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1945         return ret;
1946 }
1947
1948 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1949 {
1950         struct drm_device *dev = intel_connector->base.dev;
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         struct intel_encoder *encoder = intel_connector->encoder;
1953         int type = intel_connector->base.connector_type;
1954         enum port port = encoder->port;
1955         enum pipe pipe = 0;
1956         enum transcoder cpu_transcoder;
1957         uint32_t tmp;
1958         bool ret;
1959
1960         if (!intel_display_power_get_if_enabled(dev_priv,
1961                                                 encoder->power_domain))
1962                 return false;
1963
1964         if (!encoder->get_hw_state(encoder, &pipe)) {
1965                 ret = false;
1966                 goto out;
1967         }
1968
1969         if (port == PORT_A)
1970                 cpu_transcoder = TRANSCODER_EDP;
1971         else
1972                 cpu_transcoder = (enum transcoder) pipe;
1973
1974         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1975
1976         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1977         case TRANS_DDI_MODE_SELECT_HDMI:
1978         case TRANS_DDI_MODE_SELECT_DVI:
1979                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1980                 break;
1981
1982         case TRANS_DDI_MODE_SELECT_DP_SST:
1983                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1984                       type == DRM_MODE_CONNECTOR_DisplayPort;
1985                 break;
1986
1987         case TRANS_DDI_MODE_SELECT_DP_MST:
1988                 /* if the transcoder is in MST state then
1989                  * connector isn't connected */
1990                 ret = false;
1991                 break;
1992
1993         case TRANS_DDI_MODE_SELECT_FDI:
1994                 ret = type == DRM_MODE_CONNECTOR_VGA;
1995                 break;
1996
1997         default:
1998                 ret = false;
1999                 break;
2000         }
2001
2002 out:
2003         intel_display_power_put(dev_priv, encoder->power_domain);
2004
2005         return ret;
2006 }
2007
2008 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2009                                         u8 *pipe_mask, bool *is_dp_mst)
2010 {
2011         struct drm_device *dev = encoder->base.dev;
2012         struct drm_i915_private *dev_priv = to_i915(dev);
2013         enum port port = encoder->port;
2014         enum pipe p;
2015         u32 tmp;
2016         u8 mst_pipe_mask;
2017
2018         *pipe_mask = 0;
2019         *is_dp_mst = false;
2020
2021         if (!intel_display_power_get_if_enabled(dev_priv,
2022                                                 encoder->power_domain))
2023                 return;
2024
2025         tmp = I915_READ(DDI_BUF_CTL(port));
2026         if (!(tmp & DDI_BUF_CTL_ENABLE))
2027                 goto out;
2028
2029         if (port == PORT_A) {
2030                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2031
2032                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2033                 default:
2034                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2035                         /* fallthrough */
2036                 case TRANS_DDI_EDP_INPUT_A_ON:
2037                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2038                         *pipe_mask = BIT(PIPE_A);
2039                         break;
2040                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2041                         *pipe_mask = BIT(PIPE_B);
2042                         break;
2043                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2044                         *pipe_mask = BIT(PIPE_C);
2045                         break;
2046                 }
2047
2048                 goto out;
2049         }
2050
2051         mst_pipe_mask = 0;
2052         for_each_pipe(dev_priv, p) {
2053                 enum transcoder cpu_transcoder = (enum transcoder)p;
2054
2055                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2056
2057                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2058                         continue;
2059
2060                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2061                     TRANS_DDI_MODE_SELECT_DP_MST)
2062                         mst_pipe_mask |= BIT(p);
2063
2064                 *pipe_mask |= BIT(p);
2065         }
2066
2067         if (!*pipe_mask)
2068                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2069                               port_name(port));
2070
2071         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2072                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2073                               port_name(port), *pipe_mask);
2074                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2075         }
2076
2077         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2078                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2079                               port_name(port), *pipe_mask, mst_pipe_mask);
2080         else
2081                 *is_dp_mst = mst_pipe_mask;
2082
2083 out:
2084         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2085                 tmp = I915_READ(BXT_PHY_CTL(port));
2086                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2087                             BXT_PHY_LANE_POWERDOWN_ACK |
2088                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2089                         DRM_ERROR("Port %c enabled but PHY powered down? "
2090                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2091         }
2092
2093         intel_display_power_put(dev_priv, encoder->power_domain);
2094 }
2095
2096 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2097                             enum pipe *pipe)
2098 {
2099         u8 pipe_mask;
2100         bool is_mst;
2101
2102         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2103
2104         if (is_mst || !pipe_mask)
2105                 return false;
2106
2107         *pipe = ffs(pipe_mask) - 1;
2108
2109         return true;
2110 }
2111
2112 static inline enum intel_display_power_domain
2113 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2114 {
2115         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2116          * DC states enabled at the same time, while for driver initiated AUX
2117          * transfers we need the same AUX IOs to be powered but with DC states
2118          * disabled. Accordingly use the AUX power domain here which leaves DC
2119          * states enabled.
2120          * However, for non-A AUX ports the corresponding non-EDP transcoders
2121          * would have already enabled power well 2 and DC_OFF. This means we can
2122          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2123          * specific AUX_IO reference without powering up any extra wells.
2124          * Note that PSR is enabled only on Port A even though this function
2125          * returns the correct domain for other ports too.
2126          */
2127         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2128                                               intel_aux_power_domain(dig_port);
2129 }
2130
2131 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2132                                        struct intel_crtc_state *crtc_state)
2133 {
2134         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2135         struct intel_digital_port *dig_port;
2136         u64 domains;
2137
2138         /*
2139          * TODO: Add support for MST encoders. Atm, the following should never
2140          * happen since fake-MST encoders don't set their get_power_domains()
2141          * hook.
2142          */
2143         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2144                 return 0;
2145
2146         dig_port = enc_to_dig_port(&encoder->base);
2147         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2148
2149         /*
2150          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2151          * ports.
2152          */
2153         if (intel_crtc_has_dp_encoder(crtc_state) ||
2154             intel_port_is_tc(dev_priv, encoder->port))
2155                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2156
2157         return domains;
2158 }
2159
2160 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2161 {
2162         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2163         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2164         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2165         enum port port = encoder->port;
2166         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2167
2168         if (cpu_transcoder != TRANSCODER_EDP)
2169                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2170                            TRANS_CLK_SEL_PORT(port));
2171 }
2172
2173 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2174 {
2175         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2176         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2177
2178         if (cpu_transcoder != TRANSCODER_EDP)
2179                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2180                            TRANS_CLK_SEL_DISABLED);
2181 }
2182
2183 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2184                                 enum port port, uint8_t iboost)
2185 {
2186         u32 tmp;
2187
2188         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2189         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2190         if (iboost)
2191                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2192         else
2193                 tmp |= BALANCE_LEG_DISABLE(port);
2194         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2195 }
2196
2197 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2198                                int level, enum intel_output_type type)
2199 {
2200         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2202         enum port port = encoder->port;
2203         uint8_t iboost;
2204
2205         if (type == INTEL_OUTPUT_HDMI)
2206                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2207         else
2208                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2209
2210         if (iboost == 0) {
2211                 const struct ddi_buf_trans *ddi_translations;
2212                 int n_entries;
2213
2214                 if (type == INTEL_OUTPUT_HDMI)
2215                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2216                 else if (type == INTEL_OUTPUT_EDP)
2217                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2218                 else
2219                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2220
2221                 if (WARN_ON_ONCE(!ddi_translations))
2222                         return;
2223                 if (WARN_ON_ONCE(level >= n_entries))
2224                         level = n_entries - 1;
2225
2226                 iboost = ddi_translations[level].i_boost;
2227         }
2228
2229         /* Make sure that the requested I_boost is valid */
2230         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2231                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2232                 return;
2233         }
2234
2235         _skl_ddi_set_iboost(dev_priv, port, iboost);
2236
2237         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2238                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2239 }
2240
2241 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2242                                     int level, enum intel_output_type type)
2243 {
2244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2245         const struct bxt_ddi_buf_trans *ddi_translations;
2246         enum port port = encoder->port;
2247         int n_entries;
2248
2249         if (type == INTEL_OUTPUT_HDMI)
2250                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2251         else if (type == INTEL_OUTPUT_EDP)
2252                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2253         else
2254                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2255
2256         if (WARN_ON_ONCE(!ddi_translations))
2257                 return;
2258         if (WARN_ON_ONCE(level >= n_entries))
2259                 level = n_entries - 1;
2260
2261         bxt_ddi_phy_set_signal_level(dev_priv, port,
2262                                      ddi_translations[level].margin,
2263                                      ddi_translations[level].scale,
2264                                      ddi_translations[level].enable,
2265                                      ddi_translations[level].deemphasis);
2266 }
2267
2268 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2269 {
2270         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2271         enum port port = encoder->port;
2272         int n_entries;
2273
2274         if (IS_ICELAKE(dev_priv)) {
2275                 if (intel_port_is_combophy(dev_priv, port))
2276                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2277                                                 &n_entries);
2278                 else
2279                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2280         } else if (IS_CANNONLAKE(dev_priv)) {
2281                 if (encoder->type == INTEL_OUTPUT_EDP)
2282                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2283                 else
2284                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2285         } else if (IS_GEN9_LP(dev_priv)) {
2286                 if (encoder->type == INTEL_OUTPUT_EDP)
2287                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2288                 else
2289                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2290         } else {
2291                 if (encoder->type == INTEL_OUTPUT_EDP)
2292                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2293                 else
2294                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2295         }
2296
2297         if (WARN_ON(n_entries < 1))
2298                 n_entries = 1;
2299         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2300                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2301
2302         return index_to_dp_signal_levels[n_entries - 1] &
2303                 DP_TRAIN_VOLTAGE_SWING_MASK;
2304 }
2305
2306 /*
2307  * We assume that the full set of pre-emphasis values can be
2308  * used on all DDI platforms. Should that change we need to
2309  * rethink this code.
2310  */
2311 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2312 {
2313         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2314         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2315                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2316         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2317                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2318         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2319                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2320         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2321         default:
2322                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2323         }
2324 }
2325
2326 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2327                                    int level, enum intel_output_type type)
2328 {
2329         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2330         const struct cnl_ddi_buf_trans *ddi_translations;
2331         enum port port = encoder->port;
2332         int n_entries, ln;
2333         u32 val;
2334
2335         if (type == INTEL_OUTPUT_HDMI)
2336                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2337         else if (type == INTEL_OUTPUT_EDP)
2338                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2339         else
2340                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2341
2342         if (WARN_ON_ONCE(!ddi_translations))
2343                 return;
2344         if (WARN_ON_ONCE(level >= n_entries))
2345                 level = n_entries - 1;
2346
2347         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2348         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2349         val &= ~SCALING_MODE_SEL_MASK;
2350         val |= SCALING_MODE_SEL(2);
2351         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2352
2353         /* Program PORT_TX_DW2 */
2354         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2355         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2356                  RCOMP_SCALAR_MASK);
2357         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2358         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2359         /* Rcomp scalar is fixed as 0x98 for every table entry */
2360         val |= RCOMP_SCALAR(0x98);
2361         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2362
2363         /* Program PORT_TX_DW4 */
2364         /* We cannot write to GRP. It would overrite individual loadgen */
2365         for (ln = 0; ln < 4; ln++) {
2366                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2367                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2368                          CURSOR_COEFF_MASK);
2369                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2370                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2371                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2372                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2373         }
2374
2375         /* Program PORT_TX_DW5 */
2376         /* All DW5 values are fixed for every table entry */
2377         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2378         val &= ~RTERM_SELECT_MASK;
2379         val |= RTERM_SELECT(6);
2380         val |= TAP3_DISABLE;
2381         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2382
2383         /* Program PORT_TX_DW7 */
2384         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2385         val &= ~N_SCALAR_MASK;
2386         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2387         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2388 }
2389
2390 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2391                                     int level, enum intel_output_type type)
2392 {
2393         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2394         enum port port = encoder->port;
2395         int width, rate, ln;
2396         u32 val;
2397
2398         if (type == INTEL_OUTPUT_HDMI) {
2399                 width = 4;
2400                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2401         } else {
2402                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2403
2404                 width = intel_dp->lane_count;
2405                 rate = intel_dp->link_rate;
2406         }
2407
2408         /*
2409          * 1. If port type is eDP or DP,
2410          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2411          * else clear to 0b.
2412          */
2413         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2414         if (type != INTEL_OUTPUT_HDMI)
2415                 val |= COMMON_KEEPER_EN;
2416         else
2417                 val &= ~COMMON_KEEPER_EN;
2418         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2419
2420         /* 2. Program loadgen select */
2421         /*
2422          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2423          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2424          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2425          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2426          */
2427         for (ln = 0; ln <= 3; ln++) {
2428                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2429                 val &= ~LOADGEN_SELECT;
2430
2431                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2432                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2433                         val |= LOADGEN_SELECT;
2434                 }
2435                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2436         }
2437
2438         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2439         val = I915_READ(CNL_PORT_CL1CM_DW5);
2440         val |= SUS_CLOCK_CONFIG;
2441         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2442
2443         /* 4. Clear training enable to change swing values */
2444         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2445         val &= ~TX_TRAINING_EN;
2446         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2447
2448         /* 5. Program swing and de-emphasis */
2449         cnl_ddi_vswing_program(encoder, level, type);
2450
2451         /* 6. Set training enable to trigger update */
2452         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2453         val |= TX_TRAINING_EN;
2454         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2455 }
2456
2457 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2458                                          u32 level, enum port port, int type)
2459 {
2460         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2461         u32 n_entries, val;
2462         int ln;
2463
2464         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2465                                                    &n_entries);
2466         if (!ddi_translations)
2467                 return;
2468
2469         if (level >= n_entries) {
2470                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2471                 level = n_entries - 1;
2472         }
2473
2474         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2475         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2476         val &= ~RTERM_SELECT_MASK;
2477         val |= RTERM_SELECT(0x6);
2478         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2479
2480         /* Program PORT_TX_DW5 */
2481         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2482         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2483          * Clear DisableTap2 and DisableTap3 for all other Ports
2484          */
2485         if (type == INTEL_OUTPUT_DSI) {
2486                 val |= TAP2_DISABLE;
2487                 val |= TAP3_DISABLE;
2488         } else {
2489                 val &= ~TAP2_DISABLE;
2490                 val &= ~TAP3_DISABLE;
2491         }
2492         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2493
2494         /* Program PORT_TX_DW2 */
2495         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2496         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2497                  RCOMP_SCALAR_MASK);
2498         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2499         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2500         /* Program Rcomp scalar for every table entry */
2501         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2502         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2503
2504         /* Program PORT_TX_DW4 */
2505         /* We cannot write to GRP. It would overwrite individual loadgen. */
2506         for (ln = 0; ln <= 3; ln++) {
2507                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2508                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2509                          CURSOR_COEFF_MASK);
2510                 val |= ddi_translations[level].dw4_scaling;
2511                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2512         }
2513 }
2514
2515 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2516                                               u32 level,
2517                                               enum intel_output_type type)
2518 {
2519         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2520         enum port port = encoder->port;
2521         int width = 0;
2522         int rate = 0;
2523         u32 val;
2524         int ln = 0;
2525
2526         if (type == INTEL_OUTPUT_HDMI) {
2527                 width = 4;
2528                 /* Rate is always < than 6GHz for HDMI */
2529         } else {
2530                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2531
2532                 width = intel_dp->lane_count;
2533                 rate = intel_dp->link_rate;
2534         }
2535
2536         /*
2537          * 1. If port type is eDP or DP,
2538          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2539          * else clear to 0b.
2540          */
2541         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2542         if (type == INTEL_OUTPUT_HDMI)
2543                 val &= ~COMMON_KEEPER_EN;
2544         else
2545                 val |= COMMON_KEEPER_EN;
2546         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2547
2548         /* 2. Program loadgen select */
2549         /*
2550          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2551          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2552          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2553          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2554          */
2555         for (ln = 0; ln <= 3; ln++) {
2556                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2557                 val &= ~LOADGEN_SELECT;
2558
2559                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2560                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2561                         val |= LOADGEN_SELECT;
2562                 }
2563                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2564         }
2565
2566         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2567         val = I915_READ(ICL_PORT_CL_DW5(port));
2568         val |= SUS_CLOCK_CONFIG;
2569         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2570
2571         /* 4. Clear training enable to change swing values */
2572         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2573         val &= ~TX_TRAINING_EN;
2574         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2575
2576         /* 5. Program swing and de-emphasis */
2577         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2578
2579         /* 6. Set training enable to trigger update */
2580         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2581         val |= TX_TRAINING_EN;
2582         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2583 }
2584
2585 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2586                                            int link_clock,
2587                                            u32 level)
2588 {
2589         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2590         enum port port = encoder->port;
2591         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2592         u32 n_entries, val;
2593         int ln;
2594
2595         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2596         ddi_translations = icl_mg_phy_ddi_translations;
2597         /* The table does not have values for level 3 and level 9. */
2598         if (level >= n_entries || level == 3 || level == 9) {
2599                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2600                               level, n_entries - 2);
2601                 level = n_entries - 2;
2602         }
2603
2604         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2605         for (ln = 0; ln < 2; ln++) {
2606                 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2607                 val &= ~CRI_USE_FS32;
2608                 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2609
2610                 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2611                 val &= ~CRI_USE_FS32;
2612                 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2613         }
2614
2615         /* Program MG_TX_SWINGCTRL with values from vswing table */
2616         for (ln = 0; ln < 2; ln++) {
2617                 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2618                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2619                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2620                         ddi_translations[level].cri_txdeemph_override_17_12);
2621                 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2622
2623                 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2624                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2625                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2626                         ddi_translations[level].cri_txdeemph_override_17_12);
2627                 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2628         }
2629
2630         /* Program MG_TX_DRVCTRL with values from vswing table */
2631         for (ln = 0; ln < 2; ln++) {
2632                 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2633                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2634                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2635                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2636                         ddi_translations[level].cri_txdeemph_override_5_0) |
2637                         CRI_TXDEEMPH_OVERRIDE_11_6(
2638                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2639                         CRI_TXDEEMPH_OVERRIDE_EN;
2640                 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2641
2642                 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2643                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2644                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2645                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2646                         ddi_translations[level].cri_txdeemph_override_5_0) |
2647                         CRI_TXDEEMPH_OVERRIDE_11_6(
2648                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2649                         CRI_TXDEEMPH_OVERRIDE_EN;
2650                 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2651
2652                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2653         }
2654
2655         /*
2656          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2657          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2658          * values from table for which TX1 and TX2 enabled.
2659          */
2660         for (ln = 0; ln < 2; ln++) {
2661                 val = I915_READ(MG_CLKHUB(port, ln));
2662                 if (link_clock < 300000)
2663                         val |= CFG_LOW_RATE_LKREN_EN;
2664                 else
2665                         val &= ~CFG_LOW_RATE_LKREN_EN;
2666                 I915_WRITE(MG_CLKHUB(port, ln), val);
2667         }
2668
2669         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2670         for (ln = 0; ln < 2; ln++) {
2671                 val = I915_READ(MG_TX1_DCC(port, ln));
2672                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2673                 if (link_clock <= 500000) {
2674                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2675                 } else {
2676                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2677                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2678                 }
2679                 I915_WRITE(MG_TX1_DCC(port, ln), val);
2680
2681                 val = I915_READ(MG_TX2_DCC(port, ln));
2682                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2683                 if (link_clock <= 500000) {
2684                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2685                 } else {
2686                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2687                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2688                 }
2689                 I915_WRITE(MG_TX2_DCC(port, ln), val);
2690         }
2691
2692         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2693         for (ln = 0; ln < 2; ln++) {
2694                 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2695                 val |= CRI_CALCINIT;
2696                 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2697
2698                 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2699                 val |= CRI_CALCINIT;
2700                 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2701         }
2702 }
2703
2704 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2705                                     int link_clock,
2706                                     u32 level,
2707                                     enum intel_output_type type)
2708 {
2709         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2710         enum port port = encoder->port;
2711
2712         if (intel_port_is_combophy(dev_priv, port))
2713                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2714         else
2715                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2716 }
2717
2718 static uint32_t translate_signal_level(int signal_levels)
2719 {
2720         int i;
2721
2722         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2723                 if (index_to_dp_signal_levels[i] == signal_levels)
2724                         return i;
2725         }
2726
2727         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2728              signal_levels);
2729
2730         return 0;
2731 }
2732
2733 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2734 {
2735         uint8_t train_set = intel_dp->train_set[0];
2736         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2737                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2738
2739         return translate_signal_level(signal_levels);
2740 }
2741
2742 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2743 {
2744         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2745         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2746         struct intel_encoder *encoder = &dport->base;
2747         int level = intel_ddi_dp_level(intel_dp);
2748
2749         if (IS_ICELAKE(dev_priv))
2750                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2751                                         level, encoder->type);
2752         else if (IS_CANNONLAKE(dev_priv))
2753                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2754         else
2755                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2756
2757         return 0;
2758 }
2759
2760 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2761 {
2762         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2763         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2764         struct intel_encoder *encoder = &dport->base;
2765         int level = intel_ddi_dp_level(intel_dp);
2766
2767         if (IS_GEN9_BC(dev_priv))
2768                 skl_ddi_set_iboost(encoder, level, encoder->type);
2769
2770         return DDI_BUF_TRANS_SELECT(level);
2771 }
2772
2773 static inline
2774 uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2775                                    enum port port)
2776 {
2777         if (intel_port_is_combophy(dev_priv, port)) {
2778                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2779         } else if (intel_port_is_tc(dev_priv, port)) {
2780                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2781
2782                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2783         }
2784
2785         return 0;
2786 }
2787
2788 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2789                            struct intel_crtc_state *crtc_state,
2790                            struct drm_atomic_state *old_state)
2791 {
2792         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2793         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2794         struct drm_connector_state *conn_state;
2795         struct drm_connector *conn;
2796         int i;
2797
2798         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2799                 struct intel_encoder *encoder =
2800                         to_intel_encoder(conn_state->best_encoder);
2801                 enum port port;
2802                 uint32_t val;
2803
2804                 if (conn_state->crtc != crtc)
2805                         continue;
2806
2807                 port = encoder->port;
2808                 mutex_lock(&dev_priv->dpll_lock);
2809
2810                 val = I915_READ(DPCLKA_CFGCR0_ICL);
2811                 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2812
2813                 if (intel_port_is_combophy(dev_priv, port)) {
2814                         val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2815                         val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2816                         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2817                         POSTING_READ(DPCLKA_CFGCR0_ICL);
2818                 }
2819
2820                 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2821                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2822
2823                 mutex_unlock(&dev_priv->dpll_lock);
2824         }
2825 }
2826
2827 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2828                              struct intel_crtc_state *crtc_state,
2829                              struct drm_atomic_state *old_state)
2830 {
2831         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2832         struct drm_connector_state *old_conn_state;
2833         struct drm_connector *conn;
2834         int i;
2835
2836         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2837                 struct intel_encoder *encoder =
2838                         to_intel_encoder(old_conn_state->best_encoder);
2839                 enum port port;
2840
2841                 if (old_conn_state->crtc != crtc)
2842                         continue;
2843
2844                 port = encoder->port;
2845                 mutex_lock(&dev_priv->dpll_lock);
2846                 I915_WRITE(DPCLKA_CFGCR0_ICL,
2847                            I915_READ(DPCLKA_CFGCR0_ICL) |
2848                            icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2849                 mutex_unlock(&dev_priv->dpll_lock);
2850         }
2851 }
2852
2853 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2854 {
2855         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2856         u32 val;
2857         enum port port = encoder->port;
2858         bool clk_enabled;
2859
2860         /*
2861          * In case of DP MST, we sanitize the primary encoder only, not the
2862          * virtual ones.
2863          */
2864         if (encoder->type == INTEL_OUTPUT_DP_MST)
2865                 return;
2866
2867         val = I915_READ(DPCLKA_CFGCR0_ICL);
2868         clk_enabled = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, port));
2869
2870         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2871                 u8 pipe_mask;
2872                 bool is_mst;
2873
2874                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2875                 /*
2876                  * In the unlikely case that BIOS enables DP in MST mode, just
2877                  * warn since our MST HW readout is incomplete.
2878                  */
2879                 if (WARN_ON(is_mst))
2880                         return;
2881         }
2882
2883         if (clk_enabled == !!encoder->base.crtc)
2884                 return;
2885
2886         /*
2887          * Punt on the case now where clock is disabled, but the encoder is
2888          * enabled, something else is really broken then.
2889          */
2890         if (WARN_ON(!clk_enabled))
2891                 return;
2892
2893         DRM_NOTE("Port %c is disabled but it has a mapped PLL, unmap it\n",
2894                  port_name(port));
2895         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2896         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2897 }
2898
2899 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2900                                  const struct intel_crtc_state *crtc_state)
2901 {
2902         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2903         enum port port = encoder->port;
2904         uint32_t val;
2905         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2906
2907         if (WARN_ON(!pll))
2908                 return;
2909
2910         mutex_lock(&dev_priv->dpll_lock);
2911
2912         if (IS_ICELAKE(dev_priv)) {
2913                 if (!intel_port_is_combophy(dev_priv, port))
2914                         I915_WRITE(DDI_CLK_SEL(port),
2915                                    icl_pll_to_ddi_pll_sel(encoder, crtc_state));
2916         } else if (IS_CANNONLAKE(dev_priv)) {
2917                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2918                 val = I915_READ(DPCLKA_CFGCR0);
2919                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2920                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2921                 I915_WRITE(DPCLKA_CFGCR0, val);
2922
2923                 /*
2924                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2925                  * This step and the step before must be done with separate
2926                  * register writes.
2927                  */
2928                 val = I915_READ(DPCLKA_CFGCR0);
2929                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2930                 I915_WRITE(DPCLKA_CFGCR0, val);
2931         } else if (IS_GEN9_BC(dev_priv)) {
2932                 /* DDI -> PLL mapping  */
2933                 val = I915_READ(DPLL_CTRL2);
2934
2935                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2936                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2937                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2938                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2939
2940                 I915_WRITE(DPLL_CTRL2, val);
2941
2942         } else if (INTEL_GEN(dev_priv) < 9) {
2943                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2944         }
2945
2946         mutex_unlock(&dev_priv->dpll_lock);
2947 }
2948
2949 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2950 {
2951         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2952         enum port port = encoder->port;
2953
2954         if (IS_ICELAKE(dev_priv)) {
2955                 if (!intel_port_is_combophy(dev_priv, port))
2956                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2957         } else if (IS_CANNONLAKE(dev_priv)) {
2958                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2959                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2960         } else if (IS_GEN9_BC(dev_priv)) {
2961                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2962                            DPLL_CTRL2_DDI_CLK_OFF(port));
2963         } else if (INTEL_GEN(dev_priv) < 9) {
2964                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2965         }
2966 }
2967
2968 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2969 {
2970         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2971         enum port port = dig_port->base.port;
2972         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2973         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2974         u32 val;
2975         int i;
2976
2977         if (tc_port == PORT_TC_NONE)
2978                 return;
2979
2980         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2981                 val = I915_READ(mg_regs[i]);
2982                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2983                        MG_DP_MODE_CFG_TRPWR_GATING |
2984                        MG_DP_MODE_CFG_CLNPWR_GATING |
2985                        MG_DP_MODE_CFG_DIGPWR_GATING |
2986                        MG_DP_MODE_CFG_GAONPWR_GATING;
2987                 I915_WRITE(mg_regs[i], val);
2988         }
2989
2990         val = I915_READ(MG_MISC_SUS0(tc_port));
2991         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2992                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2993                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2994                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2995                MG_MISC_SUS0_CFG_TRPWR_GATING |
2996                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2997                MG_MISC_SUS0_CFG_DGPWR_GATING;
2998         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2999 }
3000
3001 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
3002 {
3003         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3004         enum port port = dig_port->base.port;
3005         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3006         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
3007         u32 val;
3008         int i;
3009
3010         if (tc_port == PORT_TC_NONE)
3011                 return;
3012
3013         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
3014                 val = I915_READ(mg_regs[i]);
3015                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
3016                          MG_DP_MODE_CFG_TRPWR_GATING |
3017                          MG_DP_MODE_CFG_CLNPWR_GATING |
3018                          MG_DP_MODE_CFG_DIGPWR_GATING |
3019                          MG_DP_MODE_CFG_GAONPWR_GATING);
3020                 I915_WRITE(mg_regs[i], val);
3021         }
3022
3023         val = I915_READ(MG_MISC_SUS0(tc_port));
3024         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
3025                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
3026                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
3027                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
3028                  MG_MISC_SUS0_CFG_TRPWR_GATING |
3029                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
3030                  MG_MISC_SUS0_CFG_DGPWR_GATING);
3031         I915_WRITE(MG_MISC_SUS0(tc_port), val);
3032 }
3033
3034 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3035 {
3036         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3037         enum port port = intel_dig_port->base.port;
3038         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3039         u32 ln0, ln1, lane_info;
3040
3041         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
3042                 return;
3043
3044         ln0 = I915_READ(MG_DP_MODE(port, 0));
3045         ln1 = I915_READ(MG_DP_MODE(port, 1));
3046
3047         switch (intel_dig_port->tc_type) {
3048         case TC_PORT_TYPEC:
3049                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3050                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3051
3052                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3053                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3054                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3055
3056                 switch (lane_info) {
3057                 case 0x1:
3058                 case 0x4:
3059                         break;
3060                 case 0x2:
3061                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3062                         break;
3063                 case 0x3:
3064                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3065                                MG_DP_MODE_CFG_DP_X2_MODE;
3066                         break;
3067                 case 0x8:
3068                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3069                         break;
3070                 case 0xC:
3071                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3072                                MG_DP_MODE_CFG_DP_X2_MODE;
3073                         break;
3074                 case 0xF:
3075                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3076                                MG_DP_MODE_CFG_DP_X2_MODE;
3077                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3078                                MG_DP_MODE_CFG_DP_X2_MODE;
3079                         break;
3080                 default:
3081                         MISSING_CASE(lane_info);
3082                 }
3083                 break;
3084
3085         case TC_PORT_LEGACY:
3086                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3087                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3088                 break;
3089
3090         default:
3091                 MISSING_CASE(intel_dig_port->tc_type);
3092                 return;
3093         }
3094
3095         I915_WRITE(MG_DP_MODE(port, 0), ln0);
3096         I915_WRITE(MG_DP_MODE(port, 1), ln1);
3097 }
3098
3099 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3100                                     const struct intel_crtc_state *crtc_state,
3101                                     const struct drm_connector_state *conn_state)
3102 {
3103         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3104         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3105         enum port port = encoder->port;
3106         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3107         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3108         int level = intel_ddi_dp_level(intel_dp);
3109
3110         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3111
3112         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3113                                  crtc_state->lane_count, is_mst);
3114
3115         intel_edp_panel_on(intel_dp);
3116
3117         intel_ddi_clk_select(encoder, crtc_state);
3118
3119         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3120
3121         icl_program_mg_dp_mode(dig_port);
3122         icl_disable_phy_clock_gating(dig_port);
3123
3124         if (IS_ICELAKE(dev_priv))
3125                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3126                                         level, encoder->type);
3127         else if (IS_CANNONLAKE(dev_priv))
3128                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3129         else if (IS_GEN9_LP(dev_priv))
3130                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3131         else
3132                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3133
3134         intel_ddi_init_dp_buf_reg(encoder);
3135         if (!is_mst)
3136                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3137         intel_dp_start_link_train(intel_dp);
3138         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3139                 intel_dp_stop_link_train(intel_dp);
3140
3141         icl_enable_phy_clock_gating(dig_port);
3142
3143         if (!is_mst)
3144                 intel_ddi_enable_pipe_clock(crtc_state);
3145 }
3146
3147 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3148                                       const struct intel_crtc_state *crtc_state,
3149                                       const struct drm_connector_state *conn_state)
3150 {
3151         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3152         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3154         enum port port = encoder->port;
3155         int level = intel_ddi_hdmi_level(dev_priv, port);
3156         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3157
3158         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3159         intel_ddi_clk_select(encoder, crtc_state);
3160
3161         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3162
3163         icl_program_mg_dp_mode(dig_port);
3164         icl_disable_phy_clock_gating(dig_port);
3165
3166         if (IS_ICELAKE(dev_priv))
3167                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3168                                         level, INTEL_OUTPUT_HDMI);
3169         else if (IS_CANNONLAKE(dev_priv))
3170                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3171         else if (IS_GEN9_LP(dev_priv))
3172                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3173         else
3174                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3175
3176         icl_enable_phy_clock_gating(dig_port);
3177
3178         if (IS_GEN9_BC(dev_priv))
3179                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3180
3181         intel_ddi_enable_pipe_clock(crtc_state);
3182
3183         intel_dig_port->set_infoframes(encoder,
3184                                        crtc_state->has_infoframe,
3185                                        crtc_state, conn_state);
3186 }
3187
3188 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3189                                  const struct intel_crtc_state *crtc_state,
3190                                  const struct drm_connector_state *conn_state)
3191 {
3192         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3193         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3194         enum pipe pipe = crtc->pipe;
3195
3196         /*
3197          * When called from DP MST code:
3198          * - conn_state will be NULL
3199          * - encoder will be the main encoder (ie. mst->primary)
3200          * - the main connector associated with this port
3201          *   won't be active or linked to a crtc
3202          * - crtc_state will be the state of the first stream to
3203          *   be activated on this port, and it may not be the same
3204          *   stream that will be deactivated last, but each stream
3205          *   should have a state that is identical when it comes to
3206          *   the DP link parameteres
3207          */
3208
3209         WARN_ON(crtc_state->has_pch_encoder);
3210
3211         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3212
3213         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3214                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3215         } else {
3216                 struct intel_lspcon *lspcon =
3217                                 enc_to_intel_lspcon(&encoder->base);
3218
3219                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3220                 if (lspcon->active) {
3221                         struct intel_digital_port *dig_port =
3222                                         enc_to_dig_port(&encoder->base);
3223
3224                         dig_port->set_infoframes(encoder,
3225                                                  crtc_state->has_infoframe,
3226                                                  crtc_state, conn_state);
3227                 }
3228         }
3229 }
3230
3231 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
3232 {
3233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3234         enum port port = encoder->port;
3235         bool wait = false;
3236         u32 val;
3237
3238         val = I915_READ(DDI_BUF_CTL(port));
3239         if (val & DDI_BUF_CTL_ENABLE) {
3240                 val &= ~DDI_BUF_CTL_ENABLE;
3241                 I915_WRITE(DDI_BUF_CTL(port), val);
3242                 wait = true;
3243         }
3244
3245         val = I915_READ(DP_TP_CTL(port));
3246         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3247         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3248         I915_WRITE(DP_TP_CTL(port), val);
3249
3250         if (wait)
3251                 intel_wait_ddi_buf_idle(dev_priv, port);
3252 }
3253
3254 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3255                                       const struct intel_crtc_state *old_crtc_state,
3256                                       const struct drm_connector_state *old_conn_state)
3257 {
3258         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3259         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3260         struct intel_dp *intel_dp = &dig_port->dp;
3261         bool is_mst = intel_crtc_has_type(old_crtc_state,
3262                                           INTEL_OUTPUT_DP_MST);
3263
3264         if (!is_mst) {
3265                 intel_ddi_disable_pipe_clock(old_crtc_state);
3266                 /*
3267                  * Power down sink before disabling the port, otherwise we end
3268                  * up getting interrupts from the sink on detecting link loss.
3269                  */
3270                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3271         }
3272
3273         intel_disable_ddi_buf(encoder);
3274
3275         intel_edp_panel_vdd_on(intel_dp);
3276         intel_edp_panel_off(intel_dp);
3277
3278         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3279
3280         intel_ddi_clk_disable(encoder);
3281 }
3282
3283 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3284                                         const struct intel_crtc_state *old_crtc_state,
3285                                         const struct drm_connector_state *old_conn_state)
3286 {
3287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3288         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3289         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3290
3291         dig_port->set_infoframes(encoder, false,
3292                                  old_crtc_state, old_conn_state);
3293
3294         intel_ddi_disable_pipe_clock(old_crtc_state);
3295
3296         intel_disable_ddi_buf(encoder);
3297
3298         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3299
3300         intel_ddi_clk_disable(encoder);
3301
3302         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3303 }
3304
3305 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3306                                    const struct intel_crtc_state *old_crtc_state,
3307                                    const struct drm_connector_state *old_conn_state)
3308 {
3309         /*
3310          * When called from DP MST code:
3311          * - old_conn_state will be NULL
3312          * - encoder will be the main encoder (ie. mst->primary)
3313          * - the main connector associated with this port
3314          *   won't be active or linked to a crtc
3315          * - old_crtc_state will be the state of the last stream to
3316          *   be deactivated on this port, and it may not be the same
3317          *   stream that was activated last, but each stream
3318          *   should have a state that is identical when it comes to
3319          *   the DP link parameteres
3320          */
3321
3322         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3323                 intel_ddi_post_disable_hdmi(encoder,
3324                                             old_crtc_state, old_conn_state);
3325         else
3326                 intel_ddi_post_disable_dp(encoder,
3327                                           old_crtc_state, old_conn_state);
3328 }
3329
3330 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3331                                 const struct intel_crtc_state *old_crtc_state,
3332                                 const struct drm_connector_state *old_conn_state)
3333 {
3334         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3335         uint32_t val;
3336
3337         /*
3338          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3339          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3340          * step 13 is the correct place for it. Step 18 is where it was
3341          * originally before the BUN.
3342          */
3343         val = I915_READ(FDI_RX_CTL(PIPE_A));
3344         val &= ~FDI_RX_ENABLE;
3345         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3346
3347         intel_disable_ddi_buf(encoder);
3348         intel_ddi_clk_disable(encoder);
3349
3350         val = I915_READ(FDI_RX_MISC(PIPE_A));
3351         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3352         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3353         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3354
3355         val = I915_READ(FDI_RX_CTL(PIPE_A));
3356         val &= ~FDI_PCDCLK;
3357         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3358
3359         val = I915_READ(FDI_RX_CTL(PIPE_A));
3360         val &= ~FDI_RX_PLL_ENABLE;
3361         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3362 }
3363
3364 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3365                                 const struct intel_crtc_state *crtc_state,
3366                                 const struct drm_connector_state *conn_state)
3367 {
3368         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3369         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3370         enum port port = encoder->port;
3371
3372         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3373                 intel_dp_stop_link_train(intel_dp);
3374
3375         intel_edp_backlight_on(crtc_state, conn_state);
3376         intel_psr_enable(intel_dp, crtc_state);
3377         intel_edp_drrs_enable(intel_dp, crtc_state);
3378
3379         if (crtc_state->has_audio)
3380                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3381 }
3382
3383 static i915_reg_t
3384 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3385                                enum port port)
3386 {
3387         static const i915_reg_t regs[] = {
3388                 [PORT_A] = CHICKEN_TRANS_EDP,
3389                 [PORT_B] = CHICKEN_TRANS_A,
3390                 [PORT_C] = CHICKEN_TRANS_B,
3391                 [PORT_D] = CHICKEN_TRANS_C,
3392                 [PORT_E] = CHICKEN_TRANS_A,
3393         };
3394
3395         WARN_ON(INTEL_GEN(dev_priv) < 9);
3396
3397         if (WARN_ON(port < PORT_A || port > PORT_E))
3398                 port = PORT_A;
3399
3400         return regs[port];
3401 }
3402
3403 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3404                                   const struct intel_crtc_state *crtc_state,
3405                                   const struct drm_connector_state *conn_state)
3406 {
3407         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3408         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3409         struct drm_connector *connector = conn_state->connector;
3410         enum port port = encoder->port;
3411
3412         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3413                                                crtc_state->hdmi_high_tmds_clock_ratio,
3414                                                crtc_state->hdmi_scrambling))
3415                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3416                           connector->base.id, connector->name);
3417
3418         /* Display WA #1143: skl,kbl,cfl */
3419         if (IS_GEN9_BC(dev_priv)) {
3420                 /*
3421                  * For some reason these chicken bits have been
3422                  * stuffed into a transcoder register, event though
3423                  * the bits affect a specific DDI port rather than
3424                  * a specific transcoder.
3425                  */
3426                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3427                 u32 val;
3428
3429                 val = I915_READ(reg);
3430
3431                 if (port == PORT_E)
3432                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3433                                 DDIE_TRAINING_OVERRIDE_VALUE;
3434                 else
3435                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3436                                 DDI_TRAINING_OVERRIDE_VALUE;
3437
3438                 I915_WRITE(reg, val);
3439                 POSTING_READ(reg);
3440
3441                 udelay(1);
3442
3443                 if (port == PORT_E)
3444                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3445                                  DDIE_TRAINING_OVERRIDE_VALUE);
3446                 else
3447                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3448                                  DDI_TRAINING_OVERRIDE_VALUE);
3449
3450                 I915_WRITE(reg, val);
3451         }
3452
3453         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3454          * are ignored so nothing special needs to be done besides
3455          * enabling the port.
3456          */
3457         I915_WRITE(DDI_BUF_CTL(port),
3458                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3459
3460         if (crtc_state->has_audio)
3461                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3462 }
3463
3464 static void intel_enable_ddi(struct intel_encoder *encoder,
3465                              const struct intel_crtc_state *crtc_state,
3466                              const struct drm_connector_state *conn_state)
3467 {
3468         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3469                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3470         else
3471                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3472
3473         /* Enable hdcp if it's desired */
3474         if (conn_state->content_protection ==
3475             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3476                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3477 }
3478
3479 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3480                                  const struct intel_crtc_state *old_crtc_state,
3481                                  const struct drm_connector_state *old_conn_state)
3482 {
3483         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3484
3485         intel_dp->link_trained = false;
3486
3487         if (old_crtc_state->has_audio)
3488                 intel_audio_codec_disable(encoder,
3489                                           old_crtc_state, old_conn_state);
3490
3491         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3492         intel_psr_disable(intel_dp, old_crtc_state);
3493         intel_edp_backlight_off(old_conn_state);
3494 }
3495
3496 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3497                                    const struct intel_crtc_state *old_crtc_state,
3498                                    const struct drm_connector_state *old_conn_state)
3499 {
3500         struct drm_connector *connector = old_conn_state->connector;
3501
3502         if (old_crtc_state->has_audio)
3503                 intel_audio_codec_disable(encoder,
3504                                           old_crtc_state, old_conn_state);
3505
3506         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3507                                                false, false))
3508                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3509                               connector->base.id, connector->name);
3510 }
3511
3512 static void intel_disable_ddi(struct intel_encoder *encoder,
3513                               const struct intel_crtc_state *old_crtc_state,
3514                               const struct drm_connector_state *old_conn_state)
3515 {
3516         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3517
3518         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3519                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3520         else
3521                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3522 }
3523
3524 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3525                                          const struct intel_crtc_state *pipe_config,
3526                                          enum port port)
3527 {
3528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3529         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3530         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3531         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3532         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3533
3534         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3535         switch (pipe_config->lane_count) {
3536         case 1:
3537                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3538                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3539                 break;
3540         case 2:
3541                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3542                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3543                 break;
3544         case 4:
3545                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3546                 break;
3547         default:
3548                 MISSING_CASE(pipe_config->lane_count);
3549         }
3550         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3551 }
3552
3553 static void
3554 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3555                          const struct intel_crtc_state *crtc_state,
3556                          const struct drm_connector_state *conn_state)
3557 {
3558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3559         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3560         enum port port = encoder->port;
3561
3562         if (intel_crtc_has_dp_encoder(crtc_state) ||
3563             intel_port_is_tc(dev_priv, encoder->port))
3564                 intel_display_power_get(dev_priv,
3565                                         intel_ddi_main_link_aux_domain(dig_port));
3566
3567         if (IS_GEN9_LP(dev_priv))
3568                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3569                                                 crtc_state->lane_lat_optim_mask);
3570
3571         /*
3572          * Program the lane count for static/dynamic connections on Type-C ports.
3573          * Skip this step for TBT.
3574          */
3575         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3576             dig_port->tc_type == TC_PORT_TBT)
3577                 return;
3578
3579         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3580 }
3581
3582 static void
3583 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3584                            const struct intel_crtc_state *crtc_state,
3585                            const struct drm_connector_state *conn_state)
3586 {
3587         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3588         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3589
3590         if (intel_crtc_has_dp_encoder(crtc_state) ||
3591             intel_port_is_tc(dev_priv, encoder->port))
3592                 intel_display_power_put(dev_priv,
3593                                         intel_ddi_main_link_aux_domain(dig_port));
3594 }
3595
3596 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3597 {
3598         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3599         struct drm_i915_private *dev_priv =
3600                 to_i915(intel_dig_port->base.base.dev);
3601         enum port port = intel_dig_port->base.port;
3602         uint32_t val;
3603         bool wait = false;
3604
3605         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3606                 val = I915_READ(DDI_BUF_CTL(port));
3607                 if (val & DDI_BUF_CTL_ENABLE) {
3608                         val &= ~DDI_BUF_CTL_ENABLE;
3609                         I915_WRITE(DDI_BUF_CTL(port), val);
3610                         wait = true;
3611                 }
3612
3613                 val = I915_READ(DP_TP_CTL(port));
3614                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3615                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3616                 I915_WRITE(DP_TP_CTL(port), val);
3617                 POSTING_READ(DP_TP_CTL(port));
3618
3619                 if (wait)
3620                         intel_wait_ddi_buf_idle(dev_priv, port);
3621         }
3622
3623         val = DP_TP_CTL_ENABLE |
3624               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3625         if (intel_dp->link_mst)
3626                 val |= DP_TP_CTL_MODE_MST;
3627         else {
3628                 val |= DP_TP_CTL_MODE_SST;
3629                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3630                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3631         }
3632         I915_WRITE(DP_TP_CTL(port), val);
3633         POSTING_READ(DP_TP_CTL(port));
3634
3635         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3636         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3637         POSTING_READ(DDI_BUF_CTL(port));
3638
3639         udelay(600);
3640 }
3641
3642 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3643                                        enum transcoder cpu_transcoder)
3644 {
3645         if (cpu_transcoder == TRANSCODER_EDP)
3646                 return false;
3647
3648         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3649                 return false;
3650
3651         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3652                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3653 }
3654
3655 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3656                                          struct intel_crtc_state *crtc_state)
3657 {
3658         if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3659                 crtc_state->min_voltage_level = 1;
3660         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3661                 crtc_state->min_voltage_level = 2;
3662 }
3663
3664 void intel_ddi_get_config(struct intel_encoder *encoder,
3665                           struct intel_crtc_state *pipe_config)
3666 {
3667         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3668         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3669         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3670         struct intel_digital_port *intel_dig_port;
3671         u32 temp, flags = 0;
3672
3673         /* XXX: DSI transcoder paranoia */
3674         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3675                 return;
3676
3677         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3678         if (temp & TRANS_DDI_PHSYNC)
3679                 flags |= DRM_MODE_FLAG_PHSYNC;
3680         else
3681                 flags |= DRM_MODE_FLAG_NHSYNC;
3682         if (temp & TRANS_DDI_PVSYNC)
3683                 flags |= DRM_MODE_FLAG_PVSYNC;
3684         else
3685                 flags |= DRM_MODE_FLAG_NVSYNC;
3686
3687         pipe_config->base.adjusted_mode.flags |= flags;
3688
3689         switch (temp & TRANS_DDI_BPC_MASK) {
3690         case TRANS_DDI_BPC_6:
3691                 pipe_config->pipe_bpp = 18;
3692                 break;
3693         case TRANS_DDI_BPC_8:
3694                 pipe_config->pipe_bpp = 24;
3695                 break;
3696         case TRANS_DDI_BPC_10:
3697                 pipe_config->pipe_bpp = 30;
3698                 break;
3699         case TRANS_DDI_BPC_12:
3700                 pipe_config->pipe_bpp = 36;
3701                 break;
3702         default:
3703                 break;
3704         }
3705
3706         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3707         case TRANS_DDI_MODE_SELECT_HDMI:
3708                 pipe_config->has_hdmi_sink = true;
3709                 intel_dig_port = enc_to_dig_port(&encoder->base);
3710
3711                 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
3712                         pipe_config->has_infoframe = true;
3713
3714                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3715                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3716                         pipe_config->hdmi_scrambling = true;
3717                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3718                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3719                 /* fall through */
3720         case TRANS_DDI_MODE_SELECT_DVI:
3721                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3722                 pipe_config->lane_count = 4;
3723                 break;
3724         case TRANS_DDI_MODE_SELECT_FDI:
3725                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3726                 break;
3727         case TRANS_DDI_MODE_SELECT_DP_SST:
3728                 if (encoder->type == INTEL_OUTPUT_EDP)
3729                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3730                 else
3731                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3732                 pipe_config->lane_count =
3733                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3734                 intel_dp_get_m_n(intel_crtc, pipe_config);
3735                 break;
3736         case TRANS_DDI_MODE_SELECT_DP_MST:
3737                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3738                 pipe_config->lane_count =
3739                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3740                 intel_dp_get_m_n(intel_crtc, pipe_config);
3741                 break;
3742         default:
3743                 break;
3744         }
3745
3746         pipe_config->has_audio =
3747                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3748
3749         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3750             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3751                 /*
3752                  * This is a big fat ugly hack.
3753                  *
3754                  * Some machines in UEFI boot mode provide us a VBT that has 18
3755                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3756                  * unknown we fail to light up. Yet the same BIOS boots up with
3757                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3758                  * max, not what it tells us to use.
3759                  *
3760                  * Note: This will still be broken if the eDP panel is not lit
3761                  * up by the BIOS, and thus we can't get the mode at module
3762                  * load.
3763                  */
3764                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3765                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3766                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3767         }
3768
3769         intel_ddi_clock_get(encoder, pipe_config);
3770
3771         if (IS_GEN9_LP(dev_priv))
3772                 pipe_config->lane_lat_optim_mask =
3773                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3774
3775         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3776 }
3777
3778 static enum intel_output_type
3779 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3780                               struct intel_crtc_state *crtc_state,
3781                               struct drm_connector_state *conn_state)
3782 {
3783         switch (conn_state->connector->connector_type) {
3784         case DRM_MODE_CONNECTOR_HDMIA:
3785                 return INTEL_OUTPUT_HDMI;
3786         case DRM_MODE_CONNECTOR_eDP:
3787                 return INTEL_OUTPUT_EDP;
3788         case DRM_MODE_CONNECTOR_DisplayPort:
3789                 return INTEL_OUTPUT_DP;
3790         default:
3791                 MISSING_CASE(conn_state->connector->connector_type);
3792                 return INTEL_OUTPUT_UNUSED;
3793         }
3794 }
3795
3796 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3797                                      struct intel_crtc_state *pipe_config,
3798                                      struct drm_connector_state *conn_state)
3799 {
3800         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3801         enum port port = encoder->port;
3802         int ret;
3803
3804         if (port == PORT_A)
3805                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3806
3807         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3808                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3809         else
3810                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3811
3812         if (IS_GEN9_LP(dev_priv) && ret)
3813                 pipe_config->lane_lat_optim_mask =
3814                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3815
3816         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3817
3818         return ret;
3819
3820 }
3821
3822 static const struct drm_encoder_funcs intel_ddi_funcs = {
3823         .reset = intel_dp_encoder_reset,
3824         .destroy = intel_dp_encoder_destroy,
3825 };
3826
3827 static struct intel_connector *
3828 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3829 {
3830         struct intel_connector *connector;
3831         enum port port = intel_dig_port->base.port;
3832
3833         connector = intel_connector_alloc();
3834         if (!connector)
3835                 return NULL;
3836
3837         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3838         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3839                 kfree(connector);
3840                 return NULL;
3841         }
3842
3843         return connector;
3844 }
3845
3846 static int modeset_pipe(struct drm_crtc *crtc,
3847                         struct drm_modeset_acquire_ctx *ctx)
3848 {
3849         struct drm_atomic_state *state;
3850         struct drm_crtc_state *crtc_state;
3851         int ret;
3852
3853         state = drm_atomic_state_alloc(crtc->dev);
3854         if (!state)
3855                 return -ENOMEM;
3856
3857         state->acquire_ctx = ctx;
3858
3859         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3860         if (IS_ERR(crtc_state)) {
3861                 ret = PTR_ERR(crtc_state);
3862                 goto out;
3863         }
3864
3865         crtc_state->mode_changed = true;
3866
3867         ret = drm_atomic_add_affected_connectors(state, crtc);
3868         if (ret)
3869                 goto out;
3870
3871         ret = drm_atomic_add_affected_planes(state, crtc);
3872         if (ret)
3873                 goto out;
3874
3875         ret = drm_atomic_commit(state);
3876         if (ret)
3877                 goto out;
3878
3879         return 0;
3880
3881  out:
3882         drm_atomic_state_put(state);
3883
3884         return ret;
3885 }
3886
3887 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3888                                  struct drm_modeset_acquire_ctx *ctx)
3889 {
3890         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3891         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3892         struct intel_connector *connector = hdmi->attached_connector;
3893         struct i2c_adapter *adapter =
3894                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3895         struct drm_connector_state *conn_state;
3896         struct intel_crtc_state *crtc_state;
3897         struct intel_crtc *crtc;
3898         u8 config;
3899         int ret;
3900
3901         if (!connector || connector->base.status != connector_status_connected)
3902                 return 0;
3903
3904         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3905                                ctx);
3906         if (ret)
3907                 return ret;
3908
3909         conn_state = connector->base.state;
3910
3911         crtc = to_intel_crtc(conn_state->crtc);
3912         if (!crtc)
3913                 return 0;
3914
3915         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3916         if (ret)
3917                 return ret;
3918
3919         crtc_state = to_intel_crtc_state(crtc->base.state);
3920
3921         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3922
3923         if (!crtc_state->base.active)
3924                 return 0;
3925
3926         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3927             !crtc_state->hdmi_scrambling)
3928                 return 0;
3929
3930         if (conn_state->commit &&
3931             !try_wait_for_completion(&conn_state->commit->hw_done))
3932                 return 0;
3933
3934         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3935         if (ret < 0) {
3936                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3937                 return 0;
3938         }
3939
3940         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3941             crtc_state->hdmi_high_tmds_clock_ratio &&
3942             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3943             crtc_state->hdmi_scrambling)
3944                 return 0;
3945
3946         /*
3947          * HDMI 2.0 says that one should not send scrambled data
3948          * prior to configuring the sink scrambling, and that
3949          * TMDS clock/data transmission should be suspended when
3950          * changing the TMDS clock rate in the sink. So let's
3951          * just do a full modeset here, even though some sinks
3952          * would be perfectly happy if were to just reconfigure
3953          * the SCDC settings on the fly.
3954          */
3955         return modeset_pipe(&crtc->base, ctx);
3956 }
3957
3958 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3959                               struct intel_connector *connector)
3960 {
3961         struct drm_modeset_acquire_ctx ctx;
3962         bool changed;
3963         int ret;
3964
3965         changed = intel_encoder_hotplug(encoder, connector);
3966
3967         drm_modeset_acquire_init(&ctx, 0);
3968
3969         for (;;) {
3970                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3971                         ret = intel_hdmi_reset_link(encoder, &ctx);
3972                 else
3973                         ret = intel_dp_retrain_link(encoder, &ctx);
3974
3975                 if (ret == -EDEADLK) {
3976                         drm_modeset_backoff(&ctx);
3977                         continue;
3978                 }
3979
3980                 break;
3981         }
3982
3983         drm_modeset_drop_locks(&ctx);
3984         drm_modeset_acquire_fini(&ctx);
3985         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3986
3987         return changed;
3988 }
3989
3990 static struct intel_connector *
3991 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3992 {
3993         struct intel_connector *connector;
3994         enum port port = intel_dig_port->base.port;
3995
3996         connector = intel_connector_alloc();
3997         if (!connector)
3998                 return NULL;
3999
4000         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4001         intel_hdmi_init_connector(intel_dig_port, connector);
4002
4003         return connector;
4004 }
4005
4006 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4007 {
4008         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4009
4010         if (dport->base.port != PORT_A)
4011                 return false;
4012
4013         if (dport->saved_port_bits & DDI_A_4_LANES)
4014                 return false;
4015
4016         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4017          *                     supported configuration
4018          */
4019         if (IS_GEN9_LP(dev_priv))
4020                 return true;
4021
4022         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4023          *             one who does also have a full A/E split called
4024          *             DDI_F what makes DDI_E useless. However for this
4025          *             case let's trust VBT info.
4026          */
4027         if (IS_CANNONLAKE(dev_priv) &&
4028             !intel_bios_is_port_present(dev_priv, PORT_E))
4029                 return true;
4030
4031         return false;
4032 }
4033
4034 static int
4035 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4036 {
4037         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4038         enum port port = intel_dport->base.port;
4039         int max_lanes = 4;
4040
4041         if (INTEL_GEN(dev_priv) >= 11)
4042                 return max_lanes;
4043
4044         if (port == PORT_A || port == PORT_E) {
4045                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4046                         max_lanes = port == PORT_A ? 4 : 0;
4047                 else
4048                         /* Both A and E share 2 lanes */
4049                         max_lanes = 2;
4050         }
4051
4052         /*
4053          * Some BIOS might fail to set this bit on port A if eDP
4054          * wasn't lit up at boot.  Force this bit set when needed
4055          * so we use the proper lane count for our calculations.
4056          */
4057         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4058                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4059                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4060                 max_lanes = 4;
4061         }
4062
4063         return max_lanes;
4064 }
4065
4066 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4067 {
4068         struct intel_digital_port *intel_dig_port;
4069         struct intel_encoder *intel_encoder;
4070         struct drm_encoder *encoder;
4071         bool init_hdmi, init_dp, init_lspcon = false;
4072         enum pipe pipe;
4073
4074
4075         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
4076                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
4077         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
4078
4079         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4080                 /*
4081                  * Lspcon device needs to be driven with DP connector
4082                  * with special detection sequence. So make sure DP
4083                  * is initialized before lspcon.
4084                  */
4085                 init_dp = true;
4086                 init_lspcon = true;
4087                 init_hdmi = false;
4088                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4089         }
4090
4091         if (!init_dp && !init_hdmi) {
4092                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4093                               port_name(port));
4094                 return;
4095         }
4096
4097         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4098         if (!intel_dig_port)
4099                 return;
4100
4101         intel_encoder = &intel_dig_port->base;
4102         encoder = &intel_encoder->base;
4103
4104         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4105                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4106
4107         intel_encoder->hotplug = intel_ddi_hotplug;
4108         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4109         intel_encoder->compute_config = intel_ddi_compute_config;
4110         intel_encoder->enable = intel_enable_ddi;
4111         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4112         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4113         intel_encoder->pre_enable = intel_ddi_pre_enable;
4114         intel_encoder->disable = intel_disable_ddi;
4115         intel_encoder->post_disable = intel_ddi_post_disable;
4116         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4117         intel_encoder->get_config = intel_ddi_get_config;
4118         intel_encoder->suspend = intel_dp_encoder_suspend;
4119         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4120         intel_encoder->type = INTEL_OUTPUT_DDI;
4121         intel_encoder->power_domain = intel_port_to_power_domain(port);
4122         intel_encoder->port = port;
4123         intel_encoder->cloneable = 0;
4124         for_each_pipe(dev_priv, pipe)
4125                 intel_encoder->crtc_mask |= BIT(pipe);
4126
4127         if (INTEL_GEN(dev_priv) >= 11)
4128                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4129                         DDI_BUF_PORT_REVERSAL;
4130         else
4131                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4132                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4133         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4134         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4135         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4136
4137         switch (port) {
4138         case PORT_A:
4139                 intel_dig_port->ddi_io_power_domain =
4140                         POWER_DOMAIN_PORT_DDI_A_IO;
4141                 break;
4142         case PORT_B:
4143                 intel_dig_port->ddi_io_power_domain =
4144                         POWER_DOMAIN_PORT_DDI_B_IO;
4145                 break;
4146         case PORT_C:
4147                 intel_dig_port->ddi_io_power_domain =
4148                         POWER_DOMAIN_PORT_DDI_C_IO;
4149                 break;
4150         case PORT_D:
4151                 intel_dig_port->ddi_io_power_domain =
4152                         POWER_DOMAIN_PORT_DDI_D_IO;
4153                 break;
4154         case PORT_E:
4155                 intel_dig_port->ddi_io_power_domain =
4156                         POWER_DOMAIN_PORT_DDI_E_IO;
4157                 break;
4158         case PORT_F:
4159                 intel_dig_port->ddi_io_power_domain =
4160                         POWER_DOMAIN_PORT_DDI_F_IO;
4161                 break;
4162         default:
4163                 MISSING_CASE(port);
4164         }
4165
4166         if (init_dp) {
4167                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4168                         goto err;
4169
4170                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4171         }
4172
4173         /* In theory we don't need the encoder->type check, but leave it just in
4174          * case we have some really bad VBTs... */
4175         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4176                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4177                         goto err;
4178         }
4179
4180         if (init_lspcon) {
4181                 if (lspcon_init(intel_dig_port))
4182                         /* TODO: handle hdmi info frame part */
4183                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4184                                 port_name(port));
4185                 else
4186                         /*
4187                          * LSPCON init faied, but DP init was success, so
4188                          * lets try to drive as DP++ port.
4189                          */
4190                         DRM_ERROR("LSPCON init failed on port %c\n",
4191                                 port_name(port));
4192         }
4193
4194         intel_infoframe_init(intel_dig_port);
4195         return;
4196
4197 err:
4198         drm_encoder_cleanup(encoder);
4199         kfree(intel_dig_port);
4200 }