drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30 #include "i915_selftest.h"
  31
  32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
  33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  34
  35 #define GEN_DEFAULT_PIPEOFFSETS \
  36         .pipe_offsets = { \
  37                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  38                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  39                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  40                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  41         }, \
  42         .trans_offsets = { \
  43                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  44                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  45                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  46                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  47         }
  48
  49 #define GEN_CHV_PIPEOFFSETS \
  50         .pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  54         }, \
  55         .trans_offsets = { \
  56                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  57                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  58                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  59         }
  60
  61 #define CURSOR_OFFSETS \
  62         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  63
  64 #define IVB_CURSOR_OFFSETS \
  65         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  66
  67 #define BDW_COLORS \
  68         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  69 #define CHV_COLORS \
  70         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  71 #define GLK_COLORS \
  72         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
  73
  74 /* Keep in gen based order, and chronological order within a gen */
  75
  76 #define GEN_DEFAULT_PAGE_SIZES \
  77         .page_sizes = I915_GTT_PAGE_SIZE_4K
  78
  79 #define GEN2_FEATURES \
  80         GEN(2), \
  81         .num_pipes = 1, \
  82         .has_overlay = 1, .overlay_needs_physical = 1, \
  83         .has_gmch_display = 1, \
  84         .hws_needs_physical = 1, \
  85         .unfenced_needs_alignment = 1, \
  86         .ring_mask = RENDER_RING, \
  87         .has_snoop = true, \
  88         .has_coherent_ggtt = false, \
  89         GEN_DEFAULT_PIPEOFFSETS, \
  90         GEN_DEFAULT_PAGE_SIZES, \
  91         CURSOR_OFFSETS
  92
  93 static const struct intel_device_info intel_i830_info = {
  94         GEN2_FEATURES,
  95         PLATFORM(INTEL_I830),
  96         .is_mobile = 1, .cursor_needs_physical = 1,
  97         .num_pipes = 2, /* legal, last one wins */
  98 };
  99
 100 static const struct intel_device_info intel_i845g_info = {
 101         GEN2_FEATURES,
 102         PLATFORM(INTEL_I845G),
 103 };
 104
 105 static const struct intel_device_info intel_i85x_info = {
 106         GEN2_FEATURES,
 107         PLATFORM(INTEL_I85X),
 108         .is_mobile = 1,
 109         .num_pipes = 2, /* legal, last one wins */
 110         .cursor_needs_physical = 1,
 111         .has_fbc = 1,
 112 };
 113
 114 static const struct intel_device_info intel_i865g_info = {
 115         GEN2_FEATURES,
 116         PLATFORM(INTEL_I865G),
 117 };
 118
 119 #define GEN3_FEATURES \
 120         GEN(3), \
 121         .num_pipes = 2, \
 122         .has_gmch_display = 1, \
 123         .ring_mask = RENDER_RING, \
 124         .has_snoop = true, \
 125         .has_coherent_ggtt = true, \
 126         GEN_DEFAULT_PIPEOFFSETS, \
 127         GEN_DEFAULT_PAGE_SIZES, \
 128         CURSOR_OFFSETS
 129
 130 static const struct intel_device_info intel_i915g_info = {
 131         GEN3_FEATURES,
 132         PLATFORM(INTEL_I915G),
 133         .has_coherent_ggtt = false,
 134         .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136         .hws_needs_physical = 1,
 137         .unfenced_needs_alignment = 1,
 138 };
 139
 140 static const struct intel_device_info intel_i915gm_info = {
 141         GEN3_FEATURES,
 142         PLATFORM(INTEL_I915GM),
 143         .is_mobile = 1,
 144         .cursor_needs_physical = 1,
 145         .has_overlay = 1, .overlay_needs_physical = 1,
 146         .supports_tv = 1,
 147         .has_fbc = 1,
 148         .hws_needs_physical = 1,
 149         .unfenced_needs_alignment = 1,
 150 };
 151
 152 static const struct intel_device_info intel_i945g_info = {
 153         GEN3_FEATURES,
 154         PLATFORM(INTEL_I945G),
 155         .has_hotplug = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157         .hws_needs_physical = 1,
 158         .unfenced_needs_alignment = 1,
 159 };
 160
 161 static const struct intel_device_info intel_i945gm_info = {
 162         GEN3_FEATURES,
 163         PLATFORM(INTEL_I945GM),
 164         .is_mobile = 1,
 165         .has_hotplug = 1, .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167         .supports_tv = 1,
 168         .has_fbc = 1,
 169         .hws_needs_physical = 1,
 170         .unfenced_needs_alignment = 1,
 171 };
 172
 173 static const struct intel_device_info intel_g33_info = {
 174         GEN3_FEATURES,
 175         PLATFORM(INTEL_G33),
 176         .has_hotplug = 1,
 177         .has_overlay = 1,
 178 };
 179
 180 static const struct intel_device_info intel_pineview_info = {
 181         GEN3_FEATURES,
 182         PLATFORM(INTEL_PINEVIEW),
 183         .is_mobile = 1,
 184         .has_hotplug = 1,
 185         .has_overlay = 1,
 186 };
 187
 188 #define GEN4_FEATURES \
 189         GEN(4), \
 190         .num_pipes = 2, \
 191         .has_hotplug = 1, \
 192         .has_gmch_display = 1, \
 193         .ring_mask = RENDER_RING, \
 194         .has_snoop = true, \
 195         .has_coherent_ggtt = true, \
 196         GEN_DEFAULT_PIPEOFFSETS, \
 197         GEN_DEFAULT_PAGE_SIZES, \
 198         CURSOR_OFFSETS
 199
 200 static const struct intel_device_info intel_i965g_info = {
 201         GEN4_FEATURES,
 202         PLATFORM(INTEL_I965G),
 203         .has_overlay = 1,
 204         .hws_needs_physical = 1,
 205         .has_snoop = false,
 206 };
 207
 208 static const struct intel_device_info intel_i965gm_info = {
 209         GEN4_FEATURES,
 210         PLATFORM(INTEL_I965GM),
 211         .is_mobile = 1, .has_fbc = 1,
 212         .has_overlay = 1,
 213         .supports_tv = 1,
 214         .hws_needs_physical = 1,
 215         .has_snoop = false,
 216 };
 217
 218 static const struct intel_device_info intel_g45_info = {
 219         GEN4_FEATURES,
 220         PLATFORM(INTEL_G45),
 221         .ring_mask = RENDER_RING | BSD_RING,
 222 };
 223
 224 static const struct intel_device_info intel_gm45_info = {
 225         GEN4_FEATURES,
 226         PLATFORM(INTEL_GM45),
 227         .is_mobile = 1, .has_fbc = 1,
 228         .supports_tv = 1,
 229         .ring_mask = RENDER_RING | BSD_RING,
 230 };
 231
 232 #define GEN5_FEATURES \
 233         GEN(5), \
 234         .num_pipes = 2, \
 235         .has_hotplug = 1, \
 236         .ring_mask = RENDER_RING | BSD_RING, \
 237         .has_snoop = true, \
 238         .has_coherent_ggtt = true, \
 239         /* ilk does support rc6, but we do not implement [power] contexts */ \
 240         .has_rc6 = 0, \
 241         GEN_DEFAULT_PIPEOFFSETS, \
 242         GEN_DEFAULT_PAGE_SIZES, \
 243         CURSOR_OFFSETS
 244
 245 static const struct intel_device_info intel_ironlake_d_info = {
 246         GEN5_FEATURES,
 247         PLATFORM(INTEL_IRONLAKE),
 248 };
 249
 250 static const struct intel_device_info intel_ironlake_m_info = {
 251         GEN5_FEATURES,
 252         PLATFORM(INTEL_IRONLAKE),
 253         .is_mobile = 1, .has_fbc = 1,
 254 };
 255
 256 #define GEN6_FEATURES \
 257         GEN(6), \
 258         .num_pipes = 2, \
 259         .has_hotplug = 1, \
 260         .has_fbc = 1, \
 261         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 262         .has_coherent_ggtt = true, \
 263         .has_llc = 1, \
 264         .has_rc6 = 1, \
 265         .has_rc6p = 1, \
 266         .ppgtt = INTEL_PPGTT_ALIASING, \
 267         GEN_DEFAULT_PIPEOFFSETS, \
 268         GEN_DEFAULT_PAGE_SIZES, \
 269         CURSOR_OFFSETS
 270
 271 #define SNB_D_PLATFORM \
 272         GEN6_FEATURES, \
 273         PLATFORM(INTEL_SANDYBRIDGE)
 274
 275 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 276         SNB_D_PLATFORM,
 277         .gt = 1,
 278 };
 279
 280 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 281         SNB_D_PLATFORM,
 282         .gt = 2,
 283 };
 284
 285 #define SNB_M_PLATFORM \
 286         GEN6_FEATURES, \
 287         PLATFORM(INTEL_SANDYBRIDGE), \
 288         .is_mobile = 1
 289
 290
 291 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 292         SNB_M_PLATFORM,
 293         .gt = 1,
 294 };
 295
 296 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 297         SNB_M_PLATFORM,
 298         .gt = 2,
 299 };
 300
 301 #define GEN7_FEATURES  \
 302         GEN(7), \
 303         .num_pipes = 3, \
 304         .has_hotplug = 1, \
 305         .has_fbc = 1, \
 306         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 307         .has_coherent_ggtt = true, \
 308         .has_llc = 1, \
 309         .has_rc6 = 1, \
 310         .has_rc6p = 1, \
 311         .ppgtt = INTEL_PPGTT_FULL, \
 312         GEN_DEFAULT_PIPEOFFSETS, \
 313         GEN_DEFAULT_PAGE_SIZES, \
 314         IVB_CURSOR_OFFSETS
 315
 316 #define IVB_D_PLATFORM \
 317         GEN7_FEATURES, \
 318         PLATFORM(INTEL_IVYBRIDGE), \
 319         .has_l3_dpf = 1
 320
 321 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 322         IVB_D_PLATFORM,
 323         .gt = 1,
 324 };
 325
 326 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 327         IVB_D_PLATFORM,
 328         .gt = 2,
 329 };
 330
 331 #define IVB_M_PLATFORM \
 332         GEN7_FEATURES, \
 333         PLATFORM(INTEL_IVYBRIDGE), \
 334         .is_mobile = 1, \
 335         .has_l3_dpf = 1
 336
 337 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 338         IVB_M_PLATFORM,
 339         .gt = 1,
 340 };
 341
 342 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 343         IVB_M_PLATFORM,
 344         .gt = 2,
 345 };
 346
 347 static const struct intel_device_info intel_ivybridge_q_info = {
 348         GEN7_FEATURES,
 349         PLATFORM(INTEL_IVYBRIDGE),
 350         .gt = 2,
 351         .num_pipes = 0, /* legal, last one wins */
 352         .has_l3_dpf = 1,
 353 };
 354
 355 static const struct intel_device_info intel_valleyview_info = {
 356         PLATFORM(INTEL_VALLEYVIEW),
 357         GEN(7),
 358         .is_lp = 1,
 359         .num_pipes = 2,
 360         .has_runtime_pm = 1,
 361         .has_rc6 = 1,
 362         .has_gmch_display = 1,
 363         .has_hotplug = 1,
 364         .ppgtt = INTEL_PPGTT_FULL,
 365         .has_snoop = true,
 366         .has_coherent_ggtt = false,
 367         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 368         .display_mmio_offset = VLV_DISPLAY_BASE,
 369         GEN_DEFAULT_PAGE_SIZES,
 370         GEN_DEFAULT_PIPEOFFSETS,
 371         CURSOR_OFFSETS
 372 };
 373
 374 #define G75_FEATURES  \
 375         GEN7_FEATURES, \
 376         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 377         .has_ddi = 1, \
 378         .has_fpga_dbg = 1, \
 379         .has_psr = 1, \
 380         .has_dp_mst = 1, \
 381         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 382         .has_runtime_pm = 1
 383
 384 #define HSW_PLATFORM \
 385         G75_FEATURES, \
 386         PLATFORM(INTEL_HASWELL), \
 387         .has_l3_dpf = 1
 388
 389 static const struct intel_device_info intel_haswell_gt1_info = {
 390         HSW_PLATFORM,
 391         .gt = 1,
 392 };
 393
 394 static const struct intel_device_info intel_haswell_gt2_info = {
 395         HSW_PLATFORM,
 396         .gt = 2,
 397 };
 398
 399 static const struct intel_device_info intel_haswell_gt3_info = {
 400         HSW_PLATFORM,
 401         .gt = 3,
 402 };
 403
 404 #define GEN8_FEATURES \
 405         G75_FEATURES, \
 406         GEN(8), \
 407         BDW_COLORS, \
 408         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 409                       I915_GTT_PAGE_SIZE_2M, \
 410         .has_logical_ring_contexts = 1, \
 411         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 412         .has_64bit_reloc = 1, \
 413         .has_reset_engine = 1
 414
 415 #define BDW_PLATFORM \
 416         GEN8_FEATURES, \
 417         PLATFORM(INTEL_BROADWELL)
 418
 419 static const struct intel_device_info intel_broadwell_gt1_info = {
 420         BDW_PLATFORM,
 421         .gt = 1,
 422 };
 423
 424 static const struct intel_device_info intel_broadwell_gt2_info = {
 425         BDW_PLATFORM,
 426         .gt = 2,
 427 };
 428
 429 static const struct intel_device_info intel_broadwell_rsvd_info = {
 430         BDW_PLATFORM,
 431         .gt = 3,
 432         /* According to the device ID those devices are GT3, they were
 433          * previously treated as not GT3, keep it like that.
 434          */
 435 };
 436
 437 static const struct intel_device_info intel_broadwell_gt3_info = {
 438         BDW_PLATFORM,
 439         .gt = 3,
 440         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 441 };
 442
 443 static const struct intel_device_info intel_cherryview_info = {
 444         PLATFORM(INTEL_CHERRYVIEW),
 445         GEN(8),
 446         .num_pipes = 3,
 447         .has_hotplug = 1,
 448         .is_lp = 1,
 449         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 450         .has_64bit_reloc = 1,
 451         .has_runtime_pm = 1,
 452         .has_rc6 = 1,
 453         .has_logical_ring_contexts = 1,
 454         .has_gmch_display = 1,
 455         .ppgtt = INTEL_PPGTT_FULL,
 456         .has_reset_engine = 1,
 457         .has_snoop = true,
 458         .has_coherent_ggtt = false,
 459         .display_mmio_offset = VLV_DISPLAY_BASE,
 460         GEN_DEFAULT_PAGE_SIZES,
 461         GEN_CHV_PIPEOFFSETS,
 462         CURSOR_OFFSETS,
 463         CHV_COLORS,
 464 };
 465
 466 #define GEN9_DEFAULT_PAGE_SIZES \
 467         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 468                       I915_GTT_PAGE_SIZE_64K | \
 469                       I915_GTT_PAGE_SIZE_2M
 470
 471 #define GEN9_FEATURES \
 472         GEN8_FEATURES, \
 473         GEN(9), \
 474         GEN9_DEFAULT_PAGE_SIZES, \
 475         .has_logical_ring_preemption = 1, \
 476         .has_csr = 1, \
 477         .has_guc = 1, \
 478         .has_ipc = 1, \
 479         .ddb_size = 896
 480
 481 #define SKL_PLATFORM \
 482         GEN9_FEATURES, \
 483         /* Display WA #0477 WaDisableIPC: skl */ \
 484         .has_ipc = 0, \
 485         PLATFORM(INTEL_SKYLAKE)
 486
 487 static const struct intel_device_info intel_skylake_gt1_info = {
 488         SKL_PLATFORM,
 489         .gt = 1,
 490 };
 491
 492 static const struct intel_device_info intel_skylake_gt2_info = {
 493         SKL_PLATFORM,
 494         .gt = 2,
 495 };
 496
 497 #define SKL_GT3_PLUS_PLATFORM \
 498         SKL_PLATFORM, \
 499         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 500
 501
 502 static const struct intel_device_info intel_skylake_gt3_info = {
 503         SKL_GT3_PLUS_PLATFORM,
 504         .gt = 3,
 505 };
 506
 507 static const struct intel_device_info intel_skylake_gt4_info = {
 508         SKL_GT3_PLUS_PLATFORM,
 509         .gt = 4,
 510 };
 511
 512 #define GEN9_LP_FEATURES \
 513         GEN(9), \
 514         .is_lp = 1, \
 515         .has_hotplug = 1, \
 516         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 517         .num_pipes = 3, \
 518         .has_64bit_reloc = 1, \
 519         .has_ddi = 1, \
 520         .has_fpga_dbg = 1, \
 521         .has_fbc = 1, \
 522         .has_psr = 1, \
 523         .has_runtime_pm = 1, \
 524         .has_pooled_eu = 0, \
 525         .has_csr = 1, \
 526         .has_rc6 = 1, \
 527         .has_dp_mst = 1, \
 528         .has_logical_ring_contexts = 1, \
 529         .has_logical_ring_preemption = 1, \
 530         .has_guc = 1, \
 531         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 532         .has_reset_engine = 1, \
 533         .has_snoop = true, \
 534         .has_coherent_ggtt = false, \
 535         .has_ipc = 1, \
 536         GEN9_DEFAULT_PAGE_SIZES, \
 537         GEN_DEFAULT_PIPEOFFSETS, \
 538         IVB_CURSOR_OFFSETS, \
 539         BDW_COLORS
 540
 541 static const struct intel_device_info intel_broxton_info = {
 542         GEN9_LP_FEATURES,
 543         PLATFORM(INTEL_BROXTON),
 544         .ddb_size = 512,
 545 };
 546
 547 static const struct intel_device_info intel_geminilake_info = {
 548         GEN9_LP_FEATURES,
 549         PLATFORM(INTEL_GEMINILAKE),
 550         .ddb_size = 1024,
 551         GLK_COLORS,
 552 };
 553
 554 #define KBL_PLATFORM \
 555         GEN9_FEATURES, \
 556         PLATFORM(INTEL_KABYLAKE)
 557
 558 static const struct intel_device_info intel_kabylake_gt1_info = {
 559         KBL_PLATFORM,
 560         .gt = 1,
 561 };
 562
 563 static const struct intel_device_info intel_kabylake_gt2_info = {
 564         KBL_PLATFORM,
 565         .gt = 2,
 566 };
 567
 568 static const struct intel_device_info intel_kabylake_gt3_info = {
 569         KBL_PLATFORM,
 570         .gt = 3,
 571         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 572 };
 573
 574 #define CFL_PLATFORM \
 575         GEN9_FEATURES, \
 576         PLATFORM(INTEL_COFFEELAKE)
 577
 578 static const struct intel_device_info intel_coffeelake_gt1_info = {
 579         CFL_PLATFORM,
 580         .gt = 1,
 581 };
 582
 583 static const struct intel_device_info intel_coffeelake_gt2_info = {
 584         CFL_PLATFORM,
 585         .gt = 2,
 586 };
 587
 588 static const struct intel_device_info intel_coffeelake_gt3_info = {
 589         CFL_PLATFORM,
 590         .gt = 3,
 591         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 592 };
 593
 594 #define GEN10_FEATURES \
 595         GEN9_FEATURES, \
 596         GEN(10), \
 597         .ddb_size = 1024, \
 598         .has_coherent_ggtt = false, \
 599         GLK_COLORS
 600
 601 static const struct intel_device_info intel_cannonlake_info = {
 602         GEN10_FEATURES,
 603         PLATFORM(INTEL_CANNONLAKE),
 604         .gt = 2,
 605 };
 606
 607 #define GEN11_FEATURES \
 608         GEN10_FEATURES, \
 609         .pipe_offsets = { \
 610                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 611                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 612                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 613                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 614                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 615                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 616         }, \
 617         .trans_offsets = { \
 618                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 619                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 620                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 621                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 622                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 623                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 624         }, \
 625         GEN(11), \
 626         .ddb_size = 2048, \
 627         .has_logical_ring_elsq = 1
 628
 629 static const struct intel_device_info intel_icelake_11_info = {
 630         GEN11_FEATURES,
 631         PLATFORM(INTEL_ICELAKE),
 632         .is_alpha_support = 1,
 633         .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 634 };
 635
 636 #undef GEN
 637 #undef PLATFORM
 638
 639 /*
 640  * Make sure any device matches here are from most specific to most
 641  * general.  For example, since the Quanta match is based on the subsystem
 642  * and subvendor IDs, we need it to come before the more general IVB
 643  * PCI ID matches, otherwise we'll use the wrong info struct above.
 644  */
 645 static const struct pci_device_id pciidlist[] = {
 646         INTEL_I830_IDS(&intel_i830_info),
 647         INTEL_I845G_IDS(&intel_i845g_info),
 648         INTEL_I85X_IDS(&intel_i85x_info),
 649         INTEL_I865G_IDS(&intel_i865g_info),
 650         INTEL_I915G_IDS(&intel_i915g_info),
 651         INTEL_I915GM_IDS(&intel_i915gm_info),
 652         INTEL_I945G_IDS(&intel_i945g_info),
 653         INTEL_I945GM_IDS(&intel_i945gm_info),
 654         INTEL_I965G_IDS(&intel_i965g_info),
 655         INTEL_G33_IDS(&intel_g33_info),
 656         INTEL_I965GM_IDS(&intel_i965gm_info),
 657         INTEL_GM45_IDS(&intel_gm45_info),
 658         INTEL_G45_IDS(&intel_g45_info),
 659         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 660         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 661         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 662         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 663         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 664         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 665         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 666         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 667         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 668         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 669         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 670         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 671         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 672         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 673         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 674         INTEL_VLV_IDS(&intel_valleyview_info),
 675         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 676         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 677         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 678         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 679         INTEL_CHV_IDS(&intel_cherryview_info),
 680         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 681         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 682         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 683         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 684         INTEL_BXT_IDS(&intel_broxton_info),
 685         INTEL_GLK_IDS(&intel_geminilake_info),
 686         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 687         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 688         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 689         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 690         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 691         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 692         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 693         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 694         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 695         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 696         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 697         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 698         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 699         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 700         INTEL_CNL_IDS(&intel_cannonlake_info),
 701         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 702         {0, 0, 0}
 703 };
 704 MODULE_DEVICE_TABLE(pci, pciidlist);
 705
 706 static void i915_pci_remove(struct pci_dev *pdev)
 707 {
 708         struct drm_device *dev;
 709
 710         dev = pci_get_drvdata(pdev);
 711         if (!dev) /* driver load aborted, nothing to cleanup */
 712                 return;
 713
 714         i915_driver_unload(dev);
 715         drm_dev_put(dev);
 716
 717         pci_set_drvdata(pdev, NULL);
 718 }
 719
 720 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 721 {
 722         struct intel_device_info *intel_info =
 723                 (struct intel_device_info *) ent->driver_data;
 724         int err;
 725
 726         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 727                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 728                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 729                          "to enable support in this kernel version, or check for kernel updates.\n");
 730                 return -ENODEV;
 731         }
 732
 733         /* Only bind to function 0 of the device. Early generations
 734          * used function 1 as a placeholder for multi-head. This causes
 735          * us confusion instead, especially on the systems where both
 736          * functions have the same PCI-ID!
 737          */
 738         if (PCI_FUNC(pdev->devfn))
 739                 return -ENODEV;
 740
 741         /*
 742          * apple-gmux is needed on dual GPU MacBook Pro
 743          * to probe the panel if we're the inactive GPU.
 744          */
 745         if (vga_switcheroo_client_probe_defer(pdev))
 746                 return -EPROBE_DEFER;
 747
 748         err = i915_driver_load(pdev, ent);
 749         if (err)
 750                 return err;
 751
 752         if (i915_inject_load_failure()) {
 753                 i915_pci_remove(pdev);
 754                 return -ENODEV;
 755         }
 756
 757         err = i915_live_selftests(pdev);
 758         if (err) {
 759                 i915_pci_remove(pdev);
 760                 return err > 0 ? -ENOTTY : err;
 761         }
 762
 763         return 0;
 764 }
 765
 766 static struct pci_driver i915_pci_driver = {
 767         .name = DRIVER_NAME,
 768         .id_table = pciidlist,
 769         .probe = i915_pci_probe,
 770         .remove = i915_pci_remove,
 771         .driver.pm = &i915_pm_ops,
 772 };
 773
 774 static int __init i915_init(void)
 775 {
 776         bool use_kms = true;
 777         int err;
 778
 779         err = i915_mock_selftests();
 780         if (err)
 781                 return err > 0 ? 0 : err;
 782
 783         /*
 784          * Enable KMS by default, unless explicitly overriden by
 785          * either the i915.modeset prarameter or by the
 786          * vga_text_mode_force boot option.
 787          */
 788
 789         if (i915_modparams.modeset == 0)
 790                 use_kms = false;
 791
 792         if (vgacon_text_force() && i915_modparams.modeset == -1)
 793                 use_kms = false;
 794
 795         if (!use_kms) {
 796                 /* Silently fail loading to not upset userspace. */
 797                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 798                 return 0;
 799         }
 800
 801         return pci_register_driver(&i915_pci_driver);
 802 }
 803
 804 static void __exit i915_exit(void)
 805 {
 806         if (!i915_pci_driver.driver.owner)
 807                 return;
 808
 809         pci_unregister_driver(&i915_pci_driver);
 810 }
 811
 812 module_init(i915_init);
 813 module_exit(i915_exit);
 814
 815 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 816 MODULE_AUTHOR("Intel Corporation");
 817
 818 MODULE_DESCRIPTION(DRIVER_DESC);
 819 MODULE_LICENSE("GPL and additional rights");