drivers/acpi/cppc_acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   4  *
   5  * (C) Copyright 2014, 2015 Linaro Ltd.
   6  * Author: Ashwin Chaugule <[email protected]>
   7  *
   8  * CPPC describes a few methods for controlling CPU performance using
   9  * information from a per CPU table called CPC. This table is described in
  10  * the ACPI v5.0+ specification. The table consists of a list of
  11  * registers which may be memory mapped or hardware registers and also may
  12  * include some static integer values.
  13  *
  14  * CPU performance is on an abstract continuous scale as against a discretized
  15  * P-state scale which is tied to CPU frequency only. In brief, the basic
  16  * operation involves:
  17  *
  18  * - OS makes a CPU performance request. (Can provide min and max bounds)
  19  *
  20  * - Platform (such as BMC) is free to optimize request within requested bounds
  21  *   depending on power/thermal budgets etc.
  22  *
  23  * - Platform conveys its decision back to OS
  24  *
  25  * The communication between OS and platform occurs through another medium
  26  * called (PCC) Platform Communication Channel. This is a generic mailbox like
  27  * mechanism which includes doorbell semantics to indicate register updates.
  28  * See drivers/mailbox/pcc.c for details on PCC.
  29  *
  30  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  31  * above specifications.
  32  */
  33
  34 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
  35
  36 #include <linux/delay.h>
  37 #include <linux/iopoll.h>
  38 #include <linux/ktime.h>
  39 #include <linux/rwsem.h>
  40 #include <linux/wait.h>
  41 #include <linux/topology.h>
  42
  43 #include <acpi/cppc_acpi.h>
  44
  45 struct cppc_pcc_data {
  46         struct pcc_mbox_chan *pcc_channel;
  47         void __iomem *pcc_comm_addr;
  48         bool pcc_channel_acquired;
  49         unsigned int deadline_us;
  50         unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  51
  52         bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
  53         bool platform_owns_pcc;         /* Ownership of PCC subspace */
  54         unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
  55
  56         /*
  57          * Lock to provide controlled access to the PCC channel.
  58          *
  59          * For performance critical usecases(currently cppc_set_perf)
  60          *      We need to take read_lock and check if channel belongs to OSPM
  61          * before reading or writing to PCC subspace
  62          *      We need to take write_lock before transferring the channel
  63          * ownership to the platform via a Doorbell
  64          *      This allows us to batch a number of CPPC requests if they happen
  65          * to originate in about the same time
  66          *
  67          * For non-performance critical usecases(init)
  68          *      Take write_lock for all purposes which gives exclusive access
  69          */
  70         struct rw_semaphore pcc_lock;
  71
  72         /* Wait queue for CPUs whose requests were batched */
  73         wait_queue_head_t pcc_write_wait_q;
  74         ktime_t last_cmd_cmpl_time;
  75         ktime_t last_mpar_reset;
  76         int mpar_count;
  77         int refcount;
  78 };
  79
  80 /* Array to represent the PCC channel per subspace ID */
  81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
  82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
  83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  84
  85 /*
  86  * The cpc_desc structure contains the ACPI register details
  87  * as described in the per CPU _CPC tables. The details
  88  * include the type of register (e.g. PCC, System IO, FFH etc.)
  89  * and destination addresses which lets us READ/WRITE CPU performance
  90  * information using the appropriate I/O methods.
  91  */
  92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  93
  94 /* pcc mapped address + header size + offset within PCC subspace */
  95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
  96                                                 0x8 + (offs))
  97
  98 /* Check if a CPC register is in PCC */
  99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
 100                                 (cpc)->cpc_entry.reg.space_id ==        \
 101                                 ACPI_ADR_SPACE_PLATFORM_COMM)
 102
 103 /* Evaluates to True if reg is a NULL register descriptor */
 104 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 105                                 (reg)->address == 0 &&                  \
 106                                 (reg)->bit_width == 0 &&                \
 107                                 (reg)->bit_offset == 0 &&               \
 108                                 (reg)->access_width == 0)
 109
 110 /* Evaluates to True if an optional cpc field is supported */
 111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
 112                                 !!(cpc)->cpc_entry.int_value :          \
 113                                 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
 114 /*
 115  * Arbitrary Retries in case the remote processor is slow to respond
 116  * to PCC commands. Keeping it high enough to cover emulators where
 117  * the processors run painfully slow.
 118  */
 119 #define NUM_RETRIES 500ULL
 120
 121 #define define_one_cppc_ro(_name)               \
 122 static struct kobj_attribute _name =            \
 123 __ATTR(_name, 0444, show_##_name, NULL)
 124
 125 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 126
 127 #define show_cppc_data(access_fn, struct_name, member_name)             \
 128         static ssize_t show_##member_name(struct kobject *kobj,         \
 129                                 struct kobj_attribute *attr, char *buf) \
 130         {                                                               \
 131                 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);           \
 132                 struct struct_name st_name = {0};                       \
 133                 int ret;                                                \
 134                                                                         \
 135                 ret = access_fn(cpc_ptr->cpu_id, &st_name);             \
 136                 if (ret)                                                \
 137                         return ret;                                     \
 138                                                                         \
 139                 return scnprintf(buf, PAGE_SIZE, "%llu\n",              \
 140                                 (u64)st_name.member_name);              \
 141         }                                                               \
 142         define_one_cppc_ro(member_name)
 143
 144 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
 145 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
 146 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
 147 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
 148 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
 149 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
 150
 151 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
 152 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 153
 154 static ssize_t show_feedback_ctrs(struct kobject *kobj,
 155                 struct kobj_attribute *attr, char *buf)
 156 {
 157         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 158         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 159         int ret;
 160
 161         ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 162         if (ret)
 163                 return ret;
 164
 165         return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
 166                         fb_ctrs.reference, fb_ctrs.delivered);
 167 }
 168 define_one_cppc_ro(feedback_ctrs);
 169
 170 static struct attribute *cppc_attrs[] = {
 171         &feedback_ctrs.attr,
 172         &reference_perf.attr,
 173         &wraparound_time.attr,
 174         &highest_perf.attr,
 175         &lowest_perf.attr,
 176         &lowest_nonlinear_perf.attr,
 177         &nominal_perf.attr,
 178         &nominal_freq.attr,
 179         &lowest_freq.attr,
 180         NULL
 181 };
 182 ATTRIBUTE_GROUPS(cppc);
 183
 184 static struct kobj_type cppc_ktype = {
 185         .sysfs_ops = &kobj_sysfs_ops,
 186         .default_groups = cppc_groups,
 187 };
 188
 189 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 190 {
 191         int ret, status;
 192         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 193         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 194                 pcc_ss_data->pcc_comm_addr;
 195
 196         if (!pcc_ss_data->platform_owns_pcc)
 197                 return 0;
 198
 199         /*
 200          * Poll PCC status register every 3us(delay_us) for maximum of
 201          * deadline_us(timeout_us) until PCC command complete bit is set(cond)
 202          */
 203         ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
 204                                         status & PCC_CMD_COMPLETE_MASK, 3,
 205                                         pcc_ss_data->deadline_us);
 206
 207         if (likely(!ret)) {
 208                 pcc_ss_data->platform_owns_pcc = false;
 209                 if (chk_err_bit && (status & PCC_ERROR_MASK))
 210                         ret = -EIO;
 211         }
 212
 213         if (unlikely(ret))
 214                 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
 215                        pcc_ss_id, ret);
 216
 217         return ret;
 218 }
 219
 220 /*
 221  * This function transfers the ownership of the PCC to the platform
 222  * So it must be called while holding write_lock(pcc_lock)
 223  */
 224 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 225 {
 226         int ret = -EIO, i;
 227         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 228         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 229                 pcc_ss_data->pcc_comm_addr;
 230         unsigned int time_delta;
 231
 232         /*
 233          * For CMD_WRITE we know for a fact the caller should have checked
 234          * the channel before writing to PCC space
 235          */
 236         if (cmd == CMD_READ) {
 237                 /*
 238                  * If there are pending cpc_writes, then we stole the channel
 239                  * before write completion, so first send a WRITE command to
 240                  * platform
 241                  */
 242                 if (pcc_ss_data->pending_pcc_write_cmd)
 243                         send_pcc_cmd(pcc_ss_id, CMD_WRITE);
 244
 245                 ret = check_pcc_chan(pcc_ss_id, false);
 246                 if (ret)
 247                         goto end;
 248         } else /* CMD_WRITE */
 249                 pcc_ss_data->pending_pcc_write_cmd = FALSE;
 250
 251         /*
 252          * Handle the Minimum Request Turnaround Time(MRTT)
 253          * "The minimum amount of time that OSPM must wait after the completion
 254          * of a command before issuing the next command, in microseconds"
 255          */
 256         if (pcc_ss_data->pcc_mrtt) {
 257                 time_delta = ktime_us_delta(ktime_get(),
 258                                             pcc_ss_data->last_cmd_cmpl_time);
 259                 if (pcc_ss_data->pcc_mrtt > time_delta)
 260                         udelay(pcc_ss_data->pcc_mrtt - time_delta);
 261         }
 262
 263         /*
 264          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 265          * "The maximum number of periodic requests that the subspace channel can
 266          * support, reported in commands per minute. 0 indicates no limitation."
 267          *
 268          * This parameter should be ideally zero or large enough so that it can
 269          * handle maximum number of requests that all the cores in the system can
 270          * collectively generate. If it is not, we will follow the spec and just
 271          * not send the request to the platform after hitting the MPAR limit in
 272          * any 60s window
 273          */
 274         if (pcc_ss_data->pcc_mpar) {
 275                 if (pcc_ss_data->mpar_count == 0) {
 276                         time_delta = ktime_ms_delta(ktime_get(),
 277                                                     pcc_ss_data->last_mpar_reset);
 278                         if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
 279                                 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
 280                                          pcc_ss_id);
 281                                 ret = -EIO;
 282                                 goto end;
 283                         }
 284                         pcc_ss_data->last_mpar_reset = ktime_get();
 285                         pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
 286                 }
 287                 pcc_ss_data->mpar_count--;
 288         }
 289
 290         /* Write to the shared comm region. */
 291         writew_relaxed(cmd, &generic_comm_base->command);
 292
 293         /* Flip CMD COMPLETE bit */
 294         writew_relaxed(0, &generic_comm_base->status);
 295
 296         pcc_ss_data->platform_owns_pcc = true;
 297
 298         /* Ring doorbell */
 299         ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
 300         if (ret < 0) {
 301                 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
 302                        pcc_ss_id, cmd, ret);
 303                 goto end;
 304         }
 305
 306         /* wait for completion and check for PCC errro bit */
 307         ret = check_pcc_chan(pcc_ss_id, true);
 308
 309         if (pcc_ss_data->pcc_mrtt)
 310                 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
 311
 312         if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
 313                 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 314         else
 315                 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 316
 317 end:
 318         if (cmd == CMD_WRITE) {
 319                 if (unlikely(ret)) {
 320                         for_each_possible_cpu(i) {
 321                                 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
 322
 323                                 if (!desc)
 324                                         continue;
 325
 326                                 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
 327                                         desc->write_cmd_status = ret;
 328                         }
 329                 }
 330                 pcc_ss_data->pcc_write_cnt++;
 331                 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
 332         }
 333
 334         return ret;
 335 }
 336
 337 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 338 {
 339         if (ret < 0)
 340                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 341                                 *(u16 *)msg, ret);
 342         else
 343                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 344                                 *(u16 *)msg, ret);
 345 }
 346
 347 static struct mbox_client cppc_mbox_cl = {
 348         .tx_done = cppc_chan_tx_done,
 349         .knows_txdone = true,
 350 };
 351
 352 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 353 {
 354         int result = -EFAULT;
 355         acpi_status status = AE_OK;
 356         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 357         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 358         struct acpi_buffer state = {0, NULL};
 359         union acpi_object  *psd = NULL;
 360         struct acpi_psd_package *pdomain;
 361
 362         status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
 363                                             &buffer, ACPI_TYPE_PACKAGE);
 364         if (status == AE_NOT_FOUND)     /* _PSD is optional */
 365                 return 0;
 366         if (ACPI_FAILURE(status))
 367                 return -ENODEV;
 368
 369         psd = buffer.pointer;
 370         if (!psd || psd->package.count != 1) {
 371                 pr_debug("Invalid _PSD data\n");
 372                 goto end;
 373         }
 374
 375         pdomain = &(cpc_ptr->domain_info);
 376
 377         state.length = sizeof(struct acpi_psd_package);
 378         state.pointer = pdomain;
 379
 380         status = acpi_extract_package(&(psd->package.elements[0]),
 381                 &format, &state);
 382         if (ACPI_FAILURE(status)) {
 383                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 384                 goto end;
 385         }
 386
 387         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 388                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 389                 goto end;
 390         }
 391
 392         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 393                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 394                 goto end;
 395         }
 396
 397         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 398             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 399             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 400                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 401                 goto end;
 402         }
 403
 404         result = 0;
 405 end:
 406         kfree(buffer.pointer);
 407         return result;
 408 }
 409
 410 bool acpi_cpc_valid(void)
 411 {
 412         struct cpc_desc *cpc_ptr;
 413         int cpu;
 414
 415         for_each_possible_cpu(cpu) {
 416                 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 417                 if (!cpc_ptr)
 418                         return false;
 419         }
 420
 421         return true;
 422 }
 423 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
 424
 425 /**
 426  * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
 427  * @cpu: Find all CPUs that share a domain with cpu.
 428  * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
 429  *
 430  *      Return: 0 for success or negative value for err.
 431  */
 432 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
 433 {
 434         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 435         struct acpi_psd_package *match_pdomain;
 436         struct acpi_psd_package *pdomain;
 437         int count_target, i;
 438
 439         /*
 440          * Now that we have _PSD data from all CPUs, let's setup P-state
 441          * domain info.
 442          */
 443         cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 444         if (!cpc_ptr)
 445                 return -EFAULT;
 446
 447         pdomain = &(cpc_ptr->domain_info);
 448         cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 449         if (pdomain->num_processors <= 1)
 450                 return 0;
 451
 452         /* Validate the Domain info */
 453         count_target = pdomain->num_processors;
 454         if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 455                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 456         else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 457                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
 458         else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 459                 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 460
 461         for_each_possible_cpu(i) {
 462                 if (i == cpu)
 463                         continue;
 464
 465                 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
 466                 if (!match_cpc_ptr)
 467                         goto err_fault;
 468
 469                 match_pdomain = &(match_cpc_ptr->domain_info);
 470                 if (match_pdomain->domain != pdomain->domain)
 471                         continue;
 472
 473                 /* Here i and cpu are in the same domain */
 474                 if (match_pdomain->num_processors != count_target)
 475                         goto err_fault;
 476
 477                 if (pdomain->coord_type != match_pdomain->coord_type)
 478                         goto err_fault;
 479
 480                 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
 481         }
 482
 483         return 0;
 484
 485 err_fault:
 486         /* Assume no coordination on any error parsing domain info */
 487         cpumask_clear(cpu_data->shared_cpu_map);
 488         cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 489         cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
 490
 491         return -EFAULT;
 492 }
 493 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 494
 495 static int register_pcc_channel(int pcc_ss_idx)
 496 {
 497         struct pcc_mbox_chan *pcc_chan;
 498         u64 usecs_lat;
 499
 500         if (pcc_ss_idx >= 0) {
 501                 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
 502
 503                 if (IS_ERR(pcc_chan)) {
 504                         pr_err("Failed to find PCC channel for subspace %d\n",
 505                                pcc_ss_idx);
 506                         return -ENODEV;
 507                 }
 508
 509                 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
 510                 /*
 511                  * cppc_ss->latency is just a Nominal value. In reality
 512                  * the remote processor could be much slower to reply.
 513                  * So add an arbitrary amount of wait on top of Nominal.
 514                  */
 515                 usecs_lat = NUM_RETRIES * pcc_chan->latency;
 516                 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
 517                 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
 518                 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
 519                 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
 520
 521                 pcc_data[pcc_ss_idx]->pcc_comm_addr =
 522                         acpi_os_ioremap(pcc_chan->shmem_base_addr,
 523                                         pcc_chan->shmem_size);
 524                 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
 525                         pr_err("Failed to ioremap PCC comm region mem for %d\n",
 526                                pcc_ss_idx);
 527                         return -ENOMEM;
 528                 }
 529
 530                 /* Set flag so that we don't come here for each CPU. */
 531                 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
 532         }
 533
 534         return 0;
 535 }
 536
 537 /**
 538  * cpc_ffh_supported() - check if FFH reading supported
 539  *
 540  * Check if the architecture has support for functional fixed hardware
 541  * read/write capability.
 542  *
 543  * Return: true for supported, false for not supported
 544  */
 545 bool __weak cpc_ffh_supported(void)
 546 {
 547         return false;
 548 }
 549
 550 /**
 551  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
 552  *
 553  * Check and allocate the cppc_pcc_data memory.
 554  * In some processor configurations it is possible that same subspace
 555  * is shared between multiple CPUs. This is seen especially in CPUs
 556  * with hardware multi-threading support.
 557  *
 558  * Return: 0 for success, errno for failure
 559  */
 560 static int pcc_data_alloc(int pcc_ss_id)
 561 {
 562         if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
 563                 return -EINVAL;
 564
 565         if (pcc_data[pcc_ss_id]) {
 566                 pcc_data[pcc_ss_id]->refcount++;
 567         } else {
 568                 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
 569                                               GFP_KERNEL);
 570                 if (!pcc_data[pcc_ss_id])
 571                         return -ENOMEM;
 572                 pcc_data[pcc_ss_id]->refcount++;
 573         }
 574
 575         return 0;
 576 }
 577
 578 /* Check if CPPC revision + num_ent combination is supported */
 579 static bool is_cppc_supported(int revision, int num_ent)
 580 {
 581         int expected_num_ent;
 582
 583         switch (revision) {
 584         case CPPC_V2_REV:
 585                 expected_num_ent = CPPC_V2_NUM_ENT;
 586                 break;
 587         case CPPC_V3_REV:
 588                 expected_num_ent = CPPC_V3_NUM_ENT;
 589                 break;
 590         default:
 591                 pr_debug("Firmware exports unsupported CPPC revision: %d\n",
 592                         revision);
 593                 return false;
 594         }
 595
 596         if (expected_num_ent != num_ent) {
 597                 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
 598                         num_ent, expected_num_ent, revision);
 599                 return false;
 600         }
 601
 602         return true;
 603 }
 604
 605 /*
 606  * An example CPC table looks like the following.
 607  *
 608  *      Name(_CPC, Package()
 609  *                      {
 610  *                      17,
 611  *                      NumEntries
 612  *                      1,
 613  *                      // Revision
 614  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
 615  *                      // Highest Performance
 616  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
 617  *                      // Nominal Performance
 618  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
 619  *                      // Lowest Nonlinear Performance
 620  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
 621  *                      // Lowest Performance
 622  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
 623  *                      // Guaranteed Performance Register
 624  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
 625  *                      // Desired Performance Register
 626  *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
 627  *                      ..
 628  *                      ..
 629  *                      ..
 630  *
 631  *              }
 632  * Each Register() encodes how to access that specific register.
 633  * e.g. a sample PCC entry has the following encoding:
 634  *
 635  *      Register (
 636  *              PCC,
 637  *              AddressSpaceKeyword
 638  *              8,
 639  *              //RegisterBitWidth
 640  *              8,
 641  *              //RegisterBitOffset
 642  *              0x30,
 643  *              //RegisterAddress
 644  *              9
 645  *              //AccessSize (subspace ID)
 646  *              0
 647  *              )
 648  *      }
 649  */
 650
 651 #ifndef init_freq_invariance_cppc
 652 static inline void init_freq_invariance_cppc(void) { }
 653 #endif
 654
 655 /**
 656  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 657  * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 658  *
 659  *      Return: 0 for success or negative value for err.
 660  */
 661 int acpi_cppc_processor_probe(struct acpi_processor *pr)
 662 {
 663         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 664         union acpi_object *out_obj, *cpc_obj;
 665         struct cpc_desc *cpc_ptr;
 666         struct cpc_reg *gas_t;
 667         struct device *cpu_dev;
 668         acpi_handle handle = pr->handle;
 669         unsigned int num_ent, i, cpc_rev;
 670         int pcc_subspace_id = -1;
 671         acpi_status status;
 672         int ret = -EFAULT;
 673
 674         /* Parse the ACPI _CPC table for this CPU. */
 675         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 676                         ACPI_TYPE_PACKAGE);
 677         if (ACPI_FAILURE(status)) {
 678                 ret = -ENODEV;
 679                 goto out_buf_free;
 680         }
 681
 682         out_obj = (union acpi_object *) output.pointer;
 683
 684         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 685         if (!cpc_ptr) {
 686                 ret = -ENOMEM;
 687                 goto out_buf_free;
 688         }
 689
 690         /* First entry is NumEntries. */
 691         cpc_obj = &out_obj->package.elements[0];
 692         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 693                 num_ent = cpc_obj->integer.value;
 694         } else {
 695                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
 696                                 cpc_obj->type);
 697                 goto out_free;
 698         }
 699         cpc_ptr->num_entries = num_ent;
 700
 701         /* Second entry should be revision. */
 702         cpc_obj = &out_obj->package.elements[1];
 703         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 704                 cpc_rev = cpc_obj->integer.value;
 705         } else {
 706                 pr_debug("Unexpected entry type(%d) for Revision\n",
 707                                 cpc_obj->type);
 708                 goto out_free;
 709         }
 710         cpc_ptr->version = cpc_rev;
 711
 712         if (!is_cppc_supported(cpc_rev, num_ent))
 713                 goto out_free;
 714
 715         /* Iterate through remaining entries in _CPC */
 716         for (i = 2; i < num_ent; i++) {
 717                 cpc_obj = &out_obj->package.elements[i];
 718
 719                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 720                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 721                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 722                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 723                         gas_t = (struct cpc_reg *)
 724                                 cpc_obj->buffer.pointer;
 725
 726                         /*
 727                          * The PCC Subspace index is encoded inside
 728                          * the CPC table entries. The same PCC index
 729                          * will be used for all the PCC entries,
 730                          * so extract it only once.
 731                          */
 732                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 733                                 if (pcc_subspace_id < 0) {
 734                                         pcc_subspace_id = gas_t->access_width;
 735                                         if (pcc_data_alloc(pcc_subspace_id))
 736                                                 goto out_free;
 737                                 } else if (pcc_subspace_id != gas_t->access_width) {
 738                                         pr_debug("Mismatched PCC ids.\n");
 739                                         goto out_free;
 740                                 }
 741                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 742                                 if (gas_t->address) {
 743                                         void __iomem *addr;
 744
 745                                         addr = ioremap(gas_t->address, gas_t->bit_width/8);
 746                                         if (!addr)
 747                                                 goto out_free;
 748                                         cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 749                                 }
 750                         } else {
 751                                 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 752                                         /* Support only PCC ,SYS MEM and FFH type regs */
 753                                         pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 754                                         goto out_free;
 755                                 }
 756                         }
 757
 758                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 759                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 760                 } else {
 761                         pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id);
 762                         goto out_free;
 763                 }
 764         }
 765         per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
 766
 767         /*
 768          * Initialize the remaining cpc_regs as unsupported.
 769          * Example: In case FW exposes CPPC v2, the below loop will initialize
 770          * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
 771          */
 772         for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
 773                 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
 774                 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
 775         }
 776
 777
 778         /* Store CPU Logical ID */
 779         cpc_ptr->cpu_id = pr->id;
 780
 781         /* Parse PSD data for this CPU */
 782         ret = acpi_get_psd(cpc_ptr, handle);
 783         if (ret)
 784                 goto out_free;
 785
 786         /* Register PCC channel once for all PCC subspace ID. */
 787         if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
 788                 ret = register_pcc_channel(pcc_subspace_id);
 789                 if (ret)
 790                         goto out_free;
 791
 792                 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
 793                 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
 794         }
 795
 796         /* Everything looks okay */
 797         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 798
 799         /* Add per logical CPU nodes for reading its feedback counters. */
 800         cpu_dev = get_cpu_device(pr->id);
 801         if (!cpu_dev) {
 802                 ret = -EINVAL;
 803                 goto out_free;
 804         }
 805
 806         /* Plug PSD data into this CPU's CPC descriptor. */
 807         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 808
 809         ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
 810                         "acpi_cppc");
 811         if (ret) {
 812                 per_cpu(cpc_desc_ptr, pr->id) = NULL;
 813                 kobject_put(&cpc_ptr->kobj);
 814                 goto out_free;
 815         }
 816
 817         init_freq_invariance_cppc();
 818
 819         kfree(output.pointer);
 820         return 0;
 821
 822 out_free:
 823         /* Free all the mapped sys mem areas for this CPU */
 824         for (i = 2; i < cpc_ptr->num_entries; i++) {
 825                 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 826
 827                 if (addr)
 828                         iounmap(addr);
 829         }
 830         kfree(cpc_ptr);
 831
 832 out_buf_free:
 833         kfree(output.pointer);
 834         return ret;
 835 }
 836 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 837
 838 /**
 839  * acpi_cppc_processor_exit - Cleanup CPC structs.
 840  * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 841  *
 842  * Return: Void
 843  */
 844 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 845 {
 846         struct cpc_desc *cpc_ptr;
 847         unsigned int i;
 848         void __iomem *addr;
 849         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 850
 851         if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
 852                 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
 853                         pcc_data[pcc_ss_id]->refcount--;
 854                         if (!pcc_data[pcc_ss_id]->refcount) {
 855                                 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
 856                                 kfree(pcc_data[pcc_ss_id]);
 857                                 pcc_data[pcc_ss_id] = NULL;
 858                         }
 859                 }
 860         }
 861
 862         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 863         if (!cpc_ptr)
 864                 return;
 865
 866         /* Free all the mapped sys mem areas for this CPU */
 867         for (i = 2; i < cpc_ptr->num_entries; i++) {
 868                 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 869                 if (addr)
 870                         iounmap(addr);
 871         }
 872
 873         kobject_put(&cpc_ptr->kobj);
 874         kfree(cpc_ptr);
 875 }
 876 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 877
 878 /**
 879  * cpc_read_ffh() - Read FFH register
 880  * @cpunum:     CPU number to read
 881  * @reg:        cppc register information
 882  * @val:        place holder for return value
 883  *
 884  * Read bit_width bits from a specified address and bit_offset
 885  *
 886  * Return: 0 for success and error code
 887  */
 888 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
 889 {
 890         return -ENOTSUPP;
 891 }
 892
 893 /**
 894  * cpc_write_ffh() - Write FFH register
 895  * @cpunum:     CPU number to write
 896  * @reg:        cppc register information
 897  * @val:        value to write
 898  *
 899  * Write value of bit_width bits to a specified address and bit_offset
 900  *
 901  * Return: 0 for success and error code
 902  */
 903 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 904 {
 905         return -ENOTSUPP;
 906 }
 907
 908 /*
 909  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 910  * as fast as possible. We have already mapped the PCC subspace during init, so
 911  * we can directly write to it.
 912  */
 913
 914 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 915 {
 916         int ret_val = 0;
 917         void __iomem *vaddr = NULL;
 918         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 919         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 920
 921         if (reg_res->type == ACPI_TYPE_INTEGER) {
 922                 *val = reg_res->cpc_entry.int_value;
 923                 return ret_val;
 924         }
 925
 926         *val = 0;
 927         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 928                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 929         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 930                 vaddr = reg_res->sys_mem_vaddr;
 931         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 932                 return cpc_read_ffh(cpu, reg, val);
 933         else
 934                 return acpi_os_read_memory((acpi_physical_address)reg->address,
 935                                 val, reg->bit_width);
 936
 937         switch (reg->bit_width) {
 938         case 8:
 939                 *val = readb_relaxed(vaddr);
 940                 break;
 941         case 16:
 942                 *val = readw_relaxed(vaddr);
 943                 break;
 944         case 32:
 945                 *val = readl_relaxed(vaddr);
 946                 break;
 947         case 64:
 948                 *val = readq_relaxed(vaddr);
 949                 break;
 950         default:
 951                 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
 952                          reg->bit_width, pcc_ss_id);
 953                 ret_val = -EFAULT;
 954         }
 955
 956         return ret_val;
 957 }
 958
 959 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 960 {
 961         int ret_val = 0;
 962         void __iomem *vaddr = NULL;
 963         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 964         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 965
 966         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 967                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 968         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 969                 vaddr = reg_res->sys_mem_vaddr;
 970         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 971                 return cpc_write_ffh(cpu, reg, val);
 972         else
 973                 return acpi_os_write_memory((acpi_physical_address)reg->address,
 974                                 val, reg->bit_width);
 975
 976         switch (reg->bit_width) {
 977         case 8:
 978                 writeb_relaxed(val, vaddr);
 979                 break;
 980         case 16:
 981                 writew_relaxed(val, vaddr);
 982                 break;
 983         case 32:
 984                 writel_relaxed(val, vaddr);
 985                 break;
 986         case 64:
 987                 writeq_relaxed(val, vaddr);
 988                 break;
 989         default:
 990                 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
 991                          reg->bit_width, pcc_ss_id);
 992                 ret_val = -EFAULT;
 993                 break;
 994         }
 995
 996         return ret_val;
 997 }
 998
 999 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1000 {
1001         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1002         struct cpc_register_resource *reg;
1003
1004         if (!cpc_desc) {
1005                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1006                 return -ENODEV;
1007         }
1008
1009         reg = &cpc_desc->cpc_regs[reg_idx];
1010
1011         if (CPC_IN_PCC(reg)) {
1012                 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1013                 struct cppc_pcc_data *pcc_ss_data = NULL;
1014                 int ret = 0;
1015
1016                 if (pcc_ss_id < 0)
1017                         return -EIO;
1018
1019                 pcc_ss_data = pcc_data[pcc_ss_id];
1020
1021                 down_write(&pcc_ss_data->pcc_lock);
1022
1023                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1024                         cpc_read(cpunum, reg, perf);
1025                 else
1026                         ret = -EIO;
1027
1028                 up_write(&pcc_ss_data->pcc_lock);
1029
1030                 return ret;
1031         }
1032
1033         cpc_read(cpunum, reg, perf);
1034
1035         return 0;
1036 }
1037
1038 /**
1039  * cppc_get_desired_perf - Get the desired performance register value.
1040  * @cpunum: CPU from which to get desired performance.
1041  * @desired_perf: Return address.
1042  *
1043  * Return: 0 for success, -EIO otherwise.
1044  */
1045 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1046 {
1047         return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1048 }
1049 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1050
1051 /**
1052  * cppc_get_nominal_perf - Get the nominal performance register value.
1053  * @cpunum: CPU from which to get nominal performance.
1054  * @nominal_perf: Return address.
1055  *
1056  * Return: 0 for success, -EIO otherwise.
1057  */
1058 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1059 {
1060         return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1061 }
1062
1063 /**
1064  * cppc_get_perf_caps - Get a CPU's performance capabilities.
1065  * @cpunum: CPU from which to get capabilities info.
1066  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1067  *
1068  * Return: 0 for success with perf_caps populated else -ERRNO.
1069  */
1070 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1071 {
1072         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1073         struct cpc_register_resource *highest_reg, *lowest_reg,
1074                 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1075                 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1076         u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1077         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1078         struct cppc_pcc_data *pcc_ss_data = NULL;
1079         int ret = 0, regs_in_pcc = 0;
1080
1081         if (!cpc_desc) {
1082                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1083                 return -ENODEV;
1084         }
1085
1086         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1087         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1088         lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1089         nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1090         low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1091         nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1092         guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1093
1094         /* Are any of the regs PCC ?*/
1095         if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1096                 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1097                 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1098                 if (pcc_ss_id < 0) {
1099                         pr_debug("Invalid pcc_ss_id\n");
1100                         return -ENODEV;
1101                 }
1102                 pcc_ss_data = pcc_data[pcc_ss_id];
1103                 regs_in_pcc = 1;
1104                 down_write(&pcc_ss_data->pcc_lock);
1105                 /* Ring doorbell once to update PCC subspace */
1106                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1107                         ret = -EIO;
1108                         goto out_err;
1109                 }
1110         }
1111
1112         cpc_read(cpunum, highest_reg, &high);
1113         perf_caps->highest_perf = high;
1114
1115         cpc_read(cpunum, lowest_reg, &low);
1116         perf_caps->lowest_perf = low;
1117
1118         cpc_read(cpunum, nominal_reg, &nom);
1119         perf_caps->nominal_perf = nom;
1120
1121         if (guaranteed_reg->type != ACPI_TYPE_BUFFER  ||
1122             IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1123                 perf_caps->guaranteed_perf = 0;
1124         } else {
1125                 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1126                 perf_caps->guaranteed_perf = guaranteed;
1127         }
1128
1129         cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1130         perf_caps->lowest_nonlinear_perf = min_nonlinear;
1131
1132         if (!high || !low || !nom || !min_nonlinear)
1133                 ret = -EFAULT;
1134
1135         /* Read optional lowest and nominal frequencies if present */
1136         if (CPC_SUPPORTED(low_freq_reg))
1137                 cpc_read(cpunum, low_freq_reg, &low_f);
1138
1139         if (CPC_SUPPORTED(nom_freq_reg))
1140                 cpc_read(cpunum, nom_freq_reg, &nom_f);
1141
1142         perf_caps->lowest_freq = low_f;
1143         perf_caps->nominal_freq = nom_f;
1144
1145
1146 out_err:
1147         if (regs_in_pcc)
1148                 up_write(&pcc_ss_data->pcc_lock);
1149         return ret;
1150 }
1151 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1152
1153 /**
1154  * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1155  * @cpunum: CPU from which to read counters.
1156  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1157  *
1158  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1159  */
1160 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1161 {
1162         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1163         struct cpc_register_resource *delivered_reg, *reference_reg,
1164                 *ref_perf_reg, *ctr_wrap_reg;
1165         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1166         struct cppc_pcc_data *pcc_ss_data = NULL;
1167         u64 delivered, reference, ref_perf, ctr_wrap_time;
1168         int ret = 0, regs_in_pcc = 0;
1169
1170         if (!cpc_desc) {
1171                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1172                 return -ENODEV;
1173         }
1174
1175         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1176         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1177         ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1178         ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1179
1180         /*
1181          * If reference perf register is not supported then we should
1182          * use the nominal perf value
1183          */
1184         if (!CPC_SUPPORTED(ref_perf_reg))
1185                 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1186
1187         /* Are any of the regs PCC ?*/
1188         if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1189                 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1190                 if (pcc_ss_id < 0) {
1191                         pr_debug("Invalid pcc_ss_id\n");
1192                         return -ENODEV;
1193                 }
1194                 pcc_ss_data = pcc_data[pcc_ss_id];
1195                 down_write(&pcc_ss_data->pcc_lock);
1196                 regs_in_pcc = 1;
1197                 /* Ring doorbell once to update PCC subspace */
1198                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1199                         ret = -EIO;
1200                         goto out_err;
1201                 }
1202         }
1203
1204         cpc_read(cpunum, delivered_reg, &delivered);
1205         cpc_read(cpunum, reference_reg, &reference);
1206         cpc_read(cpunum, ref_perf_reg, &ref_perf);
1207
1208         /*
1209          * Per spec, if ctr_wrap_time optional register is unsupported, then the
1210          * performance counters are assumed to never wrap during the lifetime of
1211          * platform
1212          */
1213         ctr_wrap_time = (u64)(~((u64)0));
1214         if (CPC_SUPPORTED(ctr_wrap_reg))
1215                 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1216
1217         if (!delivered || !reference || !ref_perf) {
1218                 ret = -EFAULT;
1219                 goto out_err;
1220         }
1221
1222         perf_fb_ctrs->delivered = delivered;
1223         perf_fb_ctrs->reference = reference;
1224         perf_fb_ctrs->reference_perf = ref_perf;
1225         perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1226 out_err:
1227         if (regs_in_pcc)
1228                 up_write(&pcc_ss_data->pcc_lock);
1229         return ret;
1230 }
1231 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1232
1233 /**
1234  * cppc_set_perf - Set a CPU's performance controls.
1235  * @cpu: CPU for which to set performance controls.
1236  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1237  *
1238  * Return: 0 for success, -ERRNO otherwise.
1239  */
1240 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1241 {
1242         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1243         struct cpc_register_resource *desired_reg;
1244         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1245         struct cppc_pcc_data *pcc_ss_data = NULL;
1246         int ret = 0;
1247
1248         if (!cpc_desc) {
1249                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1250                 return -ENODEV;
1251         }
1252
1253         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1254
1255         /*
1256          * This is Phase-I where we want to write to CPC registers
1257          * -> We want all CPUs to be able to execute this phase in parallel
1258          *
1259          * Since read_lock can be acquired by multiple CPUs simultaneously we
1260          * achieve that goal here
1261          */
1262         if (CPC_IN_PCC(desired_reg)) {
1263                 if (pcc_ss_id < 0) {
1264                         pr_debug("Invalid pcc_ss_id\n");
1265                         return -ENODEV;
1266                 }
1267                 pcc_ss_data = pcc_data[pcc_ss_id];
1268                 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1269                 if (pcc_ss_data->platform_owns_pcc) {
1270                         ret = check_pcc_chan(pcc_ss_id, false);
1271                         if (ret) {
1272                                 up_read(&pcc_ss_data->pcc_lock);
1273                                 return ret;
1274                         }
1275                 }
1276                 /*
1277                  * Update the pending_write to make sure a PCC CMD_READ will not
1278                  * arrive and steal the channel during the switch to write lock
1279                  */
1280                 pcc_ss_data->pending_pcc_write_cmd = true;
1281                 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1282                 cpc_desc->write_cmd_status = 0;
1283         }
1284
1285         /*
1286          * Skip writing MIN/MAX until Linux knows how to come up with
1287          * useful values.
1288          */
1289         cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1290
1291         if (CPC_IN_PCC(desired_reg))
1292                 up_read(&pcc_ss_data->pcc_lock);        /* END Phase-I */
1293         /*
1294          * This is Phase-II where we transfer the ownership of PCC to Platform
1295          *
1296          * Short Summary: Basically if we think of a group of cppc_set_perf
1297          * requests that happened in short overlapping interval. The last CPU to
1298          * come out of Phase-I will enter Phase-II and ring the doorbell.
1299          *
1300          * We have the following requirements for Phase-II:
1301          *     1. We want to execute Phase-II only when there are no CPUs
1302          * currently executing in Phase-I
1303          *     2. Once we start Phase-II we want to avoid all other CPUs from
1304          * entering Phase-I.
1305          *     3. We want only one CPU among all those who went through Phase-I
1306          * to run phase-II
1307          *
1308          * If write_trylock fails to get the lock and doesn't transfer the
1309          * PCC ownership to the platform, then one of the following will be TRUE
1310          *     1. There is at-least one CPU in Phase-I which will later execute
1311          * write_trylock, so the CPUs in Phase-I will be responsible for
1312          * executing the Phase-II.
1313          *     2. Some other CPU has beaten this CPU to successfully execute the
1314          * write_trylock and has already acquired the write_lock. We know for a
1315          * fact it (other CPU acquiring the write_lock) couldn't have happened
1316          * before this CPU's Phase-I as we held the read_lock.
1317          *     3. Some other CPU executing pcc CMD_READ has stolen the
1318          * down_write, in which case, send_pcc_cmd will check for pending
1319          * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1320          * So this CPU can be certain that its request will be delivered
1321          *    So in all cases, this CPU knows that its request will be delivered
1322          * by another CPU and can return
1323          *
1324          * After getting the down_write we still need to check for
1325          * pending_pcc_write_cmd to take care of the following scenario
1326          *    The thread running this code could be scheduled out between
1327          * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1328          * could have delivered the request to Platform by triggering the
1329          * doorbell and transferred the ownership of PCC to platform. So this
1330          * avoids triggering an unnecessary doorbell and more importantly before
1331          * triggering the doorbell it makes sure that the PCC channel ownership
1332          * is still with OSPM.
1333          *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1334          * there was a pcc CMD_READ waiting on down_write and it steals the lock
1335          * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1336          * case during a CMD_READ and if there are pending writes it delivers
1337          * the write command before servicing the read command
1338          */
1339         if (CPC_IN_PCC(desired_reg)) {
1340                 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1341                         /* Update only if there are pending write commands */
1342                         if (pcc_ss_data->pending_pcc_write_cmd)
1343                                 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1344                         up_write(&pcc_ss_data->pcc_lock);       /* END Phase-II */
1345                 } else
1346                         /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1347                         wait_event(pcc_ss_data->pcc_write_wait_q,
1348                                    cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1349
1350                 /* send_pcc_cmd updates the status in case of failure */
1351                 ret = cpc_desc->write_cmd_status;
1352         }
1353         return ret;
1354 }
1355 EXPORT_SYMBOL_GPL(cppc_set_perf);
1356
1357 /**
1358  * cppc_get_transition_latency - returns frequency transition latency in ns
1359  *
1360  * ACPI CPPC does not explicitly specify how a platform can specify the
1361  * transition latency for performance change requests. The closest we have
1362  * is the timing information from the PCCT tables which provides the info
1363  * on the number and frequency of PCC commands the platform can handle.
1364  */
1365 unsigned int cppc_get_transition_latency(int cpu_num)
1366 {
1367         /*
1368          * Expected transition latency is based on the PCCT timing values
1369          * Below are definition from ACPI spec:
1370          * pcc_nominal- Expected latency to process a command, in microseconds
1371          * pcc_mpar   - The maximum number of periodic requests that the subspace
1372          *              channel can support, reported in commands per minute. 0
1373          *              indicates no limitation.
1374          * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1375          *              completion of a command before issuing the next command,
1376          *              in microseconds.
1377          */
1378         unsigned int latency_ns = 0;
1379         struct cpc_desc *cpc_desc;
1380         struct cpc_register_resource *desired_reg;
1381         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1382         struct cppc_pcc_data *pcc_ss_data;
1383
1384         cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1385         if (!cpc_desc)
1386                 return CPUFREQ_ETERNAL;
1387
1388         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1389         if (!CPC_IN_PCC(desired_reg))
1390                 return CPUFREQ_ETERNAL;
1391
1392         if (pcc_ss_id < 0)
1393                 return CPUFREQ_ETERNAL;
1394
1395         pcc_ss_data = pcc_data[pcc_ss_id];
1396         if (pcc_ss_data->pcc_mpar)
1397                 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1398
1399         latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1400         latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1401
1402         return latency_ns;
1403 }
1404 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);