drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/clk.h>
  15
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_gem_framebuffer_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "vc4_drv.h"
  25 #include "vc4_regs.h"
  26
  27 struct vc4_ctm_state {
  28         struct drm_private_state base;
  29         struct drm_color_ctm *ctm;
  30         int fifo;
  31 };
  32
  33 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  34 {
  35         return container_of(priv, struct vc4_ctm_state, base);
  36 }
  37
  38 struct vc4_load_tracker_state {
  39         struct drm_private_state base;
  40         u64 hvs_load;
  41         u64 membus_load;
  42 };
  43
  44 static struct vc4_load_tracker_state *
  45 to_vc4_load_tracker_state(struct drm_private_state *priv)
  46 {
  47         return container_of(priv, struct vc4_load_tracker_state, base);
  48 }
  49
  50 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  51                                                struct drm_private_obj *manager)
  52 {
  53         struct drm_device *dev = state->dev;
  54         struct vc4_dev *vc4 = to_vc4_dev(dev);
  55         struct drm_private_state *priv_state;
  56         int ret;
  57
  58         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  59         if (ret)
  60                 return ERR_PTR(ret);
  61
  62         priv_state = drm_atomic_get_private_obj_state(state, manager);
  63         if (IS_ERR(priv_state))
  64                 return ERR_CAST(priv_state);
  65
  66         return to_vc4_ctm_state(priv_state);
  67 }
  68
  69 static struct drm_private_state *
  70 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  71 {
  72         struct vc4_ctm_state *state;
  73
  74         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  75         if (!state)
  76                 return NULL;
  77
  78         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  79
  80         return &state->base;
  81 }
  82
  83 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
  84                                   struct drm_private_state *state)
  85 {
  86         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
  87
  88         kfree(ctm_state);
  89 }
  90
  91 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
  92         .atomic_duplicate_state = vc4_ctm_duplicate_state,
  93         .atomic_destroy_state = vc4_ctm_destroy_state,
  94 };
  95
  96 static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
  97 {
  98         struct vc4_dev *vc4 = to_vc4_dev(dev);
  99
 100         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 101 }
 102
 103 static int vc4_ctm_obj_init(struct vc4_dev *vc4)
 104 {
 105         struct vc4_ctm_state *ctm_state;
 106
 107         drm_modeset_lock_init(&vc4->ctm_state_lock);
 108
 109         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 110         if (!ctm_state)
 111                 return -ENOMEM;
 112
 113         drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
 114                                     &vc4_ctm_state_funcs);
 115
 116         return drmm_add_action(&vc4->base, vc4_ctm_obj_fini, NULL);
 117 }
 118
 119 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 120 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 121 {
 122         u16 r;
 123
 124         /* Sign bit. */
 125         r = in & BIT_ULL(63) ? BIT(9) : 0;
 126
 127         if ((in & GENMASK_ULL(62, 32)) > 0) {
 128                 /* We have zero integer bits so we can only saturate here. */
 129                 r |= GENMASK(8, 0);
 130         } else {
 131                 /* Otherwise take the 9 most important fractional bits. */
 132                 r |= (in >> 23) & GENMASK(8, 0);
 133         }
 134
 135         return r;
 136 }
 137
 138 static void
 139 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 140 {
 141         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 142         struct drm_color_ctm *ctm = ctm_state->ctm;
 143
 144         if (ctm_state->fifo) {
 145                 HVS_WRITE(SCALER_OLEDCOEF2,
 146                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 147                                         SCALER_OLEDCOEF2_R_TO_R) |
 148                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 149                                         SCALER_OLEDCOEF2_R_TO_G) |
 150                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 151                                         SCALER_OLEDCOEF2_R_TO_B));
 152                 HVS_WRITE(SCALER_OLEDCOEF1,
 153                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 154                                         SCALER_OLEDCOEF1_G_TO_R) |
 155                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 156                                         SCALER_OLEDCOEF1_G_TO_G) |
 157                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 158                                         SCALER_OLEDCOEF1_G_TO_B));
 159                 HVS_WRITE(SCALER_OLEDCOEF0,
 160                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 161                                         SCALER_OLEDCOEF0_B_TO_R) |
 162                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 163                                         SCALER_OLEDCOEF0_B_TO_G) |
 164                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 165                                         SCALER_OLEDCOEF0_B_TO_B));
 166         }
 167
 168         HVS_WRITE(SCALER_OLEDOFFS,
 169                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 170 }
 171
 172 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 173                                      struct drm_atomic_state *state)
 174 {
 175         struct drm_crtc_state *crtc_state;
 176         struct drm_crtc *crtc;
 177         unsigned int i;
 178
 179         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 180                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 181                 u32 dispctrl;
 182                 u32 dsp3_mux;
 183
 184                 if (!crtc_state->active)
 185                         continue;
 186
 187                 if (vc4_state->assigned_channel != 2)
 188                         continue;
 189
 190                 /*
 191                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 192                  * FIFO X'.
 193                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 194                  *
 195                  * DSP3 is connected to FIFO2 unless the transposer is
 196                  * enabled. In this case, FIFO 2 is directly accessed by the
 197                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 198                  * route.
 199                  */
 200                 if (vc4_state->feed_txp)
 201                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 202                 else
 203                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 204
 205                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 206                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 207                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 208         }
 209 }
 210
 211 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 212                                      struct drm_atomic_state *state)
 213 {
 214         struct drm_crtc_state *crtc_state;
 215         struct drm_crtc *crtc;
 216         unsigned char dsp2_mux = 0;
 217         unsigned char dsp3_mux = 3;
 218         unsigned char dsp4_mux = 3;
 219         unsigned char dsp5_mux = 3;
 220         unsigned int i;
 221         u32 reg;
 222
 223         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 224                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 225                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 226
 227                 if (!crtc_state->active)
 228                         continue;
 229
 230                 switch (vc4_crtc->data->hvs_output) {
 231                 case 2:
 232                         dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
 233                         break;
 234
 235                 case 3:
 236                         dsp3_mux = vc4_state->assigned_channel;
 237                         break;
 238
 239                 case 4:
 240                         dsp4_mux = vc4_state->assigned_channel;
 241                         break;
 242
 243                 case 5:
 244                         dsp5_mux = vc4_state->assigned_channel;
 245                         break;
 246
 247                 default:
 248                         break;
 249                 }
 250         }
 251
 252         reg = HVS_READ(SCALER_DISPECTRL);
 253         HVS_WRITE(SCALER_DISPECTRL,
 254                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 255                   VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
 256
 257         reg = HVS_READ(SCALER_DISPCTRL);
 258         HVS_WRITE(SCALER_DISPCTRL,
 259                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 260                   VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
 261
 262         reg = HVS_READ(SCALER_DISPEOLN);
 263         HVS_WRITE(SCALER_DISPEOLN,
 264                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 265                   VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
 266
 267         reg = HVS_READ(SCALER_DISPDITHER);
 268         HVS_WRITE(SCALER_DISPDITHER,
 269                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 270                   VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
 271 }
 272
 273 static void
 274 vc4_atomic_complete_commit(struct drm_atomic_state *state)
 275 {
 276         struct drm_device *dev = state->dev;
 277         struct vc4_dev *vc4 = to_vc4_dev(dev);
 278         struct vc4_hvs *hvs = vc4->hvs;
 279         struct drm_crtc_state *new_crtc_state;
 280         struct drm_crtc *crtc;
 281         int i;
 282
 283         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 284                 struct vc4_crtc_state *vc4_crtc_state;
 285
 286                 if (!new_crtc_state->commit)
 287                         continue;
 288
 289                 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
 290                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 291         }
 292
 293         if (vc4->hvs->hvs5)
 294                 clk_set_min_rate(hvs->core_clk, 500000000);
 295
 296         drm_atomic_helper_wait_for_fences(dev, state, false);
 297
 298         drm_atomic_helper_wait_for_dependencies(state);
 299
 300         drm_atomic_helper_commit_modeset_disables(dev, state);
 301
 302         vc4_ctm_commit(vc4, state);
 303
 304         if (vc4->hvs->hvs5)
 305                 vc5_hvs_pv_muxing_commit(vc4, state);
 306         else
 307                 vc4_hvs_pv_muxing_commit(vc4, state);
 308
 309         drm_atomic_helper_commit_planes(dev, state, 0);
 310
 311         drm_atomic_helper_commit_modeset_enables(dev, state);
 312
 313         drm_atomic_helper_fake_vblank(state);
 314
 315         drm_atomic_helper_commit_hw_done(state);
 316
 317         drm_atomic_helper_wait_for_flip_done(dev, state);
 318
 319         drm_atomic_helper_cleanup_planes(dev, state);
 320
 321         drm_atomic_helper_commit_cleanup_done(state);
 322
 323         if (vc4->hvs->hvs5)
 324                 clk_set_min_rate(hvs->core_clk, 0);
 325
 326         drm_atomic_state_put(state);
 327
 328         up(&vc4->async_modeset);
 329 }
 330
 331 static void commit_work(struct work_struct *work)
 332 {
 333         struct drm_atomic_state *state = container_of(work,
 334                                                       struct drm_atomic_state,
 335                                                       commit_work);
 336         vc4_atomic_complete_commit(state);
 337 }
 338
 339 /**
 340  * vc4_atomic_commit - commit validated state object
 341  * @dev: DRM device
 342  * @state: the driver state object
 343  * @nonblock: nonblocking commit
 344  *
 345  * This function commits a with drm_atomic_helper_check() pre-validated state
 346  * object. This can still fail when e.g. the framebuffer reservation fails. For
 347  * now this doesn't implement asynchronous commits.
 348  *
 349  * RETURNS
 350  * Zero for success or -errno.
 351  */
 352 static int vc4_atomic_commit(struct drm_device *dev,
 353                              struct drm_atomic_state *state,
 354                              bool nonblock)
 355 {
 356         struct vc4_dev *vc4 = to_vc4_dev(dev);
 357         int ret;
 358
 359         if (state->async_update) {
 360                 ret = down_interruptible(&vc4->async_modeset);
 361                 if (ret)
 362                         return ret;
 363
 364                 ret = drm_atomic_helper_prepare_planes(dev, state);
 365                 if (ret) {
 366                         up(&vc4->async_modeset);
 367                         return ret;
 368                 }
 369
 370                 drm_atomic_helper_async_commit(dev, state);
 371
 372                 drm_atomic_helper_cleanup_planes(dev, state);
 373
 374                 up(&vc4->async_modeset);
 375
 376                 return 0;
 377         }
 378
 379         /* We know for sure we don't want an async update here. Set
 380          * state->legacy_cursor_update to false to prevent
 381          * drm_atomic_helper_setup_commit() from auto-completing
 382          * commit->flip_done.
 383          */
 384         state->legacy_cursor_update = false;
 385         ret = drm_atomic_helper_setup_commit(state, nonblock);
 386         if (ret)
 387                 return ret;
 388
 389         INIT_WORK(&state->commit_work, commit_work);
 390
 391         ret = down_interruptible(&vc4->async_modeset);
 392         if (ret)
 393                 return ret;
 394
 395         ret = drm_atomic_helper_prepare_planes(dev, state);
 396         if (ret) {
 397                 up(&vc4->async_modeset);
 398                 return ret;
 399         }
 400
 401         if (!nonblock) {
 402                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
 403                 if (ret) {
 404                         drm_atomic_helper_cleanup_planes(dev, state);
 405                         up(&vc4->async_modeset);
 406                         return ret;
 407                 }
 408         }
 409
 410         /*
 411          * This is the point of no return - everything below never fails except
 412          * when the hw goes bonghits. Which means we can commit the new state on
 413          * the software side now.
 414          */
 415
 416         BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
 417
 418         /*
 419          * Everything below can be run asynchronously without the need to grab
 420          * any modeset locks at all under one condition: It must be guaranteed
 421          * that the asynchronous work has either been cancelled (if the driver
 422          * supports it, which at least requires that the framebuffers get
 423          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 424          * before the new state gets committed on the software side with
 425          * drm_atomic_helper_swap_state().
 426          *
 427          * This scheme allows new atomic state updates to be prepared and
 428          * checked in parallel to the asynchronous completion of the previous
 429          * update. Which is important since compositors need to figure out the
 430          * composition of the next frame right after having submitted the
 431          * current layout.
 432          */
 433
 434         drm_atomic_state_get(state);
 435         if (nonblock)
 436                 queue_work(system_unbound_wq, &state->commit_work);
 437         else
 438                 vc4_atomic_complete_commit(state);
 439
 440         return 0;
 441 }
 442
 443 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 444                                              struct drm_file *file_priv,
 445                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 446 {
 447         struct drm_mode_fb_cmd2 mode_cmd_local;
 448
 449         /* If the user didn't specify a modifier, use the
 450          * vc4_set_tiling_ioctl() state for the BO.
 451          */
 452         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 453                 struct drm_gem_object *gem_obj;
 454                 struct vc4_bo *bo;
 455
 456                 gem_obj = drm_gem_object_lookup(file_priv,
 457                                                 mode_cmd->handles[0]);
 458                 if (!gem_obj) {
 459                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 460                                   mode_cmd->handles[0]);
 461                         return ERR_PTR(-ENOENT);
 462                 }
 463                 bo = to_vc4_bo(gem_obj);
 464
 465                 mode_cmd_local = *mode_cmd;
 466
 467                 if (bo->t_format) {
 468                         mode_cmd_local.modifier[0] =
 469                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 470                 } else {
 471                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 472                 }
 473
 474                 drm_gem_object_put(gem_obj);
 475
 476                 mode_cmd = &mode_cmd_local;
 477         }
 478
 479         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 480 }
 481
 482 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 483  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 484  * we don't allow userland to set a CTM that we have no hope of approximating.
 485  */
 486 static int
 487 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 488 {
 489         struct vc4_dev *vc4 = to_vc4_dev(dev);
 490         struct vc4_ctm_state *ctm_state = NULL;
 491         struct drm_crtc *crtc;
 492         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 493         struct drm_color_ctm *ctm;
 494         int i;
 495
 496         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 497                 /* CTM is being disabled. */
 498                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 499                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 500                         if (IS_ERR(ctm_state))
 501                                 return PTR_ERR(ctm_state);
 502                         ctm_state->fifo = 0;
 503                 }
 504         }
 505
 506         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 507                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 508                         continue;
 509
 510                 if (!ctm_state) {
 511                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 512                         if (IS_ERR(ctm_state))
 513                                 return PTR_ERR(ctm_state);
 514                 }
 515
 516                 /* CTM is being enabled or the matrix changed. */
 517                 if (new_crtc_state->ctm) {
 518                         struct vc4_crtc_state *vc4_crtc_state =
 519                                 to_vc4_crtc_state(new_crtc_state);
 520
 521                         /* fifo is 1-based since 0 disables CTM. */
 522                         int fifo = vc4_crtc_state->assigned_channel + 1;
 523
 524                         /* Check userland isn't trying to turn on CTM for more
 525                          * than one CRTC at a time.
 526                          */
 527                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 528                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 529                                 return -EINVAL;
 530                         }
 531
 532                         /* Check we can approximate the specified CTM.
 533                          * We disallow scalars |c| > 1.0 since the HW has
 534                          * no integer bits.
 535                          */
 536                         ctm = new_crtc_state->ctm->data;
 537                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 538                                 u64 val = ctm->matrix[i];
 539
 540                                 val &= ~BIT_ULL(63);
 541                                 if (val > BIT_ULL(32))
 542                                         return -EINVAL;
 543                         }
 544
 545                         ctm_state->fifo = fifo;
 546                         ctm_state->ctm = ctm;
 547                 }
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 554 {
 555         struct drm_plane_state *old_plane_state, *new_plane_state;
 556         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 557         struct vc4_load_tracker_state *load_state;
 558         struct drm_private_state *priv_state;
 559         struct drm_plane *plane;
 560         int i;
 561
 562         if (!vc4->load_tracker_available)
 563                 return 0;
 564
 565         priv_state = drm_atomic_get_private_obj_state(state,
 566                                                       &vc4->load_tracker);
 567         if (IS_ERR(priv_state))
 568                 return PTR_ERR(priv_state);
 569
 570         load_state = to_vc4_load_tracker_state(priv_state);
 571         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 572                                        new_plane_state, i) {
 573                 struct vc4_plane_state *vc4_plane_state;
 574
 575                 if (old_plane_state->fb && old_plane_state->crtc) {
 576                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 577                         load_state->membus_load -= vc4_plane_state->membus_load;
 578                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 579                 }
 580
 581                 if (new_plane_state->fb && new_plane_state->crtc) {
 582                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 583                         load_state->membus_load += vc4_plane_state->membus_load;
 584                         load_state->hvs_load += vc4_plane_state->hvs_load;
 585                 }
 586         }
 587
 588         /* Don't check the load when the tracker is disabled. */
 589         if (!vc4->load_tracker_enabled)
 590                 return 0;
 591
 592         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 593          * the system work when other blocks are accessing the memory.
 594          */
 595         if (load_state->membus_load > SZ_1G + SZ_512M)
 596                 return -ENOSPC;
 597
 598         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 599          * consider the maximum number of cycles is 240M.
 600          */
 601         if (load_state->hvs_load > 240000000ULL)
 602                 return -ENOSPC;
 603
 604         return 0;
 605 }
 606
 607 static struct drm_private_state *
 608 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 609 {
 610         struct vc4_load_tracker_state *state;
 611
 612         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 613         if (!state)
 614                 return NULL;
 615
 616         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 617
 618         return &state->base;
 619 }
 620
 621 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 622                                            struct drm_private_state *state)
 623 {
 624         struct vc4_load_tracker_state *load_state;
 625
 626         load_state = to_vc4_load_tracker_state(state);
 627         kfree(load_state);
 628 }
 629
 630 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 631         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 632         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 633 };
 634
 635 static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
 636 {
 637         struct vc4_dev *vc4 = to_vc4_dev(dev);
 638
 639         if (!vc4->load_tracker_available)
 640                 return;
 641
 642         drm_atomic_private_obj_fini(&vc4->load_tracker);
 643 }
 644
 645 static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
 646 {
 647         struct vc4_load_tracker_state *load_state;
 648
 649         if (!vc4->load_tracker_available)
 650                 return 0;
 651
 652         load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 653         if (!load_state)
 654                 return -ENOMEM;
 655
 656         drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
 657                                     &load_state->base,
 658                                     &vc4_load_tracker_state_funcs);
 659
 660         return drmm_add_action(&vc4->base, vc4_load_tracker_obj_fini, NULL);
 661 }
 662
 663 #define NUM_OUTPUTS  6
 664 #define NUM_CHANNELS 3
 665
 666 static int
 667 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 668 {
 669         unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
 670         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 671         struct drm_crtc *crtc;
 672         int i, ret;
 673
 674         /*
 675          * Since the HVS FIFOs are shared across all the pixelvalves and
 676          * the TXP (and thus all the CRTCs), we need to pull the current
 677          * state of all the enabled CRTCs so that an update to a single
 678          * CRTC still keeps the previous FIFOs enabled and assigned to
 679          * the same CRTCs, instead of evaluating only the CRTC being
 680          * modified.
 681          */
 682         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 683                 struct drm_crtc_state *crtc_state;
 684
 685                 if (!crtc->state->enable)
 686                         continue;
 687
 688                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 689                 if (IS_ERR(crtc_state))
 690                         return PTR_ERR(crtc_state);
 691         }
 692
 693         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 694                 struct vc4_crtc_state *new_vc4_crtc_state =
 695                         to_vc4_crtc_state(new_crtc_state);
 696                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 697                 unsigned int matching_channels;
 698
 699                 if (old_crtc_state->enable && !new_crtc_state->enable)
 700                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 701
 702                 if (!new_crtc_state->enable)
 703                         continue;
 704
 705                 if (new_vc4_crtc_state->assigned_channel != VC4_HVS_CHANNEL_DISABLED) {
 706                         unassigned_channels &= ~BIT(new_vc4_crtc_state->assigned_channel);
 707                         continue;
 708                 }
 709
 710                 /*
 711                  * The problem we have to solve here is that we have
 712                  * up to 7 encoders, connected to up to 6 CRTCs.
 713                  *
 714                  * Those CRTCs, depending on the instance, can be
 715                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 716                  * the change the muxing between FIFOs and outputs in
 717                  * the HVS accordingly.
 718                  *
 719                  * It would be pretty hard to come up with an
 720                  * algorithm that would generically solve
 721                  * this. However, the current routing trees we support
 722                  * allow us to simplify a bit the problem.
 723                  *
 724                  * Indeed, with the current supported layouts, if we
 725                  * try to assign in the ascending crtc index order the
 726                  * FIFOs, we can't fall into the situation where an
 727                  * earlier CRTC that had multiple routes is assigned
 728                  * one that was the only option for a later CRTC.
 729                  *
 730                  * If the layout changes and doesn't give us that in
 731                  * the future, we will need to have something smarter,
 732                  * but it works so far.
 733                  */
 734                 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
 735                 if (matching_channels) {
 736                         unsigned int channel = ffs(matching_channels) - 1;
 737
 738                         new_vc4_crtc_state->assigned_channel = channel;
 739                         unassigned_channels &= ~BIT(channel);
 740                 } else {
 741                         return -EINVAL;
 742                 }
 743         }
 744
 745         ret = vc4_ctm_atomic_check(dev, state);
 746         if (ret < 0)
 747                 return ret;
 748
 749         ret = drm_atomic_helper_check(dev, state);
 750         if (ret)
 751                 return ret;
 752
 753         return vc4_load_tracker_atomic_check(state);
 754 }
 755
 756 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 757         .atomic_check = vc4_atomic_check,
 758         .atomic_commit = vc4_atomic_commit,
 759         .fb_create = vc4_fb_create,
 760 };
 761
 762 int vc4_kms_load(struct drm_device *dev)
 763 {
 764         struct vc4_dev *vc4 = to_vc4_dev(dev);
 765         bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
 766                                               "brcm,bcm2711-vc5");
 767         int ret;
 768
 769         if (!is_vc5) {
 770                 vc4->load_tracker_available = true;
 771
 772                 /* Start with the load tracker enabled. Can be
 773                  * disabled through the debugfs load_tracker file.
 774                  */
 775                 vc4->load_tracker_enabled = true;
 776         }
 777
 778         sema_init(&vc4->async_modeset, 1);
 779
 780         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 781         dev->vblank_disable_immediate = true;
 782
 783         dev->irq_enabled = true;
 784         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 785         if (ret < 0) {
 786                 dev_err(dev->dev, "failed to initialize vblank\n");
 787                 return ret;
 788         }
 789
 790         if (is_vc5) {
 791                 dev->mode_config.max_width = 7680;
 792                 dev->mode_config.max_height = 7680;
 793         } else {
 794                 dev->mode_config.max_width = 2048;
 795                 dev->mode_config.max_height = 2048;
 796         }
 797
 798         dev->mode_config.funcs = &vc4_mode_funcs;
 799         dev->mode_config.preferred_depth = 24;
 800         dev->mode_config.async_page_flip = true;
 801         dev->mode_config.allow_fb_modifiers = true;
 802
 803         ret = vc4_ctm_obj_init(vc4);
 804         if (ret)
 805                 return ret;
 806
 807         ret = vc4_load_tracker_obj_init(vc4);
 808         if (ret)
 809                 return ret;
 810
 811         drm_mode_config_reset(dev);
 812
 813         drm_kms_helper_poll_init(dev);
 814
 815         return 0;
 816 }