drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_cs.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "soc15_hw_ip.h"
  32 #include "vcn_v2_0.h"
  33 #include "mmsch_v4_0.h"
  34 #include "vcn_v4_0_5.h"
  35
  36 #include "vcn/vcn_4_0_5_offset.h"
  37 #include "vcn/vcn_4_0_5_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  39
  40 #include <drm/drm_drv.h>
  41
  42 #define mmUVD_DPG_LMA_CTL                                                       regUVD_DPG_LMA_CTL
  43 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                      regUVD_DPG_LMA_CTL_BASE_IDX
  44 #define mmUVD_DPG_LMA_DATA                                                      regUVD_DPG_LMA_DATA
  45 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                     regUVD_DPG_LMA_DATA_BASE_IDX
  46
  47 #define VCN_VID_SOC_ADDRESS_2_0                                         0x1fb00
  48 #define VCN1_VID_SOC_ADDRESS_3_0                                        (0x48300 + 0x38000)
  49
  50 #define VCN_HARVEST_MMSCH                                                       0
  51
  52 #define RDECODE_MSG_CREATE                                                      0x00000000
  53 #define RDECODE_MESSAGE_CREATE                                          0x00000001
  54
  55 static int amdgpu_ih_clientid_vcns[] = {
  56         SOC15_IH_CLIENTID_VCN,
  57         SOC15_IH_CLIENTID_VCN1
  58 };
  59
  60 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
  61 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
  62 static int vcn_v4_0_5_set_powergating_state(void *handle,
  63                 enum amd_powergating_state state);
  64 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
  65                 int inst_idx, struct dpg_pause_state *new_state);
  66 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);
  67
  68 /**
  69  * vcn_v4_0_5_early_init - set function pointers and load microcode
  70  *
  71  * @handle: amdgpu_device pointer
  72  *
  73  * Set ring and irq function pointers
  74  * Load microcode from filesystem
  75  */
  76 static int vcn_v4_0_5_early_init(void *handle)
  77 {
  78         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  79
  80         /* re-use enc ring as unified ring */
  81         adev->vcn.num_enc_rings = 1;
  82         vcn_v4_0_5_set_unified_ring_funcs(adev);
  83         vcn_v4_0_5_set_irq_funcs(adev);
  84
  85         return amdgpu_vcn_early_init(adev);
  86 }
  87
  88 /**
  89  * vcn_v4_0_5_sw_init - sw init for VCN block
  90  *
  91  * @handle: amdgpu_device pointer
  92  *
  93  * Load firmware and sw initialization
  94  */
  95 static int vcn_v4_0_5_sw_init(void *handle)
  96 {
  97         struct amdgpu_ring *ring;
  98         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  99         int i, r;
 100
 101         r = amdgpu_vcn_sw_init(adev);
 102         if (r)
 103                 return r;
 104
 105         amdgpu_vcn_setup_ucode(adev);
 106
 107         r = amdgpu_vcn_resume(adev);
 108         if (r)
 109                 return r;
 110
 111         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 112                 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 113
 114                 if (adev->vcn.harvest_config & (1 << i))
 115                         continue;
 116
 117                 atomic_set(&adev->vcn.inst[i].sched_score, 0);
 118
 119                 /* VCN UNIFIED TRAP */
 120                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 121                                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 122                 if (r)
 123                         return r;
 124
 125                 /* VCN POISON TRAP */
 126                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 127                                 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
 128                 if (r)
 129                         return r;
 130
 131                 ring = &adev->vcn.inst[i].ring_enc[0];
 132                 ring->use_doorbell = true;
 133                 if (amdgpu_sriov_vf(adev))
 134                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 135                                                 i * (adev->vcn.num_enc_rings + 1) + 1;
 136                 else
 137                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 138                                                 2 + 8 * i;
 139                 ring->vm_hub = AMDGPU_MMHUB0(0);
 140                 sprintf(ring->name, "vcn_unified_%d", i);
 141
 142                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 143                                 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
 144                 if (r)
 145                         return r;
 146
 147                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 148                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 149                 fw_shared->sq.is_enabled = 1;
 150
 151                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
 152                 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
 153                         AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
 154
 155                 if (amdgpu_sriov_vf(adev))
 156                         fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
 157
 158                 if (amdgpu_vcnfw_log)
 159                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 160         }
 161
 162         if (amdgpu_sriov_vf(adev)) {
 163                 r = amdgpu_virt_alloc_mm_table(adev);
 164                 if (r)
 165                         return r;
 166         }
 167
 168         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 169                 adev->vcn.pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;
 170
 171         return 0;
 172 }
 173
 174 /**
 175  * vcn_v4_0_5_sw_fini - sw fini for VCN block
 176  *
 177  * @handle: amdgpu_device pointer
 178  *
 179  * VCN suspend and free up sw allocation
 180  */
 181 static int vcn_v4_0_5_sw_fini(void *handle)
 182 {
 183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 184         int i, r, idx;
 185
 186         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 187                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 188                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 189
 190                         if (adev->vcn.harvest_config & (1 << i))
 191                                 continue;
 192
 193                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 194                         fw_shared->present_flag_0 = 0;
 195                         fw_shared->sq.is_enabled = 0;
 196                 }
 197
 198                 drm_dev_exit(idx);
 199         }
 200
 201         if (amdgpu_sriov_vf(adev))
 202                 amdgpu_virt_free_mm_table(adev);
 203
 204         r = amdgpu_vcn_suspend(adev);
 205         if (r)
 206                 return r;
 207
 208         r = amdgpu_vcn_sw_fini(adev);
 209
 210         return r;
 211 }
 212
 213 /**
 214  * vcn_v4_0_5_hw_init - start and test VCN block
 215  *
 216  * @handle: amdgpu_device pointer
 217  *
 218  * Initialize the hardware, boot up the VCPU and do some testing
 219  */
 220 static int vcn_v4_0_5_hw_init(void *handle)
 221 {
 222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 223         struct amdgpu_ring *ring;
 224         int i, r;
 225
 226         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 227                 if (adev->vcn.harvest_config & (1 << i))
 228                         continue;
 229
 230                 ring = &adev->vcn.inst[i].ring_enc[0];
 231
 232                 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 233                                 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
 234
 235                 r = amdgpu_ring_test_helper(ring);
 236                 if (r)
 237                         return r;
 238         }
 239
 240         return 0;
 241 }
 242
 243 /**
 244  * vcn_v4_0_5_hw_fini - stop the hardware block
 245  *
 246  * @handle: amdgpu_device pointer
 247  *
 248  * Stop the VCN block, mark ring as not ready any more
 249  */
 250 static int vcn_v4_0_5_hw_fini(void *handle)
 251 {
 252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 253         int i;
 254
 255         cancel_delayed_work_sync(&adev->vcn.idle_work);
 256
 257         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 258                 if (adev->vcn.harvest_config & (1 << i))
 259                         continue;
 260                 if (!amdgpu_sriov_vf(adev)) {
 261                         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 262                                 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 263                                 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
 264                                 vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
 265                         }
 266                 }
 267         }
 268
 269         return 0;
 270 }
 271
 272 /**
 273  * vcn_v4_0_5_suspend - suspend VCN block
 274  *
 275  * @handle: amdgpu_device pointer
 276  *
 277  * HW fini and suspend VCN block
 278  */
 279 static int vcn_v4_0_5_suspend(void *handle)
 280 {
 281         int r;
 282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 283
 284         r = vcn_v4_0_5_hw_fini(adev);
 285         if (r)
 286                 return r;
 287
 288         r = amdgpu_vcn_suspend(adev);
 289
 290         return r;
 291 }
 292
 293 /**
 294  * vcn_v4_0_5_resume - resume VCN block
 295  *
 296  * @handle: amdgpu_device pointer
 297  *
 298  * Resume firmware and hw init VCN block
 299  */
 300 static int vcn_v4_0_5_resume(void *handle)
 301 {
 302         int r;
 303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 304
 305         r = amdgpu_vcn_resume(adev);
 306         if (r)
 307                 return r;
 308
 309         r = vcn_v4_0_5_hw_init(adev);
 310
 311         return r;
 312 }
 313
 314 /**
 315  * vcn_v4_0_5_mc_resume - memory controller programming
 316  *
 317  * @adev: amdgpu_device pointer
 318  * @inst: instance number
 319  *
 320  * Let the VCN memory controller know it's offsets
 321  */
 322 static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)
 323 {
 324         uint32_t offset, size;
 325         const struct common_firmware_header *hdr;
 326
 327         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
 328         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 329
 330         /* cache window 0: fw */
 331         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 332                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 333                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 334                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 335                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 336                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 337                 offset = 0;
 338         } else {
 339                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 340                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 341                 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 342                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 343                 offset = size;
 344                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 345         }
 346         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
 347
 348         /* cache window 1: stack */
 349         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 350                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 351         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 352                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 353         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 354         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 355
 356         /* cache window 2: context */
 357         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 358                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 359         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 360                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 361         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 362         WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 363
 364         /* non-cache window */
 365         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 366                 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 367         WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 368                 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 369         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 370         WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
 371                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 372 }
 373
 374 /**
 375  * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode
 376  *
 377  * @adev: amdgpu_device pointer
 378  * @inst_idx: instance number index
 379  * @indirect: indirectly write sram
 380  *
 381  * Let the VCN memory controller know it's offsets with dpg mode
 382  */
 383 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 384 {
 385         uint32_t offset, size;
 386         const struct common_firmware_header *hdr;
 387
 388         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 389         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 390
 391         /* cache window 0: fw */
 392         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 393                 if (!indirect) {
 394                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 395                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 396                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo),
 397                         0, indirect);
 398                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 399                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 400                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi),
 401                         0, indirect);
 402                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 403                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 404                 } else {
 405                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 406                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 407                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 408                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 409                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 410                                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 411                 }
 412                 offset = 0;
 413         } else {
 414                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 415                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 416                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 417                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 418                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 419                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 420                 offset = size;
 421                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 422                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 423                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 424         }
 425
 426         if (!indirect)
 427                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 428                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 429         else
 430                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 431                         VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 432
 433         /* cache window 1: stack */
 434         if (!indirect) {
 435                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 436                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 437                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 438                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 439                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 440                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 441                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 442                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 443         } else {
 444                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 445                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 446                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 447                         VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 448                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 449                         VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 450         }
 451
 452         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 453                 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 454
 455         /* cache window 2: context */
 456         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 457                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 458                 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 459                 0, indirect);
 460         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 461                 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 462                 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 463                 0, indirect);
 464         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 465                 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 466         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 467                 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 468
 469         /* non-cache window */
 470         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 471                 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 472                 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 473         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 474                 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 475                 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 476         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 477                 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 478         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 479                 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
 480                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 481
 482         /* VCN global tiling registers */
 483         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 484                 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
 485                 adev->gfx.config.gb_addr_config, 0, indirect);
 486 }
 487
 488 /**
 489  * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating
 490  *
 491  * @adev: amdgpu_device pointer
 492  * @inst: instance number
 493  *
 494  * Disable static power gating for VCN block
 495  */
 496 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 497 {
 498         uint32_t data = 0;
 499
 500         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 501                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 502                                         1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT);
 503                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
 504                                         UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
 505                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 506                                         2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
 507                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 508                                         1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT,
 509                                         UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
 510                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 511                                         2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT);
 512                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 513                                         1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT,
 514                                         UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
 515                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 516                                         2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
 517                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 518                                         1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT,
 519                                         UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK);
 520         } else {
 521                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 522                         1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT);
 523                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 524                         0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
 525                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 526                         1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
 527                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 528                         0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
 529                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 530                         1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT);
 531                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 532                         0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
 533                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 534                         1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
 535                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 536                         0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK);
 537         }
 538
 539         data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 540         data &= ~0x103;
 541         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 542                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 543                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 544         WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 545 }
 546
 547 /**
 548  * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating
 549  *
 550  * @adev: amdgpu_device pointer
 551  * @inst: instance number
 552  *
 553  * Enable static power gating for VCN block
 554  */
 555 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 556 {
 557         uint32_t data;
 558
 559         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 560                 /* Before power off, this indicator has to be turned on */
 561                 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 562                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 563                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 564                 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
 565
 566                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 567                         2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
 568                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 569                         1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT,
 570                         UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK);
 571                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 572                         2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT);
 573                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 574                         1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT,
 575                         UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
 576                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 577                         2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
 578                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 579                         1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT,
 580                         UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
 581                 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
 582                         2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT);
 583                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
 584                         1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT,
 585                         UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
 586         }
 587 }
 588
 589 /**
 590  * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating
 591  *
 592  * @adev: amdgpu_device pointer
 593  * @inst: instance number
 594  *
 595  * Disable clock gating for VCN block
 596  */
 597 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
 598 {
 599         uint32_t data;
 600
 601         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 602                 return;
 603
 604         /* VCN disable CGC */
 605         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 606         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 607         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 608         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 609         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 610
 611         data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
 612         data &= ~(UVD_CGC_GATE__SYS_MASK
 613                 | UVD_CGC_GATE__UDEC_MASK
 614                 | UVD_CGC_GATE__MPEG2_MASK
 615                 | UVD_CGC_GATE__REGS_MASK
 616                 | UVD_CGC_GATE__RBC_MASK
 617                 | UVD_CGC_GATE__LMI_MC_MASK
 618                 | UVD_CGC_GATE__LMI_UMC_MASK
 619                 | UVD_CGC_GATE__IDCT_MASK
 620                 | UVD_CGC_GATE__MPRD_MASK
 621                 | UVD_CGC_GATE__MPC_MASK
 622                 | UVD_CGC_GATE__LBSI_MASK
 623                 | UVD_CGC_GATE__LRBBM_MASK
 624                 | UVD_CGC_GATE__UDEC_RE_MASK
 625                 | UVD_CGC_GATE__UDEC_CM_MASK
 626                 | UVD_CGC_GATE__UDEC_IT_MASK
 627                 | UVD_CGC_GATE__UDEC_DB_MASK
 628                 | UVD_CGC_GATE__UDEC_MP_MASK
 629                 | UVD_CGC_GATE__WCB_MASK
 630                 | UVD_CGC_GATE__VCPU_MASK
 631                 | UVD_CGC_GATE__MMSCH_MASK);
 632
 633         WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
 634         SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);
 635
 636         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 637         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 638                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 639                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 640                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 641                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 642                 | UVD_CGC_CTRL__SYS_MODE_MASK
 643                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 644                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 645                 | UVD_CGC_CTRL__REGS_MODE_MASK
 646                 | UVD_CGC_CTRL__RBC_MODE_MASK
 647                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 648                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 649                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 650                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 651                 | UVD_CGC_CTRL__MPC_MODE_MASK
 652                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 653                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 654                 | UVD_CGC_CTRL__WCB_MODE_MASK
 655                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 656                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 657         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 658
 659         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
 660         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 661                 | UVD_SUVD_CGC_GATE__SIT_MASK
 662                 | UVD_SUVD_CGC_GATE__SMP_MASK
 663                 | UVD_SUVD_CGC_GATE__SCM_MASK
 664                 | UVD_SUVD_CGC_GATE__SDB_MASK
 665                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 666                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 667                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 668                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 669                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 670                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 671                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 672                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 673                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 674                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 675                 | UVD_SUVD_CGC_GATE__ENT_MASK
 676                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 677                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 678                 | UVD_SUVD_CGC_GATE__SITE_MASK
 679                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 680                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 681                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 682                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 683                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 684         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
 685
 686         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 687         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 688                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 689                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 690                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 691                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 692                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 693                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 694                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 695                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 696                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 697         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 698 }
 699
 700 /**
 701  * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 702  *
 703  * @adev: amdgpu_device pointer
 704  * @sram_sel: sram select
 705  * @inst_idx: instance number index
 706  * @indirect: indirectly write sram
 707  *
 708  * Disable clock gating for VCN block with dpg mode
 709  */
 710 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 711                 int inst_idx, uint8_t indirect)
 712 {
 713         uint32_t reg_data = 0;
 714
 715         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 716                 return;
 717
 718         /* enable sw clock gating control */
 719         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 720         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 721         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 722         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 723                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 724                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 725                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 726                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 727                  UVD_CGC_CTRL__SYS_MODE_MASK |
 728                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 729                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 730                  UVD_CGC_CTRL__REGS_MODE_MASK |
 731                  UVD_CGC_CTRL__RBC_MODE_MASK |
 732                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 733                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 734                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 735                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 736                  UVD_CGC_CTRL__MPC_MODE_MASK |
 737                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 738                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 739                  UVD_CGC_CTRL__WCB_MODE_MASK |
 740                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 741         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 742                 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 743
 744         /* turn off clock gating */
 745         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 746                 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
 747
 748         /* turn on SUVD clock gating */
 749         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 750                 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 751
 752         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 753         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 754                 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 755 }
 756
 757 /**
 758  * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating
 759  *
 760  * @adev: amdgpu_device pointer
 761  * @inst: instance number
 762  *
 763  * Enable clock gating for VCN block
 764  */
 765 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
 766 {
 767         uint32_t data;
 768
 769         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 770                 return;
 771
 772         /* enable VCN CGC */
 773         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 774         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 775         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 776         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 777         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 778
 779         data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 780         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 781                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 782                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 783                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 784                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 785                 | UVD_CGC_CTRL__SYS_MODE_MASK
 786                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 787                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 788                 | UVD_CGC_CTRL__REGS_MODE_MASK
 789                 | UVD_CGC_CTRL__RBC_MODE_MASK
 790                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 791                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 792                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 793                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 794                 | UVD_CGC_CTRL__MPC_MODE_MASK
 795                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 796                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 797                 | UVD_CGC_CTRL__WCB_MODE_MASK
 798                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 799                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 800         WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
 801
 802         data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
 803         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 804                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 805                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 806                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 807                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 808                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 809                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 810                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 811                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 812                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 813         WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
 814 }
 815
 816 /**
 817  * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode
 818  *
 819  * @adev: amdgpu_device pointer
 820  * @inst_idx: instance number index
 821  * @indirect: indirectly write sram
 822  *
 823  * Start VCN block with dpg mode
 824  */
 825 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 826 {
 827         volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 828         struct amdgpu_ring *ring;
 829         uint32_t tmp;
 830
 831         /* disable register anti-hang mechanism */
 832         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
 833                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 834         /* enable dynamic power gating mode */
 835         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
 836         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 837         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 838         WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
 839
 840         if (indirect)
 841                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
 842                                         (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 843
 844         /* enable clock gating */
 845         vcn_v4_0_5_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 846
 847         /* enable VCPU clock */
 848         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 849         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
 850         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 851                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 852
 853         /* disable master interrupt */
 854         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 855                 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
 856
 857         /* setup regUVD_LMI_CTRL */
 858         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 859                 UVD_LMI_CTRL__REQ_MODE_MASK |
 860                 UVD_LMI_CTRL__CRC_RESET_MASK |
 861                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 862                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 863                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 864                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 865                 0x00100000L);
 866         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 867                 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
 868
 869         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 870                 VCN, inst_idx, regUVD_MPC_CNTL),
 871                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 872
 873         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 874                 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
 875                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 876                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 877                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 878                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 879
 880         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 881                 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
 882                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 883                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 884                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 885                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 886
 887         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 888                 VCN, inst_idx, regUVD_MPC_SET_MUX),
 889                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 890                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 891                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 892
 893         vcn_v4_0_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
 894
 895         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 896         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 897         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 898                 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
 899
 900         /* enable LMI MC and UMC channels */
 901         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
 902         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 903                 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
 904
 905         /* enable master interrupt */
 906         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 907                 VCN, inst_idx, regUVD_MASTINT_EN),
 908                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 909
 910         if (indirect)
 911                 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
 912
 913         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 914
 915         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
 916         WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 917         WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
 918
 919         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
 920         tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 921         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
 922         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
 923         WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
 924         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
 925
 926         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
 927         WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
 928         ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 929
 930         tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
 931         tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
 932         WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
 933         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 934
 935         WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
 936                         ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
 937                         VCN_RB1_DB_CTRL__EN_MASK);
 938
 939         return 0;
 940 }
 941
 942
 943 /**
 944  * vcn_v4_0_5_start - VCN start
 945  *
 946  * @adev: amdgpu_device pointer
 947  *
 948  * Start VCN block
 949  */
 950 static int vcn_v4_0_5_start(struct amdgpu_device *adev)
 951 {
 952         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 953         struct amdgpu_ring *ring;
 954         uint32_t tmp;
 955         int i, j, k, r;
 956
 957         if (adev->pm.dpm_enabled)
 958                 amdgpu_dpm_enable_uvd(adev, true);
 959
 960         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 961                 if (adev->vcn.harvest_config & (1 << i))
 962                         continue;
 963
 964                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 965
 966                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 967                         r = vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 968                         continue;
 969                 }
 970
 971                 /* disable VCN power gating */
 972                 vcn_v4_0_5_disable_static_power_gating(adev, i);
 973
 974                 /* set VCN status busy */
 975                 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 976                 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
 977
 978                 /*SW clock gating */
 979                 vcn_v4_0_5_disable_clock_gating(adev, i);
 980
 981                 /* enable VCPU clock */
 982                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
 983                                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 984
 985                 /* disable master interrupt */
 986                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
 987                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 988
 989                 /* enable LMI MC and UMC channels */
 990                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
 991                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 992
 993                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
 994                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 995                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 996                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
 997
 998                 /* setup regUVD_LMI_CTRL */
 999                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1000                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1001                                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1002                                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1003                                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1004                                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1005
1006                 /* setup regUVD_MPC_CNTL */
1007                 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1008                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1009                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1010                 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1011
1012                 /* setup UVD_MPC_SET_MUXA0 */
1013                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1014                                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1015                                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1016                                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1017                                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1018
1019                 /* setup UVD_MPC_SET_MUXB0 */
1020                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1021                                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1022                                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1023                                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1024                                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1025
1026                 /* setup UVD_MPC_SET_MUX */
1027                 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1028                                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1029                                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1030                                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1031
1032                 vcn_v4_0_5_mc_resume(adev, i);
1033
1034                 /* VCN global tiling registers */
1035                 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1036                                 adev->gfx.config.gb_addr_config);
1037
1038                 /* unblock VCPU register access */
1039                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1040                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1041
1042                 /* release VCPU reset to boot */
1043                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1044                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1045
1046                 for (j = 0; j < 10; ++j) {
1047                         uint32_t status;
1048
1049                         for (k = 0; k < 100; ++k) {
1050                                 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1051                                 if (status & 2)
1052                                         break;
1053                                 mdelay(10);
1054                                 if (amdgpu_emu_mode == 1)
1055                                         msleep(1);
1056                         }
1057
1058                         if (amdgpu_emu_mode == 1) {
1059                                 r = -1;
1060                                 if (status & 2) {
1061                                         r = 0;
1062                                         break;
1063                                 }
1064                         } else {
1065                                 r = 0;
1066                                 if (status & 2)
1067                                         break;
1068
1069                                 dev_err(adev->dev,
1070                                         "VCN[%d] is not responding, trying to reset VCPU!!!\n", i);
1071                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1072                                                         UVD_VCPU_CNTL__BLK_RST_MASK,
1073                                                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1074                                 mdelay(10);
1075                                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1076                                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1077
1078                                 mdelay(10);
1079                                 r = -1;
1080                         }
1081                 }
1082
1083                 if (r) {
1084                         dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1085                         return r;
1086                 }
1087
1088                 /* enable master interrupt */
1089                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1090                                 UVD_MASTINT_EN__VCPU_EN_MASK,
1091                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1092
1093                 /* clear the busy bit of VCN_STATUS */
1094                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1095                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1096
1097                 ring = &adev->vcn.inst[i].ring_enc[0];
1098                 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1099                                 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1100                                 VCN_RB1_DB_CTRL__EN_MASK);
1101
1102                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1103                 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1104                 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1105
1106                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1107                 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1108                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1109                 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1110                 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1111                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1112
1113                 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1114                 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1115                 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1116
1117                 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1118                 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1119                 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1120                 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1121         }
1122
1123         return 0;
1124 }
1125
1126 /**
1127  * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode
1128  *
1129  * @adev: amdgpu_device pointer
1130  * @inst_idx: instance number index
1131  *
1132  * Stop VCN block with dpg mode
1133  */
1134 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1135 {
1136         uint32_t tmp;
1137
1138         /* Wait for power status to be 1 */
1139         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1140                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1141
1142         /* wait for read ptr to be equal to write ptr */
1143         tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1144         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1145
1146         SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1147                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1148
1149         /* disable dynamic power gating mode */
1150         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1151                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1152 }
1153
1154 /**
1155  * vcn_v4_0_5_stop - VCN stop
1156  *
1157  * @adev: amdgpu_device pointer
1158  *
1159  * Stop VCN block
1160  */
1161 static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
1162 {
1163         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1164         uint32_t tmp;
1165         int i, r = 0;
1166
1167         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1168                 if (adev->vcn.harvest_config & (1 << i))
1169                         continue;
1170
1171                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1172                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1173
1174                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1175                         vcn_v4_0_5_stop_dpg_mode(adev, i);
1176                         continue;
1177                 }
1178
1179                 /* wait for vcn idle */
1180                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1181                 if (r)
1182                         return r;
1183
1184                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1185                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1186                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1187                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1188                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1189                 if (r)
1190                         return r;
1191
1192                 /* disable LMI UMC channel */
1193                 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1194                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1195                 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1196                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1197                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1198                 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1199                 if (r)
1200                         return r;
1201
1202                 /* block VCPU register access */
1203                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1204                                 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1205                                 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1206
1207                 /* reset VCPU */
1208                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1209                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1210                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1211
1212                 /* disable VCPU clock */
1213                 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1214                                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1215
1216                 /* apply soft reset */
1217                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1218                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1219                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1220                 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1221                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1222                 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1223
1224                 /* clear status */
1225                 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1226
1227                 /* apply HW clock gating */
1228                 vcn_v4_0_5_enable_clock_gating(adev, i);
1229
1230                 /* enable VCN power gating */
1231                 vcn_v4_0_5_enable_static_power_gating(adev, i);
1232         }
1233
1234         if (adev->pm.dpm_enabled)
1235                 amdgpu_dpm_enable_uvd(adev, false);
1236
1237         return 0;
1238 }
1239
1240 /**
1241  * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode
1242  *
1243  * @adev: amdgpu_device pointer
1244  * @inst_idx: instance number index
1245  * @new_state: pause state
1246  *
1247  * Pause dpg mode for VCN block
1248  */
1249 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1250                 struct dpg_pause_state *new_state)
1251 {
1252         uint32_t reg_data = 0;
1253         int ret_code;
1254
1255         /* pause/unpause if state is changed */
1256         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1257                 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1258                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1259                 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1260                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1261
1262                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1263                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1264                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1265
1266                         if (!ret_code) {
1267                                 /* pause DPG */
1268                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1269                                 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1270
1271                                 /* wait for ACK */
1272                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1273                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1274                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1275
1276                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1277                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1278                                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1279                         }
1280                 } else {
1281                         /* unpause dpg, no need to wait */
1282                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1283                         WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1284                 }
1285                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1286         }
1287
1288         return 0;
1289 }
1290
1291 /**
1292  * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer
1293  *
1294  * @ring: amdgpu_ring pointer
1295  *
1296  * Returns the current hardware unified read pointer
1297  */
1298 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring)
1299 {
1300         struct amdgpu_device *adev = ring->adev;
1301
1302         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1303                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1304
1305         return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1306 }
1307
1308 /**
1309  * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer
1310  *
1311  * @ring: amdgpu_ring pointer
1312  *
1313  * Returns the current hardware unified write pointer
1314  */
1315 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring)
1316 {
1317         struct amdgpu_device *adev = ring->adev;
1318
1319         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1320                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1321
1322         if (ring->use_doorbell)
1323                 return *ring->wptr_cpu_addr;
1324         else
1325                 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1326 }
1327
1328 /**
1329  * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer
1330  *
1331  * @ring: amdgpu_ring pointer
1332  *
1333  * Commits the enc write pointer to the hardware
1334  */
1335 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring)
1336 {
1337         struct amdgpu_device *adev = ring->adev;
1338
1339         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1340                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1341
1342         if (ring->use_doorbell) {
1343                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1344                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1345         } else {
1346                 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1347         }
1348 }
1349
1350 static int vcn_v4_0_5_limit_sched(struct amdgpu_cs_parser *p,
1351                                 struct amdgpu_job *job)
1352 {
1353         struct drm_gpu_scheduler **scheds;
1354
1355         /* The create msg must be in the first IB submitted */
1356         if (atomic_read(&job->base.entity->fence_seq))
1357                 return -EINVAL;
1358
1359         /* if VCN0 is harvested, we can't support AV1 */
1360         if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1361                 return -EINVAL;
1362
1363         scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1364                 [AMDGPU_RING_PRIO_0].sched;
1365         drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1366         return 0;
1367 }
1368
1369 static int vcn_v4_0_5_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1370                             uint64_t addr)
1371 {
1372         struct ttm_operation_ctx ctx = { false, false };
1373         struct amdgpu_bo_va_mapping *map;
1374         uint32_t *msg, num_buffers;
1375         struct amdgpu_bo *bo;
1376         uint64_t start, end;
1377         unsigned int i;
1378         void *ptr;
1379         int r;
1380
1381         addr &= AMDGPU_GMC_HOLE_MASK;
1382         r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1383         if (r) {
1384                 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
1385                 return r;
1386         }
1387
1388         start = map->start * AMDGPU_GPU_PAGE_SIZE;
1389         end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1390         if (addr & 0x7) {
1391                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1392                 return -EINVAL;
1393         }
1394
1395         bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1396         amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1397         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1398         if (r) {
1399                 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1400                 return r;
1401         }
1402
1403         r = amdgpu_bo_kmap(bo, &ptr);
1404         if (r) {
1405                 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1406                 return r;
1407         }
1408
1409         msg = ptr + addr - start;
1410
1411         /* Check length */
1412         if (msg[1] > end - addr) {
1413                 r = -EINVAL;
1414                 goto out;
1415         }
1416
1417         if (msg[3] != RDECODE_MSG_CREATE)
1418                 goto out;
1419
1420         num_buffers = msg[2];
1421         for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1422                 uint32_t offset, size, *create;
1423
1424                 if (msg[0] != RDECODE_MESSAGE_CREATE)
1425                         continue;
1426
1427                 offset = msg[1];
1428                 size = msg[2];
1429
1430                 if (offset + size > end) {
1431                         r = -EINVAL;
1432                         goto out;
1433                 }
1434
1435                 create = ptr + addr + offset - start;
1436
1437                 /* H264, HEVC and VP9 can run on any instance */
1438                 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1439                         continue;
1440
1441                 r = vcn_v4_0_5_limit_sched(p, job);
1442                 if (r)
1443                         goto out;
1444         }
1445
1446 out:
1447         amdgpu_bo_kunmap(bo);
1448         return r;
1449 }
1450
1451 #define RADEON_VCN_ENGINE_TYPE_ENCODE                   (0x00000002)
1452 #define RADEON_VCN_ENGINE_TYPE_DECODE                   (0x00000003)
1453
1454 #define RADEON_VCN_ENGINE_INFO                          (0x30000001)
1455 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET               16
1456
1457 #define RENCODE_ENCODE_STANDARD_AV1                     2
1458 #define RENCODE_IB_PARAM_SESSION_INIT                   0x00000003
1459 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET        64
1460
1461 /* return the offset in ib if id is found, -1 otherwise
1462  * to speed up the searching we only search upto max_offset
1463  */
1464 static int vcn_v4_0_5_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1465 {
1466         int i;
1467
1468         for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1469                 if (ib->ptr[i + 1] == id)
1470                         return i;
1471         }
1472         return -1;
1473 }
1474
1475 static int vcn_v4_0_5_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1476                                            struct amdgpu_job *job,
1477                                            struct amdgpu_ib *ib)
1478 {
1479         struct amdgpu_ring *ring = amdgpu_job_ring(job);
1480         struct amdgpu_vcn_decode_buffer *decode_buffer;
1481         uint64_t addr;
1482         uint32_t val;
1483         int idx;
1484
1485         /* The first instance can decode anything */
1486         if (!ring->me)
1487                 return 0;
1488
1489         /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1490         idx = vcn_v4_0_5_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1491                         RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1492         if (idx < 0) /* engine info is missing */
1493                 return 0;
1494
1495         val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1496         if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1497                 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
1498
1499                 if (!(decode_buffer->valid_buf_flag  & 0x1))
1500                         return 0;
1501
1502                 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1503                         decode_buffer->msg_buffer_address_lo;
1504                 return vcn_v4_0_5_dec_msg(p, job, addr);
1505         } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1506                 idx = vcn_v4_0_5_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1507                         RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1508                 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1509                         return vcn_v4_0_5_limit_sched(p, job);
1510         }
1511         return 0;
1512 }
1513
1514 static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
1515         .type = AMDGPU_RING_TYPE_VCN_ENC,
1516         .align_mask = 0x3f,
1517         .nop = VCN_ENC_CMD_NO_OP,
1518         .get_rptr = vcn_v4_0_5_unified_ring_get_rptr,
1519         .get_wptr = vcn_v4_0_5_unified_ring_get_wptr,
1520         .set_wptr = vcn_v4_0_5_unified_ring_set_wptr,
1521         .patch_cs_in_place = vcn_v4_0_5_ring_patch_cs_in_place,
1522         .emit_frame_size =
1523                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1524                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1525                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1526                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1527                 1, /* vcn_v2_0_enc_ring_insert_end */
1528         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1529         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1530         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1531         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1532         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1533         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1534         .insert_nop = amdgpu_ring_insert_nop,
1535         .insert_end = vcn_v2_0_enc_ring_insert_end,
1536         .pad_ib = amdgpu_ring_generic_pad_ib,
1537         .begin_use = amdgpu_vcn_ring_begin_use,
1538         .end_use = amdgpu_vcn_ring_end_use,
1539         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1540         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1541         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1542 };
1543
1544 /**
1545  * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions
1546  *
1547  * @adev: amdgpu_device pointer
1548  *
1549  * Set unified ring functions
1550  */
1551 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
1552 {
1553         int i;
1554
1555         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1556                 if (adev->vcn.harvest_config & (1 << i))
1557                         continue;
1558
1559                 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;
1560                 adev->vcn.inst[i].ring_enc[0].me = i;
1561         }
1562 }
1563
1564 /**
1565  * vcn_v4_0_5_is_idle - check VCN block is idle
1566  *
1567  * @handle: amdgpu_device pointer
1568  *
1569  * Check whether VCN block is idle
1570  */
1571 static bool vcn_v4_0_5_is_idle(void *handle)
1572 {
1573         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1574         int i, ret = 1;
1575
1576         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1577                 if (adev->vcn.harvest_config & (1 << i))
1578                         continue;
1579
1580                 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1581         }
1582
1583         return ret;
1584 }
1585
1586 /**
1587  * vcn_v4_0_5_wait_for_idle - wait for VCN block idle
1588  *
1589  * @handle: amdgpu_device pointer
1590  *
1591  * Wait for VCN block idle
1592  */
1593 static int vcn_v4_0_5_wait_for_idle(void *handle)
1594 {
1595         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1596         int i, ret = 0;
1597
1598         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1599                 if (adev->vcn.harvest_config & (1 << i))
1600                         continue;
1601
1602                 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1603                         UVD_STATUS__IDLE);
1604                 if (ret)
1605                         return ret;
1606         }
1607
1608         return ret;
1609 }
1610
1611 /**
1612  * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state
1613  *
1614  * @handle: amdgpu_device pointer
1615  * @state: clock gating state
1616  *
1617  * Set VCN block clockgating state
1618  */
1619 static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_state state)
1620 {
1621         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1622         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1623         int i;
1624
1625         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1626                 if (adev->vcn.harvest_config & (1 << i))
1627                         continue;
1628
1629                 if (enable) {
1630                         if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
1631                                 return -EBUSY;
1632                         vcn_v4_0_5_enable_clock_gating(adev, i);
1633                 } else {
1634                         vcn_v4_0_5_disable_clock_gating(adev, i);
1635                 }
1636         }
1637
1638         return 0;
1639 }
1640
1641 /**
1642  * vcn_v4_0_5_set_powergating_state - set VCN block powergating state
1643  *
1644  * @handle: amdgpu_device pointer
1645  * @state: power gating state
1646  *
1647  * Set VCN block powergating state
1648  */
1649 static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
1650 {
1651         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1652         int ret;
1653
1654         if (state == adev->vcn.cur_state)
1655                 return 0;
1656
1657         if (state == AMD_PG_STATE_GATE)
1658                 ret = vcn_v4_0_5_stop(adev);
1659         else
1660                 ret = vcn_v4_0_5_start(adev);
1661
1662         if (!ret)
1663                 adev->vcn.cur_state = state;
1664
1665         return ret;
1666 }
1667
1668 /**
1669  * vcn_v4_0_5_process_interrupt - process VCN block interrupt
1670  *
1671  * @adev: amdgpu_device pointer
1672  * @source: interrupt sources
1673  * @entry: interrupt entry from clients and sources
1674  *
1675  * Process VCN block interrupt
1676  */
1677 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1678                 struct amdgpu_iv_entry *entry)
1679 {
1680         uint32_t ip_instance;
1681
1682         switch (entry->client_id) {
1683         case SOC15_IH_CLIENTID_VCN:
1684                 ip_instance = 0;
1685                 break;
1686         case SOC15_IH_CLIENTID_VCN1:
1687                 ip_instance = 1;
1688                 break;
1689         default:
1690                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1691                 return 0;
1692         }
1693
1694         DRM_DEBUG("IH: VCN TRAP\n");
1695
1696         switch (entry->src_id) {
1697         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1698                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1699                 break;
1700         case VCN_4_0__SRCID_UVD_POISON:
1701                 amdgpu_vcn_process_poison_irq(adev, source, entry);
1702                 break;
1703         default:
1704                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1705                           entry->src_id, entry->src_data[0]);
1706                 break;
1707         }
1708
1709         return 0;
1710 }
1711
1712 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = {
1713         .process = vcn_v4_0_5_process_interrupt,
1714 };
1715
1716 /**
1717  * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions
1718  *
1719  * @adev: amdgpu_device pointer
1720  *
1721  * Set VCN block interrupt irq functions
1722  */
1723 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
1724 {
1725         int i;
1726
1727         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1728                 if (adev->vcn.harvest_config & (1 << i))
1729                         continue;
1730
1731                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1732                 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs;
1733         }
1734 }
1735
1736 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
1737         .name = "vcn_v4_0_5",
1738         .early_init = vcn_v4_0_5_early_init,
1739         .late_init = NULL,
1740         .sw_init = vcn_v4_0_5_sw_init,
1741         .sw_fini = vcn_v4_0_5_sw_fini,
1742         .hw_init = vcn_v4_0_5_hw_init,
1743         .hw_fini = vcn_v4_0_5_hw_fini,
1744         .suspend = vcn_v4_0_5_suspend,
1745         .resume = vcn_v4_0_5_resume,
1746         .is_idle = vcn_v4_0_5_is_idle,
1747         .wait_for_idle = vcn_v4_0_5_wait_for_idle,
1748         .check_soft_reset = NULL,
1749         .pre_soft_reset = NULL,
1750         .soft_reset = NULL,
1751         .post_soft_reset = NULL,
1752         .set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
1753         .set_powergating_state = vcn_v4_0_5_set_powergating_state,
1754         .dump_ip_state = NULL,
1755         .print_ip_state = NULL,
1756 };
1757
1758 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
1759         .type = AMD_IP_BLOCK_TYPE_VCN,
1760         .major = 4,
1761         .minor = 0,
1762         .rev = 5,
1763         .funcs = &vcn_v4_0_5_ip_funcs,
1764 };