drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drm_drv.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_vcn.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15.h"
  31 #include "soc15d.h"
  32 #include "soc15_hw_ip.h"
  33 #include "vcn_v2_0.h"
  34 #include "mmsch_v4_0_3.h"
  35
  36 #include "vcn/vcn_4_0_3_offset.h"
  37 #include "vcn/vcn_4_0_3_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  39
  40 #define mmUVD_DPG_LMA_CTL               regUVD_DPG_LMA_CTL
  41 #define mmUVD_DPG_LMA_CTL_BASE_IDX      regUVD_DPG_LMA_CTL_BASE_IDX
  42 #define mmUVD_DPG_LMA_DATA              regUVD_DPG_LMA_DATA
  43 #define mmUVD_DPG_LMA_DATA_BASE_IDX     regUVD_DPG_LMA_DATA_BASE_IDX
  44
  45 #define VCN_VID_SOC_ADDRESS_2_0         0x1fb00
  46 #define VCN1_VID_SOC_ADDRESS_3_0        0x48300
  47
  48 #define NORMALIZE_VCN_REG_OFFSET(offset) \
  49                 (offset & 0x1FFFF)
  50
  51 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
  52 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
  53 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
  54 static int vcn_v4_0_3_set_powergating_state(void *handle,
  55                 enum amd_powergating_state state);
  56 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
  57                 int inst_idx, struct dpg_pause_state *new_state);
  58 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);
  59 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
  60 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
  61                                   int inst_idx, bool indirect);
  62 /**
  63  * vcn_v4_0_3_early_init - set function pointers
  64  *
  65  * @handle: amdgpu_device pointer
  66  *
  67  * Set ring and irq function pointers
  68  */
  69 static int vcn_v4_0_3_early_init(void *handle)
  70 {
  71         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  72
  73         /* re-use enc ring as unified ring */
  74         adev->vcn.num_enc_rings = 1;
  75
  76         vcn_v4_0_3_set_unified_ring_funcs(adev);
  77         vcn_v4_0_3_set_irq_funcs(adev);
  78         vcn_v4_0_3_set_ras_funcs(adev);
  79
  80         return amdgpu_vcn_early_init(adev);
  81 }
  82
  83 /**
  84  * vcn_v4_0_3_sw_init - sw init for VCN block
  85  *
  86  * @handle: amdgpu_device pointer
  87  *
  88  * Load firmware and sw initialization
  89  */
  90 static int vcn_v4_0_3_sw_init(void *handle)
  91 {
  92         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  93         struct amdgpu_ring *ring;
  94         int i, r, vcn_inst;
  95
  96         r = amdgpu_vcn_sw_init(adev);
  97         if (r)
  98                 return r;
  99
 100         amdgpu_vcn_setup_ucode(adev);
 101
 102         r = amdgpu_vcn_resume(adev);
 103         if (r)
 104                 return r;
 105
 106         /* VCN DEC TRAP */
 107         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
 108                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
 109         if (r)
 110                 return r;
 111
 112         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 113                 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 114
 115                 vcn_inst = GET_INST(VCN, i);
 116
 117                 ring = &adev->vcn.inst[i].ring_enc[0];
 118                 ring->use_doorbell = true;
 119
 120                 if (!amdgpu_sriov_vf(adev))
 121                         ring->doorbell_index =
 122                                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 123                                 9 * vcn_inst;
 124                 else
 125                         ring->doorbell_index =
 126                                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 127                                 32 * vcn_inst;
 128
 129                 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
 130                 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
 131                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 132                                      AMDGPU_RING_PRIO_DEFAULT,
 133                                      &adev->vcn.inst[i].sched_score);
 134                 if (r)
 135                         return r;
 136
 137                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 138                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 139                 fw_shared->sq.is_enabled = true;
 140
 141                 if (amdgpu_vcnfw_log)
 142                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 143         }
 144
 145         if (amdgpu_sriov_vf(adev)) {
 146                 r = amdgpu_virt_alloc_mm_table(adev);
 147                 if (r)
 148                         return r;
 149         }
 150
 151         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 152                 adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
 153
 154         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
 155                 r = amdgpu_vcn_ras_sw_init(adev);
 156                 if (r) {
 157                         dev_err(adev->dev, "Failed to initialize vcn ras block!\n");
 158                         return r;
 159                 }
 160         }
 161
 162         return 0;
 163 }
 164
 165 /**
 166  * vcn_v4_0_3_sw_fini - sw fini for VCN block
 167  *
 168  * @handle: amdgpu_device pointer
 169  *
 170  * VCN suspend and free up sw allocation
 171  */
 172 static int vcn_v4_0_3_sw_fini(void *handle)
 173 {
 174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 175         int i, r, idx;
 176
 177         if (drm_dev_enter(&adev->ddev, &idx)) {
 178                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 179                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 180
 181                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 182                         fw_shared->present_flag_0 = 0;
 183                         fw_shared->sq.is_enabled = cpu_to_le32(false);
 184                 }
 185                 drm_dev_exit(idx);
 186         }
 187
 188         if (amdgpu_sriov_vf(adev))
 189                 amdgpu_virt_free_mm_table(adev);
 190
 191         r = amdgpu_vcn_suspend(adev);
 192         if (r)
 193                 return r;
 194
 195         r = amdgpu_vcn_sw_fini(adev);
 196
 197         return r;
 198 }
 199
 200 /**
 201  * vcn_v4_0_3_hw_init - start and test VCN block
 202  *
 203  * @handle: amdgpu_device pointer
 204  *
 205  * Initialize the hardware, boot up the VCPU and do some testing
 206  */
 207 static int vcn_v4_0_3_hw_init(void *handle)
 208 {
 209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 210         struct amdgpu_ring *ring;
 211         int i, r, vcn_inst;
 212
 213         if (amdgpu_sriov_vf(adev)) {
 214                 r = vcn_v4_0_3_start_sriov(adev);
 215                 if (r)
 216                         return r;
 217
 218                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 219                         ring = &adev->vcn.inst[i].ring_enc[0];
 220                         ring->wptr = 0;
 221                         ring->wptr_old = 0;
 222                         vcn_v4_0_3_unified_ring_set_wptr(ring);
 223                         ring->sched.ready = true;
 224                 }
 225         } else {
 226                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 227                         vcn_inst = GET_INST(VCN, i);
 228                         ring = &adev->vcn.inst[i].ring_enc[0];
 229
 230                         if (ring->use_doorbell) {
 231                                 adev->nbio.funcs->vcn_doorbell_range(
 232                                         adev, ring->use_doorbell,
 233                                         (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 234                                                 9 * vcn_inst,
 235                                         adev->vcn.inst[i].aid_id);
 236
 237                                 WREG32_SOC15(
 238                                         VCN, GET_INST(VCN, ring->me),
 239                                         regVCN_RB1_DB_CTRL,
 240                                         ring->doorbell_index
 241                                                         << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
 242                                                 VCN_RB1_DB_CTRL__EN_MASK);
 243
 244                                 /* Read DB_CTRL to flush the write DB_CTRL command. */
 245                                 RREG32_SOC15(
 246                                         VCN, GET_INST(VCN, ring->me),
 247                                         regVCN_RB1_DB_CTRL);
 248                         }
 249
 250                         r = amdgpu_ring_test_helper(ring);
 251                         if (r)
 252                                 return r;
 253                 }
 254         }
 255
 256         return r;
 257 }
 258
 259 /**
 260  * vcn_v4_0_3_hw_fini - stop the hardware block
 261  *
 262  * @handle: amdgpu_device pointer
 263  *
 264  * Stop the VCN block, mark ring as not ready any more
 265  */
 266 static int vcn_v4_0_3_hw_fini(void *handle)
 267 {
 268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 269
 270         cancel_delayed_work_sync(&adev->vcn.idle_work);
 271
 272         if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
 273                 vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
 274
 275         return 0;
 276 }
 277
 278 /**
 279  * vcn_v4_0_3_suspend - suspend VCN block
 280  *
 281  * @handle: amdgpu_device pointer
 282  *
 283  * HW fini and suspend VCN block
 284  */
 285 static int vcn_v4_0_3_suspend(void *handle)
 286 {
 287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 288         int r;
 289
 290         r = vcn_v4_0_3_hw_fini(adev);
 291         if (r)
 292                 return r;
 293
 294         r = amdgpu_vcn_suspend(adev);
 295
 296         return r;
 297 }
 298
 299 /**
 300  * vcn_v4_0_3_resume - resume VCN block
 301  *
 302  * @handle: amdgpu_device pointer
 303  *
 304  * Resume firmware and hw init VCN block
 305  */
 306 static int vcn_v4_0_3_resume(void *handle)
 307 {
 308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 309         int r;
 310
 311         r = amdgpu_vcn_resume(adev);
 312         if (r)
 313                 return r;
 314
 315         r = vcn_v4_0_3_hw_init(adev);
 316
 317         return r;
 318 }
 319
 320 /**
 321  * vcn_v4_0_3_mc_resume - memory controller programming
 322  *
 323  * @adev: amdgpu_device pointer
 324  * @inst_idx: instance number
 325  *
 326  * Let the VCN memory controller know it's offsets
 327  */
 328 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)
 329 {
 330         uint32_t offset, size, vcn_inst;
 331         const struct common_firmware_header *hdr;
 332
 333         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 334         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 335
 336         vcn_inst = GET_INST(VCN, inst_idx);
 337         /* cache window 0: fw */
 338         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 339                 WREG32_SOC15(
 340                         VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 341                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx]
 342                                  .tmr_mc_addr_lo));
 343                 WREG32_SOC15(
 344                         VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 345                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx]
 346                                  .tmr_mc_addr_hi));
 347                 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 348                 offset = 0;
 349         } else {
 350                 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 351                              lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
 352                 WREG32_SOC15(VCN, vcn_inst,
 353                              regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 354                              upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
 355                 offset = size;
 356                 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0,
 357                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 358         }
 359         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size);
 360
 361         /* cache window 1: stack */
 362         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 363                      lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
 364         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 365                      upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
 366         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 367         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1,
 368                      AMDGPU_VCN_STACK_SIZE);
 369
 370         /* cache window 2: context */
 371         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 372                      lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 373                                    AMDGPU_VCN_STACK_SIZE));
 374         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 375                      upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 376                                    AMDGPU_VCN_STACK_SIZE));
 377         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 378         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2,
 379                      AMDGPU_VCN_CONTEXT_SIZE);
 380
 381         /* non-cache window */
 382         WREG32_SOC15(
 383                 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 384                 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
 385         WREG32_SOC15(
 386                 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 387                 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
 388         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 389         WREG32_SOC15(
 390                 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0,
 391                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 392 }
 393
 394 /**
 395  * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode
 396  *
 397  * @adev: amdgpu_device pointer
 398  * @inst_idx: instance number index
 399  * @indirect: indirectly write sram
 400  *
 401  * Let the VCN memory controller know it's offsets with dpg mode
 402  */
 403 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 404 {
 405         uint32_t offset, size;
 406         const struct common_firmware_header *hdr;
 407
 408         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 409         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 410
 411         /* cache window 0: fw */
 412         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 413                 if (!indirect) {
 414                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 415                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 416                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
 417                                         inst_idx].tmr_mc_addr_lo), 0, indirect);
 418                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 419                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 420                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
 421                                         inst_idx].tmr_mc_addr_hi), 0, indirect);
 422                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 423                                 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 424                 } else {
 425                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 426                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 427                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 428                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 429                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 430                                 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 431                 }
 432                 offset = 0;
 433         } else {
 434                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 435                         VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 436                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 437                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 438                         VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 439                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 440                 offset = size;
 441                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 442                         VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
 443                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 444         }
 445
 446         if (!indirect)
 447                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 448                         VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 449         else
 450                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 451                         VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 452
 453         /* cache window 1: stack */
 454         if (!indirect) {
 455                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 456                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 457                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 458                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 459                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 460                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 461                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 462                         VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 463         } else {
 464                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 465                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 466                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 467                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 468                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 469                         VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 470         }
 471         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 472                         VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 473
 474         /* cache window 2: context */
 475         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 476                         VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 477                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 478                                 AMDGPU_VCN_STACK_SIZE), 0, indirect);
 479         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 480                         VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 481                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 482                                 AMDGPU_VCN_STACK_SIZE), 0, indirect);
 483         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 484                         VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 485         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 486                         VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 487
 488         /* non-cache window */
 489         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 490                         VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 491                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 492         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 493                         VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 494                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 495         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 496                         VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 497         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 498                         VCN, 0, regUVD_VCPU_NONCACHE_SIZE0),
 499                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 500
 501         /* VCN global tiling registers */
 502         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 503                 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 504         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 505                 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 506 }
 507
 508 /**
 509  * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating
 510  *
 511  * @adev: amdgpu_device pointer
 512  * @inst_idx: instance number
 513  *
 514  * Disable clock gating for VCN block
 515  */
 516 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
 517 {
 518         uint32_t data;
 519         int vcn_inst;
 520
 521         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 522                 return;
 523
 524         vcn_inst = GET_INST(VCN, inst_idx);
 525
 526         /* VCN disable CGC */
 527         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 528         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 529         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 530         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 531         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 532
 533         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE);
 534         data &= ~(UVD_CGC_GATE__SYS_MASK
 535                 | UVD_CGC_GATE__MPEG2_MASK
 536                 | UVD_CGC_GATE__REGS_MASK
 537                 | UVD_CGC_GATE__RBC_MASK
 538                 | UVD_CGC_GATE__LMI_MC_MASK
 539                 | UVD_CGC_GATE__LMI_UMC_MASK
 540                 | UVD_CGC_GATE__MPC_MASK
 541                 | UVD_CGC_GATE__LBSI_MASK
 542                 | UVD_CGC_GATE__LRBBM_MASK
 543                 | UVD_CGC_GATE__WCB_MASK
 544                 | UVD_CGC_GATE__VCPU_MASK
 545                 | UVD_CGC_GATE__MMSCH_MASK);
 546
 547         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data);
 548         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
 549
 550         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 551         data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK
 552                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 553                 | UVD_CGC_CTRL__REGS_MODE_MASK
 554                 | UVD_CGC_CTRL__RBC_MODE_MASK
 555                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 556                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 557                 | UVD_CGC_CTRL__MPC_MODE_MASK
 558                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 559                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 560                 | UVD_CGC_CTRL__WCB_MODE_MASK
 561                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 562                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 563         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 564
 565         data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE);
 566         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 567                 | UVD_SUVD_CGC_GATE__SIT_MASK
 568                 | UVD_SUVD_CGC_GATE__SMP_MASK
 569                 | UVD_SUVD_CGC_GATE__SCM_MASK
 570                 | UVD_SUVD_CGC_GATE__SDB_MASK
 571                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 572                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 573                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 574                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 575                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 576                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 577                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 578                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 579                 | UVD_SUVD_CGC_GATE__ENT_MASK
 580                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 581                 | UVD_SUVD_CGC_GATE__SITE_MASK
 582                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 583                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 584                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 585                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 586                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 587         WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data);
 588
 589         data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);
 590         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 591                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 592                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 593                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 594                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 595                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 596                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 597                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 598         WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data);
 599 }
 600
 601 /**
 602  * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 603  *
 604  * @adev: amdgpu_device pointer
 605  * @sram_sel: sram select
 606  * @inst_idx: instance number index
 607  * @indirect: indirectly write sram
 608  *
 609  * Disable clock gating for VCN block with dpg mode
 610  */
 611 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 612                                 int inst_idx, uint8_t indirect)
 613 {
 614         uint32_t reg_data = 0;
 615
 616         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 617                 return;
 618
 619         /* enable sw clock gating control */
 620         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 621         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 622         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 623         reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK |
 624                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 625                  UVD_CGC_CTRL__REGS_MODE_MASK |
 626                  UVD_CGC_CTRL__RBC_MODE_MASK |
 627                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 628                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 629                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 630                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 631                  UVD_CGC_CTRL__MPC_MODE_MASK |
 632                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 633                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 634                  UVD_CGC_CTRL__WCB_MODE_MASK |
 635                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 636         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 637                 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 638
 639         /* turn off clock gating */
 640         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 641                 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect);
 642
 643         /* turn on SUVD clock gating */
 644         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 645                 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 646
 647         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 648         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 649                 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 650 }
 651
 652 /**
 653  * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating
 654  *
 655  * @adev: amdgpu_device pointer
 656  * @inst_idx: instance number
 657  *
 658  * Enable clock gating for VCN block
 659  */
 660 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
 661 {
 662         uint32_t data;
 663         int vcn_inst;
 664
 665         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 666                 return;
 667
 668         vcn_inst = GET_INST(VCN, inst_idx);
 669
 670         /* enable VCN CGC */
 671         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 672         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 673         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 674         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 675         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 676
 677         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 678         data |= (UVD_CGC_CTRL__SYS_MODE_MASK
 679                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 680                 | UVD_CGC_CTRL__REGS_MODE_MASK
 681                 | UVD_CGC_CTRL__RBC_MODE_MASK
 682                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 683                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 684                 | UVD_CGC_CTRL__MPC_MODE_MASK
 685                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 686                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 687                 | UVD_CGC_CTRL__WCB_MODE_MASK
 688                 | UVD_CGC_CTRL__VCPU_MODE_MASK);
 689         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 690
 691         data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);
 692         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 693                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 694                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 695                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 696                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 697                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 698                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 699                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 700         WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data);
 701 }
 702
 703 /**
 704  * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode
 705  *
 706  * @adev: amdgpu_device pointer
 707  * @inst_idx: instance number index
 708  * @indirect: indirectly write sram
 709  *
 710  * Start VCN block with dpg mode
 711  */
 712 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 713 {
 714         volatile struct amdgpu_vcn4_fw_shared *fw_shared =
 715                                                 adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 716         struct amdgpu_ring *ring;
 717         int vcn_inst;
 718         uint32_t tmp;
 719
 720         vcn_inst = GET_INST(VCN, inst_idx);
 721         /* disable register anti-hang mechanism */
 722         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,
 723                  ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 724         /* enable dynamic power gating mode */
 725         tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);
 726         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 727         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 728         WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);
 729
 730         if (indirect) {
 731                 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d",
 732                         inst_idx, adev->vcn.inst[inst_idx].aid_id);
 733                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
 734                                 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 735                 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */
 736                 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF,
 737                         adev->vcn.inst[inst_idx].aid_id, 0, true);
 738         }
 739
 740         /* enable clock gating */
 741         vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 742
 743         /* enable VCPU clock */
 744         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 745         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 746         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 747
 748         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 749                 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
 750
 751         /* disable master interrupt */
 752         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 753                 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
 754
 755         /* setup regUVD_LMI_CTRL */
 756         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 757                 UVD_LMI_CTRL__REQ_MODE_MASK |
 758                 UVD_LMI_CTRL__CRC_RESET_MASK |
 759                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 760                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 761                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 762                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 763                 0x00100000L);
 764         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 765                 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
 766
 767         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 768                 VCN, 0, regUVD_MPC_CNTL),
 769                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 770
 771         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 772                 VCN, 0, regUVD_MPC_SET_MUXA0),
 773                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 774                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 775                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 776                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 777
 778         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 779                 VCN, 0, regUVD_MPC_SET_MUXB0),
 780                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 781                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 782                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 783                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 784
 785         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 786                 VCN, 0, regUVD_MPC_SET_MUX),
 787                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 788                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 789                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 790
 791         vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect);
 792
 793         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 794         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 795         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 796                 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
 797
 798         /* enable LMI MC and UMC channels */
 799         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
 800         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 801                 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
 802
 803         vcn_v4_0_3_enable_ras(adev, inst_idx, indirect);
 804
 805         /* enable master interrupt */
 806         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 807                 VCN, 0, regUVD_MASTINT_EN),
 808                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 809
 810         if (indirect)
 811                 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
 812
 813         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 814
 815         /* program the RB_BASE for ring buffer */
 816         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
 817                      lower_32_bits(ring->gpu_addr));
 818         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
 819                      upper_32_bits(ring->gpu_addr));
 820
 821         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
 822                      ring->ring_size / sizeof(uint32_t));
 823
 824         /* resetting ring, fw should not check RB ring */
 825         tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
 826         tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
 827         WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
 828         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
 829
 830         /* Initialize the ring buffer's read and write pointers */
 831         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
 832         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
 833         ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
 834
 835         tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
 836         tmp |= VCN_RB_ENABLE__RB_EN_MASK;
 837         WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
 838         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 839
 840         /*resetting done, fw can check RB ring */
 841         fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
 842
 843         return 0;
 844 }
 845
 846 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
 847 {
 848         int i, vcn_inst;
 849         struct amdgpu_ring *ring_enc;
 850         uint64_t cache_addr;
 851         uint64_t rb_enc_addr;
 852         uint64_t ctx_addr;
 853         uint32_t param, resp, expected;
 854         uint32_t offset, cache_size;
 855         uint32_t tmp, timeout;
 856
 857         struct amdgpu_mm_table *table = &adev->virt.mm_table;
 858         uint32_t *table_loc;
 859         uint32_t table_size;
 860         uint32_t size, size_dw;
 861         uint32_t init_status;
 862         uint32_t enabled_vcn;
 863
 864         struct mmsch_v4_0_cmd_direct_write
 865                 direct_wt = { {0} };
 866         struct mmsch_v4_0_cmd_direct_read_modify_write
 867                 direct_rd_mod_wt = { {0} };
 868         struct mmsch_v4_0_cmd_end end = { {0} };
 869         struct mmsch_v4_0_3_init_header header;
 870
 871         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 872         volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
 873
 874         direct_wt.cmd_header.command_type =
 875                 MMSCH_COMMAND__DIRECT_REG_WRITE;
 876         direct_rd_mod_wt.cmd_header.command_type =
 877                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 878         end.cmd_header.command_type = MMSCH_COMMAND__END;
 879
 880         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 881                 vcn_inst = GET_INST(VCN, i);
 882
 883                 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header));
 884                 header.version = MMSCH_VERSION;
 885                 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2;
 886
 887                 table_loc = (uint32_t *)table->cpu_addr;
 888                 table_loc += header.total_size;
 889
 890                 table_size = 0;
 891
 892                 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
 893                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
 894
 895                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
 896
 897                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 898                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 899                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 900                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
 901
 902                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 903                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 904                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
 905
 906                         offset = 0;
 907                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 908                                 regUVD_VCPU_CACHE_OFFSET0), 0);
 909                 } else {
 910                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 911                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 912                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
 913                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 914                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 915                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
 916                         offset = cache_size;
 917                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 918                                 regUVD_VCPU_CACHE_OFFSET0),
 919                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 920                 }
 921
 922                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 923                         regUVD_VCPU_CACHE_SIZE0),
 924                         cache_size);
 925
 926                 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
 927                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 928                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
 929                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 930                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
 931                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 932                         regUVD_VCPU_CACHE_OFFSET1), 0);
 933                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 934                         regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);
 935
 936                 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
 937                         AMDGPU_VCN_STACK_SIZE;
 938
 939                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 940                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
 941
 942                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 943                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
 944
 945                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 946                         regUVD_VCPU_CACHE_OFFSET2), 0);
 947
 948                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 949                         regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE);
 950
 951                 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
 952                 rb_setup = &fw_shared->rb_setup;
 953
 954                 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
 955                 ring_enc->wptr = 0;
 956                 rb_enc_addr = ring_enc->gpu_addr;
 957
 958                 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
 959                 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
 960                 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
 961                 rb_setup->rb_size = ring_enc->ring_size / 4;
 962                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
 963
 964                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 965                         regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 966                         lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
 967                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 968                         regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 969                         upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
 970                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 971                         regUVD_VCPU_NONCACHE_SIZE0),
 972                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 973                 MMSCH_V4_0_INSERT_END();
 974
 975                 header.vcn0.init_status = 0;
 976                 header.vcn0.table_offset = header.total_size;
 977                 header.vcn0.table_size = table_size;
 978                 header.total_size += table_size;
 979
 980                 /* Send init table to mmsch */
 981                 size = sizeof(struct mmsch_v4_0_3_init_header);
 982                 table_loc = (uint32_t *)table->cpu_addr;
 983                 memcpy((void *)table_loc, &header, size);
 984
 985                 ctx_addr = table->gpu_addr;
 986                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
 987                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
 988
 989                 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
 990                 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 991                 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
 992                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
 993
 994                 size = header.total_size;
 995                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size);
 996
 997                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0);
 998
 999                 param = 0x00000001;
1000                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param);
1001                 tmp = 0;
1002                 timeout = 1000;
1003                 resp = 0;
1004                 expected = MMSCH_VF_MAILBOX_RESP__OK;
1005                 while (resp != expected) {
1006                         resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);
1007                         if (resp != 0)
1008                                 break;
1009
1010                         udelay(10);
1011                         tmp = tmp + 10;
1012                         if (tmp >= timeout) {
1013                                 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1014                                         " waiting for regMMSCH_VF_MAILBOX_RESP "\
1015                                         "(expected=0x%08x, readback=0x%08x)\n",
1016                                         tmp, expected, resp);
1017                                 return -EBUSY;
1018                         }
1019                 }
1020
1021                 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1022                 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status;
1023                 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1024                                         && init_status != MMSCH_VF_ENGINE_STATUS__PASS) {
1025                         DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1026                                 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1027                 }
1028         }
1029
1030         return 0;
1031 }
1032
1033 /**
1034  * vcn_v4_0_3_start - VCN start
1035  *
1036  * @adev: amdgpu_device pointer
1037  *
1038  * Start VCN block
1039  */
1040 static int vcn_v4_0_3_start(struct amdgpu_device *adev)
1041 {
1042         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1043         struct amdgpu_ring *ring;
1044         int i, j, k, r, vcn_inst;
1045         uint32_t tmp;
1046
1047         if (adev->pm.dpm_enabled)
1048                 amdgpu_dpm_enable_uvd(adev, true);
1049
1050         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1051                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1052                         r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1053                         continue;
1054                 }
1055
1056                 vcn_inst = GET_INST(VCN, i);
1057                 /* set VCN status busy */
1058                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
1059                       UVD_STATUS__UVD_BUSY;
1060                 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
1061
1062                 /*SW clock gating */
1063                 vcn_v4_0_3_disable_clock_gating(adev, i);
1064
1065                 /* enable VCPU clock */
1066                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
1067                          UVD_VCPU_CNTL__CLK_EN_MASK,
1068                          ~UVD_VCPU_CNTL__CLK_EN_MASK);
1069
1070                 /* disable master interrupt */
1071                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
1072                          ~UVD_MASTINT_EN__VCPU_EN_MASK);
1073
1074                 /* enable LMI MC and UMC channels */
1075                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
1076                          ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1077
1078                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1079                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1080                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1081                 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1082
1083                 /* setup regUVD_LMI_CTRL */
1084                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
1085                 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
1086                              tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1087                                      UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1088                                      UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1089                                      UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1090
1091                 /* setup regUVD_MPC_CNTL */
1092                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
1093                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1094                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1095                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
1096
1097                 /* setup UVD_MPC_SET_MUXA0 */
1098                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
1099                              ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1100                               (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1101                               (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1102                               (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1103
1104                 /* setup UVD_MPC_SET_MUXB0 */
1105                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
1106                              ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1107                               (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1108                               (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1109                               (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1110
1111                 /* setup UVD_MPC_SET_MUX */
1112                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
1113                              ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1114                               (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1115                               (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1116
1117                 vcn_v4_0_3_mc_resume(adev, i);
1118
1119                 /* VCN global tiling registers */
1120                 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
1121                              adev->gfx.config.gb_addr_config);
1122                 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
1123                              adev->gfx.config.gb_addr_config);
1124
1125                 /* unblock VCPU register access */
1126                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
1127                          ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1128
1129                 /* release VCPU reset to boot */
1130                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
1131                          ~UVD_VCPU_CNTL__BLK_RST_MASK);
1132
1133                 for (j = 0; j < 10; ++j) {
1134                         uint32_t status;
1135
1136                         for (k = 0; k < 100; ++k) {
1137                                 status = RREG32_SOC15(VCN, vcn_inst,
1138                                                       regUVD_STATUS);
1139                                 if (status & 2)
1140                                         break;
1141                                 mdelay(10);
1142                         }
1143                         r = 0;
1144                         if (status & 2)
1145                                 break;
1146
1147                         DRM_DEV_ERROR(adev->dev,
1148                                 "VCN decode not responding, trying to reset the VCPU!!!\n");
1149                         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
1150                                                   regUVD_VCPU_CNTL),
1151                                  UVD_VCPU_CNTL__BLK_RST_MASK,
1152                                  ~UVD_VCPU_CNTL__BLK_RST_MASK);
1153                         mdelay(10);
1154                         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
1155                                                   regUVD_VCPU_CNTL),
1156                                  0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
1157
1158                         mdelay(10);
1159                         r = -1;
1160                 }
1161
1162                 if (r) {
1163                         DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
1164                         return r;
1165                 }
1166
1167                 /* enable master interrupt */
1168                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
1169                          UVD_MASTINT_EN__VCPU_EN_MASK,
1170                          ~UVD_MASTINT_EN__VCPU_EN_MASK);
1171
1172                 /* clear the busy bit of VCN_STATUS */
1173                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
1174                          ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1175
1176                 ring = &adev->vcn.inst[i].ring_enc[0];
1177                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1178
1179                 /* program the RB_BASE for ring buffer */
1180                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
1181                              lower_32_bits(ring->gpu_addr));
1182                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
1183                              upper_32_bits(ring->gpu_addr));
1184
1185                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
1186                              ring->ring_size / sizeof(uint32_t));
1187
1188                 /* resetting ring, fw should not check RB ring */
1189                 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
1190                 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
1191                 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
1192
1193                 /* Initialize the ring buffer's read and write pointers */
1194                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
1195                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
1196
1197                 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
1198                 tmp |= VCN_RB_ENABLE__RB_EN_MASK;
1199                 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
1200
1201                 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1202                 fw_shared->sq.queue_mode &=
1203                         cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
1204
1205         }
1206         return 0;
1207 }
1208
1209 /**
1210  * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode
1211  *
1212  * @adev: amdgpu_device pointer
1213  * @inst_idx: instance number index
1214  *
1215  * Stop VCN block with dpg mode
1216  */
1217 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1218 {
1219         uint32_t tmp;
1220         int vcn_inst;
1221
1222         vcn_inst = GET_INST(VCN, inst_idx);
1223
1224         /* Wait for power status to be 1 */
1225         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
1226                            UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1227
1228         /* wait for read ptr to be equal to write ptr */
1229         tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1230         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1231
1232         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
1233                            UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1234
1235         /* disable dynamic power gating mode */
1236         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
1237                  ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1238         return 0;
1239 }
1240
1241 /**
1242  * vcn_v4_0_3_stop - VCN stop
1243  *
1244  * @adev: amdgpu_device pointer
1245  *
1246  * Stop VCN block
1247  */
1248 static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
1249 {
1250         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1251         int i, r = 0, vcn_inst;
1252         uint32_t tmp;
1253
1254         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1255                 vcn_inst = GET_INST(VCN, i);
1256
1257                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1258                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1259
1260                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1261                         vcn_v4_0_3_stop_dpg_mode(adev, i);
1262                         continue;
1263                 }
1264
1265                 /* wait for vcn idle */
1266                 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
1267                                        UVD_STATUS__IDLE, 0x7);
1268                 if (r)
1269                         goto Done;
1270
1271                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1272                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1273                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1274                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1275                 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
1276                                        tmp);
1277                 if (r)
1278                         goto Done;
1279
1280                 /* stall UMC channel */
1281                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
1282                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1283                 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
1284                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1285                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1286                 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
1287                                        tmp);
1288                 if (r)
1289                         goto Done;
1290
1291                 /* Unblock VCPU Register access */
1292                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
1293                          UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1294                          ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1295
1296                 /* release VCPU reset to boot */
1297                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
1298                          UVD_VCPU_CNTL__BLK_RST_MASK,
1299                          ~UVD_VCPU_CNTL__BLK_RST_MASK);
1300
1301                 /* disable VCPU clock */
1302                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
1303                          ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1304
1305                 /* reset LMI UMC/LMI/VCPU */
1306                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1307                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1308                 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1309
1310                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1311                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1312                 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1313
1314                 /* clear VCN status */
1315                 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
1316
1317                 /* apply HW clock gating */
1318                 vcn_v4_0_3_enable_clock_gating(adev, i);
1319         }
1320 Done:
1321         if (adev->pm.dpm_enabled)
1322                 amdgpu_dpm_enable_uvd(adev, false);
1323
1324         return 0;
1325 }
1326
1327 /**
1328  * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode
1329  *
1330  * @adev: amdgpu_device pointer
1331  * @inst_idx: instance number index
1332  * @new_state: pause state
1333  *
1334  * Pause dpg mode for VCN block
1335  */
1336 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1337                                 struct dpg_pause_state *new_state)
1338 {
1339
1340         return 0;
1341 }
1342
1343 /**
1344  * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer
1345  *
1346  * @ring: amdgpu_ring pointer
1347  *
1348  * Returns the current hardware unified read pointer
1349  */
1350 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring)
1351 {
1352         struct amdgpu_device *adev = ring->adev;
1353
1354         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1355                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1356
1357         return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);
1358 }
1359
1360 /**
1361  * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer
1362  *
1363  * @ring: amdgpu_ring pointer
1364  *
1365  * Returns the current hardware unified write pointer
1366  */
1367 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring)
1368 {
1369         struct amdgpu_device *adev = ring->adev;
1370
1371         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1372                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1373
1374         if (ring->use_doorbell)
1375                 return *ring->wptr_cpu_addr;
1376         else
1377                 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),
1378                                     regUVD_RB_WPTR);
1379 }
1380
1381 static void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1382                                 uint32_t val, uint32_t mask)
1383 {
1384         /* For VF, only local offsets should be used */
1385         if (amdgpu_sriov_vf(ring->adev))
1386                 reg = NORMALIZE_VCN_REG_OFFSET(reg);
1387
1388         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1389         amdgpu_ring_write(ring, reg << 2);
1390         amdgpu_ring_write(ring, mask);
1391         amdgpu_ring_write(ring, val);
1392 }
1393
1394 static void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1395 {
1396         /* For VF, only local offsets should be used */
1397         if (amdgpu_sriov_vf(ring->adev))
1398                 reg = NORMALIZE_VCN_REG_OFFSET(reg);
1399
1400         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1401         amdgpu_ring_write(ring, reg << 2);
1402         amdgpu_ring_write(ring, val);
1403 }
1404
1405 static void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1406                                 unsigned int vmid, uint64_t pd_addr)
1407 {
1408         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1409
1410         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1411
1412         /* wait for reg writes */
1413         vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1414                                         vmid * hub->ctx_addr_distance,
1415                                         lower_32_bits(pd_addr), 0xffffffff);
1416 }
1417
1418 static void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1419 {
1420         /* VCN engine access for HDP flush doesn't work when RRMT is enabled.
1421          * This is a workaround to avoid any HDP flush through VCN ring.
1422          */
1423 }
1424
1425 /**
1426  * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer
1427  *
1428  * @ring: amdgpu_ring pointer
1429  *
1430  * Commits the enc write pointer to the hardware
1431  */
1432 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring)
1433 {
1434         struct amdgpu_device *adev = ring->adev;
1435
1436         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1437                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1438
1439         if (ring->use_doorbell) {
1440                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1441                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1442         } else {
1443                 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,
1444                              lower_32_bits(ring->wptr));
1445         }
1446 }
1447
1448 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
1449         .type = AMDGPU_RING_TYPE_VCN_ENC,
1450         .align_mask = 0x3f,
1451         .nop = VCN_ENC_CMD_NO_OP,
1452         .get_rptr = vcn_v4_0_3_unified_ring_get_rptr,
1453         .get_wptr = vcn_v4_0_3_unified_ring_get_wptr,
1454         .set_wptr = vcn_v4_0_3_unified_ring_set_wptr,
1455         .emit_frame_size =
1456                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1457                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1458                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1459                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1460                 1, /* vcn_v2_0_enc_ring_insert_end */
1461         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1462         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1463         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1464         .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush,
1465         .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush,
1466         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1467         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1468         .insert_nop = amdgpu_ring_insert_nop,
1469         .insert_end = vcn_v2_0_enc_ring_insert_end,
1470         .pad_ib = amdgpu_ring_generic_pad_ib,
1471         .begin_use = amdgpu_vcn_ring_begin_use,
1472         .end_use = amdgpu_vcn_ring_end_use,
1473         .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg,
1474         .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait,
1475         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1476 };
1477
1478 /**
1479  * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions
1480  *
1481  * @adev: amdgpu_device pointer
1482  *
1483  * Set unified ring functions
1484  */
1485 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
1486 {
1487         int i, vcn_inst;
1488
1489         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1490                 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
1491                 adev->vcn.inst[i].ring_enc[0].me = i;
1492                 vcn_inst = GET_INST(VCN, i);
1493                 adev->vcn.inst[i].aid_id =
1494                         vcn_inst / adev->vcn.num_inst_per_aid;
1495         }
1496 }
1497
1498 /**
1499  * vcn_v4_0_3_is_idle - check VCN block is idle
1500  *
1501  * @handle: amdgpu_device pointer
1502  *
1503  * Check whether VCN block is idle
1504  */
1505 static bool vcn_v4_0_3_is_idle(void *handle)
1506 {
1507         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1508         int i, ret = 1;
1509
1510         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1511                 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
1512                         UVD_STATUS__IDLE);
1513         }
1514
1515         return ret;
1516 }
1517
1518 /**
1519  * vcn_v4_0_3_wait_for_idle - wait for VCN block idle
1520  *
1521  * @handle: amdgpu_device pointer
1522  *
1523  * Wait for VCN block idle
1524  */
1525 static int vcn_v4_0_3_wait_for_idle(void *handle)
1526 {
1527         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1528         int i, ret = 0;
1529
1530         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1531                 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,
1532                                          UVD_STATUS__IDLE, UVD_STATUS__IDLE);
1533                 if (ret)
1534                         return ret;
1535         }
1536
1537         return ret;
1538 }
1539
1540 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state
1541  *
1542  * @handle: amdgpu_device pointer
1543  * @state: clock gating state
1544  *
1545  * Set VCN block clockgating state
1546  */
1547 static int vcn_v4_0_3_set_clockgating_state(void *handle,
1548                                           enum amd_clockgating_state state)
1549 {
1550         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1551         bool enable = state == AMD_CG_STATE_GATE;
1552         int i;
1553
1554         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1555                 if (enable) {
1556                         if (RREG32_SOC15(VCN, GET_INST(VCN, i),
1557                                          regUVD_STATUS) != UVD_STATUS__IDLE)
1558                                 return -EBUSY;
1559                         vcn_v4_0_3_enable_clock_gating(adev, i);
1560                 } else {
1561                         vcn_v4_0_3_disable_clock_gating(adev, i);
1562                 }
1563         }
1564         return 0;
1565 }
1566
1567 /**
1568  * vcn_v4_0_3_set_powergating_state - set VCN block powergating state
1569  *
1570  * @handle: amdgpu_device pointer
1571  * @state: power gating state
1572  *
1573  * Set VCN block powergating state
1574  */
1575 static int vcn_v4_0_3_set_powergating_state(void *handle,
1576                                           enum amd_powergating_state state)
1577 {
1578         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1579         int ret;
1580
1581         /* for SRIOV, guest should not control VCN Power-gating
1582          * MMSCH FW should control Power-gating and clock-gating
1583          * guest should avoid touching CGC and PG
1584          */
1585         if (amdgpu_sriov_vf(adev)) {
1586                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1587                 return 0;
1588         }
1589
1590         if (state == adev->vcn.cur_state)
1591                 return 0;
1592
1593         if (state == AMD_PG_STATE_GATE)
1594                 ret = vcn_v4_0_3_stop(adev);
1595         else
1596                 ret = vcn_v4_0_3_start(adev);
1597
1598         if (!ret)
1599                 adev->vcn.cur_state = state;
1600
1601         return ret;
1602 }
1603
1604 /**
1605  * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state
1606  *
1607  * @adev: amdgpu_device pointer
1608  * @source: interrupt sources
1609  * @type: interrupt types
1610  * @state: interrupt states
1611  *
1612  * Set VCN block interrupt state
1613  */
1614 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,
1615                                         struct amdgpu_irq_src *source,
1616                                         unsigned int type,
1617                                         enum amdgpu_interrupt_state state)
1618 {
1619         return 0;
1620 }
1621
1622 /**
1623  * vcn_v4_0_3_process_interrupt - process VCN block interrupt
1624  *
1625  * @adev: amdgpu_device pointer
1626  * @source: interrupt sources
1627  * @entry: interrupt entry from clients and sources
1628  *
1629  * Process VCN block interrupt
1630  */
1631 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev,
1632                                       struct amdgpu_irq_src *source,
1633                                       struct amdgpu_iv_entry *entry)
1634 {
1635         uint32_t i, inst;
1636
1637         i = node_id_to_phys_map[entry->node_id];
1638
1639         DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n");
1640
1641         for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)
1642                 if (adev->vcn.inst[inst].aid_id == i)
1643                         break;
1644
1645         if (inst >= adev->vcn.num_vcn_inst) {
1646                 dev_WARN_ONCE(adev->dev, 1,
1647                               "Interrupt received for unknown VCN instance %d",
1648                               entry->node_id);
1649                 return 0;
1650         }
1651
1652         switch (entry->src_id) {
1653         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1654                 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);
1655                 break;
1656         default:
1657                 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
1658                           entry->src_id, entry->src_data[0]);
1659                 break;
1660         }
1661
1662         return 0;
1663 }
1664
1665 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = {
1666         .set = vcn_v4_0_3_set_interrupt_state,
1667         .process = vcn_v4_0_3_process_interrupt,
1668 };
1669
1670 /**
1671  * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions
1672  *
1673  * @adev: amdgpu_device pointer
1674  *
1675  * Set VCN block interrupt irq functions
1676  */
1677 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
1678 {
1679         int i;
1680
1681         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1682                 adev->vcn.inst->irq.num_types++;
1683         }
1684         adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
1685 }
1686
1687 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
1688         .name = "vcn_v4_0_3",
1689         .early_init = vcn_v4_0_3_early_init,
1690         .late_init = NULL,
1691         .sw_init = vcn_v4_0_3_sw_init,
1692         .sw_fini = vcn_v4_0_3_sw_fini,
1693         .hw_init = vcn_v4_0_3_hw_init,
1694         .hw_fini = vcn_v4_0_3_hw_fini,
1695         .suspend = vcn_v4_0_3_suspend,
1696         .resume = vcn_v4_0_3_resume,
1697         .is_idle = vcn_v4_0_3_is_idle,
1698         .wait_for_idle = vcn_v4_0_3_wait_for_idle,
1699         .check_soft_reset = NULL,
1700         .pre_soft_reset = NULL,
1701         .soft_reset = NULL,
1702         .post_soft_reset = NULL,
1703         .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
1704         .set_powergating_state = vcn_v4_0_3_set_powergating_state,
1705         .dump_ip_state = NULL,
1706         .print_ip_state = NULL,
1707 };
1708
1709 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
1710         .type = AMD_IP_BLOCK_TYPE_VCN,
1711         .major = 4,
1712         .minor = 0,
1713         .rev = 3,
1714         .funcs = &vcn_v4_0_3_ip_funcs,
1715 };
1716
1717 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = {
1718         {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD),
1719         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"},
1720         {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV),
1721         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"},
1722 };
1723
1724 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev,
1725                                                   uint32_t vcn_inst,
1726                                                   void *ras_err_status)
1727 {
1728         struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
1729
1730         /* vcn v4_0_3 only support query uncorrectable errors */
1731         amdgpu_ras_inst_query_ras_error_count(adev,
1732                         vcn_v4_0_3_ue_reg_list,
1733                         ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),
1734                         NULL, 0, GET_INST(VCN, vcn_inst),
1735                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1736                         &err_data->ue_count);
1737 }
1738
1739 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev,
1740                                              void *ras_err_status)
1741 {
1742         uint32_t i;
1743
1744         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
1745                 dev_warn(adev->dev, "VCN RAS is not supported\n");
1746                 return;
1747         }
1748
1749         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1750                 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status);
1751 }
1752
1753 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev,
1754                                                   uint32_t vcn_inst)
1755 {
1756         amdgpu_ras_inst_reset_ras_error_count(adev,
1757                                         vcn_v4_0_3_ue_reg_list,
1758                                         ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),
1759                                         GET_INST(VCN, vcn_inst));
1760 }
1761
1762 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)
1763 {
1764         uint32_t i;
1765
1766         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
1767                 dev_warn(adev->dev, "VCN RAS is not supported\n");
1768                 return;
1769         }
1770
1771         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1772                 vcn_v4_0_3_inst_reset_ras_error_count(adev, i);
1773 }
1774
1775 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = {
1776         .query_ras_error_count = vcn_v4_0_3_query_ras_error_count,
1777         .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count,
1778 };
1779
1780 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = {
1781         .ras_block = {
1782                 .hw_ops = &vcn_v4_0_3_ras_hw_ops,
1783         },
1784 };
1785
1786 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
1787 {
1788         adev->vcn.ras = &vcn_v4_0_3_ras;
1789 }
1790
1791 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
1792                                   int inst_idx, bool indirect)
1793 {
1794         uint32_t tmp;
1795
1796         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
1797                 return;
1798
1799         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
1800               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
1801               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
1802               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
1803         WREG32_SOC15_DPG_MODE(inst_idx,
1804                               SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
1805                               tmp, 0, indirect);
1806
1807         tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK;
1808         WREG32_SOC15_DPG_MODE(inst_idx,
1809                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2),
1810                               tmp, 0, indirect);
1811
1812         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
1813         WREG32_SOC15_DPG_MODE(inst_idx,
1814                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
1815                               tmp, 0, indirect);
1816 }