1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
4 #include <linux/acpi.h>
6 #include <linux/module.h>
7 #include <linux/delay.h>
8 #include <linux/pm_runtime.h>
9 #include <media/v4l2-ctrls.h>
10 #include <media/v4l2-device.h>
11 #include <media/v4l2-fwnode.h>
13 #define OV08X40_REG_VALUE_08BIT 1
14 #define OV08X40_REG_VALUE_16BIT 2
15 #define OV08X40_REG_VALUE_24BIT 3
17 #define OV08X40_REG_MODE_SELECT 0x0100
18 #define OV08X40_MODE_STANDBY 0x00
19 #define OV08X40_MODE_STREAMING 0x01
21 #define OV08X40_REG_AO_STANDBY 0x1000
22 #define OV08X40_AO_STREAMING 0x04
24 #define OV08X40_REG_MS_SELECT 0x1001
25 #define OV08X40_MS_STANDBY 0x00
26 #define OV08X40_MS_STREAMING 0x04
28 #define OV08X40_REG_SOFTWARE_RST 0x0103
29 #define OV08X40_SOFTWARE_RST 0x01
32 #define OV08X40_REG_CHIP_ID 0x300a
33 #define OV08X40_CHIP_ID 0x560858
35 /* V_TIMING internal */
36 #define OV08X40_REG_VTS 0x380e
37 #define OV08X40_VTS_30FPS 0x1388
38 #define OV08X40_VTS_BIN_30FPS 0x115c
39 #define OV08X40_VTS_MAX 0x7fff
41 /* H TIMING internal */
42 #define OV08X40_REG_HTS 0x380c
43 #define OV08X40_HTS_30FPS 0x0280
45 /* Exposure control */
46 #define OV08X40_REG_EXPOSURE 0x3500
47 #define OV08X40_EXPOSURE_MAX_MARGIN 31
48 #define OV08X40_EXPOSURE_MIN 1
49 #define OV08X40_EXPOSURE_STEP 1
50 #define OV08X40_EXPOSURE_DEFAULT 0x40
52 /* Short Exposure control */
53 #define OV08X40_REG_SHORT_EXPOSURE 0x3540
55 /* Analog gain control */
56 #define OV08X40_REG_ANALOG_GAIN 0x3508
57 #define OV08X40_ANA_GAIN_MIN 0x80
58 #define OV08X40_ANA_GAIN_MAX 0x07c0
59 #define OV08X40_ANA_GAIN_STEP 1
60 #define OV08X40_ANA_GAIN_DEFAULT 0x80
62 /* Digital gain control */
63 #define OV08X40_REG_DGTL_GAIN_H 0x350a
64 #define OV08X40_REG_DGTL_GAIN_M 0x350b
65 #define OV08X40_REG_DGTL_GAIN_L 0x350c
67 #define OV08X40_DGTL_GAIN_MIN 1024 /* Min = 1 X */
68 #define OV08X40_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */
69 #define OV08X40_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */
70 #define OV08X40_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
72 #define OV08X40_DGTL_GAIN_L_SHIFT 6
73 #define OV08X40_DGTL_GAIN_L_MASK 0x3
74 #define OV08X40_DGTL_GAIN_M_SHIFT 2
75 #define OV08X40_DGTL_GAIN_M_MASK 0xff
76 #define OV08X40_DGTL_GAIN_H_SHIFT 10
77 #define OV08X40_DGTL_GAIN_H_MASK 0x1F
79 /* Test Pattern Control */
80 #define OV08X40_REG_TEST_PATTERN 0x50C1
81 #define OV08X40_REG_ISP 0x5000
82 #define OV08X40_REG_SHORT_TEST_PATTERN 0x53C1
83 #define OV08X40_TEST_PATTERN_ENABLE BIT(0)
84 #define OV08X40_TEST_PATTERN_MASK 0xcf
85 #define OV08X40_TEST_PATTERN_BAR_SHIFT 4
88 #define OV08X40_REG_VFLIP 0x3820
89 #define OV08X40_REG_MIRROR 0x3821
91 /* Horizontal Window Offset */
92 #define OV08X40_REG_H_WIN_OFFSET 0x3811
94 /* Vertical Window Offset */
95 #define OV08X40_REG_V_WIN_OFFSET 0x3813
98 OV08X40_LINK_FREQ_400MHZ_INDEX,
106 struct ov08x40_reg_list {
108 const struct ov08x40_reg *regs;
111 /* Link frequency config */
112 struct ov08x40_link_freq_config {
113 /* registers for this link frequency */
114 struct ov08x40_reg_list reg_list;
117 /* Mode : resolution and related config&values */
118 struct ov08x40_mode {
132 /* Index of Link frequency config to be used */
134 /* Default register values */
135 struct ov08x40_reg_list reg_list;
138 static const struct ov08x40_reg mipi_data_rate_800mbps[] = {
158 static const struct ov08x40_reg mode_3856x2416_regs[] = {
1822 static const struct ov08x40_reg mode_1928x1208_regs[] = {
2347 static const char * const ov08x40_test_pattern_menu[] = {
2349 "Vertical Color Bar Type 1",
2350 "Vertical Color Bar Type 2",
2351 "Vertical Color Bar Type 3",
2352 "Vertical Color Bar Type 4"
2355 /* Configurations for supported link frequencies */
2356 #define OV08X40_LINK_FREQ_400MHZ 400000000ULL
2358 #define OV08X40_EXT_CLK 19200000
2359 #define OV08X40_DATA_LANES 4
2362 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
2363 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
2365 static u64 link_freq_to_pixel_rate(u64 f)
2367 f *= 2 * OV08X40_DATA_LANES;
2373 /* Menu items for LINK_FREQ V4L2 control */
2374 static const s64 link_freq_menu_items[] = {
2375 OV08X40_LINK_FREQ_400MHZ,
2378 /* Link frequency configs */
2379 static const struct ov08x40_link_freq_config link_freq_configs[] = {
2380 [OV08X40_LINK_FREQ_400MHZ_INDEX] = {
2382 .num_of_regs = ARRAY_SIZE(mipi_data_rate_800mbps),
2383 .regs = mipi_data_rate_800mbps,
2389 static const struct ov08x40_mode supported_modes[] = {
2393 .vts_def = OV08X40_VTS_30FPS,
2394 .vts_min = OV08X40_VTS_30FPS,
2398 .num_of_regs = ARRAY_SIZE(mode_3856x2416_regs),
2399 .regs = mode_3856x2416_regs,
2401 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX,
2406 .vts_def = OV08X40_VTS_BIN_30FPS,
2407 .vts_min = OV08X40_VTS_BIN_30FPS,
2411 .num_of_regs = ARRAY_SIZE(mode_1928x1208_regs),
2412 .regs = mode_1928x1208_regs,
2414 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX,
2419 struct v4l2_subdev sd;
2420 struct media_pad pad;
2422 struct v4l2_ctrl_handler ctrl_handler;
2424 struct v4l2_ctrl *link_freq;
2425 struct v4l2_ctrl *pixel_rate;
2426 struct v4l2_ctrl *vblank;
2427 struct v4l2_ctrl *hblank;
2428 struct v4l2_ctrl *exposure;
2431 const struct ov08x40_mode *cur_mode;
2433 /* Mutex for serialized access */
2437 #define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd)
2439 /* Read registers up to 4 at a time */
2440 static int ov08x40_read_reg(struct ov08x40 *ov08x,
2441 u16 reg, u32 len, u32 *val)
2443 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2444 struct i2c_msg msgs[2];
2448 __be16 reg_addr_be = cpu_to_be16(reg);
2453 data_be_p = (u8 *)&data_be;
2454 /* Write register address */
2455 msgs[0].addr = client->addr;
2458 msgs[0].buf = (u8 *)®_addr_be;
2460 /* Read data from register */
2461 msgs[1].addr = client->addr;
2462 msgs[1].flags = I2C_M_RD;
2464 msgs[1].buf = &data_be_p[4 - len];
2466 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
2467 if (ret != ARRAY_SIZE(msgs))
2470 *val = be32_to_cpu(data_be);
2475 /* Write registers up to 4 at a time */
2476 static int ov08x40_write_reg(struct ov08x40 *ov08x,
2477 u16 reg, u32 len, u32 __val)
2479 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2488 buf[1] = reg & 0xff;
2490 val = cpu_to_be32(__val);
2496 buf[buf_i++] = val_p[val_i++];
2498 if (i2c_master_send(client, buf, len + 2) != len + 2)
2504 /* Write a list of registers */
2505 static int ov08x40_write_regs(struct ov08x40 *ov08x,
2506 const struct ov08x40_reg *regs, u32 len)
2508 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2512 for (i = 0; i < len; i++) {
2513 ret = ov08x40_write_reg(ov08x, regs[i].address, 1,
2517 dev_err_ratelimited(&client->dev,
2518 "Failed to write reg 0x%4.4x. error = %d\n",
2519 regs[i].address, ret);
2528 static int ov08x40_write_reg_list(struct ov08x40 *ov08x,
2529 const struct ov08x40_reg_list *r_list)
2531 return ov08x40_write_regs(ov08x, r_list->regs, r_list->num_of_regs);
2534 static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2536 const struct ov08x40_mode *default_mode = &supported_modes[0];
2537 struct ov08x40 *ov08x = to_ov08x40(sd);
2538 struct v4l2_mbus_framefmt *try_fmt =
2539 v4l2_subdev_get_try_format(sd, fh->state, 0);
2541 mutex_lock(&ov08x->mutex);
2543 /* Initialize try_fmt */
2544 try_fmt->width = default_mode->width;
2545 try_fmt->height = default_mode->height;
2546 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
2547 try_fmt->field = V4L2_FIELD_NONE;
2549 /* No crop or compose */
2550 mutex_unlock(&ov08x->mutex);
2555 static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain)
2561 * 0x350C[1:0], 0x350B[7:0], 0x350A[4:0]
2564 val = (d_gain & OV08X40_DGTL_GAIN_L_MASK) << OV08X40_DGTL_GAIN_L_SHIFT;
2565 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_L,
2566 OV08X40_REG_VALUE_08BIT, val);
2570 val = (d_gain >> OV08X40_DGTL_GAIN_M_SHIFT) & OV08X40_DGTL_GAIN_M_MASK;
2571 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_M,
2572 OV08X40_REG_VALUE_08BIT, val);
2576 val = (d_gain >> OV08X40_DGTL_GAIN_H_SHIFT) & OV08X40_DGTL_GAIN_H_MASK;
2578 return ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_H,
2579 OV08X40_REG_VALUE_08BIT, val);
2582 static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern)
2587 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN,
2588 OV08X40_REG_VALUE_08BIT, &val);
2593 ret = ov08x40_read_reg(ov08x, OV08X40_REG_ISP,
2594 OV08X40_REG_VALUE_08BIT, &val);
2598 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ISP,
2599 OV08X40_REG_VALUE_08BIT,
2604 ret = ov08x40_read_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN,
2605 OV08X40_REG_VALUE_08BIT, &val);
2609 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN,
2610 OV08X40_REG_VALUE_08BIT,
2615 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN,
2616 OV08X40_REG_VALUE_08BIT, &val);
2620 val &= OV08X40_TEST_PATTERN_MASK;
2621 val |= ((pattern - 1) << OV08X40_TEST_PATTERN_BAR_SHIFT) |
2622 OV08X40_TEST_PATTERN_ENABLE;
2624 val &= ~OV08X40_TEST_PATTERN_ENABLE;
2627 return ov08x40_write_reg(ov08x, OV08X40_REG_TEST_PATTERN,
2628 OV08X40_REG_VALUE_08BIT, val);
2631 static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val)
2636 ret = ov08x40_read_reg(ov08x, OV08X40_REG_MIRROR,
2637 OV08X40_REG_VALUE_08BIT, &val);
2641 return ov08x40_write_reg(ov08x, OV08X40_REG_MIRROR,
2642 OV08X40_REG_VALUE_08BIT,
2643 ctrl_val ? val | BIT(2) : val & ~BIT(2));
2646 static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val)
2651 ret = ov08x40_read_reg(ov08x, OV08X40_REG_VFLIP,
2652 OV08X40_REG_VALUE_08BIT, &val);
2656 return ov08x40_write_reg(ov08x, OV08X40_REG_VFLIP,
2657 OV08X40_REG_VALUE_08BIT,
2658 ctrl_val ? val | BIT(2) : val & ~BIT(2));
2661 static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl)
2663 struct ov08x40 *ov08x = container_of(ctrl->handler,
2664 struct ov08x40, ctrl_handler);
2665 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2669 /* Propagate change of current control to all related controls */
2671 case V4L2_CID_VBLANK:
2672 /* Update max exposure while meeting expected vblanking */
2673 max = ov08x->cur_mode->height + ctrl->val - OV08X40_EXPOSURE_MAX_MARGIN;
2674 __v4l2_ctrl_modify_range(ov08x->exposure,
2675 ov08x->exposure->minimum,
2676 max, ov08x->exposure->step, max);
2681 * Applying V4L2 control value only happens
2682 * when power is up for streaming
2684 if (!pm_runtime_get_if_in_use(&client->dev))
2688 case V4L2_CID_ANALOGUE_GAIN:
2689 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ANALOG_GAIN,
2690 OV08X40_REG_VALUE_16BIT,
2693 case V4L2_CID_DIGITAL_GAIN:
2694 ret = ov08x40_update_digital_gain(ov08x, ctrl->val);
2696 case V4L2_CID_EXPOSURE:
2697 ret = ov08x40_write_reg(ov08x, OV08X40_REG_EXPOSURE,
2698 OV08X40_REG_VALUE_24BIT,
2701 case V4L2_CID_VBLANK:
2702 ret = ov08x40_write_reg(ov08x, OV08X40_REG_VTS,
2703 OV08X40_REG_VALUE_16BIT,
2704 ov08x->cur_mode->height
2707 case V4L2_CID_TEST_PATTERN:
2708 ret = ov08x40_enable_test_pattern(ov08x, ctrl->val);
2710 case V4L2_CID_HFLIP:
2711 ov08x40_set_ctrl_hflip(ov08x, ctrl->val);
2713 case V4L2_CID_VFLIP:
2714 ov08x40_set_ctrl_vflip(ov08x, ctrl->val);
2717 dev_info(&client->dev,
2718 "ctrl(id:0x%x,val:0x%x) is not handled\n",
2719 ctrl->id, ctrl->val);
2723 pm_runtime_put(&client->dev);
2728 static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = {
2729 .s_ctrl = ov08x40_set_ctrl,
2732 static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd,
2733 struct v4l2_subdev_state *sd_state,
2734 struct v4l2_subdev_mbus_code_enum *code)
2736 /* Only one bayer order(GRBG) is supported */
2737 if (code->index > 0)
2740 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
2745 static int ov08x40_enum_frame_size(struct v4l2_subdev *sd,
2746 struct v4l2_subdev_state *sd_state,
2747 struct v4l2_subdev_frame_size_enum *fse)
2749 if (fse->index >= ARRAY_SIZE(supported_modes))
2752 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
2755 fse->min_width = supported_modes[fse->index].width;
2756 fse->max_width = fse->min_width;
2757 fse->min_height = supported_modes[fse->index].height;
2758 fse->max_height = fse->min_height;
2763 static void ov08x40_update_pad_format(const struct ov08x40_mode *mode,
2764 struct v4l2_subdev_format *fmt)
2766 fmt->format.width = mode->width;
2767 fmt->format.height = mode->height;
2768 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
2769 fmt->format.field = V4L2_FIELD_NONE;
2772 static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x,
2773 struct v4l2_subdev_state *sd_state,
2774 struct v4l2_subdev_format *fmt)
2776 struct v4l2_mbus_framefmt *framefmt;
2777 struct v4l2_subdev *sd = &ov08x->sd;
2779 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2780 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
2781 fmt->format = *framefmt;
2783 ov08x40_update_pad_format(ov08x->cur_mode, fmt);
2789 static int ov08x40_get_pad_format(struct v4l2_subdev *sd,
2790 struct v4l2_subdev_state *sd_state,
2791 struct v4l2_subdev_format *fmt)
2793 struct ov08x40 *ov08x = to_ov08x40(sd);
2796 mutex_lock(&ov08x->mutex);
2797 ret = ov08x40_do_get_pad_format(ov08x, sd_state, fmt);
2798 mutex_unlock(&ov08x->mutex);
2804 ov08x40_set_pad_format(struct v4l2_subdev *sd,
2805 struct v4l2_subdev_state *sd_state,
2806 struct v4l2_subdev_format *fmt)
2808 struct ov08x40 *ov08x = to_ov08x40(sd);
2809 const struct ov08x40_mode *mode;
2810 struct v4l2_mbus_framefmt *framefmt;
2817 mutex_lock(&ov08x->mutex);
2819 /* Only one raw bayer(GRBG) order is supported */
2820 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
2821 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
2823 mode = v4l2_find_nearest_size(supported_modes,
2824 ARRAY_SIZE(supported_modes),
2826 fmt->format.width, fmt->format.height);
2827 ov08x40_update_pad_format(mode, fmt);
2828 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2829 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
2830 *framefmt = fmt->format;
2832 ov08x->cur_mode = mode;
2833 __v4l2_ctrl_s_ctrl(ov08x->link_freq, mode->link_freq_index);
2834 link_freq = link_freq_menu_items[mode->link_freq_index];
2835 pixel_rate = link_freq_to_pixel_rate(link_freq);
2836 __v4l2_ctrl_s_ctrl_int64(ov08x->pixel_rate, pixel_rate);
2838 /* Update limits and set FPS to default */
2839 vblank_def = ov08x->cur_mode->vts_def -
2840 ov08x->cur_mode->height;
2841 vblank_min = ov08x->cur_mode->vts_min -
2842 ov08x->cur_mode->height;
2843 __v4l2_ctrl_modify_range(ov08x->vblank, vblank_min,
2845 - ov08x->cur_mode->height,
2848 __v4l2_ctrl_s_ctrl(ov08x->vblank, vblank_def);
2849 h_blank = ov08x->cur_mode->hts;
2850 __v4l2_ctrl_modify_range(ov08x->hblank, h_blank,
2851 h_blank, 1, h_blank);
2854 mutex_unlock(&ov08x->mutex);
2859 static int ov08x40_start_streaming(struct ov08x40 *ov08x)
2861 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2862 const struct ov08x40_reg_list *reg_list;
2863 int ret, link_freq_index;
2865 /* Get out of from software reset */
2866 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SOFTWARE_RST,
2867 OV08X40_REG_VALUE_08BIT, OV08X40_SOFTWARE_RST);
2869 dev_err(&client->dev, "%s failed to set powerup registers\n",
2874 link_freq_index = ov08x->cur_mode->link_freq_index;
2875 reg_list = &link_freq_configs[link_freq_index].reg_list;
2877 ret = ov08x40_write_reg_list(ov08x, reg_list);
2879 dev_err(&client->dev, "%s failed to set plls\n", __func__);
2883 /* Apply default values of current mode */
2884 reg_list = &ov08x->cur_mode->reg_list;
2885 ret = ov08x40_write_reg_list(ov08x, reg_list);
2887 dev_err(&client->dev, "%s failed to set mode\n", __func__);
2891 /* Apply customized values from user */
2892 ret = __v4l2_ctrl_handler_setup(ov08x->sd.ctrl_handler);
2896 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT,
2897 OV08X40_REG_VALUE_08BIT,
2898 OV08X40_MODE_STREAMING);
2901 /* Stop streaming */
2902 static int ov08x40_stop_streaming(struct ov08x40 *ov08x)
2904 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT,
2905 OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY);
2908 static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable)
2910 struct ov08x40 *ov08x = to_ov08x40(sd);
2911 struct i2c_client *client = v4l2_get_subdevdata(sd);
2914 mutex_lock(&ov08x->mutex);
2917 ret = pm_runtime_resume_and_get(&client->dev);
2922 * Apply default & customized values
2923 * and then start streaming.
2925 ret = ov08x40_start_streaming(ov08x);
2929 ov08x40_stop_streaming(ov08x);
2930 pm_runtime_put(&client->dev);
2933 mutex_unlock(&ov08x->mutex);
2938 pm_runtime_put(&client->dev);
2940 mutex_unlock(&ov08x->mutex);
2945 /* Verify chip ID */
2946 static int ov08x40_identify_module(struct ov08x40 *ov08x)
2948 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2952 ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID,
2953 OV08X40_REG_VALUE_24BIT, &val);
2957 if (val != OV08X40_CHIP_ID) {
2958 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
2959 OV08X40_CHIP_ID, val);
2966 static const struct v4l2_subdev_video_ops ov08x40_video_ops = {
2967 .s_stream = ov08x40_set_stream,
2970 static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = {
2971 .enum_mbus_code = ov08x40_enum_mbus_code,
2972 .get_fmt = ov08x40_get_pad_format,
2973 .set_fmt = ov08x40_set_pad_format,
2974 .enum_frame_size = ov08x40_enum_frame_size,
2977 static const struct v4l2_subdev_ops ov08x40_subdev_ops = {
2978 .video = &ov08x40_video_ops,
2979 .pad = &ov08x40_pad_ops,
2982 static const struct media_entity_operations ov08x40_subdev_entity_ops = {
2983 .link_validate = v4l2_subdev_link_validate,
2986 static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = {
2987 .open = ov08x40_open,
2990 static int ov08x40_init_controls(struct ov08x40 *ov08x)
2992 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2993 struct v4l2_fwnode_device_properties props;
2994 struct v4l2_ctrl_handler *ctrl_hdlr;
3001 const struct ov08x40_mode *mode;
3005 ctrl_hdlr = &ov08x->ctrl_handler;
3006 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
3010 mutex_init(&ov08x->mutex);
3011 ctrl_hdlr->lock = &ov08x->mutex;
3012 max = ARRAY_SIZE(link_freq_menu_items) - 1;
3013 ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
3018 link_freq_menu_items);
3019 if (ov08x->link_freq)
3020 ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
3022 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
3024 /* By default, PIXEL_RATE is read only */
3025 ov08x->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
3026 V4L2_CID_PIXEL_RATE,
3027 pixel_rate_min, pixel_rate_max,
3030 mode = ov08x->cur_mode;
3031 vblank_def = mode->vts_def - mode->height;
3032 vblank_min = mode->vts_min - mode->height;
3033 ov08x->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
3036 OV08X40_VTS_MAX - mode->height, 1,
3039 hblank = ov08x->cur_mode->hts;
3040 ov08x->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
3042 hblank, hblank, 1, hblank);
3044 ov08x->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
3046 exposure_max = mode->vts_def - OV08X40_EXPOSURE_MAX_MARGIN;
3047 ov08x->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
3049 OV08X40_EXPOSURE_MIN,
3050 exposure_max, OV08X40_EXPOSURE_STEP,
3053 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
3054 OV08X40_ANA_GAIN_MIN, OV08X40_ANA_GAIN_MAX,
3055 OV08X40_ANA_GAIN_STEP, OV08X40_ANA_GAIN_DEFAULT);
3058 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
3059 OV08X40_DGTL_GAIN_MIN, OV08X40_DGTL_GAIN_MAX,
3060 OV08X40_DGTL_GAIN_STEP, OV08X40_DGTL_GAIN_DEFAULT);
3062 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08x40_ctrl_ops,
3063 V4L2_CID_TEST_PATTERN,
3064 ARRAY_SIZE(ov08x40_test_pattern_menu) - 1,
3065 0, 0, ov08x40_test_pattern_menu);
3067 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
3068 V4L2_CID_HFLIP, 0, 1, 1, 0);
3069 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
3070 V4L2_CID_VFLIP, 0, 1, 1, 0);
3072 if (ctrl_hdlr->error) {
3073 ret = ctrl_hdlr->error;
3074 dev_err(&client->dev, "%s control init failed (%d)\n",
3079 ret = v4l2_fwnode_device_parse(&client->dev, &props);
3083 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov08x40_ctrl_ops,
3088 ov08x->sd.ctrl_handler = ctrl_hdlr;
3093 v4l2_ctrl_handler_free(ctrl_hdlr);
3094 mutex_destroy(&ov08x->mutex);
3099 static void ov08x40_free_controls(struct ov08x40 *ov08x)
3101 v4l2_ctrl_handler_free(ov08x->sd.ctrl_handler);
3102 mutex_destroy(&ov08x->mutex);
3105 static int ov08x40_check_hwcfg(struct device *dev)
3107 struct v4l2_fwnode_endpoint bus_cfg = {
3108 .bus_type = V4L2_MBUS_CSI2_DPHY
3110 struct fwnode_handle *ep;
3111 struct fwnode_handle *fwnode = dev_fwnode(dev);
3119 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
3122 dev_err(dev, "can't get clock frequency");
3126 if (ext_clk != OV08X40_EXT_CLK) {
3127 dev_err(dev, "external clock %d is not supported",
3132 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
3136 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
3137 fwnode_handle_put(ep);
3141 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV08X40_DATA_LANES) {
3142 dev_err(dev, "number of CSI2 data lanes %d is not supported",
3143 bus_cfg.bus.mipi_csi2.num_data_lanes);
3148 if (!bus_cfg.nr_of_link_frequencies) {
3149 dev_err(dev, "no link frequencies defined");
3154 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
3155 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
3156 if (link_freq_menu_items[i] ==
3157 bus_cfg.link_frequencies[j])
3161 if (j == bus_cfg.nr_of_link_frequencies) {
3162 dev_err(dev, "no link frequency %lld supported",
3163 link_freq_menu_items[i]);
3170 v4l2_fwnode_endpoint_free(&bus_cfg);
3175 static int ov08x40_probe(struct i2c_client *client)
3177 struct ov08x40 *ov08x;
3180 /* Check HW config */
3181 ret = ov08x40_check_hwcfg(&client->dev);
3183 dev_err(&client->dev, "failed to check hwcfg: %d", ret);
3187 ov08x = devm_kzalloc(&client->dev, sizeof(*ov08x), GFP_KERNEL);
3191 /* Initialize subdev */
3192 v4l2_i2c_subdev_init(&ov08x->sd, client, &ov08x40_subdev_ops);
3194 /* Check module identity */
3195 ret = ov08x40_identify_module(ov08x);
3197 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
3201 /* Set default mode to max resolution */
3202 ov08x->cur_mode = &supported_modes[0];
3204 ret = ov08x40_init_controls(ov08x);
3208 /* Initialize subdev */
3209 ov08x->sd.internal_ops = &ov08x40_internal_ops;
3210 ov08x->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
3211 ov08x->sd.entity.ops = &ov08x40_subdev_entity_ops;
3212 ov08x->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
3214 /* Initialize source pad */
3215 ov08x->pad.flags = MEDIA_PAD_FL_SOURCE;
3216 ret = media_entity_pads_init(&ov08x->sd.entity, 1, &ov08x->pad);
3218 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
3219 goto error_handler_free;
3222 ret = v4l2_async_register_subdev_sensor(&ov08x->sd);
3224 goto error_media_entity;
3227 * Device is already turned on by i2c-core with ACPI domain PM.
3228 * Enable runtime PM and turn off the device.
3230 pm_runtime_set_active(&client->dev);
3231 pm_runtime_enable(&client->dev);
3232 pm_runtime_idle(&client->dev);
3237 media_entity_cleanup(&ov08x->sd.entity);
3240 ov08x40_free_controls(ov08x);
3245 static void ov08x40_remove(struct i2c_client *client)
3247 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3248 struct ov08x40 *ov08x = to_ov08x40(sd);
3250 v4l2_async_unregister_subdev(sd);
3251 media_entity_cleanup(&sd->entity);
3252 ov08x40_free_controls(ov08x);
3254 pm_runtime_disable(&client->dev);
3255 pm_runtime_set_suspended(&client->dev);
3259 static const struct acpi_device_id ov08x40_acpi_ids[] = {
3264 MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids);
3267 static struct i2c_driver ov08x40_i2c_driver = {
3270 .acpi_match_table = ACPI_PTR(ov08x40_acpi_ids),
3272 .probe = ov08x40_probe,
3273 .remove = ov08x40_remove,
3276 module_i2c_driver(ov08x40_i2c_driver);
3279 MODULE_AUTHOR("Shawn Tu");
3280 MODULE_DESCRIPTION("OmniVision OV08X40 sensor driver");
3281 MODULE_LICENSE("GPL");
projects / J-linux.git / blob