drivers/media/i2c/mt9v032.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
   4  *
   5  * Copyright (C) 2010, Laurent Pinchart <[email protected]>
   6  *
   7  * Based on the MT9M001 driver,
   8  *
   9  * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/i2c.h>
  16 #include <linux/log2.h>
  17 #include <linux/mod_devicetable.h>
  18 #include <linux/mutex.h>
  19 #include <linux/of.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/regmap.h>
  22 #include <linux/slab.h>
  23 #include <linux/videodev2.h>
  24 #include <linux/v4l2-mediabus.h>
  25 #include <linux/module.h>
  26
  27 #include <media/i2c/mt9v032.h>
  28 #include <media/v4l2-ctrls.h>
  29 #include <media/v4l2-device.h>
  30 #include <media/v4l2-fwnode.h>
  31 #include <media/v4l2-subdev.h>
  32
  33 /* The first four rows are black rows. The active area spans 753x481 pixels. */
  34 #define MT9V032_PIXEL_ARRAY_HEIGHT                      485
  35 #define MT9V032_PIXEL_ARRAY_WIDTH                       753
  36
  37 #define MT9V032_SYSCLK_FREQ_DEF                         26600000
  38
  39 #define MT9V032_CHIP_VERSION                            0x00
  40 #define         MT9V032_CHIP_ID_REV1                    0x1311
  41 #define         MT9V032_CHIP_ID_REV3                    0x1313
  42 #define         MT9V034_CHIP_ID_REV1                    0X1324
  43 #define MT9V032_COLUMN_START                            0x01
  44 #define         MT9V032_COLUMN_START_MIN                1
  45 #define         MT9V032_COLUMN_START_DEF                1
  46 #define         MT9V032_COLUMN_START_MAX                752
  47 #define MT9V032_ROW_START                               0x02
  48 #define         MT9V032_ROW_START_MIN                   4
  49 #define         MT9V032_ROW_START_DEF                   5
  50 #define         MT9V032_ROW_START_MAX                   482
  51 #define MT9V032_WINDOW_HEIGHT                           0x03
  52 #define         MT9V032_WINDOW_HEIGHT_MIN               1
  53 #define         MT9V032_WINDOW_HEIGHT_DEF               480
  54 #define         MT9V032_WINDOW_HEIGHT_MAX               480
  55 #define MT9V032_WINDOW_WIDTH                            0x04
  56 #define         MT9V032_WINDOW_WIDTH_MIN                1
  57 #define         MT9V032_WINDOW_WIDTH_DEF                752
  58 #define         MT9V032_WINDOW_WIDTH_MAX                752
  59 #define MT9V032_HORIZONTAL_BLANKING                     0x05
  60 #define         MT9V032_HORIZONTAL_BLANKING_MIN         43
  61 #define         MT9V034_HORIZONTAL_BLANKING_MIN         61
  62 #define         MT9V032_HORIZONTAL_BLANKING_DEF         94
  63 #define         MT9V032_HORIZONTAL_BLANKING_MAX         1023
  64 #define MT9V032_VERTICAL_BLANKING                       0x06
  65 #define         MT9V032_VERTICAL_BLANKING_MIN           4
  66 #define         MT9V034_VERTICAL_BLANKING_MIN           2
  67 #define         MT9V032_VERTICAL_BLANKING_DEF           45
  68 #define         MT9V032_VERTICAL_BLANKING_MAX           3000
  69 #define         MT9V034_VERTICAL_BLANKING_MAX           32288
  70 #define MT9V032_CHIP_CONTROL                            0x07
  71 #define         MT9V032_CHIP_CONTROL_MASTER_MODE        (1 << 3)
  72 #define         MT9V032_CHIP_CONTROL_DOUT_ENABLE        (1 << 7)
  73 #define         MT9V032_CHIP_CONTROL_SEQUENTIAL         (1 << 8)
  74 #define MT9V032_SHUTTER_WIDTH1                          0x08
  75 #define MT9V032_SHUTTER_WIDTH2                          0x09
  76 #define MT9V032_SHUTTER_WIDTH_CONTROL                   0x0a
  77 #define MT9V032_TOTAL_SHUTTER_WIDTH                     0x0b
  78 #define         MT9V032_TOTAL_SHUTTER_WIDTH_MIN         1
  79 #define         MT9V034_TOTAL_SHUTTER_WIDTH_MIN         0
  80 #define         MT9V032_TOTAL_SHUTTER_WIDTH_DEF         480
  81 #define         MT9V032_TOTAL_SHUTTER_WIDTH_MAX         32767
  82 #define         MT9V034_TOTAL_SHUTTER_WIDTH_MAX         32765
  83 #define MT9V032_RESET                                   0x0c
  84 #define MT9V032_READ_MODE                               0x0d
  85 #define         MT9V032_READ_MODE_ROW_BIN_MASK          (3 << 0)
  86 #define         MT9V032_READ_MODE_ROW_BIN_SHIFT         0
  87 #define         MT9V032_READ_MODE_COLUMN_BIN_MASK       (3 << 2)
  88 #define         MT9V032_READ_MODE_COLUMN_BIN_SHIFT      2
  89 #define         MT9V032_READ_MODE_ROW_FLIP              (1 << 4)
  90 #define         MT9V032_READ_MODE_COLUMN_FLIP           (1 << 5)
  91 #define         MT9V032_READ_MODE_DARK_COLUMNS          (1 << 6)
  92 #define         MT9V032_READ_MODE_DARK_ROWS             (1 << 7)
  93 #define         MT9V032_READ_MODE_RESERVED              0x0300
  94 #define MT9V032_PIXEL_OPERATION_MODE                    0x0f
  95 #define         MT9V034_PIXEL_OPERATION_MODE_HDR        (1 << 0)
  96 #define         MT9V034_PIXEL_OPERATION_MODE_COLOR      (1 << 1)
  97 #define         MT9V032_PIXEL_OPERATION_MODE_COLOR      (1 << 2)
  98 #define         MT9V032_PIXEL_OPERATION_MODE_HDR        (1 << 6)
  99 #define MT9V032_ANALOG_GAIN                             0x35
 100 #define         MT9V032_ANALOG_GAIN_MIN                 16
 101 #define         MT9V032_ANALOG_GAIN_DEF                 16
 102 #define         MT9V032_ANALOG_GAIN_MAX                 64
 103 #define MT9V032_MAX_ANALOG_GAIN                         0x36
 104 #define         MT9V032_MAX_ANALOG_GAIN_MAX             127
 105 #define MT9V032_FRAME_DARK_AVERAGE                      0x42
 106 #define MT9V032_DARK_AVG_THRESH                         0x46
 107 #define         MT9V032_DARK_AVG_LOW_THRESH_MASK        (255 << 0)
 108 #define         MT9V032_DARK_AVG_LOW_THRESH_SHIFT       0
 109 #define         MT9V032_DARK_AVG_HIGH_THRESH_MASK       (255 << 8)
 110 #define         MT9V032_DARK_AVG_HIGH_THRESH_SHIFT      8
 111 #define MT9V032_ROW_NOISE_CORR_CONTROL                  0x70
 112 #define         MT9V034_ROW_NOISE_CORR_ENABLE           (1 << 0)
 113 #define         MT9V034_ROW_NOISE_CORR_USE_BLK_AVG      (1 << 1)
 114 #define         MT9V032_ROW_NOISE_CORR_ENABLE           (1 << 5)
 115 #define         MT9V032_ROW_NOISE_CORR_USE_BLK_AVG      (1 << 7)
 116 #define MT9V032_PIXEL_CLOCK                             0x74
 117 #define MT9V034_PIXEL_CLOCK                             0x72
 118 #define         MT9V032_PIXEL_CLOCK_INV_LINE            (1 << 0)
 119 #define         MT9V032_PIXEL_CLOCK_INV_FRAME           (1 << 1)
 120 #define         MT9V032_PIXEL_CLOCK_XOR_LINE            (1 << 2)
 121 #define         MT9V032_PIXEL_CLOCK_CONT_LINE           (1 << 3)
 122 #define         MT9V032_PIXEL_CLOCK_INV_PXL_CLK         (1 << 4)
 123 #define MT9V032_TEST_PATTERN                            0x7f
 124 #define         MT9V032_TEST_PATTERN_DATA_MASK          (1023 << 0)
 125 #define         MT9V032_TEST_PATTERN_DATA_SHIFT         0
 126 #define         MT9V032_TEST_PATTERN_USE_DATA           (1 << 10)
 127 #define         MT9V032_TEST_PATTERN_GRAY_MASK          (3 << 11)
 128 #define         MT9V032_TEST_PATTERN_GRAY_NONE          (0 << 11)
 129 #define         MT9V032_TEST_PATTERN_GRAY_VERTICAL      (1 << 11)
 130 #define         MT9V032_TEST_PATTERN_GRAY_HORIZONTAL    (2 << 11)
 131 #define         MT9V032_TEST_PATTERN_GRAY_DIAGONAL      (3 << 11)
 132 #define         MT9V032_TEST_PATTERN_ENABLE             (1 << 13)
 133 #define         MT9V032_TEST_PATTERN_FLIP               (1 << 14)
 134 #define MT9V032_AEGC_DESIRED_BIN                        0xa5
 135 #define MT9V032_AEC_UPDATE_FREQUENCY                    0xa6
 136 #define MT9V032_AEC_LPF                                 0xa8
 137 #define MT9V032_AGC_UPDATE_FREQUENCY                    0xa9
 138 #define MT9V032_AGC_LPF                                 0xaa
 139 #define MT9V032_AEC_AGC_ENABLE                          0xaf
 140 #define         MT9V032_AEC_ENABLE                      (1 << 0)
 141 #define         MT9V032_AGC_ENABLE                      (1 << 1)
 142 #define MT9V034_AEC_MAX_SHUTTER_WIDTH                   0xad
 143 #define MT9V032_AEC_MAX_SHUTTER_WIDTH                   0xbd
 144 #define MT9V032_THERMAL_INFO                            0xc1
 145
 146 enum mt9v032_model {
 147         MT9V032_MODEL_V022_COLOR,       /* MT9V022IX7ATC */
 148         MT9V032_MODEL_V022_MONO,        /* MT9V022IX7ATM */
 149         MT9V032_MODEL_V024_COLOR,       /* MT9V024IA7XTC */
 150         MT9V032_MODEL_V024_MONO,        /* MT9V024IA7XTM */
 151         MT9V032_MODEL_V032_COLOR,       /* MT9V032C12STM */
 152         MT9V032_MODEL_V032_MONO,        /* MT9V032C12STC */
 153         MT9V032_MODEL_V034_COLOR,
 154         MT9V032_MODEL_V034_MONO,
 155 };
 156
 157 struct mt9v032_model_version {
 158         unsigned int version;
 159         const char *name;
 160 };
 161
 162 struct mt9v032_model_data {
 163         unsigned int min_row_time;
 164         unsigned int min_hblank;
 165         unsigned int min_vblank;
 166         unsigned int max_vblank;
 167         unsigned int min_shutter;
 168         unsigned int max_shutter;
 169         unsigned int pclk_reg;
 170         unsigned int aec_max_shutter_reg;
 171         const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
 172 };
 173
 174 struct mt9v032_model_info {
 175         const struct mt9v032_model_data *data;
 176         bool color;
 177 };
 178
 179 static const struct mt9v032_model_version mt9v032_versions[] = {
 180         { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
 181         { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
 182         { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
 183 };
 184
 185 struct mt9v032 {
 186         struct v4l2_subdev subdev;
 187         struct media_pad pad;
 188
 189         struct v4l2_mbus_framefmt format;
 190         struct v4l2_rect crop;
 191         unsigned int hratio;
 192         unsigned int vratio;
 193
 194         struct v4l2_ctrl_handler ctrls;
 195         struct {
 196                 struct v4l2_ctrl *link_freq;
 197                 struct v4l2_ctrl *pixel_rate;
 198         };
 199
 200         struct mutex power_lock;
 201         int power_count;
 202
 203         struct regmap *regmap;
 204         struct clk *clk;
 205         struct gpio_desc *reset_gpio;
 206         struct gpio_desc *standby_gpio;
 207
 208         struct mt9v032_platform_data *pdata;
 209         const struct mt9v032_model_info *model;
 210         const struct mt9v032_model_version *version;
 211
 212         u32 sysclk;
 213         u16 aec_agc;
 214         u16 hblank;
 215         struct {
 216                 struct v4l2_ctrl *test_pattern;
 217                 struct v4l2_ctrl *test_pattern_color;
 218         };
 219 };
 220
 221 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
 222 {
 223         return container_of(sd, struct mt9v032, subdev);
 224 }
 225
 226 static int
 227 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
 228 {
 229         struct regmap *map = mt9v032->regmap;
 230         u16 value = mt9v032->aec_agc;
 231         int ret;
 232
 233         if (enable)
 234                 value |= which;
 235         else
 236                 value &= ~which;
 237
 238         ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
 239         if (ret < 0)
 240                 return ret;
 241
 242         mt9v032->aec_agc = value;
 243         return 0;
 244 }
 245
 246 static int
 247 mt9v032_update_hblank(struct mt9v032 *mt9v032)
 248 {
 249         struct v4l2_rect *crop = &mt9v032->crop;
 250         unsigned int min_hblank = mt9v032->model->data->min_hblank;
 251         unsigned int hblank;
 252
 253         if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
 254                 min_hblank += (mt9v032->hratio - 1) * 10;
 255         min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
 256                            min_hblank);
 257         hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
 258
 259         return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
 260                             hblank);
 261 }
 262
 263 static int mt9v032_power_on(struct mt9v032 *mt9v032)
 264 {
 265         struct regmap *map = mt9v032->regmap;
 266         int ret;
 267
 268         gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
 269
 270         ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
 271         if (ret < 0)
 272                 return ret;
 273
 274         /* System clock has to be enabled before releasing the reset */
 275         ret = clk_prepare_enable(mt9v032->clk);
 276         if (ret)
 277                 return ret;
 278
 279         udelay(1);
 280
 281         if (mt9v032->reset_gpio) {
 282                 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
 283
 284                 /* After releasing reset we need to wait 10 clock cycles
 285                  * before accessing the sensor over I2C. As the minimum SYSCLK
 286                  * frequency is 13MHz, waiting 1µs will be enough in the worst
 287                  * case.
 288                  */
 289                 udelay(1);
 290         }
 291
 292         /* Reset the chip and stop data read out */
 293         ret = regmap_write(map, MT9V032_RESET, 1);
 294         if (ret < 0)
 295                 goto err;
 296
 297         ret = regmap_write(map, MT9V032_RESET, 0);
 298         if (ret < 0)
 299                 goto err;
 300
 301         ret = regmap_write(map, MT9V032_CHIP_CONTROL,
 302                            MT9V032_CHIP_CONTROL_MASTER_MODE);
 303         if (ret < 0)
 304                 goto err;
 305
 306         return 0;
 307
 308 err:
 309         clk_disable_unprepare(mt9v032->clk);
 310         return ret;
 311 }
 312
 313 static void mt9v032_power_off(struct mt9v032 *mt9v032)
 314 {
 315         clk_disable_unprepare(mt9v032->clk);
 316 }
 317
 318 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
 319 {
 320         struct regmap *map = mt9v032->regmap;
 321         int ret;
 322
 323         if (!on) {
 324                 mt9v032_power_off(mt9v032);
 325                 return 0;
 326         }
 327
 328         ret = mt9v032_power_on(mt9v032);
 329         if (ret < 0)
 330                 return ret;
 331
 332         /* Configure the pixel clock polarity */
 333         if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
 334                 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
 335                                 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
 336                 if (ret < 0)
 337                         return ret;
 338         }
 339
 340         /* Disable the noise correction algorithm and restore the controls. */
 341         ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
 342         if (ret < 0)
 343                 return ret;
 344
 345         return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
 346 }
 347
 348 /* -----------------------------------------------------------------------------
 349  * V4L2 subdev video operations
 350  */
 351
 352 static struct v4l2_mbus_framefmt *
 353 __mt9v032_get_pad_format(struct mt9v032 *mt9v032,
 354                          struct v4l2_subdev_state *sd_state,
 355                          unsigned int pad, enum v4l2_subdev_format_whence which)
 356 {
 357         switch (which) {
 358         case V4L2_SUBDEV_FORMAT_TRY:
 359                 return v4l2_subdev_get_try_format(&mt9v032->subdev, sd_state,
 360                                                   pad);
 361         case V4L2_SUBDEV_FORMAT_ACTIVE:
 362                 return &mt9v032->format;
 363         default:
 364                 return NULL;
 365         }
 366 }
 367
 368 static struct v4l2_rect *
 369 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032,
 370                        struct v4l2_subdev_state *sd_state,
 371                        unsigned int pad, enum v4l2_subdev_format_whence which)
 372 {
 373         switch (which) {
 374         case V4L2_SUBDEV_FORMAT_TRY:
 375                 return v4l2_subdev_get_try_crop(&mt9v032->subdev, sd_state,
 376                                                 pad);
 377         case V4L2_SUBDEV_FORMAT_ACTIVE:
 378                 return &mt9v032->crop;
 379         default:
 380                 return NULL;
 381         }
 382 }
 383
 384 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
 385 {
 386         const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
 387                        | MT9V032_CHIP_CONTROL_SEQUENTIAL;
 388         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 389         struct v4l2_rect *crop = &mt9v032->crop;
 390         struct regmap *map = mt9v032->regmap;
 391         unsigned int hbin;
 392         unsigned int vbin;
 393         int ret;
 394
 395         if (!enable)
 396                 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
 397
 398         /* Configure the window size and row/column bin */
 399         hbin = fls(mt9v032->hratio) - 1;
 400         vbin = fls(mt9v032->vratio) - 1;
 401         ret = regmap_update_bits(map, MT9V032_READ_MODE,
 402                                  ~MT9V032_READ_MODE_RESERVED,
 403                                  hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
 404                                  vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
 405         if (ret < 0)
 406                 return ret;
 407
 408         ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
 409         if (ret < 0)
 410                 return ret;
 411
 412         ret = regmap_write(map, MT9V032_ROW_START, crop->top);
 413         if (ret < 0)
 414                 return ret;
 415
 416         ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
 417         if (ret < 0)
 418                 return ret;
 419
 420         ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
 421         if (ret < 0)
 422                 return ret;
 423
 424         ret = mt9v032_update_hblank(mt9v032);
 425         if (ret < 0)
 426                 return ret;
 427
 428         /* Switch to master "normal" mode */
 429         return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
 430 }
 431
 432 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
 433                                   struct v4l2_subdev_state *sd_state,
 434                                   struct v4l2_subdev_mbus_code_enum *code)
 435 {
 436         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 437
 438         if (code->index > 0)
 439                 return -EINVAL;
 440
 441         code->code = mt9v032->format.code;
 442         return 0;
 443 }
 444
 445 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
 446                                    struct v4l2_subdev_state *sd_state,
 447                                    struct v4l2_subdev_frame_size_enum *fse)
 448 {
 449         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 450
 451         if (fse->index >= 3)
 452                 return -EINVAL;
 453         if (mt9v032->format.code != fse->code)
 454                 return -EINVAL;
 455
 456         fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
 457         fse->max_width = fse->min_width;
 458         fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
 459         fse->max_height = fse->min_height;
 460
 461         return 0;
 462 }
 463
 464 static int mt9v032_get_format(struct v4l2_subdev *subdev,
 465                               struct v4l2_subdev_state *sd_state,
 466                               struct v4l2_subdev_format *format)
 467 {
 468         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 469
 470         format->format = *__mt9v032_get_pad_format(mt9v032, sd_state,
 471                                                    format->pad,
 472                                                    format->which);
 473         return 0;
 474 }
 475
 476 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
 477 {
 478         struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
 479         int ret;
 480
 481         ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
 482                                      mt9v032->sysclk / mt9v032->hratio);
 483         if (ret < 0)
 484                 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
 485 }
 486
 487 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
 488 {
 489         /* Compute the power-of-two binning factor closest to the input size to
 490          * output size ratio. Given that the output size is bounded by input/4
 491          * and input, a generic implementation would be an ineffective luxury.
 492          */
 493         if (output * 3 > input * 2)
 494                 return 1;
 495         if (output * 3 > input)
 496                 return 2;
 497         return 4;
 498 }
 499
 500 static int mt9v032_set_format(struct v4l2_subdev *subdev,
 501                               struct v4l2_subdev_state *sd_state,
 502                               struct v4l2_subdev_format *format)
 503 {
 504         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 505         struct v4l2_mbus_framefmt *__format;
 506         struct v4l2_rect *__crop;
 507         unsigned int width;
 508         unsigned int height;
 509         unsigned int hratio;
 510         unsigned int vratio;
 511
 512         __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, format->pad,
 513                                         format->which);
 514
 515         /* Clamp the width and height to avoid dividing by zero. */
 516         width = clamp(ALIGN(format->format.width, 2),
 517                       max_t(unsigned int, __crop->width / 4,
 518                             MT9V032_WINDOW_WIDTH_MIN),
 519                       __crop->width);
 520         height = clamp(ALIGN(format->format.height, 2),
 521                        max_t(unsigned int, __crop->height / 4,
 522                              MT9V032_WINDOW_HEIGHT_MIN),
 523                        __crop->height);
 524
 525         hratio = mt9v032_calc_ratio(__crop->width, width);
 526         vratio = mt9v032_calc_ratio(__crop->height, height);
 527
 528         __format = __mt9v032_get_pad_format(mt9v032, sd_state, format->pad,
 529                                             format->which);
 530         __format->width = __crop->width / hratio;
 531         __format->height = __crop->height / vratio;
 532
 533         if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 534                 mt9v032->hratio = hratio;
 535                 mt9v032->vratio = vratio;
 536                 mt9v032_configure_pixel_rate(mt9v032);
 537         }
 538
 539         format->format = *__format;
 540
 541         return 0;
 542 }
 543
 544 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
 545                                  struct v4l2_subdev_state *sd_state,
 546                                  struct v4l2_subdev_selection *sel)
 547 {
 548         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 549
 550         if (sel->target != V4L2_SEL_TGT_CROP)
 551                 return -EINVAL;
 552
 553         sel->r = *__mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad,
 554                                          sel->which);
 555         return 0;
 556 }
 557
 558 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
 559                                  struct v4l2_subdev_state *sd_state,
 560                                  struct v4l2_subdev_selection *sel)
 561 {
 562         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 563         struct v4l2_mbus_framefmt *__format;
 564         struct v4l2_rect *__crop;
 565         struct v4l2_rect rect;
 566
 567         if (sel->target != V4L2_SEL_TGT_CROP)
 568                 return -EINVAL;
 569
 570         /* Clamp the crop rectangle boundaries and align them to a non multiple
 571          * of 2 pixels to ensure a GRBG Bayer pattern.
 572          */
 573         rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
 574                           MT9V032_COLUMN_START_MIN,
 575                           MT9V032_COLUMN_START_MAX);
 576         rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
 577                          MT9V032_ROW_START_MIN,
 578                          MT9V032_ROW_START_MAX);
 579         rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
 580                              MT9V032_WINDOW_WIDTH_MIN,
 581                              MT9V032_WINDOW_WIDTH_MAX);
 582         rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
 583                               MT9V032_WINDOW_HEIGHT_MIN,
 584                               MT9V032_WINDOW_HEIGHT_MAX);
 585
 586         rect.width = min_t(unsigned int,
 587                            rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
 588         rect.height = min_t(unsigned int,
 589                             rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
 590
 591         __crop = __mt9v032_get_pad_crop(mt9v032, sd_state, sel->pad,
 592                                         sel->which);
 593
 594         if (rect.width != __crop->width || rect.height != __crop->height) {
 595                 /* Reset the output image size if the crop rectangle size has
 596                  * been modified.
 597                  */
 598                 __format = __mt9v032_get_pad_format(mt9v032, sd_state,
 599                                                     sel->pad,
 600                                                     sel->which);
 601                 __format->width = rect.width;
 602                 __format->height = rect.height;
 603                 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
 604                         mt9v032->hratio = 1;
 605                         mt9v032->vratio = 1;
 606                         mt9v032_configure_pixel_rate(mt9v032);
 607                 }
 608         }
 609
 610         *__crop = rect;
 611         sel->r = rect;
 612
 613         return 0;
 614 }
 615
 616 /* -----------------------------------------------------------------------------
 617  * V4L2 subdev control operations
 618  */
 619
 620 #define V4L2_CID_TEST_PATTERN_COLOR     (V4L2_CID_USER_BASE | 0x1001)
 621 /*
 622  * Value between 1 and 64 to set the desired bin. This is effectively a measure
 623  * of how bright the image is supposed to be. Both AGC and AEC try to reach
 624  * this.
 625  */
 626 #define V4L2_CID_AEGC_DESIRED_BIN       (V4L2_CID_USER_BASE | 0x1002)
 627 /*
 628  * LPF is the low pass filter capability of the chip. Both AEC and AGC have
 629  * this setting. This limits the speed in which AGC/AEC adjust their settings.
 630  * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
 631  *
 632  * if |(calculated new exp - current exp)| > (current exp / 4)
 633  *      next exp = calculated new exp
 634  * else
 635  *      next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
 636  */
 637 #define V4L2_CID_AEC_LPF                (V4L2_CID_USER_BASE | 0x1003)
 638 #define V4L2_CID_AGC_LPF                (V4L2_CID_USER_BASE | 0x1004)
 639 /*
 640  * Value between 0 and 15. This is the number of frames being skipped before
 641  * updating the auto exposure/gain.
 642  */
 643 #define V4L2_CID_AEC_UPDATE_INTERVAL    (V4L2_CID_USER_BASE | 0x1005)
 644 #define V4L2_CID_AGC_UPDATE_INTERVAL    (V4L2_CID_USER_BASE | 0x1006)
 645 /*
 646  * Maximum shutter width used for AEC.
 647  */
 648 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH  (V4L2_CID_USER_BASE | 0x1007)
 649
 650 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
 651 {
 652         struct mt9v032 *mt9v032 =
 653                         container_of(ctrl->handler, struct mt9v032, ctrls);
 654         struct regmap *map = mt9v032->regmap;
 655         u32 freq;
 656         u16 data;
 657
 658         switch (ctrl->id) {
 659         case V4L2_CID_AUTOGAIN:
 660                 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
 661                                               ctrl->val);
 662
 663         case V4L2_CID_GAIN:
 664                 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
 665
 666         case V4L2_CID_EXPOSURE_AUTO:
 667                 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
 668                                               !ctrl->val);
 669
 670         case V4L2_CID_EXPOSURE:
 671                 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
 672                                     ctrl->val);
 673
 674         case V4L2_CID_HBLANK:
 675                 mt9v032->hblank = ctrl->val;
 676                 return mt9v032_update_hblank(mt9v032);
 677
 678         case V4L2_CID_VBLANK:
 679                 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
 680                                     ctrl->val);
 681
 682         case V4L2_CID_PIXEL_RATE:
 683         case V4L2_CID_LINK_FREQ:
 684                 if (mt9v032->link_freq == NULL)
 685                         break;
 686
 687                 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
 688                 *mt9v032->pixel_rate->p_new.p_s64 = freq;
 689                 mt9v032->sysclk = freq;
 690                 break;
 691
 692         case V4L2_CID_TEST_PATTERN:
 693                 switch (mt9v032->test_pattern->val) {
 694                 case 0:
 695                         data = 0;
 696                         break;
 697                 case 1:
 698                         data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
 699                              | MT9V032_TEST_PATTERN_ENABLE;
 700                         break;
 701                 case 2:
 702                         data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
 703                              | MT9V032_TEST_PATTERN_ENABLE;
 704                         break;
 705                 case 3:
 706                         data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
 707                              | MT9V032_TEST_PATTERN_ENABLE;
 708                         break;
 709                 default:
 710                         data = (mt9v032->test_pattern_color->val <<
 711                                 MT9V032_TEST_PATTERN_DATA_SHIFT)
 712                              | MT9V032_TEST_PATTERN_USE_DATA
 713                              | MT9V032_TEST_PATTERN_ENABLE
 714                              | MT9V032_TEST_PATTERN_FLIP;
 715                         break;
 716                 }
 717                 return regmap_write(map, MT9V032_TEST_PATTERN, data);
 718
 719         case V4L2_CID_AEGC_DESIRED_BIN:
 720                 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
 721
 722         case V4L2_CID_AEC_LPF:
 723                 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
 724
 725         case V4L2_CID_AGC_LPF:
 726                 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
 727
 728         case V4L2_CID_AEC_UPDATE_INTERVAL:
 729                 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
 730                                     ctrl->val);
 731
 732         case V4L2_CID_AGC_UPDATE_INTERVAL:
 733                 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
 734                                     ctrl->val);
 735
 736         case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
 737                 return regmap_write(map,
 738                                     mt9v032->model->data->aec_max_shutter_reg,
 739                                     ctrl->val);
 740         }
 741
 742         return 0;
 743 }
 744
 745 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
 746         .s_ctrl = mt9v032_s_ctrl,
 747 };
 748
 749 static const char * const mt9v032_test_pattern_menu[] = {
 750         "Disabled",
 751         "Gray Vertical Shade",
 752         "Gray Horizontal Shade",
 753         "Gray Diagonal Shade",
 754         "Plain",
 755 };
 756
 757 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
 758         .ops            = &mt9v032_ctrl_ops,
 759         .id             = V4L2_CID_TEST_PATTERN_COLOR,
 760         .type           = V4L2_CTRL_TYPE_INTEGER,
 761         .name           = "Test Pattern Color",
 762         .min            = 0,
 763         .max            = 1023,
 764         .step           = 1,
 765         .def            = 0,
 766         .flags          = 0,
 767 };
 768
 769 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
 770         {
 771                 .ops            = &mt9v032_ctrl_ops,
 772                 .id             = V4L2_CID_AEGC_DESIRED_BIN,
 773                 .type           = V4L2_CTRL_TYPE_INTEGER,
 774                 .name           = "AEC/AGC Desired Bin",
 775                 .min            = 1,
 776                 .max            = 64,
 777                 .step           = 1,
 778                 .def            = 58,
 779                 .flags          = 0,
 780         }, {
 781                 .ops            = &mt9v032_ctrl_ops,
 782                 .id             = V4L2_CID_AEC_LPF,
 783                 .type           = V4L2_CTRL_TYPE_INTEGER,
 784                 .name           = "AEC Low Pass Filter",
 785                 .min            = 0,
 786                 .max            = 2,
 787                 .step           = 1,
 788                 .def            = 0,
 789                 .flags          = 0,
 790         }, {
 791                 .ops            = &mt9v032_ctrl_ops,
 792                 .id             = V4L2_CID_AGC_LPF,
 793                 .type           = V4L2_CTRL_TYPE_INTEGER,
 794                 .name           = "AGC Low Pass Filter",
 795                 .min            = 0,
 796                 .max            = 2,
 797                 .step           = 1,
 798                 .def            = 2,
 799                 .flags          = 0,
 800         }, {
 801                 .ops            = &mt9v032_ctrl_ops,
 802                 .id             = V4L2_CID_AEC_UPDATE_INTERVAL,
 803                 .type           = V4L2_CTRL_TYPE_INTEGER,
 804                 .name           = "AEC Update Interval",
 805                 .min            = 0,
 806                 .max            = 16,
 807                 .step           = 1,
 808                 .def            = 2,
 809                 .flags          = 0,
 810         }, {
 811                 .ops            = &mt9v032_ctrl_ops,
 812                 .id             = V4L2_CID_AGC_UPDATE_INTERVAL,
 813                 .type           = V4L2_CTRL_TYPE_INTEGER,
 814                 .name           = "AGC Update Interval",
 815                 .min            = 0,
 816                 .max            = 16,
 817                 .step           = 1,
 818                 .def            = 2,
 819                 .flags          = 0,
 820         }
 821 };
 822
 823 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
 824         .ops            = &mt9v032_ctrl_ops,
 825         .id             = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
 826         .type           = V4L2_CTRL_TYPE_INTEGER,
 827         .name           = "AEC Max Shutter Width",
 828         .min            = 1,
 829         .max            = 2047,
 830         .step           = 1,
 831         .def            = 480,
 832         .flags          = 0,
 833 };
 834
 835 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
 836         .ops            = &mt9v032_ctrl_ops,
 837         .id             = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
 838         .type           = V4L2_CTRL_TYPE_INTEGER,
 839         .name           = "AEC Max Shutter Width",
 840         .min            = 1,
 841         .max            = 32765,
 842         .step           = 1,
 843         .def            = 480,
 844         .flags          = 0,
 845 };
 846
 847 /* -----------------------------------------------------------------------------
 848  * V4L2 subdev core operations
 849  */
 850
 851 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
 852 {
 853         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 854         int ret = 0;
 855
 856         mutex_lock(&mt9v032->power_lock);
 857
 858         /* If the power count is modified from 0 to != 0 or from != 0 to 0,
 859          * update the power state.
 860          */
 861         if (mt9v032->power_count == !on) {
 862                 ret = __mt9v032_set_power(mt9v032, !!on);
 863                 if (ret < 0)
 864                         goto done;
 865         }
 866
 867         /* Update the power count. */
 868         mt9v032->power_count += on ? 1 : -1;
 869         WARN_ON(mt9v032->power_count < 0);
 870
 871 done:
 872         mutex_unlock(&mt9v032->power_lock);
 873         return ret;
 874 }
 875
 876 /* -----------------------------------------------------------------------------
 877  * V4L2 subdev internal operations
 878  */
 879
 880 static int mt9v032_registered(struct v4l2_subdev *subdev)
 881 {
 882         struct i2c_client *client = v4l2_get_subdevdata(subdev);
 883         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 884         unsigned int i;
 885         u32 version;
 886         int ret;
 887
 888         dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
 889                         client->addr);
 890
 891         ret = mt9v032_power_on(mt9v032);
 892         if (ret < 0) {
 893                 dev_err(&client->dev, "MT9V032 power up failed\n");
 894                 return ret;
 895         }
 896
 897         /* Read and check the sensor version */
 898         ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
 899
 900         mt9v032_power_off(mt9v032);
 901
 902         if (ret < 0) {
 903                 dev_err(&client->dev, "Failed reading chip version\n");
 904                 return ret;
 905         }
 906
 907         for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
 908                 if (mt9v032_versions[i].version == version) {
 909                         mt9v032->version = &mt9v032_versions[i];
 910                         break;
 911                 }
 912         }
 913
 914         if (mt9v032->version == NULL) {
 915                 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
 916                         version);
 917                 return -ENODEV;
 918         }
 919
 920         dev_info(&client->dev, "%s detected at address 0x%02x\n",
 921                  mt9v032->version->name, client->addr);
 922
 923         mt9v032_configure_pixel_rate(mt9v032);
 924
 925         return ret;
 926 }
 927
 928 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
 929 {
 930         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
 931         struct v4l2_mbus_framefmt *format;
 932         struct v4l2_rect *crop;
 933
 934         crop = v4l2_subdev_get_try_crop(subdev, fh->state, 0);
 935         crop->left = MT9V032_COLUMN_START_DEF;
 936         crop->top = MT9V032_ROW_START_DEF;
 937         crop->width = MT9V032_WINDOW_WIDTH_DEF;
 938         crop->height = MT9V032_WINDOW_HEIGHT_DEF;
 939
 940         format = v4l2_subdev_get_try_format(subdev, fh->state, 0);
 941
 942         if (mt9v032->model->color)
 943                 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 944         else
 945                 format->code = MEDIA_BUS_FMT_Y10_1X10;
 946
 947         format->width = MT9V032_WINDOW_WIDTH_DEF;
 948         format->height = MT9V032_WINDOW_HEIGHT_DEF;
 949         format->field = V4L2_FIELD_NONE;
 950         format->colorspace = V4L2_COLORSPACE_SRGB;
 951
 952         return mt9v032_set_power(subdev, 1);
 953 }
 954
 955 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
 956 {
 957         return mt9v032_set_power(subdev, 0);
 958 }
 959
 960 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
 961         .s_power        = mt9v032_set_power,
 962 };
 963
 964 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
 965         .s_stream       = mt9v032_s_stream,
 966 };
 967
 968 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
 969         .enum_mbus_code = mt9v032_enum_mbus_code,
 970         .enum_frame_size = mt9v032_enum_frame_size,
 971         .get_fmt = mt9v032_get_format,
 972         .set_fmt = mt9v032_set_format,
 973         .get_selection = mt9v032_get_selection,
 974         .set_selection = mt9v032_set_selection,
 975 };
 976
 977 static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
 978         .core   = &mt9v032_subdev_core_ops,
 979         .video  = &mt9v032_subdev_video_ops,
 980         .pad    = &mt9v032_subdev_pad_ops,
 981 };
 982
 983 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
 984         .registered = mt9v032_registered,
 985         .open = mt9v032_open,
 986         .close = mt9v032_close,
 987 };
 988
 989 static const struct regmap_config mt9v032_regmap_config = {
 990         .reg_bits = 8,
 991         .val_bits = 16,
 992         .max_register = 0xff,
 993         .cache_type = REGCACHE_RBTREE,
 994 };
 995
 996 /* -----------------------------------------------------------------------------
 997  * Driver initialization and probing
 998  */
 999
1000 static struct mt9v032_platform_data *
1001 mt9v032_get_pdata(struct i2c_client *client)
1002 {
1003         struct mt9v032_platform_data *pdata = NULL;
1004         struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1005         struct device_node *np;
1006         struct property *prop;
1007
1008         if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1009                 return client->dev.platform_data;
1010
1011         np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1012         if (!np)
1013                 return NULL;
1014
1015         if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1016                 goto done;
1017
1018         pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1019         if (!pdata)
1020                 goto done;
1021
1022         prop = of_find_property(np, "link-frequencies", NULL);
1023         if (prop) {
1024                 u64 *link_freqs;
1025                 size_t size = prop->length / sizeof(*link_freqs);
1026
1027                 link_freqs = devm_kcalloc(&client->dev, size,
1028                                           sizeof(*link_freqs), GFP_KERNEL);
1029                 if (!link_freqs)
1030                         goto done;
1031
1032                 if (of_property_read_u64_array(np, "link-frequencies",
1033                                                link_freqs, size) < 0)
1034                         goto done;
1035
1036                 pdata->link_freqs = link_freqs;
1037                 pdata->link_def_freq = link_freqs[0];
1038         }
1039
1040         pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1041                             V4L2_MBUS_PCLK_SAMPLE_RISING);
1042
1043 done:
1044         of_node_put(np);
1045         return pdata;
1046 }
1047
1048 static int mt9v032_probe(struct i2c_client *client)
1049 {
1050         struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1051         struct mt9v032 *mt9v032;
1052         unsigned int i;
1053         int ret;
1054
1055         mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1056         if (!mt9v032)
1057                 return -ENOMEM;
1058
1059         mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1060         if (IS_ERR(mt9v032->regmap))
1061                 return PTR_ERR(mt9v032->regmap);
1062
1063         mt9v032->clk = devm_clk_get(&client->dev, NULL);
1064         if (IS_ERR(mt9v032->clk))
1065                 return PTR_ERR(mt9v032->clk);
1066
1067         mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1068                                                       GPIOD_OUT_HIGH);
1069         if (IS_ERR(mt9v032->reset_gpio))
1070                 return PTR_ERR(mt9v032->reset_gpio);
1071
1072         mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1073                                                         GPIOD_OUT_LOW);
1074         if (IS_ERR(mt9v032->standby_gpio))
1075                 return PTR_ERR(mt9v032->standby_gpio);
1076
1077         mutex_init(&mt9v032->power_lock);
1078         mt9v032->pdata = pdata;
1079         mt9v032->model = i2c_get_match_data(client);
1080
1081         v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1082                                ARRAY_SIZE(mt9v032_aegc_controls));
1083
1084         v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1085                           V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1086         v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1087                           V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1088                           MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1089         v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1090                                V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1091                                V4L2_EXPOSURE_AUTO);
1092         v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1093                           V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1094                           mt9v032->model->data->max_shutter, 1,
1095                           MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1096         v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1097                           V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1098                           MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1099                           MT9V032_HORIZONTAL_BLANKING_DEF);
1100         v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1101                           V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1102                           mt9v032->model->data->max_vblank, 1,
1103                           MT9V032_VERTICAL_BLANKING_DEF);
1104         mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1105                                 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1106                                 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1107                                 mt9v032_test_pattern_menu);
1108         mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1109                                       &mt9v032_test_pattern_color, NULL);
1110
1111         v4l2_ctrl_new_custom(&mt9v032->ctrls,
1112                              mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1113                              NULL);
1114         for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1115                 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1116                                      NULL);
1117
1118         v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1119
1120         mt9v032->pixel_rate =
1121                 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1122                                   V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1123
1124         if (pdata && pdata->link_freqs) {
1125                 unsigned int def = 0;
1126
1127                 for (i = 0; pdata->link_freqs[i]; ++i) {
1128                         if (pdata->link_freqs[i] == pdata->link_def_freq)
1129                                 def = i;
1130                 }
1131
1132                 mt9v032->link_freq =
1133                         v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1134                                                &mt9v032_ctrl_ops,
1135                                                V4L2_CID_LINK_FREQ, i - 1, def,
1136                                                pdata->link_freqs);
1137                 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1138         }
1139
1140
1141         mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1142
1143         if (mt9v032->ctrls.error) {
1144                 dev_err(&client->dev, "control initialization error %d\n",
1145                         mt9v032->ctrls.error);
1146                 ret = mt9v032->ctrls.error;
1147                 goto err;
1148         }
1149
1150         mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1151         mt9v032->crop.top = MT9V032_ROW_START_DEF;
1152         mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1153         mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1154
1155         if (mt9v032->model->color)
1156                 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1157         else
1158                 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1159
1160         mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1161         mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1162         mt9v032->format.field = V4L2_FIELD_NONE;
1163         mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1164
1165         mt9v032->hratio = 1;
1166         mt9v032->vratio = 1;
1167
1168         mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1169         mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1170         mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1171
1172         v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1173         mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1174         mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1175
1176         mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1177         mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1178         ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1179         if (ret < 0)
1180                 goto err;
1181
1182         mt9v032->subdev.dev = &client->dev;
1183         ret = v4l2_async_register_subdev(&mt9v032->subdev);
1184         if (ret < 0)
1185                 goto err;
1186
1187         return 0;
1188
1189 err:
1190         media_entity_cleanup(&mt9v032->subdev.entity);
1191         v4l2_ctrl_handler_free(&mt9v032->ctrls);
1192         return ret;
1193 }
1194
1195 static void mt9v032_remove(struct i2c_client *client)
1196 {
1197         struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1198         struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1199
1200         v4l2_async_unregister_subdev(subdev);
1201         v4l2_ctrl_handler_free(&mt9v032->ctrls);
1202         media_entity_cleanup(&subdev->entity);
1203 }
1204
1205 static const struct mt9v032_model_data mt9v032_model_data[] = {
1206         {
1207                 /* MT9V022, MT9V032 revisions 1/2/3 */
1208                 .min_row_time = 660,
1209                 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1210                 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1211                 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1212                 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1213                 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1214                 .pclk_reg = MT9V032_PIXEL_CLOCK,
1215                 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1216                 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1217         }, {
1218                 /* MT9V024, MT9V034 */
1219                 .min_row_time = 690,
1220                 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1221                 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1222                 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1223                 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1224                 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1225                 .pclk_reg = MT9V034_PIXEL_CLOCK,
1226                 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1227                 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1228         },
1229 };
1230
1231 static const struct mt9v032_model_info mt9v032_models[] = {
1232         [MT9V032_MODEL_V022_COLOR] = {
1233                 .data = &mt9v032_model_data[0],
1234                 .color = true,
1235         },
1236         [MT9V032_MODEL_V022_MONO] = {
1237                 .data = &mt9v032_model_data[0],
1238                 .color = false,
1239         },
1240         [MT9V032_MODEL_V024_COLOR] = {
1241                 .data = &mt9v032_model_data[1],
1242                 .color = true,
1243         },
1244         [MT9V032_MODEL_V024_MONO] = {
1245                 .data = &mt9v032_model_data[1],
1246                 .color = false,
1247         },
1248         [MT9V032_MODEL_V032_COLOR] = {
1249                 .data = &mt9v032_model_data[0],
1250                 .color = true,
1251         },
1252         [MT9V032_MODEL_V032_MONO] = {
1253                 .data = &mt9v032_model_data[0],
1254                 .color = false,
1255         },
1256         [MT9V032_MODEL_V034_COLOR] = {
1257                 .data = &mt9v032_model_data[1],
1258                 .color = true,
1259         },
1260         [MT9V032_MODEL_V034_MONO] = {
1261                 .data = &mt9v032_model_data[1],
1262                 .color = false,
1263         },
1264 };
1265
1266 static const struct i2c_device_id mt9v032_id[] = {
1267         { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1268         { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1269         { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1270         { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1271         { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1272         { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1273         { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1274         { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1275         { /* Sentinel */ }
1276 };
1277 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1278
1279 static const struct of_device_id mt9v032_of_match[] = {
1280         { .compatible = "aptina,mt9v022", .data = &mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1281         { .compatible = "aptina,mt9v022m", .data = &mt9v032_models[MT9V032_MODEL_V022_MONO] },
1282         { .compatible = "aptina,mt9v024", .data = &mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1283         { .compatible = "aptina,mt9v024m", .data = &mt9v032_models[MT9V032_MODEL_V024_MONO] },
1284         { .compatible = "aptina,mt9v032", .data = &mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1285         { .compatible = "aptina,mt9v032m", .data = &mt9v032_models[MT9V032_MODEL_V032_MONO] },
1286         { .compatible = "aptina,mt9v034", .data = &mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1287         { .compatible = "aptina,mt9v034m", .data = &mt9v032_models[MT9V032_MODEL_V034_MONO] },
1288         { /* Sentinel */ }
1289 };
1290 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1291
1292 static struct i2c_driver mt9v032_driver = {
1293         .driver = {
1294                 .name = "mt9v032",
1295                 .of_match_table = mt9v032_of_match,
1296         },
1297         .probe          = mt9v032_probe,
1298         .remove         = mt9v032_remove,
1299         .id_table       = mt9v032_id,
1300 };
1301
1302 module_i2c_driver(mt9v032_driver);
1303
1304 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1305 MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
1306 MODULE_LICENSE("GPL");