drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "amdgpu.h"
  28
  29 #include "dc.h"
  30
  31 #include "core_status.h"
  32 #include "core_types.h"
  33 #include "hw_sequencer.h"
  34 #include "dce/dce_hwseq.h"
  35
  36 #include "resource.h"
  37 #include "dc_state.h"
  38 #include "dc_state_priv.h"
  39 #include "dc_plane_priv.h"
  40
  41 #include "gpio_service_interface.h"
  42 #include "clk_mgr.h"
  43 #include "clock_source.h"
  44 #include "dc_bios_types.h"
  45
  46 #include "bios_parser_interface.h"
  47 #include "bios/bios_parser_helper.h"
  48 #include "include/irq_service_interface.h"
  49 #include "transform.h"
  50 #include "dmcu.h"
  51 #include "dpp.h"
  52 #include "timing_generator.h"
  53 #include "abm.h"
  54 #include "virtual/virtual_link_encoder.h"
  55 #include "hubp.h"
  56
  57 #include "link_hwss.h"
  58 #include "link_encoder.h"
  59 #include "link_enc_cfg.h"
  60
  61 #include "link.h"
  62 #include "dm_helpers.h"
  63 #include "mem_input.h"
  64
  65 #include "dc_dmub_srv.h"
  66
  67 #include "dsc.h"
  68
  69 #include "vm_helper.h"
  70
  71 #include "dce/dce_i2c.h"
  72
  73 #include "dmub/dmub_srv.h"
  74
  75 #include "dce/dmub_psr.h"
  76
  77 #include "dce/dmub_hw_lock_mgr.h"
  78
  79 #include "dc_trace.h"
  80
  81 #include "hw_sequencer_private.h"
  82
  83 #if defined(CONFIG_DRM_AMD_DC_FP)
  84 #include "dml2/dml2_internal_types.h"
  85 #endif
  86
  87 #include "dce/dmub_outbox.h"
  88
  89 #define CTX \
  90         dc->ctx
  91
  92 #define DC_LOGGER \
  93         dc->ctx->logger
  94
  95 static const char DC_BUILD_ID[] = "production-build";
  96
  97 /**
  98  * DOC: Overview
  99  *
 100  * DC is the OS-agnostic component of the amdgpu DC driver.
 101  *
 102  * DC maintains and validates a set of structs representing the state of the
 103  * driver and writes that state to AMD hardware
 104  *
 105  * Main DC HW structs:
 106  *
 107  * struct dc - The central struct.  One per driver.  Created on driver load,
 108  * destroyed on driver unload.
 109  *
 110  * struct dc_context - One per driver.
 111  * Used as a backpointer by most other structs in dc.
 112  *
 113  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 114  * plugpoints).  Created on driver load, destroyed on driver unload.
 115  *
 116  * struct dc_sink - One per display.  Created on boot or hotplug.
 117  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 118  * (the display directly attached).  It may also have one or more remote
 119  * sinks (in the Multi-Stream Transport case)
 120  *
 121  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 122  * main pipeline.  Not directly accessible by dm.
 123  *
 124  * Main dc state structs:
 125  *
 126  * These structs can be created and destroyed as needed.  There is a full set of
 127  * these structs in dc->current_state representing the currently programmed state.
 128  *
 129  * struct dc_state - The global DC state to track global state information,
 130  * such as bandwidth values.
 131  *
 132  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 133  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 134  *
 135  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 136  * and may have more in the Multi-Plane Overlay case.
 137  *
 138  * struct resource_context - Represents the programmable state of everything in
 139  * the resource_pool.  Not directly accessible by dm.
 140  *
 141  * struct pipe_ctx - A member of struct resource_context.  Represents the
 142  * internal hardware pipeline components.  Each dc_plane_state has either
 143  * one or two (in the pipe-split case).
 144  */
 145
 146 /* Private functions */
 147
 148 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 149 {
 150         if (new > *original)
 151                 *original = new;
 152 }
 153
 154 static void destroy_links(struct dc *dc)
 155 {
 156         uint32_t i;
 157
 158         for (i = 0; i < dc->link_count; i++) {
 159                 if (NULL != dc->links[i])
 160                         dc->link_srv->destroy_link(&dc->links[i]);
 161         }
 162 }
 163
 164 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 165 {
 166         int i;
 167         uint32_t count = 0;
 168
 169         for (i = 0; i < num_links; i++) {
 170                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 171                                 links[i]->is_internal_display)
 172                         count++;
 173         }
 174
 175         return count;
 176 }
 177
 178 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 179 {
 180         uint8_t i;
 181         uint8_t seamless_boot_stream_count = 0;
 182
 183         for (i = 0; i < ctx->stream_count; i++)
 184                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 185                         seamless_boot_stream_count++;
 186
 187         return seamless_boot_stream_count;
 188 }
 189
 190 static bool create_links(
 191                 struct dc *dc,
 192                 uint32_t num_virtual_links)
 193 {
 194         int i;
 195         int connectors_num;
 196         struct dc_bios *bios = dc->ctx->dc_bios;
 197
 198         dc->link_count = 0;
 199
 200         connectors_num = bios->funcs->get_connectors_number(bios);
 201
 202         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 203
 204         if (connectors_num > ENUM_ID_COUNT) {
 205                 dm_error(
 206                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 207                         connectors_num,
 208                         ENUM_ID_COUNT);
 209                 return false;
 210         }
 211
 212         dm_output_to_console(
 213                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 214                 __func__,
 215                 connectors_num,
 216                 num_virtual_links);
 217
 218         // condition loop on link_count to allow skipping invalid indices
 219         for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
 220                 struct link_init_data link_init_params = {0};
 221                 struct dc_link *link;
 222
 223                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 224
 225                 link_init_params.ctx = dc->ctx;
 226                 /* next BIOS object table connector */
 227                 link_init_params.connector_index = i;
 228                 link_init_params.link_index = dc->link_count;
 229                 link_init_params.dc = dc;
 230                 link = dc->link_srv->create_link(&link_init_params);
 231
 232                 if (link) {
 233                         dc->links[dc->link_count] = link;
 234                         link->dc = dc;
 235                         ++dc->link_count;
 236                 }
 237         }
 238
 239         DC_LOG_DC("BIOS object table - end");
 240
 241         /* Create a link for each usb4 dpia port */
 242         for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
 243                 struct link_init_data link_init_params = {0};
 244                 struct dc_link *link;
 245
 246                 link_init_params.ctx = dc->ctx;
 247                 link_init_params.connector_index = i;
 248                 link_init_params.link_index = dc->link_count;
 249                 link_init_params.dc = dc;
 250                 link_init_params.is_dpia_link = true;
 251
 252                 link = dc->link_srv->create_link(&link_init_params);
 253                 if (link) {
 254                         dc->links[dc->link_count] = link;
 255                         link->dc = dc;
 256                         ++dc->link_count;
 257                 }
 258         }
 259
 260         for (i = 0; i < num_virtual_links; i++) {
 261                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 262                 struct encoder_init_data enc_init = {0};
 263
 264                 if (link == NULL) {
 265                         BREAK_TO_DEBUGGER();
 266                         goto failed_alloc;
 267                 }
 268
 269                 link->link_index = dc->link_count;
 270                 dc->links[dc->link_count] = link;
 271                 dc->link_count++;
 272
 273                 link->ctx = dc->ctx;
 274                 link->dc = dc;
 275                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 276                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 277                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 278                 link->link_id.enum_id = ENUM_ID_1;
 279                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 280
 281                 if (!link->link_enc) {
 282                         BREAK_TO_DEBUGGER();
 283                         goto failed_alloc;
 284                 }
 285
 286                 link->link_status.dpcd_caps = &link->dpcd_caps;
 287
 288                 enc_init.ctx = dc->ctx;
 289                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 290                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 291                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 292                 enc_init.connector = link->link_id;
 293                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 294                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 295                 enc_init.encoder.enum_id = ENUM_ID_1;
 296                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 297         }
 298
 299         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 300
 301         return true;
 302
 303 failed_alloc:
 304         return false;
 305 }
 306
 307 /* Create additional DIG link encoder objects if fewer than the platform
 308  * supports were created during link construction. This can happen if the
 309  * number of physical connectors is less than the number of DIGs.
 310  */
 311 static bool create_link_encoders(struct dc *dc)
 312 {
 313         bool res = true;
 314         unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 315         unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 316         int i;
 317
 318         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 319          * link encoders and physical display endpoints and does not require
 320          * additional link encoder objects.
 321          */
 322         if (num_usb4_dpia == 0)
 323                 return res;
 324
 325         /* Create as many link encoder objects as the platform supports. DPIA
 326          * endpoints can be programmably mapped to any DIG.
 327          */
 328         if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
 329                 for (i = 0; i < num_dig_link_enc; i++) {
 330                         struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 331
 332                         if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
 333                                 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
 334                                                 (enum engine_id)(ENGINE_ID_DIGA + i));
 335                                 if (link_enc) {
 336                                         dc->res_pool->link_encoders[i] = link_enc;
 337                                         dc->res_pool->dig_link_enc_count++;
 338                                 } else {
 339                                         res = false;
 340                                 }
 341                         }
 342                 }
 343         }
 344
 345         return res;
 346 }
 347
 348 /* Destroy any additional DIG link encoder objects created by
 349  * create_link_encoders().
 350  * NB: Must only be called after destroy_links().
 351  */
 352 static void destroy_link_encoders(struct dc *dc)
 353 {
 354         unsigned int num_usb4_dpia;
 355         unsigned int num_dig_link_enc;
 356         int i;
 357
 358         if (!dc->res_pool)
 359                 return;
 360
 361         num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 362         num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 363
 364         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 365          * link encoders and physical display endpoints and does not require
 366          * additional link encoder objects.
 367          */
 368         if (num_usb4_dpia == 0)
 369                 return;
 370
 371         for (i = 0; i < num_dig_link_enc; i++) {
 372                 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 373
 374                 if (link_enc) {
 375                         link_enc->funcs->destroy(&link_enc);
 376                         dc->res_pool->link_encoders[i] = NULL;
 377                         dc->res_pool->dig_link_enc_count--;
 378                 }
 379         }
 380 }
 381
 382 static struct dc_perf_trace *dc_perf_trace_create(void)
 383 {
 384         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 385 }
 386
 387 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 388 {
 389         kfree(*perf_trace);
 390         *perf_trace = NULL;
 391 }
 392
 393 static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust)
 394 {
 395         if (!dc || !stream || !adjust)
 396                 return false;
 397
 398         if (!dc->current_state)
 399                 return false;
 400
 401         int i;
 402
 403         for (i = 0; i < MAX_PIPES; i++) {
 404                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 405
 406                 if (pipe->stream == stream && pipe->stream_res.tg) {
 407                         if (dc->hwss.set_long_vtotal)
 408                                 dc->hwss.set_long_vtotal(&pipe, 1, adjust->v_total_min, adjust->v_total_max);
 409
 410                         return true;
 411                 }
 412         }
 413
 414         return false;
 415 }
 416
 417 /**
 418  *  dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
 419  *  @dc:     dc reference
 420  *  @stream: Initial dc stream state
 421  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 422  *
 423  *  Looks up the pipe context of dc_stream_state and updates the
 424  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 425  *  Rate, which is a power-saving feature that targets reducing panel
 426  *  refresh rate while the screen is static
 427  *
 428  *  Return: %true if the pipe context is found and adjusted;
 429  *          %false if the pipe context is not found.
 430  */
 431 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 432                 struct dc_stream_state *stream,
 433                 struct dc_crtc_timing_adjust *adjust)
 434 {
 435         int i;
 436
 437         /*
 438          * Don't adjust DRR while there's bandwidth optimizations pending to
 439          * avoid conflicting with firmware updates.
 440          */
 441         if (dc->ctx->dce_version > DCE_VERSION_MAX)
 442                 if (dc->optimized_required || dc->wm_optimized_required)
 443                         return false;
 444
 445         dc_exit_ips_for_hw_access(dc);
 446
 447         stream->adjust.v_total_max = adjust->v_total_max;
 448         stream->adjust.v_total_mid = adjust->v_total_mid;
 449         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 450         stream->adjust.v_total_min = adjust->v_total_min;
 451         stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt;
 452
 453         if (dc->caps.max_v_total != 0 &&
 454                 (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) {
 455                 if (adjust->allow_otg_v_count_halt)
 456                         return set_long_vtotal(dc, stream, adjust);
 457                 else
 458                         return false;
 459         }
 460
 461         for (i = 0; i < MAX_PIPES; i++) {
 462                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 463
 464                 if (pipe->stream == stream && pipe->stream_res.tg) {
 465                         dc->hwss.set_drr(&pipe,
 466                                         1,
 467                                         *adjust);
 468
 469                         return true;
 470                 }
 471         }
 472         return false;
 473 }
 474
 475 /**
 476  * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
 477  * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
 478  *
 479  * @dc: [in] dc reference
 480  * @stream: [in] Initial dc stream state
 481  * @refresh_rate: [in] new refresh_rate
 482  *
 483  * Return: %true if the pipe context is found and there is an associated
 484  *         timing_generator for the DC;
 485  *         %false if the pipe context is not found or there is no
 486  *         timing_generator for the DC.
 487  */
 488 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 489                 struct dc_stream_state *stream,
 490                 uint32_t *refresh_rate)
 491 {
 492         bool status = false;
 493
 494         int i = 0;
 495
 496         dc_exit_ips_for_hw_access(dc);
 497
 498         for (i = 0; i < MAX_PIPES; i++) {
 499                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 500
 501                 if (pipe->stream == stream && pipe->stream_res.tg) {
 502                         /* Only execute if a function pointer has been defined for
 503                          * the DC version in question
 504                          */
 505                         if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
 506                                 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
 507
 508                                 status = true;
 509
 510                                 break;
 511                         }
 512                 }
 513         }
 514
 515         return status;
 516 }
 517
 518 bool dc_stream_get_crtc_position(struct dc *dc,
 519                 struct dc_stream_state **streams, int num_streams,
 520                 unsigned int *v_pos, unsigned int *nom_v_pos)
 521 {
 522         /* TODO: Support multiple streams */
 523         const struct dc_stream_state *stream = streams[0];
 524         int i;
 525         bool ret = false;
 526         struct crtc_position position;
 527
 528         dc_exit_ips_for_hw_access(dc);
 529
 530         for (i = 0; i < MAX_PIPES; i++) {
 531                 struct pipe_ctx *pipe =
 532                                 &dc->current_state->res_ctx.pipe_ctx[i];
 533
 534                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 535                         dc->hwss.get_position(&pipe, 1, &position);
 536
 537                         *v_pos = position.vertical_count;
 538                         *nom_v_pos = position.nominal_vcount;
 539                         ret = true;
 540                 }
 541         }
 542         return ret;
 543 }
 544
 545 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 546 static inline void
 547 dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
 548                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 549 {
 550         union dmub_rb_cmd cmd = {0};
 551
 552         cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
 553         cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
 554
 555         if (is_stop) {
 556                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 557                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
 558         } else {
 559                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 560                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
 561                 cmd.secure_display.roi_info.x_start = rect->x;
 562                 cmd.secure_display.roi_info.y_start = rect->y;
 563                 cmd.secure_display.roi_info.x_end = rect->x + rect->width;
 564                 cmd.secure_display.roi_info.y_end = rect->y + rect->height;
 565         }
 566
 567         dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 568 }
 569
 570 static inline void
 571 dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
 572                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 573 {
 574         if (is_stop)
 575                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 576         else
 577                 dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);
 578 }
 579
 580 bool
 581 dc_stream_forward_crc_window(struct dc_stream_state *stream,
 582                 struct rect *rect, bool is_stop)
 583 {
 584         struct dmcu *dmcu;
 585         struct dc_dmub_srv *dmub_srv;
 586         struct otg_phy_mux mux_mapping;
 587         struct pipe_ctx *pipe;
 588         int i;
 589         struct dc *dc = stream->ctx->dc;
 590
 591         for (i = 0; i < MAX_PIPES; i++) {
 592                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 593                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 594                         break;
 595         }
 596
 597         /* Stream not found */
 598         if (i == MAX_PIPES)
 599                 return false;
 600
 601         mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
 602         mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
 603
 604         dmcu = dc->res_pool->dmcu;
 605         dmub_srv = dc->ctx->dmub_srv;
 606
 607         /* forward to dmub */
 608         if (dmub_srv)
 609                 dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);
 610         /* forward to dmcu */
 611         else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 612                 dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);
 613         else
 614                 return false;
 615
 616         return true;
 617 }
 618 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 619
 620 /**
 621  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 622  * @dc: DC Object
 623  * @stream: The stream to configure CRC on.
 624  * @enable: Enable CRC if true, disable otherwise.
 625  * @crc_window: CRC window (x/y start/end) information
 626  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 627  *              once.
 628  *
 629  * By default, only CRC0 is configured, and the entire frame is used to
 630  * calculate the CRC.
 631  *
 632  * Return: %false if the stream is not found or CRC capture is not supported;
 633  *         %true if the stream has been configured.
 634  */
 635 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 636                              struct crc_params *crc_window, bool enable, bool continuous)
 637 {
 638         struct pipe_ctx *pipe;
 639         struct crc_params param;
 640         struct timing_generator *tg;
 641
 642         pipe = resource_get_otg_master_for_stream(
 643                         &dc->current_state->res_ctx, stream);
 644
 645         /* Stream not found */
 646         if (pipe == NULL)
 647                 return false;
 648
 649         dc_exit_ips_for_hw_access(dc);
 650
 651         /* By default, capture the full frame */
 652         param.windowa_x_start = 0;
 653         param.windowa_y_start = 0;
 654         param.windowa_x_end = pipe->stream->timing.h_addressable;
 655         param.windowa_y_end = pipe->stream->timing.v_addressable;
 656         param.windowb_x_start = 0;
 657         param.windowb_y_start = 0;
 658         param.windowb_x_end = pipe->stream->timing.h_addressable;
 659         param.windowb_y_end = pipe->stream->timing.v_addressable;
 660
 661         if (crc_window) {
 662                 param.windowa_x_start = crc_window->windowa_x_start;
 663                 param.windowa_y_start = crc_window->windowa_y_start;
 664                 param.windowa_x_end = crc_window->windowa_x_end;
 665                 param.windowa_y_end = crc_window->windowa_y_end;
 666                 param.windowb_x_start = crc_window->windowb_x_start;
 667                 param.windowb_y_start = crc_window->windowb_y_start;
 668                 param.windowb_x_end = crc_window->windowb_x_end;
 669                 param.windowb_y_end = crc_window->windowb_y_end;
 670         }
 671
 672         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 673         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 674
 675         /* Default to the union of both windows */
 676         param.selection = UNION_WINDOW_A_B;
 677         param.continuous_mode = continuous;
 678         param.enable = enable;
 679
 680         tg = pipe->stream_res.tg;
 681
 682         /* Only call if supported */
 683         if (tg->funcs->configure_crc)
 684                 return tg->funcs->configure_crc(tg, &param);
 685         DC_LOG_WARNING("CRC capture not supported.");
 686         return false;
 687 }
 688
 689 /**
 690  * dc_stream_get_crc() - Get CRC values for the given stream.
 691  *
 692  * @dc: DC object.
 693  * @stream: The DC stream state of the stream to get CRCs from.
 694  * @r_cr: CRC value for the red component.
 695  * @g_y:  CRC value for the green component.
 696  * @b_cb: CRC value for the blue component.
 697  *
 698  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 699  *
 700  * Return:
 701  * %false if stream is not found, or if CRCs are not enabled.
 702  */
 703 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 704                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 705 {
 706         int i;
 707         struct pipe_ctx *pipe;
 708         struct timing_generator *tg;
 709
 710         dc_exit_ips_for_hw_access(dc);
 711
 712         for (i = 0; i < MAX_PIPES; i++) {
 713                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 714                 if (pipe->stream == stream)
 715                         break;
 716         }
 717         /* Stream not found */
 718         if (i == MAX_PIPES)
 719                 return false;
 720
 721         tg = pipe->stream_res.tg;
 722
 723         if (tg->funcs->get_crc)
 724                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 725         DC_LOG_WARNING("CRC capture not supported.");
 726         return false;
 727 }
 728
 729 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 730                 enum dc_dynamic_expansion option)
 731 {
 732         /* OPP FMT dyn expansion updates*/
 733         int i;
 734         struct pipe_ctx *pipe_ctx;
 735
 736         dc_exit_ips_for_hw_access(dc);
 737
 738         for (i = 0; i < MAX_PIPES; i++) {
 739                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 740                                 == stream) {
 741                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 742                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 743                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 744                                         pipe_ctx->stream_res.opp,
 745                                         COLOR_SPACE_YCBCR601,
 746                                         stream->timing.display_color_depth,
 747                                         stream->signal);
 748                 }
 749         }
 750 }
 751
 752 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 753                 enum dc_dither_option option)
 754 {
 755         struct bit_depth_reduction_params params;
 756         struct dc_link *link = stream->link;
 757         struct pipe_ctx *pipes = NULL;
 758         int i;
 759
 760         for (i = 0; i < MAX_PIPES; i++) {
 761                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 762                                 stream) {
 763                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 764                         break;
 765                 }
 766         }
 767
 768         if (!pipes)
 769                 return;
 770         if (option > DITHER_OPTION_MAX)
 771                 return;
 772
 773         dc_exit_ips_for_hw_access(stream->ctx->dc);
 774
 775         stream->dither_option = option;
 776
 777         memset(&params, 0, sizeof(params));
 778         resource_build_bit_depth_reduction_params(stream, &params);
 779         stream->bit_depth_params = params;
 780
 781         if (pipes->plane_res.xfm &&
 782             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 783                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 784                         pipes->plane_res.xfm,
 785                         pipes->plane_res.scl_data.lb_params.depth,
 786                         &stream->bit_depth_params);
 787         }
 788
 789         pipes->stream_res.opp->funcs->
 790                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 791 }
 792
 793 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 794 {
 795         int i;
 796         bool ret = false;
 797         struct pipe_ctx *pipes;
 798
 799         dc_exit_ips_for_hw_access(dc);
 800
 801         for (i = 0; i < MAX_PIPES; i++) {
 802                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 803                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 804                         dc->hwss.program_gamut_remap(pipes);
 805                         ret = true;
 806                 }
 807         }
 808
 809         return ret;
 810 }
 811
 812 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 813 {
 814         int i;
 815         bool ret = false;
 816         struct pipe_ctx *pipes;
 817
 818         dc_exit_ips_for_hw_access(dc);
 819
 820         for (i = 0; i < MAX_PIPES; i++) {
 821                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 822                                 == stream) {
 823
 824                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 825                         dc->hwss.program_output_csc(dc,
 826                                         pipes,
 827                                         stream->output_color_space,
 828                                         stream->csc_color_matrix.matrix,
 829                                         pipes->stream_res.opp->inst);
 830                         ret = true;
 831                 }
 832         }
 833
 834         return ret;
 835 }
 836
 837 void dc_stream_set_static_screen_params(struct dc *dc,
 838                 struct dc_stream_state **streams,
 839                 int num_streams,
 840                 const struct dc_static_screen_params *params)
 841 {
 842         int i, j;
 843         struct pipe_ctx *pipes_affected[MAX_PIPES];
 844         int num_pipes_affected = 0;
 845
 846         dc_exit_ips_for_hw_access(dc);
 847
 848         for (i = 0; i < num_streams; i++) {
 849                 struct dc_stream_state *stream = streams[i];
 850
 851                 for (j = 0; j < MAX_PIPES; j++) {
 852                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 853                                         == stream) {
 854                                 pipes_affected[num_pipes_affected++] =
 855                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 856                         }
 857                 }
 858         }
 859
 860         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 861 }
 862
 863 static void dc_destruct(struct dc *dc)
 864 {
 865         // reset link encoder assignment table on destruct
 866         if (dc->res_pool && dc->res_pool->funcs->link_encs_assign)
 867                 link_enc_cfg_init(dc, dc->current_state);
 868
 869         if (dc->current_state) {
 870                 dc_state_release(dc->current_state);
 871                 dc->current_state = NULL;
 872         }
 873
 874         destroy_links(dc);
 875
 876         destroy_link_encoders(dc);
 877
 878         if (dc->clk_mgr) {
 879                 dc_destroy_clk_mgr(dc->clk_mgr);
 880                 dc->clk_mgr = NULL;
 881         }
 882
 883         dc_destroy_resource_pool(dc);
 884
 885         if (dc->link_srv)
 886                 link_destroy_link_service(&dc->link_srv);
 887
 888         if (dc->ctx->gpio_service)
 889                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 890
 891         if (dc->ctx->created_bios)
 892                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 893
 894         kfree(dc->ctx->logger);
 895         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 896
 897         kfree(dc->ctx);
 898         dc->ctx = NULL;
 899
 900         kfree(dc->bw_vbios);
 901         dc->bw_vbios = NULL;
 902
 903         kfree(dc->bw_dceip);
 904         dc->bw_dceip = NULL;
 905
 906         kfree(dc->dcn_soc);
 907         dc->dcn_soc = NULL;
 908
 909         kfree(dc->dcn_ip);
 910         dc->dcn_ip = NULL;
 911
 912         kfree(dc->vm_helper);
 913         dc->vm_helper = NULL;
 914
 915 }
 916
 917 static bool dc_construct_ctx(struct dc *dc,
 918                 const struct dc_init_data *init_params)
 919 {
 920         struct dc_context *dc_ctx;
 921
 922         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 923         if (!dc_ctx)
 924                 return false;
 925
 926         dc_ctx->cgs_device = init_params->cgs_device;
 927         dc_ctx->driver_context = init_params->driver;
 928         dc_ctx->dc = dc;
 929         dc_ctx->asic_id = init_params->asic_id;
 930         dc_ctx->dc_sink_id_count = 0;
 931         dc_ctx->dc_stream_id_count = 0;
 932         dc_ctx->dce_environment = init_params->dce_environment;
 933         dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
 934         dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
 935         dc_ctx->clk_reg_offsets = init_params->clk_reg_offsets;
 936
 937         /* Create logger */
 938         dc_ctx->logger = kmalloc(sizeof(*dc_ctx->logger), GFP_KERNEL);
 939
 940         if (!dc_ctx->logger) {
 941                 kfree(dc_ctx);
 942                 return false;
 943         }
 944
 945         dc_ctx->logger->dev = adev_to_drm(init_params->driver);
 946         dc->dml.logger = dc_ctx->logger;
 947
 948         dc_ctx->dce_version = resource_parse_asic_id(init_params->asic_id);
 949
 950         dc_ctx->perf_trace = dc_perf_trace_create();
 951         if (!dc_ctx->perf_trace) {
 952                 kfree(dc_ctx);
 953                 ASSERT_CRITICAL(false);
 954                 return false;
 955         }
 956
 957         dc->ctx = dc_ctx;
 958
 959         dc->link_srv = link_create_link_service();
 960         if (!dc->link_srv)
 961                 return false;
 962
 963         return true;
 964 }
 965
 966 static bool dc_construct(struct dc *dc,
 967                 const struct dc_init_data *init_params)
 968 {
 969         struct dc_context *dc_ctx;
 970         struct bw_calcs_dceip *dc_dceip;
 971         struct bw_calcs_vbios *dc_vbios;
 972         struct dcn_soc_bounding_box *dcn_soc;
 973         struct dcn_ip_params *dcn_ip;
 974
 975         dc->config = init_params->flags;
 976
 977         // Allocate memory for the vm_helper
 978         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 979         if (!dc->vm_helper) {
 980                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 981                 goto fail;
 982         }
 983
 984         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 985
 986         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 987         if (!dc_dceip) {
 988                 dm_error("%s: failed to create dceip\n", __func__);
 989                 goto fail;
 990         }
 991
 992         dc->bw_dceip = dc_dceip;
 993
 994         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 995         if (!dc_vbios) {
 996                 dm_error("%s: failed to create vbios\n", __func__);
 997                 goto fail;
 998         }
 999
1000         dc->bw_vbios = dc_vbios;
1001         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
1002         if (!dcn_soc) {
1003                 dm_error("%s: failed to create dcn_soc\n", __func__);
1004                 goto fail;
1005         }
1006
1007         dc->dcn_soc = dcn_soc;
1008
1009         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
1010         if (!dcn_ip) {
1011                 dm_error("%s: failed to create dcn_ip\n", __func__);
1012                 goto fail;
1013         }
1014
1015         dc->dcn_ip = dcn_ip;
1016
1017         if (init_params->bb_from_dmub)
1018                 dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub;
1019         else
1020                 dc->dml2_options.bb_from_dmub = NULL;
1021
1022         if (!dc_construct_ctx(dc, init_params)) {
1023                 dm_error("%s: failed to create ctx\n", __func__);
1024                 goto fail;
1025         }
1026
1027         dc_ctx = dc->ctx;
1028
1029         /* Resource should construct all asic specific resources.
1030          * This should be the only place where we need to parse the asic id
1031          */
1032         if (init_params->vbios_override)
1033                 dc_ctx->dc_bios = init_params->vbios_override;
1034         else {
1035                 /* Create BIOS parser */
1036                 struct bp_init_data bp_init_data;
1037
1038                 bp_init_data.ctx = dc_ctx;
1039                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
1040
1041                 dc_ctx->dc_bios = dal_bios_parser_create(
1042                                 &bp_init_data, dc_ctx->dce_version);
1043
1044                 if (!dc_ctx->dc_bios) {
1045                         ASSERT_CRITICAL(false);
1046                         goto fail;
1047                 }
1048
1049                 dc_ctx->created_bios = true;
1050         }
1051
1052         dc->vendor_signature = init_params->vendor_signature;
1053
1054         /* Create GPIO service */
1055         dc_ctx->gpio_service = dal_gpio_service_create(
1056                         dc_ctx->dce_version,
1057                         dc_ctx->dce_environment,
1058                         dc_ctx);
1059
1060         if (!dc_ctx->gpio_service) {
1061                 ASSERT_CRITICAL(false);
1062                 goto fail;
1063         }
1064
1065         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
1066         if (!dc->res_pool)
1067                 goto fail;
1068
1069         /* set i2c speed if not done by the respective dcnxxx__resource.c */
1070         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
1071                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
1072         if (dc->caps.max_optimizable_video_width == 0)
1073                 dc->caps.max_optimizable_video_width = 5120;
1074         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
1075         if (!dc->clk_mgr)
1076                 goto fail;
1077 #ifdef CONFIG_DRM_AMD_DC_FP
1078         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
1079
1080         if (dc->res_pool->funcs->update_bw_bounding_box) {
1081                 DC_FP_START();
1082                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1083                 DC_FP_END();
1084         }
1085 #endif
1086
1087         if (!create_links(dc, init_params->num_virtual_links))
1088                 goto fail;
1089
1090         /* Create additional DIG link encoder objects if fewer than the platform
1091          * supports were created during link construction.
1092          */
1093         if (!create_link_encoders(dc))
1094                 goto fail;
1095
1096         /* Creation of current_state must occur after dc->dml
1097          * is initialized in dc_create_resource_pool because
1098          * on creation it copies the contents of dc->dml
1099          */
1100         dc->current_state = dc_state_create(dc, NULL);
1101
1102         if (!dc->current_state) {
1103                 dm_error("%s: failed to create validate ctx\n", __func__);
1104                 goto fail;
1105         }
1106
1107         return true;
1108
1109 fail:
1110         return false;
1111 }
1112
1113 static void disable_all_writeback_pipes_for_stream(
1114                 const struct dc *dc,
1115                 struct dc_stream_state *stream,
1116                 struct dc_state *context)
1117 {
1118         int i;
1119
1120         for (i = 0; i < stream->num_wb_info; i++)
1121                 stream->writeback_info[i].wb_enabled = false;
1122 }
1123
1124 static void apply_ctx_interdependent_lock(struct dc *dc,
1125                                           struct dc_state *context,
1126                                           struct dc_stream_state *stream,
1127                                           bool lock)
1128 {
1129         int i;
1130
1131         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
1132         if (dc->hwss.interdependent_update_lock)
1133                 dc->hwss.interdependent_update_lock(dc, context, lock);
1134         else {
1135                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1136                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1137                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1138
1139                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
1140                         if (stream == pipe_ctx->stream) {
1141                                 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&
1142                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
1143                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
1144                         }
1145                 }
1146         }
1147 }
1148
1149 static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1150 {
1151         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1152                 memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
1153
1154                 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
1155                         get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1156                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1157                         get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1158                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
1159                         get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1160                 else {
1161                         if (dc->ctx->dce_version < DCN_VERSION_2_0)
1162                                 color_space_to_black_color(
1163                                         dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
1164                 }
1165                 if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
1166                         if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
1167                                 get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1168                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
1169                                 get_subvp_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1170                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
1171                                 get_mclk_switch_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1172                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2)
1173                                 get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1174                 }
1175         }
1176 }
1177
1178 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
1179 {
1180         int i, j;
1181         struct dc_state *dangling_context = dc_state_create_current_copy(dc);
1182         struct dc_state *current_ctx;
1183         struct pipe_ctx *pipe;
1184         struct timing_generator *tg;
1185
1186         if (dangling_context == NULL)
1187                 return;
1188
1189         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1190                 struct dc_stream_state *old_stream =
1191                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
1192                 bool should_disable = true;
1193                 bool pipe_split_change = false;
1194
1195                 if ((context->res_ctx.pipe_ctx[i].top_pipe) &&
1196                         (dc->current_state->res_ctx.pipe_ctx[i].top_pipe))
1197                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=
1198                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;
1199                 else
1200                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=
1201                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
1202
1203                 for (j = 0; j < context->stream_count; j++) {
1204                         if (old_stream == context->streams[j]) {
1205                                 should_disable = false;
1206                                 break;
1207                         }
1208                 }
1209                 if (!should_disable && pipe_split_change &&
1210                                 dc->current_state->stream_count != context->stream_count)
1211                         should_disable = true;
1212
1213                 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
1214                                 !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
1215                         struct pipe_ctx *old_pipe, *new_pipe;
1216
1217                         old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1218                         new_pipe = &context->res_ctx.pipe_ctx[i];
1219
1220                         if (old_pipe->plane_state && !new_pipe->plane_state)
1221                                 should_disable = true;
1222                 }
1223
1224                 if (should_disable && old_stream) {
1225                         bool is_phantom = dc_state_get_stream_subvp_type(dc->current_state, old_stream) == SUBVP_PHANTOM;
1226                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1227                         tg = pipe->stream_res.tg;
1228                         /* When disabling plane for a phantom pipe, we must turn on the
1229                          * phantom OTG so the disable programming gets the double buffer
1230                          * update. Otherwise the pipe will be left in a partially disabled
1231                          * state that can result in underflow or hang when enabling it
1232                          * again for different use.
1233                          */
1234                         if (is_phantom) {
1235                                 if (tg->funcs->enable_crtc) {
1236                                         int main_pipe_width = 0, main_pipe_height = 0;
1237                                         struct dc_stream_state *old_paired_stream = dc_state_get_paired_subvp_stream(dc->current_state, old_stream);
1238
1239                                         if (old_paired_stream) {
1240                                                 main_pipe_width = old_paired_stream->dst.width;
1241                                                 main_pipe_height = old_paired_stream->dst.height;
1242                                         }
1243
1244                                         if (dc->hwss.blank_phantom)
1245                                                 dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);
1246                                         tg->funcs->enable_crtc(tg);
1247                                 }
1248                         }
1249
1250                         if (is_phantom)
1251                                 dc_state_rem_all_phantom_planes_for_stream(dc, old_stream, dangling_context, true);
1252                         else
1253                                 dc_state_rem_all_planes_for_stream(dc, old_stream, dangling_context);
1254                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
1255
1256                         if (pipe->stream && pipe->plane_state) {
1257                                 set_p_state_switch_method(dc, context, pipe);
1258                                 dc_update_visual_confirm_color(dc, context, pipe);
1259                         }
1260
1261                         if (dc->hwss.apply_ctx_for_surface) {
1262                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
1263                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
1264                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
1265                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1266                         }
1267
1268                         if (dc->res_pool->funcs->prepare_mcache_programming)
1269                                 dc->res_pool->funcs->prepare_mcache_programming(dc, dangling_context);
1270                         if (dc->hwss.program_front_end_for_ctx) {
1271                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
1272                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
1273                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
1274                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1275                         }
1276                         /* We need to put the phantom OTG back into it's default (disabled) state or we
1277                          * can get corruption when transition from one SubVP config to a different one.
1278                          * The OTG is set to disable on falling edge of VUPDATE so the plane disable
1279                          * will still get it's double buffer update.
1280                          */
1281                         if (is_phantom) {
1282                                 if (tg->funcs->disable_phantom_crtc)
1283                                         tg->funcs->disable_phantom_crtc(tg);
1284                         }
1285                 }
1286         }
1287
1288         current_ctx = dc->current_state;
1289         dc->current_state = dangling_context;
1290         dc_state_release(current_ctx);
1291 }
1292
1293 static void disable_vbios_mode_if_required(
1294                 struct dc *dc,
1295                 struct dc_state *context)
1296 {
1297         unsigned int i, j;
1298
1299         /* check if timing_changed, disable stream*/
1300         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1301                 struct dc_stream_state *stream = NULL;
1302                 struct dc_link *link = NULL;
1303                 struct pipe_ctx *pipe = NULL;
1304
1305                 pipe = &context->res_ctx.pipe_ctx[i];
1306                 stream = pipe->stream;
1307                 if (stream == NULL)
1308                         continue;
1309
1310                 if (stream->apply_seamless_boot_optimization)
1311                         continue;
1312
1313                 // only looking for first odm pipe
1314                 if (pipe->prev_odm_pipe)
1315                         continue;
1316
1317                 if (stream->link->local_sink &&
1318                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1319                         link = stream->link;
1320                 }
1321
1322                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1323                         unsigned int enc_inst, tg_inst = 0;
1324                         unsigned int pix_clk_100hz = 0;
1325
1326                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1327                         if (enc_inst != ENGINE_ID_UNKNOWN) {
1328                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1329                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1330                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1331                                                         dc->res_pool->stream_enc[j]);
1332                                                 break;
1333                                         }
1334                                 }
1335
1336                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1337                                         dc->res_pool->dp_clock_source,
1338                                         tg_inst, &pix_clk_100hz);
1339
1340                                 if (link->link_status.link_active) {
1341                                         uint32_t requested_pix_clk_100hz =
1342                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1343
1344                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1345                                                 dc->link_srv->set_dpms_off(pipe);
1346                                                 pipe->stream->dpms_off = false;
1347                                         }
1348                                 }
1349                         }
1350                 }
1351         }
1352 }
1353
1354 /**
1355  * wait_for_blank_complete - wait for all active OPPs to finish pending blank
1356  * pattern updates
1357  *
1358  * @dc: [in] dc reference
1359  * @context: [in] hardware context in use
1360  */
1361 static void wait_for_blank_complete(struct dc *dc,
1362                 struct dc_state *context)
1363 {
1364         struct pipe_ctx *opp_head;
1365         struct dce_hwseq *hws = dc->hwseq;
1366         int i;
1367
1368         if (!hws->funcs.wait_for_blank_complete)
1369                 return;
1370
1371         for (i = 0; i < MAX_PIPES; i++) {
1372                 opp_head = &context->res_ctx.pipe_ctx[i];
1373
1374                 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
1375                                 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
1376                         continue;
1377
1378                 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
1379         }
1380 }
1381
1382 static void wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
1383 {
1384         struct pipe_ctx *otg_master;
1385         struct timing_generator *tg;
1386         int i;
1387
1388         for (i = 0; i < MAX_PIPES; i++) {
1389                 otg_master = &context->res_ctx.pipe_ctx[i];
1390                 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
1391                                 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
1392                         continue;
1393                 tg = otg_master->stream_res.tg;
1394                 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
1395                         tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
1396         }
1397
1398         /* ODM update may require to reprogram blank pattern for each OPP */
1399         wait_for_blank_complete(dc, context);
1400 }
1401
1402 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1403 {
1404         int i;
1405         PERF_TRACE();
1406         for (i = 0; i < MAX_PIPES; i++) {
1407                 int count = 0;
1408                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1409
1410                 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1411                         continue;
1412
1413                 /* Timeout 100 ms */
1414                 while (count < 100000) {
1415                         /* Must set to false to start with, due to OR in update function */
1416                         pipe->plane_state->status.is_flip_pending = false;
1417                         dc->hwss.update_pending_status(pipe);
1418                         if (!pipe->plane_state->status.is_flip_pending)
1419                                 break;
1420                         udelay(1);
1421                         count++;
1422                 }
1423                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1424         }
1425         PERF_TRACE();
1426 }
1427
1428 /* Public functions */
1429
1430 struct dc *dc_create(const struct dc_init_data *init_params)
1431 {
1432         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1433         unsigned int full_pipe_count;
1434
1435         if (!dc)
1436                 return NULL;
1437
1438         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1439                 dc->caps.linear_pitch_alignment = 64;
1440                 if (!dc_construct_ctx(dc, init_params))
1441                         goto destruct_dc;
1442         } else {
1443                 if (!dc_construct(dc, init_params))
1444                         goto destruct_dc;
1445
1446                 full_pipe_count = dc->res_pool->pipe_count;
1447                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1448                         full_pipe_count--;
1449                 dc->caps.max_streams = min(
1450                                 full_pipe_count,
1451                                 dc->res_pool->stream_enc_count);
1452
1453                 dc->caps.max_links = dc->link_count;
1454                 dc->caps.max_audios = dc->res_pool->audio_count;
1455                 dc->caps.linear_pitch_alignment = 64;
1456
1457                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1458
1459                 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
1460
1461                 if (dc->res_pool->dmcu != NULL)
1462                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1463         }
1464
1465         dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
1466         dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
1467         dc->clk_reg_offsets = init_params->clk_reg_offsets;
1468
1469         /* Populate versioning information */
1470         dc->versions.dc_ver = DC_VER;
1471
1472         dc->build_id = DC_BUILD_ID;
1473
1474         DC_LOG_DC("Display Core initialized\n");
1475
1476         return dc;
1477
1478 destruct_dc:
1479         dc_destruct(dc);
1480         kfree(dc);
1481         return NULL;
1482 }
1483
1484 static void detect_edp_presence(struct dc *dc)
1485 {
1486         struct dc_link *edp_links[MAX_NUM_EDP];
1487         struct dc_link *edp_link = NULL;
1488         enum dc_connection_type type;
1489         int i;
1490         int edp_num;
1491
1492         dc_get_edp_links(dc, edp_links, &edp_num);
1493         if (!edp_num)
1494                 return;
1495
1496         for (i = 0; i < edp_num; i++) {
1497                 edp_link = edp_links[i];
1498                 if (dc->config.edp_not_connected) {
1499                         edp_link->edp_sink_present = false;
1500                 } else {
1501                         dc_link_detect_connection_type(edp_link, &type);
1502                         edp_link->edp_sink_present = (type != dc_connection_none);
1503                 }
1504         }
1505 }
1506
1507 void dc_hardware_init(struct dc *dc)
1508 {
1509
1510         detect_edp_presence(dc);
1511         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1512                 dc->hwss.init_hw(dc);
1513 }
1514
1515 void dc_init_callbacks(struct dc *dc,
1516                 const struct dc_callback_init *init_params)
1517 {
1518         dc->ctx->cp_psp = init_params->cp_psp;
1519 }
1520
1521 void dc_deinit_callbacks(struct dc *dc)
1522 {
1523         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1524 }
1525
1526 void dc_destroy(struct dc **dc)
1527 {
1528         dc_destruct(*dc);
1529         kfree(*dc);
1530         *dc = NULL;
1531 }
1532
1533 static void enable_timing_multisync(
1534                 struct dc *dc,
1535                 struct dc_state *ctx)
1536 {
1537         int i, multisync_count = 0;
1538         int pipe_count = dc->res_pool->pipe_count;
1539         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1540
1541         for (i = 0; i < pipe_count; i++) {
1542                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1543                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1544                         continue;
1545                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1546                         continue;
1547                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1548                 multisync_count++;
1549         }
1550
1551         if (multisync_count > 0) {
1552                 dc->hwss.enable_per_frame_crtc_position_reset(
1553                         dc, multisync_count, multisync_pipes);
1554         }
1555 }
1556
1557 static void program_timing_sync(
1558                 struct dc *dc,
1559                 struct dc_state *ctx)
1560 {
1561         int i, j, k;
1562         int group_index = 0;
1563         int num_group = 0;
1564         int pipe_count = dc->res_pool->pipe_count;
1565         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1566
1567         for (i = 0; i < pipe_count; i++) {
1568                 if (!ctx->res_ctx.pipe_ctx[i].stream
1569                                 || ctx->res_ctx.pipe_ctx[i].top_pipe
1570                                 || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
1571                         continue;
1572
1573                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1574         }
1575
1576         for (i = 0; i < pipe_count; i++) {
1577                 int group_size = 1;
1578                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1579                 struct pipe_ctx *pipe_set[MAX_PIPES];
1580
1581                 if (!unsynced_pipes[i])
1582                         continue;
1583
1584                 pipe_set[0] = unsynced_pipes[i];
1585                 unsynced_pipes[i] = NULL;
1586
1587                 /* Add tg to the set, search rest of the tg's for ones with
1588                  * same timing, add all tgs with same timing to the group
1589                  */
1590                 for (j = i + 1; j < pipe_count; j++) {
1591                         if (!unsynced_pipes[j])
1592                                 continue;
1593                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1594                                 dc->hwss.enable_vblanks_synchronization &&
1595                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1596                                 resource_are_vblanks_synchronizable(
1597                                         unsynced_pipes[j]->stream,
1598                                         pipe_set[0]->stream)) {
1599                                 sync_type = VBLANK_SYNCHRONIZABLE;
1600                                 pipe_set[group_size] = unsynced_pipes[j];
1601                                 unsynced_pipes[j] = NULL;
1602                                 group_size++;
1603                         } else
1604                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1605                                 resource_are_streams_timing_synchronizable(
1606                                         unsynced_pipes[j]->stream,
1607                                         pipe_set[0]->stream)) {
1608                                 sync_type = TIMING_SYNCHRONIZABLE;
1609                                 pipe_set[group_size] = unsynced_pipes[j];
1610                                 unsynced_pipes[j] = NULL;
1611                                 group_size++;
1612                         }
1613                 }
1614
1615                 /* set first unblanked pipe as master */
1616                 for (j = 0; j < group_size; j++) {
1617                         bool is_blanked;
1618
1619                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1620                                 is_blanked =
1621                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1622                         else
1623                                 is_blanked =
1624                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1625                         if (!is_blanked) {
1626                                 if (j == 0)
1627                                         break;
1628
1629                                 swap(pipe_set[0], pipe_set[j]);
1630                                 break;
1631                         }
1632                 }
1633
1634                 for (k = 0; k < group_size; k++) {
1635                         struct dc_stream_status *status = dc_state_get_stream_status(ctx, pipe_set[k]->stream);
1636
1637                         if (!status)
1638                                 continue;
1639
1640                         status->timing_sync_info.group_id = num_group;
1641                         status->timing_sync_info.group_size = group_size;
1642                         if (k == 0)
1643                                 status->timing_sync_info.master = true;
1644                         else
1645                                 status->timing_sync_info.master = false;
1646
1647                 }
1648
1649                 /* remove any other unblanked pipes as they have already been synced */
1650                 if (dc->config.use_pipe_ctx_sync_logic) {
1651                         /* check pipe's syncd to decide which pipe to be removed */
1652                         for (j = 1; j < group_size; j++) {
1653                                 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1654                                         group_size--;
1655                                         pipe_set[j] = pipe_set[group_size];
1656                                         j--;
1657                                 } else
1658                                         /* link slave pipe's syncd with master pipe */
1659                                         pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1660                         }
1661                 } else {
1662                         /* remove any other pipes by checking valid plane */
1663                         for (j = j + 1; j < group_size; j++) {
1664                                 bool is_blanked;
1665
1666                                 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1667                                         is_blanked =
1668                                                 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1669                                 else
1670                                         is_blanked =
1671                                                 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1672                                 if (!is_blanked) {
1673                                         group_size--;
1674                                         pipe_set[j] = pipe_set[group_size];
1675                                         j--;
1676                                 }
1677                         }
1678                 }
1679
1680                 if (group_size > 1) {
1681                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1682                                 dc->hwss.enable_timing_synchronization(
1683                                         dc, ctx, group_index, group_size, pipe_set);
1684                         } else
1685                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1686                                 dc->hwss.enable_vblanks_synchronization(
1687                                         dc, group_index, group_size, pipe_set);
1688                                 }
1689                         group_index++;
1690                 }
1691                 num_group++;
1692         }
1693 }
1694
1695 static bool streams_changed(struct dc *dc,
1696                             struct dc_stream_state *streams[],
1697                             uint8_t stream_count)
1698 {
1699         uint8_t i;
1700
1701         if (stream_count != dc->current_state->stream_count)
1702                 return true;
1703
1704         for (i = 0; i < dc->current_state->stream_count; i++) {
1705                 if (dc->current_state->streams[i] != streams[i])
1706                         return true;
1707                 if (!streams[i]->link->link_state_valid)
1708                         return true;
1709         }
1710
1711         return false;
1712 }
1713
1714 bool dc_validate_boot_timing(const struct dc *dc,
1715                                 const struct dc_sink *sink,
1716                                 struct dc_crtc_timing *crtc_timing)
1717 {
1718         struct timing_generator *tg;
1719         struct stream_encoder *se = NULL;
1720
1721         struct dc_crtc_timing hw_crtc_timing = {0};
1722
1723         struct dc_link *link = sink->link;
1724         unsigned int i, enc_inst, tg_inst = 0;
1725
1726         /* Support seamless boot on EDP displays only */
1727         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1728                 return false;
1729         }
1730
1731         if (dc->debug.force_odm_combine)
1732                 return false;
1733
1734         /* Check for enabled DIG to identify enabled display */
1735         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1736                 return false;
1737
1738         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1739
1740         if (enc_inst == ENGINE_ID_UNKNOWN)
1741                 return false;
1742
1743         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1744                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1745
1746                         se = dc->res_pool->stream_enc[i];
1747
1748                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1749                                 dc->res_pool->stream_enc[i]);
1750                         break;
1751                 }
1752         }
1753
1754         // tg_inst not found
1755         if (i == dc->res_pool->stream_enc_count)
1756                 return false;
1757
1758         if (tg_inst >= dc->res_pool->timing_generator_count)
1759                 return false;
1760
1761         if (tg_inst != link->link_enc->preferred_engine)
1762                 return false;
1763
1764         tg = dc->res_pool->timing_generators[tg_inst];
1765
1766         if (!tg->funcs->get_hw_timing)
1767                 return false;
1768
1769         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1770                 return false;
1771
1772         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1773                 return false;
1774
1775         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1776                 return false;
1777
1778         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1779                 return false;
1780
1781         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1782                 return false;
1783
1784         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1785                 return false;
1786
1787         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1788                 return false;
1789
1790         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1791                 return false;
1792
1793         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1794                 return false;
1795
1796         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1797                 return false;
1798
1799         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1800                 return false;
1801
1802         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1803                 return false;
1804
1805         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1806                 return false;
1807
1808         /* block DSC for now, as VBIOS does not currently support DSC timings */
1809         if (crtc_timing->flags.DSC)
1810                 return false;
1811
1812         if (dc_is_dp_signal(link->connector_signal)) {
1813                 unsigned int pix_clk_100hz = 0;
1814                 uint32_t numOdmPipes = 1;
1815                 uint32_t id_src[4] = {0};
1816
1817                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1818                         dc->res_pool->dp_clock_source,
1819                         tg_inst, &pix_clk_100hz);
1820
1821                 if (tg->funcs->get_optc_source)
1822                         tg->funcs->get_optc_source(tg,
1823                                                 &numOdmPipes, &id_src[0], &id_src[1]);
1824
1825                 if (numOdmPipes == 2)
1826                         pix_clk_100hz *= 2;
1827                 if (numOdmPipes == 4)
1828                         pix_clk_100hz *= 4;
1829
1830                 // Note: In rare cases, HW pixclk may differ from crtc's pixclk
1831                 // slightly due to rounding issues in 10 kHz units.
1832                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1833                         return false;
1834
1835                 if (!se->funcs->dp_get_pixel_format)
1836                         return false;
1837
1838                 if (!se->funcs->dp_get_pixel_format(
1839                         se,
1840                         &hw_crtc_timing.pixel_encoding,
1841                         &hw_crtc_timing.display_color_depth))
1842                         return false;
1843
1844                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1845                         return false;
1846
1847                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1848                         return false;
1849         }
1850
1851         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1852                 return false;
1853         }
1854
1855         if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)
1856                 return false;
1857
1858         if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
1859                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1860                 return false;
1861         }
1862
1863         return true;
1864 }
1865
1866 static inline bool should_update_pipe_for_stream(
1867                 struct dc_state *context,
1868                 struct pipe_ctx *pipe_ctx,
1869                 struct dc_stream_state *stream)
1870 {
1871         return (pipe_ctx->stream && pipe_ctx->stream == stream);
1872 }
1873
1874 static inline bool should_update_pipe_for_plane(
1875                 struct dc_state *context,
1876                 struct pipe_ctx *pipe_ctx,
1877                 struct dc_plane_state *plane_state)
1878 {
1879         return (pipe_ctx->plane_state == plane_state);
1880 }
1881
1882 void dc_enable_stereo(
1883         struct dc *dc,
1884         struct dc_state *context,
1885         struct dc_stream_state *streams[],
1886         uint8_t stream_count)
1887 {
1888         int i, j;
1889         struct pipe_ctx *pipe;
1890
1891         dc_exit_ips_for_hw_access(dc);
1892
1893         for (i = 0; i < MAX_PIPES; i++) {
1894                 if (context != NULL) {
1895                         pipe = &context->res_ctx.pipe_ctx[i];
1896                 } else {
1897                         context = dc->current_state;
1898                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1899                 }
1900
1901                 for (j = 0; pipe && j < stream_count; j++)  {
1902                         if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1903                                 dc->hwss.setup_stereo)
1904                                 dc->hwss.setup_stereo(pipe, dc);
1905                 }
1906         }
1907 }
1908
1909 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1910 {
1911         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1912                 dc_exit_ips_for_hw_access(dc);
1913
1914                 enable_timing_multisync(dc, context);
1915                 program_timing_sync(dc, context);
1916         }
1917 }
1918
1919 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1920 {
1921         int i;
1922         unsigned int stream_mask = 0;
1923
1924         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1925                 if (context->res_ctx.pipe_ctx[i].stream)
1926                         stream_mask |= 1 << i;
1927         }
1928
1929         return stream_mask;
1930 }
1931
1932 void dc_z10_restore(const struct dc *dc)
1933 {
1934         if (dc->hwss.z10_restore)
1935                 dc->hwss.z10_restore(dc);
1936 }
1937
1938 void dc_z10_save_init(struct dc *dc)
1939 {
1940         if (dc->hwss.z10_save_init)
1941                 dc->hwss.z10_save_init(dc);
1942 }
1943
1944 /**
1945  * dc_commit_state_no_check - Apply context to the hardware
1946  *
1947  * @dc: DC object with the current status to be updated
1948  * @context: New state that will become the current status at the end of this function
1949  *
1950  * Applies given context to the hardware and copy it into current context.
1951  * It's up to the user to release the src context afterwards.
1952  *
1953  * Return: an enum dc_status result code for the operation
1954  */
1955 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1956 {
1957         struct dc_bios *dcb = dc->ctx->dc_bios;
1958         enum dc_status result = DC_ERROR_UNEXPECTED;
1959         struct pipe_ctx *pipe;
1960         int i, k, l;
1961         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1962         struct dc_state *old_state;
1963         bool subvp_prev_use = false;
1964
1965         dc_z10_restore(dc);
1966         dc_allow_idle_optimizations(dc, false);
1967
1968         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1969                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1970
1971                 /* Check old context for SubVP */
1972                 subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);
1973                 if (subvp_prev_use)
1974                         break;
1975         }
1976
1977         for (i = 0; i < context->stream_count; i++)
1978                 dc_streams[i] =  context->streams[i];
1979
1980         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1981                 disable_vbios_mode_if_required(dc, context);
1982                 dc->hwss.enable_accelerated_mode(dc, context);
1983         }
1984
1985         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1986                 context->stream_count == 0)
1987                 dc->hwss.prepare_bandwidth(dc, context);
1988
1989         /* When SubVP is active, all HW programming must be done while
1990          * SubVP lock is acquired
1991          */
1992         if (dc->hwss.subvp_pipe_control_lock)
1993                 dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
1994         if (dc->hwss.fams2_global_control_lock)
1995                 dc->hwss.fams2_global_control_lock(dc, context, true);
1996
1997         if (dc->hwss.update_dsc_pg)
1998                 dc->hwss.update_dsc_pg(dc, context, false);
1999
2000         disable_dangling_plane(dc, context);
2001         /* re-program planes for existing stream, in case we need to
2002          * free up plane resource for later use
2003          */
2004         if (dc->hwss.apply_ctx_for_surface) {
2005                 for (i = 0; i < context->stream_count; i++) {
2006                         if (context->streams[i]->mode_changed)
2007                                 continue;
2008                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
2009                         dc->hwss.apply_ctx_for_surface(
2010                                 dc, context->streams[i],
2011                                 context->stream_status[i].plane_count,
2012                                 context); /* use new pipe config in new context */
2013                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
2014                         dc->hwss.post_unlock_program_front_end(dc, context);
2015                 }
2016         }
2017
2018         /* Program hardware */
2019         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2020                 pipe = &context->res_ctx.pipe_ctx[i];
2021                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
2022         }
2023
2024         result = dc->hwss.apply_ctx_to_hw(dc, context);
2025
2026         if (result != DC_OK) {
2027                 /* Application of dc_state to hardware stopped. */
2028                 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
2029                 return result;
2030         }
2031
2032         dc_trigger_sync(dc, context);
2033
2034         /* Full update should unconditionally be triggered when dc_commit_state_no_check is called */
2035         for (i = 0; i < context->stream_count; i++) {
2036                 uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;
2037
2038                 context->streams[i]->update_flags.raw = 0xFFFFFFFF;
2039                 context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed;
2040         }
2041
2042         /* Program all planes within new context*/
2043         if (dc->res_pool->funcs->prepare_mcache_programming)
2044                 dc->res_pool->funcs->prepare_mcache_programming(dc, context);
2045         if (dc->hwss.program_front_end_for_ctx) {
2046                 dc->hwss.interdependent_update_lock(dc, context, true);
2047                 dc->hwss.program_front_end_for_ctx(dc, context);
2048                 dc->hwss.interdependent_update_lock(dc, context, false);
2049                 dc->hwss.post_unlock_program_front_end(dc, context);
2050         }
2051
2052         if (dc->hwss.commit_subvp_config)
2053                 dc->hwss.commit_subvp_config(dc, context);
2054         if (dc->hwss.subvp_pipe_control_lock)
2055                 dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
2056         if (dc->hwss.fams2_global_control_lock)
2057                 dc->hwss.fams2_global_control_lock(dc, context, false);
2058
2059         for (i = 0; i < context->stream_count; i++) {
2060                 const struct dc_link *link = context->streams[i]->link;
2061
2062                 if (!context->streams[i]->mode_changed)
2063                         continue;
2064
2065                 if (dc->hwss.apply_ctx_for_surface) {
2066                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
2067                         dc->hwss.apply_ctx_for_surface(
2068                                         dc, context->streams[i],
2069                                         context->stream_status[i].plane_count,
2070                                         context);
2071                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
2072                         dc->hwss.post_unlock_program_front_end(dc, context);
2073                 }
2074
2075                 /*
2076                  * enable stereo
2077                  * TODO rework dc_enable_stereo call to work with validation sets?
2078                  */
2079                 for (k = 0; k < MAX_PIPES; k++) {
2080                         pipe = &context->res_ctx.pipe_ctx[k];
2081
2082                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
2083                                 if (context->streams[l] &&
2084                                         context->streams[l] == pipe->stream &&
2085                                         dc->hwss.setup_stereo)
2086                                         dc->hwss.setup_stereo(pipe, dc);
2087                         }
2088                 }
2089
2090                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
2091                                 context->streams[i]->timing.h_addressable,
2092                                 context->streams[i]->timing.v_addressable,
2093                                 context->streams[i]->timing.h_total,
2094                                 context->streams[i]->timing.v_total,
2095                                 context->streams[i]->timing.pix_clk_100hz / 10);
2096         }
2097
2098         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
2099
2100         if (context->stream_count > get_seamless_boot_stream_count(context) ||
2101                 context->stream_count == 0) {
2102                 /* Must wait for no flips to be pending before doing optimize bw */
2103                 wait_for_no_pipes_pending(dc, context);
2104                 /*
2105                  * optimized dispclk depends on ODM setup. Need to wait for ODM
2106                  * update pending complete before optimizing bandwidth.
2107                  */
2108                 wait_for_odm_update_pending_complete(dc, context);
2109                 /* pplib is notified if disp_num changed */
2110                 dc->hwss.optimize_bandwidth(dc, context);
2111                 /* Need to do otg sync again as otg could be out of sync due to otg
2112                  * workaround applied during clock update
2113                  */
2114                 dc_trigger_sync(dc, context);
2115         }
2116
2117         if (dc->hwss.update_dsc_pg)
2118                 dc->hwss.update_dsc_pg(dc, context, true);
2119
2120         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
2121                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2122         else
2123                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2124
2125         context->stream_mask = get_stream_mask(dc, context);
2126
2127         if (context->stream_mask != dc->current_state->stream_mask)
2128                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
2129
2130         for (i = 0; i < context->stream_count; i++)
2131                 context->streams[i]->mode_changed = false;
2132
2133         /* Clear update flags that were set earlier to avoid redundant programming */
2134         for (i = 0; i < context->stream_count; i++) {
2135                 context->streams[i]->update_flags.raw = 0x0;
2136         }
2137
2138         old_state = dc->current_state;
2139         dc->current_state = context;
2140
2141         dc_state_release(old_state);
2142
2143         dc_state_retain(dc->current_state);
2144
2145         return result;
2146 }
2147
2148 static bool commit_minimal_transition_state(struct dc *dc,
2149                 struct dc_state *transition_base_context);
2150
2151 /**
2152  * dc_commit_streams - Commit current stream state
2153  *
2154  * @dc: DC object with the commit state to be configured in the hardware
2155  * @params: Parameters for the commit, including the streams to be committed
2156  *
2157  * Function responsible for commit streams change to the hardware.
2158  *
2159  * Return:
2160  * Return DC_OK if everything work as expected, otherwise, return a dc_status
2161  * code.
2162  */
2163 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params)
2164 {
2165         int i, j;
2166         struct dc_state *context;
2167         enum dc_status res = DC_OK;
2168         struct dc_validation_set set[MAX_STREAMS] = {0};
2169         struct pipe_ctx *pipe;
2170         bool handle_exit_odm2to1 = false;
2171
2172         if (!params)
2173                 return DC_ERROR_UNEXPECTED;
2174
2175         if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
2176                 return res;
2177
2178         if (!streams_changed(dc, params->streams, params->stream_count) &&
2179                         dc->current_state->power_source == params->power_source)
2180                 return res;
2181
2182         dc_exit_ips_for_hw_access(dc);
2183
2184         DC_LOG_DC("%s: %d streams\n", __func__, params->stream_count);
2185
2186         for (i = 0; i < params->stream_count; i++) {
2187                 struct dc_stream_state *stream = params->streams[i];
2188                 struct dc_stream_status *status = dc_stream_get_status(stream);
2189
2190                 dc_stream_log(dc, stream);
2191
2192                 set[i].stream = stream;
2193
2194                 if (status) {
2195                         set[i].plane_count = status->plane_count;
2196                         for (j = 0; j < status->plane_count; j++)
2197                                 set[i].plane_states[j] = status->plane_states[j];
2198                 }
2199         }
2200
2201         /* ODM Combine 2:1 power optimization is only applied for single stream
2202          * scenario, it uses extra pipes than needed to reduce power consumption
2203          * We need to switch off this feature to make room for new streams.
2204          */
2205         if (params->stream_count > dc->current_state->stream_count &&
2206                         dc->current_state->stream_count == 1) {
2207                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2208                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2209                         if (pipe->next_odm_pipe)
2210                                 handle_exit_odm2to1 = true;
2211                 }
2212         }
2213
2214         if (handle_exit_odm2to1)
2215                 res = commit_minimal_transition_state(dc, dc->current_state);
2216
2217         context = dc_state_create_current_copy(dc);
2218         if (!context)
2219                 goto context_alloc_fail;
2220
2221         context->power_source = params->power_source;
2222
2223         res = dc_validate_with_context(dc, set, params->stream_count, context, false);
2224         if (res != DC_OK) {
2225                 BREAK_TO_DEBUGGER();
2226                 goto fail;
2227         }
2228
2229         res = dc_commit_state_no_check(dc, context);
2230
2231         for (i = 0; i < params->stream_count; i++) {
2232                 for (j = 0; j < context->stream_count; j++) {
2233                         if (params->streams[i]->stream_id == context->streams[j]->stream_id)
2234                                 params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
2235
2236                         if (dc_is_embedded_signal(params->streams[i]->signal)) {
2237                                 struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]);
2238
2239                                 if (!status)
2240                                         continue;
2241
2242                                 if (dc->hwss.is_abm_supported)
2243                                         status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, params->streams[i]);
2244                                 else
2245                                         status->is_abm_supported = true;
2246                         }
2247                 }
2248         }
2249
2250 fail:
2251         dc_state_release(context);
2252
2253 context_alloc_fail:
2254
2255         DC_LOG_DC("%s Finished.\n", __func__);
2256
2257         return res;
2258 }
2259
2260 bool dc_acquire_release_mpc_3dlut(
2261                 struct dc *dc, bool acquire,
2262                 struct dc_stream_state *stream,
2263                 struct dc_3dlut **lut,
2264                 struct dc_transfer_func **shaper)
2265 {
2266         int pipe_idx;
2267         bool ret = false;
2268         bool found_pipe_idx = false;
2269         const struct resource_pool *pool = dc->res_pool;
2270         struct resource_context *res_ctx = &dc->current_state->res_ctx;
2271         int mpcc_id = 0;
2272
2273         if (pool && res_ctx) {
2274                 if (acquire) {
2275                         /*find pipe idx for the given stream*/
2276                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
2277                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
2278                                         found_pipe_idx = true;
2279                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
2280                                         break;
2281                                 }
2282                         }
2283                 } else
2284                         found_pipe_idx = true;/*for release pipe_idx is not required*/
2285
2286                 if (found_pipe_idx) {
2287                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
2288                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
2289                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
2290                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
2291                 }
2292         }
2293         return ret;
2294 }
2295
2296 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
2297 {
2298         int i;
2299         struct pipe_ctx *pipe;
2300
2301         for (i = 0; i < MAX_PIPES; i++) {
2302                 pipe = &context->res_ctx.pipe_ctx[i];
2303
2304                 // Don't check flip pending on phantom pipes
2305                 if (!pipe->plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))
2306                         continue;
2307
2308                 /* Must set to false to start with, due to OR in update function */
2309                 pipe->plane_state->status.is_flip_pending = false;
2310                 dc->hwss.update_pending_status(pipe);
2311                 if (pipe->plane_state->status.is_flip_pending)
2312                         return true;
2313         }
2314         return false;
2315 }
2316
2317 /* Perform updates here which need to be deferred until next vupdate
2318  *
2319  * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
2320  * but forcing lut memory to shutdown state is immediate. This causes
2321  * single frame corruption as lut gets disabled mid-frame unless shutdown
2322  * is deferred until after entering bypass.
2323  */
2324 static void process_deferred_updates(struct dc *dc)
2325 {
2326         int i = 0;
2327
2328         if (dc->debug.enable_mem_low_power.bits.cm) {
2329                 ASSERT(dc->dcn_ip->max_num_dpp);
2330                 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
2331                         if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
2332                                 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
2333         }
2334 }
2335
2336 void dc_post_update_surfaces_to_stream(struct dc *dc)
2337 {
2338         int i;
2339         struct dc_state *context = dc->current_state;
2340
2341         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
2342                 return;
2343
2344         post_surface_trace(dc);
2345
2346         /*
2347          * Only relevant for DCN behavior where we can guarantee the optimization
2348          * is safe to apply - retain the legacy behavior for DCE.
2349          */
2350
2351         if (dc->ctx->dce_version < DCE_VERSION_MAX)
2352                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2353         else {
2354                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2355
2356                 if (is_flip_pending_in_pipes(dc, context))
2357                         return;
2358
2359                 for (i = 0; i < dc->res_pool->pipe_count; i++)
2360                         if (context->res_ctx.pipe_ctx[i].stream == NULL ||
2361                                         context->res_ctx.pipe_ctx[i].plane_state == NULL) {
2362                                 context->res_ctx.pipe_ctx[i].pipe_idx = i;
2363                                 dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);
2364                         }
2365
2366                 process_deferred_updates(dc);
2367
2368                 dc->hwss.optimize_bandwidth(dc, context);
2369
2370                 if (dc->hwss.update_dsc_pg)
2371                         dc->hwss.update_dsc_pg(dc, context, true);
2372         }
2373
2374         dc->optimized_required = false;
2375         dc->wm_optimized_required = false;
2376 }
2377
2378 bool dc_set_generic_gpio_for_stereo(bool enable,
2379                 struct gpio_service *gpio_service)
2380 {
2381         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
2382         struct gpio_pin_info pin_info;
2383         struct gpio *generic;
2384         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
2385                            GFP_KERNEL);
2386
2387         if (!config)
2388                 return false;
2389         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
2390
2391         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
2392                 kfree(config);
2393                 return false;
2394         } else {
2395                 generic = dal_gpio_service_create_generic_mux(
2396                         gpio_service,
2397                         pin_info.offset,
2398                         pin_info.mask);
2399         }
2400
2401         if (!generic) {
2402                 kfree(config);
2403                 return false;
2404         }
2405
2406         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
2407
2408         config->enable_output_from_mux = enable;
2409         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
2410
2411         if (gpio_result == GPIO_RESULT_OK)
2412                 gpio_result = dal_mux_setup_config(generic, config);
2413
2414         if (gpio_result == GPIO_RESULT_OK) {
2415                 dal_gpio_close(generic);
2416                 dal_gpio_destroy_generic_mux(&generic);
2417                 kfree(config);
2418                 return true;
2419         } else {
2420                 dal_gpio_close(generic);
2421                 dal_gpio_destroy_generic_mux(&generic);
2422                 kfree(config);
2423                 return false;
2424         }
2425 }
2426
2427 static bool is_surface_in_context(
2428                 const struct dc_state *context,
2429                 const struct dc_plane_state *plane_state)
2430 {
2431         int j;
2432
2433         for (j = 0; j < MAX_PIPES; j++) {
2434                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2435
2436                 if (plane_state == pipe_ctx->plane_state) {
2437                         return true;
2438                 }
2439         }
2440
2441         return false;
2442 }
2443
2444 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
2445 {
2446         union surface_update_flags *update_flags = &u->surface->update_flags;
2447         enum surface_update_type update_type = UPDATE_TYPE_FAST;
2448
2449         if (!u->plane_info)
2450                 return UPDATE_TYPE_FAST;
2451
2452         if (u->plane_info->color_space != u->surface->color_space) {
2453                 update_flags->bits.color_space_change = 1;
2454                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2455         }
2456
2457         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
2458                 update_flags->bits.horizontal_mirror_change = 1;
2459                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2460         }
2461
2462         if (u->plane_info->rotation != u->surface->rotation) {
2463                 update_flags->bits.rotation_change = 1;
2464                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2465         }
2466
2467         if (u->plane_info->format != u->surface->format) {
2468                 update_flags->bits.pixel_format_change = 1;
2469                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2470         }
2471
2472         if (u->plane_info->stereo_format != u->surface->stereo_format) {
2473                 update_flags->bits.stereo_format_change = 1;
2474                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2475         }
2476
2477         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
2478                 update_flags->bits.per_pixel_alpha_change = 1;
2479                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2480         }
2481
2482         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
2483                 update_flags->bits.global_alpha_change = 1;
2484                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2485         }
2486
2487         if (u->plane_info->dcc.enable != u->surface->dcc.enable
2488                         || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
2489                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
2490                 /* During DCC on/off, stutter period is calculated before
2491                  * DCC has fully transitioned. This results in incorrect
2492                  * stutter period calculation. Triggering a full update will
2493                  * recalculate stutter period.
2494                  */
2495                 update_flags->bits.dcc_change = 1;
2496                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2497         }
2498
2499         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2500                         resource_pixel_format_to_bpp(u->surface->format)) {
2501                 /* different bytes per element will require full bandwidth
2502                  * and DML calculation
2503                  */
2504                 update_flags->bits.bpp_change = 1;
2505                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2506         }
2507
2508         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2509                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2510                 update_flags->bits.plane_size_change = 1;
2511                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2512         }
2513
2514
2515         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2516                         sizeof(union dc_tiling_info)) != 0) {
2517                 update_flags->bits.swizzle_change = 1;
2518                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2519
2520                 /* todo: below are HW dependent, we should add a hook to
2521                  * DCE/N resource and validated there.
2522                  */
2523                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2524                         /* swizzled mode requires RQ to be setup properly,
2525                          * thus need to run DML to calculate RQ settings
2526                          */
2527                         update_flags->bits.bandwidth_change = 1;
2528                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2529                 }
2530         }
2531
2532         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2533         return update_type;
2534 }
2535
2536 static enum surface_update_type get_scaling_info_update_type(
2537                 const struct dc *dc,
2538                 const struct dc_surface_update *u)
2539 {
2540         union surface_update_flags *update_flags = &u->surface->update_flags;
2541
2542         if (!u->scaling_info)
2543                 return UPDATE_TYPE_FAST;
2544
2545         if (u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2546                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2547                         || u->scaling_info->scaling_quality.integer_scaling !=
2548                                 u->surface->scaling_quality.integer_scaling
2549                         ) {
2550                 update_flags->bits.scaling_change = 1;
2551
2552                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2553                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2554                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2555                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2556                         /* Making dst rect smaller requires a bandwidth change */
2557                         update_flags->bits.bandwidth_change = 1;
2558         }
2559
2560         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2561                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2562
2563                 update_flags->bits.scaling_change = 1;
2564                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2565                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2566                         /* Making src rect bigger requires a bandwidth change */
2567                         update_flags->bits.clock_change = 1;
2568         }
2569
2570         if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width &&
2571                 (u->scaling_info->clip_rect.width > u->surface->clip_rect.width ||
2572                  u->scaling_info->clip_rect.height > u->surface->clip_rect.height))
2573                  /* Changing clip size of a large surface may result in MPC slice count change */
2574                 update_flags->bits.bandwidth_change = 1;
2575
2576         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width ||
2577                         u->scaling_info->clip_rect.height != u->surface->clip_rect.height)
2578                 update_flags->bits.clip_size_change = 1;
2579
2580         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2581                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2582                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2583                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2584                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2585                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2586                 update_flags->bits.position_change = 1;
2587
2588         if (update_flags->bits.clock_change
2589                         || update_flags->bits.bandwidth_change
2590                         || update_flags->bits.scaling_change)
2591                 return UPDATE_TYPE_FULL;
2592
2593         if (update_flags->bits.position_change ||
2594                         update_flags->bits.clip_size_change)
2595                 return UPDATE_TYPE_MED;
2596
2597         return UPDATE_TYPE_FAST;
2598 }
2599
2600 static enum surface_update_type det_surface_update(const struct dc *dc,
2601                 const struct dc_surface_update *u)
2602 {
2603         const struct dc_state *context = dc->current_state;
2604         enum surface_update_type type;
2605         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2606         union surface_update_flags *update_flags = &u->surface->update_flags;
2607
2608         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2609                 update_flags->raw = 0xFFFFFFFF;
2610                 return UPDATE_TYPE_FULL;
2611         }
2612
2613         update_flags->raw = 0; // Reset all flags
2614
2615         type = get_plane_info_update_type(u);
2616         elevate_update_type(&overall_type, type);
2617
2618         type = get_scaling_info_update_type(dc, u);
2619         elevate_update_type(&overall_type, type);
2620
2621         if (u->flip_addr) {
2622                 update_flags->bits.addr_update = 1;
2623                 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {
2624                         update_flags->bits.tmz_changed = 1;
2625                         elevate_update_type(&overall_type, UPDATE_TYPE_FULL);
2626                 }
2627         }
2628         if (u->in_transfer_func)
2629                 update_flags->bits.in_transfer_func_change = 1;
2630
2631         if (u->input_csc_color_matrix)
2632                 update_flags->bits.input_csc_change = 1;
2633
2634         if (u->coeff_reduction_factor)
2635                 update_flags->bits.coeff_reduction_change = 1;
2636
2637         if (u->gamut_remap_matrix)
2638                 update_flags->bits.gamut_remap_change = 1;
2639
2640         if (u->blend_tf)
2641                 update_flags->bits.gamma_change = 1;
2642
2643         if (u->gamma) {
2644                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2645
2646                 if (u->plane_info)
2647                         format = u->plane_info->format;
2648                 else
2649                         format = u->surface->format;
2650
2651                 if (dce_use_lut(format))
2652                         update_flags->bits.gamma_change = 1;
2653         }
2654
2655         if (u->lut3d_func || u->func_shaper)
2656                 update_flags->bits.lut_3d = 1;
2657
2658         if (u->hdr_mult.value)
2659                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2660                         update_flags->bits.hdr_mult = 1;
2661                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2662                 }
2663
2664         if (u->cm2_params) {
2665                 if ((u->cm2_params->component_settings.shaper_3dlut_setting
2666                                         != u->surface->mcm_shaper_3dlut_setting)
2667                                 || (u->cm2_params->component_settings.lut1d_enable
2668                                         != u->surface->mcm_lut1d_enable))
2669                         update_flags->bits.mcm_transfer_function_enable_change = 1;
2670                 if (u->cm2_params->cm2_luts.lut3d_data.lut3d_src
2671                                 != u->surface->mcm_luts.lut3d_data.lut3d_src)
2672                         update_flags->bits.mcm_transfer_function_enable_change = 1;
2673         }
2674         if (update_flags->bits.in_transfer_func_change) {
2675                 type = UPDATE_TYPE_MED;
2676                 elevate_update_type(&overall_type, type);
2677         }
2678
2679         if (update_flags->bits.lut_3d) {
2680                 type = UPDATE_TYPE_FULL;
2681                 elevate_update_type(&overall_type, type);
2682         }
2683         if (update_flags->bits.mcm_transfer_function_enable_change) {
2684                 type = UPDATE_TYPE_FULL;
2685                 elevate_update_type(&overall_type, type);
2686         }
2687
2688         if (dc->debug.enable_legacy_fast_update &&
2689                         (update_flags->bits.gamma_change ||
2690                         update_flags->bits.gamut_remap_change ||
2691                         update_flags->bits.input_csc_change ||
2692                         update_flags->bits.coeff_reduction_change)) {
2693                 type = UPDATE_TYPE_FULL;
2694                 elevate_update_type(&overall_type, type);
2695         }
2696         return overall_type;
2697 }
2698
2699 static enum surface_update_type check_update_surfaces_for_stream(
2700                 struct dc *dc,
2701                 struct dc_surface_update *updates,
2702                 int surface_count,
2703                 struct dc_stream_update *stream_update,
2704                 const struct dc_stream_status *stream_status)
2705 {
2706         int i;
2707         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2708
2709         if (dc->idle_optimizations_allowed)
2710                 overall_type = UPDATE_TYPE_FULL;
2711
2712         if (stream_status == NULL || stream_status->plane_count != surface_count)
2713                 overall_type = UPDATE_TYPE_FULL;
2714
2715         if (stream_update && stream_update->pending_test_pattern) {
2716                 overall_type = UPDATE_TYPE_FULL;
2717         }
2718
2719         /* some stream updates require passive update */
2720         if (stream_update) {
2721                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2722
2723                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2724                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2725                         stream_update->integer_scaling_update)
2726                         su_flags->bits.scaling = 1;
2727
2728                 if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2729                         su_flags->bits.out_tf = 1;
2730
2731                 if (stream_update->abm_level)
2732                         su_flags->bits.abm_level = 1;
2733
2734                 if (stream_update->dpms_off)
2735                         su_flags->bits.dpms_off = 1;
2736
2737                 if (stream_update->gamut_remap)
2738                         su_flags->bits.gamut_remap = 1;
2739
2740                 if (stream_update->wb_update)
2741                         su_flags->bits.wb_update = 1;
2742
2743                 if (stream_update->dsc_config)
2744                         su_flags->bits.dsc_changed = 1;
2745
2746                 if (stream_update->mst_bw_update)
2747                         su_flags->bits.mst_bw = 1;
2748
2749                 if (stream_update->stream->freesync_on_desktop &&
2750                         (stream_update->vrr_infopacket || stream_update->allow_freesync ||
2751                                 stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
2752                         su_flags->bits.fams_changed = 1;
2753
2754                 if (su_flags->raw != 0)
2755                         overall_type = UPDATE_TYPE_FULL;
2756
2757                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2758                         su_flags->bits.out_csc = 1;
2759
2760                 /* Output transfer function changes do not require bandwidth recalculation,
2761                  * so don't trigger a full update
2762                  */
2763                 if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2764                         su_flags->bits.out_tf = 1;
2765         }
2766
2767         for (i = 0 ; i < surface_count; i++) {
2768                 enum surface_update_type type =
2769                                 det_surface_update(dc, &updates[i]);
2770
2771                 elevate_update_type(&overall_type, type);
2772         }
2773
2774         return overall_type;
2775 }
2776
2777 /*
2778  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2779  *
2780  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2781  */
2782 enum surface_update_type dc_check_update_surfaces_for_stream(
2783                 struct dc *dc,
2784                 struct dc_surface_update *updates,
2785                 int surface_count,
2786                 struct dc_stream_update *stream_update,
2787                 const struct dc_stream_status *stream_status)
2788 {
2789         int i;
2790         enum surface_update_type type;
2791
2792         if (stream_update)
2793                 stream_update->stream->update_flags.raw = 0;
2794         for (i = 0; i < surface_count; i++)
2795                 updates[i].surface->update_flags.raw = 0;
2796
2797         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2798         if (type == UPDATE_TYPE_FULL) {
2799                 if (stream_update) {
2800                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2801                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2802                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2803                 }
2804                 for (i = 0; i < surface_count; i++)
2805                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2806         }
2807
2808         if (type == UPDATE_TYPE_FAST) {
2809                 // If there's an available clock comparator, we use that.
2810                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2811                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2812                                 dc->optimized_required = true;
2813                 // Else we fallback to mem compare.
2814                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2815                         dc->optimized_required = true;
2816                 }
2817
2818                 dc->optimized_required |= dc->wm_optimized_required;
2819         }
2820
2821         return type;
2822 }
2823
2824 static struct dc_stream_status *stream_get_status(
2825         struct dc_state *ctx,
2826         struct dc_stream_state *stream)
2827 {
2828         uint8_t i;
2829
2830         for (i = 0; i < ctx->stream_count; i++) {
2831                 if (stream == ctx->streams[i]) {
2832                         return &ctx->stream_status[i];
2833                 }
2834         }
2835
2836         return NULL;
2837 }
2838
2839 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2840
2841 static void copy_surface_update_to_plane(
2842                 struct dc_plane_state *surface,
2843                 struct dc_surface_update *srf_update)
2844 {
2845         if (srf_update->flip_addr) {
2846                 surface->address = srf_update->flip_addr->address;
2847                 surface->flip_immediate =
2848                         srf_update->flip_addr->flip_immediate;
2849                 surface->time.time_elapsed_in_us[surface->time.index] =
2850                         srf_update->flip_addr->flip_timestamp_in_us -
2851                                 surface->time.prev_update_time_in_us;
2852                 surface->time.prev_update_time_in_us =
2853                         srf_update->flip_addr->flip_timestamp_in_us;
2854                 surface->time.index++;
2855                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2856                         surface->time.index = 0;
2857
2858                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2859         }
2860
2861         if (srf_update->scaling_info) {
2862                 surface->scaling_quality =
2863                                 srf_update->scaling_info->scaling_quality;
2864                 surface->dst_rect =
2865                                 srf_update->scaling_info->dst_rect;
2866                 surface->src_rect =
2867                                 srf_update->scaling_info->src_rect;
2868                 surface->clip_rect =
2869                                 srf_update->scaling_info->clip_rect;
2870         }
2871
2872         if (srf_update->plane_info) {
2873                 surface->color_space =
2874                                 srf_update->plane_info->color_space;
2875                 surface->format =
2876                                 srf_update->plane_info->format;
2877                 surface->plane_size =
2878                                 srf_update->plane_info->plane_size;
2879                 surface->rotation =
2880                                 srf_update->plane_info->rotation;
2881                 surface->horizontal_mirror =
2882                                 srf_update->plane_info->horizontal_mirror;
2883                 surface->stereo_format =
2884                                 srf_update->plane_info->stereo_format;
2885                 surface->tiling_info =
2886                                 srf_update->plane_info->tiling_info;
2887                 surface->visible =
2888                                 srf_update->plane_info->visible;
2889                 surface->per_pixel_alpha =
2890                                 srf_update->plane_info->per_pixel_alpha;
2891                 surface->global_alpha =
2892                                 srf_update->plane_info->global_alpha;
2893                 surface->global_alpha_value =
2894                                 srf_update->plane_info->global_alpha_value;
2895                 surface->dcc =
2896                                 srf_update->plane_info->dcc;
2897                 surface->layer_index =
2898                                 srf_update->plane_info->layer_index;
2899         }
2900
2901         if (srf_update->gamma) {
2902                 memcpy(&surface->gamma_correction.entries,
2903                         &srf_update->gamma->entries,
2904                         sizeof(struct dc_gamma_entries));
2905                 surface->gamma_correction.is_identity =
2906                         srf_update->gamma->is_identity;
2907                 surface->gamma_correction.num_entries =
2908                         srf_update->gamma->num_entries;
2909                 surface->gamma_correction.type =
2910                         srf_update->gamma->type;
2911         }
2912
2913         if (srf_update->in_transfer_func) {
2914                 surface->in_transfer_func.sdr_ref_white_level =
2915                         srf_update->in_transfer_func->sdr_ref_white_level;
2916                 surface->in_transfer_func.tf =
2917                         srf_update->in_transfer_func->tf;
2918                 surface->in_transfer_func.type =
2919                         srf_update->in_transfer_func->type;
2920                 memcpy(&surface->in_transfer_func.tf_pts,
2921                         &srf_update->in_transfer_func->tf_pts,
2922                         sizeof(struct dc_transfer_func_distributed_points));
2923         }
2924
2925         if (srf_update->func_shaper)
2926                 memcpy(&surface->in_shaper_func, srf_update->func_shaper,
2927                 sizeof(surface->in_shaper_func));
2928
2929         if (srf_update->lut3d_func)
2930                 memcpy(&surface->lut3d_func, srf_update->lut3d_func,
2931                 sizeof(surface->lut3d_func));
2932
2933         if (srf_update->hdr_mult.value)
2934                 surface->hdr_mult =
2935                                 srf_update->hdr_mult;
2936
2937         if (srf_update->blend_tf)
2938                 memcpy(&surface->blend_tf, srf_update->blend_tf,
2939                 sizeof(surface->blend_tf));
2940
2941         if (srf_update->input_csc_color_matrix)
2942                 surface->input_csc_color_matrix =
2943                         *srf_update->input_csc_color_matrix;
2944
2945         if (srf_update->coeff_reduction_factor)
2946                 surface->coeff_reduction_factor =
2947                         *srf_update->coeff_reduction_factor;
2948
2949         if (srf_update->gamut_remap_matrix)
2950                 surface->gamut_remap_matrix =
2951                         *srf_update->gamut_remap_matrix;
2952         if (srf_update->cm2_params) {
2953                 surface->mcm_shaper_3dlut_setting = srf_update->cm2_params->component_settings.shaper_3dlut_setting;
2954                 surface->mcm_lut1d_enable = srf_update->cm2_params->component_settings.lut1d_enable;
2955                 surface->mcm_luts = srf_update->cm2_params->cm2_luts;
2956         }
2957         if (srf_update->cursor_csc_color_matrix)
2958                 surface->cursor_csc_color_matrix =
2959                         *srf_update->cursor_csc_color_matrix;
2960 }
2961
2962 static void copy_stream_update_to_stream(struct dc *dc,
2963                                          struct dc_state *context,
2964                                          struct dc_stream_state *stream,
2965                                          struct dc_stream_update *update)
2966 {
2967         struct dc_context *dc_ctx = dc->ctx;
2968
2969         if (update == NULL || stream == NULL)
2970                 return;
2971
2972         if (update->src.height && update->src.width)
2973                 stream->src = update->src;
2974
2975         if (update->dst.height && update->dst.width)
2976                 stream->dst = update->dst;
2977
2978         if (update->out_transfer_func) {
2979                 stream->out_transfer_func.sdr_ref_white_level =
2980                         update->out_transfer_func->sdr_ref_white_level;
2981                 stream->out_transfer_func.tf = update->out_transfer_func->tf;
2982                 stream->out_transfer_func.type =
2983                         update->out_transfer_func->type;
2984                 memcpy(&stream->out_transfer_func.tf_pts,
2985                        &update->out_transfer_func->tf_pts,
2986                        sizeof(struct dc_transfer_func_distributed_points));
2987         }
2988
2989         if (update->hdr_static_metadata)
2990                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2991
2992         if (update->abm_level)
2993                 stream->abm_level = *update->abm_level;
2994
2995         if (update->periodic_interrupt)
2996                 stream->periodic_interrupt = *update->periodic_interrupt;
2997
2998         if (update->gamut_remap)
2999                 stream->gamut_remap_matrix = *update->gamut_remap;
3000
3001         /* Note: this being updated after mode set is currently not a use case
3002          * however if it arises OCSC would need to be reprogrammed at the
3003          * minimum
3004          */
3005         if (update->output_color_space)
3006                 stream->output_color_space = *update->output_color_space;
3007
3008         if (update->output_csc_transform)
3009                 stream->csc_color_matrix = *update->output_csc_transform;
3010
3011         if (update->vrr_infopacket)
3012                 stream->vrr_infopacket = *update->vrr_infopacket;
3013
3014         if (update->allow_freesync)
3015                 stream->allow_freesync = *update->allow_freesync;
3016
3017         if (update->vrr_active_variable)
3018                 stream->vrr_active_variable = *update->vrr_active_variable;
3019
3020         if (update->vrr_active_fixed)
3021                 stream->vrr_active_fixed = *update->vrr_active_fixed;
3022
3023         if (update->crtc_timing_adjust)
3024                 stream->adjust = *update->crtc_timing_adjust;
3025
3026         if (update->dpms_off)
3027                 stream->dpms_off = *update->dpms_off;
3028
3029         if (update->hfvsif_infopacket)
3030                 stream->hfvsif_infopacket = *update->hfvsif_infopacket;
3031
3032         if (update->vtem_infopacket)
3033                 stream->vtem_infopacket = *update->vtem_infopacket;
3034
3035         if (update->vsc_infopacket)
3036                 stream->vsc_infopacket = *update->vsc_infopacket;
3037
3038         if (update->vsp_infopacket)
3039                 stream->vsp_infopacket = *update->vsp_infopacket;
3040
3041         if (update->adaptive_sync_infopacket)
3042                 stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;
3043
3044         if (update->dither_option)
3045                 stream->dither_option = *update->dither_option;
3046
3047         if (update->pending_test_pattern)
3048                 stream->test_pattern = *update->pending_test_pattern;
3049         /* update current stream with writeback info */
3050         if (update->wb_update) {
3051                 int i;
3052
3053                 stream->num_wb_info = update->wb_update->num_wb_info;
3054                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
3055                 for (i = 0; i < stream->num_wb_info; i++)
3056                         stream->writeback_info[i] =
3057                                 update->wb_update->writeback_info[i];
3058         }
3059         if (update->dsc_config) {
3060                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
3061                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
3062                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
3063                                        update->dsc_config->num_slices_v != 0);
3064
3065                 /* Use temporarry context for validating new DSC config */
3066                 struct dc_state *dsc_validate_context = dc_state_create_copy(dc->current_state);
3067
3068                 if (dsc_validate_context) {
3069                         stream->timing.dsc_cfg = *update->dsc_config;
3070                         stream->timing.flags.DSC = enable_dsc;
3071                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
3072                                 stream->timing.dsc_cfg = old_dsc_cfg;
3073                                 stream->timing.flags.DSC = old_dsc_enabled;
3074                                 update->dsc_config = NULL;
3075                         }
3076
3077                         dc_state_release(dsc_validate_context);
3078                 } else {
3079                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
3080                         update->dsc_config = NULL;
3081                 }
3082         }
3083 }
3084
3085 static void backup_planes_and_stream_state(
3086                 struct dc_scratch_space *scratch,
3087                 struct dc_stream_state *stream)
3088 {
3089         int i;
3090         struct dc_stream_status *status = dc_stream_get_status(stream);
3091
3092         if (!status)
3093                 return;
3094
3095         for (i = 0; i < status->plane_count; i++) {
3096                 scratch->plane_states[i] = *status->plane_states[i];
3097         }
3098         scratch->stream_state = *stream;
3099 }
3100
3101 static void restore_planes_and_stream_state(
3102                 struct dc_scratch_space *scratch,
3103                 struct dc_stream_state *stream)
3104 {
3105         int i;
3106         struct dc_stream_status *status = dc_stream_get_status(stream);
3107
3108         if (!status)
3109                 return;
3110
3111         for (i = 0; i < status->plane_count; i++) {
3112                 *status->plane_states[i] = scratch->plane_states[i];
3113         }
3114         *stream = scratch->stream_state;
3115 }
3116
3117 /**
3118  * update_seamless_boot_flags() - Helper function for updating seamless boot flags
3119  *
3120  * @dc: Current DC state
3121  * @context: New DC state to be programmed
3122  * @surface_count: Number of surfaces that have an updated
3123  * @stream: Corresponding stream to be updated in the current flip
3124  *
3125  * Updating seamless boot flags do not need to be part of the commit sequence. This
3126  * helper function will update the seamless boot flags on each flip (if required)
3127  * outside of the HW commit sequence (fast or slow).
3128  *
3129  * Return: void
3130  */
3131 static void update_seamless_boot_flags(struct dc *dc,
3132                 struct dc_state *context,
3133                 int surface_count,
3134                 struct dc_stream_state *stream)
3135 {
3136         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
3137                 /* Optimize seamless boot flag keeps clocks and watermarks high until
3138                  * first flip. After first flip, optimization is required to lower
3139                  * bandwidth. Important to note that it is expected UEFI will
3140                  * only light up a single display on POST, therefore we only expect
3141                  * one stream with seamless boot flag set.
3142                  */
3143                 if (stream->apply_seamless_boot_optimization) {
3144                         stream->apply_seamless_boot_optimization = false;
3145
3146                         if (get_seamless_boot_stream_count(context) == 0)
3147                                 dc->optimized_required = true;
3148                 }
3149         }
3150 }
3151
3152 /**
3153  * update_planes_and_stream_state() - The function takes planes and stream
3154  * updates as inputs and determines the appropriate update type. If update type
3155  * is FULL, the function allocates a new context, populates and validates it.
3156  * Otherwise, it updates current dc context. The function will return both
3157  * new_context and new_update_type back to the caller. The function also backs
3158  * up both current and new contexts into corresponding dc state scratch memory.
3159  * TODO: The function does too many things, and even conditionally allocates dc
3160  * context memory implicitly. We should consider to break it down.
3161  *
3162  * @dc: Current DC state
3163  * @srf_updates: an array of surface updates
3164  * @surface_count: surface update count
3165  * @stream: Corresponding stream to be updated
3166  * @stream_update: stream update
3167  * @new_update_type: [out] determined update type by the function
3168  * @new_context: [out] new context allocated and validated if update type is
3169  * FULL, reference to current context if update type is less than FULL.
3170  *
3171  * Return: true if a valid update is populated into new_context, false
3172  * otherwise.
3173  */
3174 static bool update_planes_and_stream_state(struct dc *dc,
3175                 struct dc_surface_update *srf_updates, int surface_count,
3176                 struct dc_stream_state *stream,
3177                 struct dc_stream_update *stream_update,
3178                 enum surface_update_type *new_update_type,
3179                 struct dc_state **new_context)
3180 {
3181         struct dc_state *context;
3182         int i, j;
3183         enum surface_update_type update_type;
3184         const struct dc_stream_status *stream_status;
3185         struct dc_context *dc_ctx = dc->ctx;
3186
3187         stream_status = dc_stream_get_status(stream);
3188
3189         if (!stream_status) {
3190                 if (surface_count) /* Only an error condition if surf_count non-zero*/
3191                         ASSERT(false);
3192
3193                 return false; /* Cannot commit surface to stream that is not committed */
3194         }
3195
3196         context = dc->current_state;
3197         update_type = dc_check_update_surfaces_for_stream(
3198                         dc, srf_updates, surface_count, stream_update, stream_status);
3199         if (update_type == UPDATE_TYPE_FULL)
3200                 backup_planes_and_stream_state(&dc->scratch.current_state, stream);
3201
3202         /* update current stream with the new updates */
3203         copy_stream_update_to_stream(dc, context, stream, stream_update);
3204
3205         /* do not perform surface update if surface has invalid dimensions
3206          * (all zero) and no scaling_info is provided
3207          */
3208         if (surface_count > 0) {
3209                 for (i = 0; i < surface_count; i++) {
3210                         if ((srf_updates[i].surface->src_rect.width == 0 ||
3211                                  srf_updates[i].surface->src_rect.height == 0 ||
3212                                  srf_updates[i].surface->dst_rect.width == 0 ||
3213                                  srf_updates[i].surface->dst_rect.height == 0) &&
3214                                 (!srf_updates[i].scaling_info ||
3215                                   srf_updates[i].scaling_info->src_rect.width == 0 ||
3216                                   srf_updates[i].scaling_info->src_rect.height == 0 ||
3217                                   srf_updates[i].scaling_info->dst_rect.width == 0 ||
3218                                   srf_updates[i].scaling_info->dst_rect.height == 0)) {
3219                                 DC_ERROR("Invalid src/dst rects in surface update!\n");
3220                                 return false;
3221                         }
3222                 }
3223         }
3224
3225         if (update_type >= update_surface_trace_level)
3226                 update_surface_trace(dc, srf_updates, surface_count);
3227
3228         for (i = 0; i < surface_count; i++)
3229                 copy_surface_update_to_plane(srf_updates[i].surface, &srf_updates[i]);
3230
3231         if (update_type >= UPDATE_TYPE_FULL) {
3232                 struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
3233
3234                 for (i = 0; i < surface_count; i++)
3235                         new_planes[i] = srf_updates[i].surface;
3236
3237                 /* initialize scratch memory for building context */
3238                 context = dc_state_create_copy(dc->current_state);
3239                 if (context == NULL) {
3240                         DC_ERROR("Failed to allocate new validate context!\n");
3241                         return false;
3242                 }
3243
3244                 /* For each full update, remove all existing phantom pipes first.
3245                  * Ensures that we have enough pipes for newly added MPO planes
3246                  */
3247                 dc_state_remove_phantom_streams_and_planes(dc, context);
3248                 dc_state_release_phantom_streams_and_planes(dc, context);
3249
3250                 /*remove old surfaces from context */
3251                 if (!dc_state_rem_all_planes_for_stream(dc, stream, context)) {
3252
3253                         BREAK_TO_DEBUGGER();
3254                         goto fail;
3255                 }
3256
3257                 /* add surface to context */
3258                 if (!dc_state_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
3259
3260                         BREAK_TO_DEBUGGER();
3261                         goto fail;
3262                 }
3263         }
3264
3265         /* save update parameters into surface */
3266         for (i = 0; i < surface_count; i++) {
3267                 struct dc_plane_state *surface = srf_updates[i].surface;
3268
3269                 if (update_type != UPDATE_TYPE_MED)
3270                         continue;
3271                 if (surface->update_flags.bits.clip_size_change ||
3272                                 surface->update_flags.bits.position_change) {
3273                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3274                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3275
3276                                 if (pipe_ctx->plane_state != surface)
3277                                         continue;
3278
3279                                 resource_build_scaling_params(pipe_ctx);
3280                         }
3281                 }
3282         }
3283
3284         if (update_type == UPDATE_TYPE_FULL) {
3285                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
3286                         BREAK_TO_DEBUGGER();
3287                         goto fail;
3288                 }
3289         }
3290         update_seamless_boot_flags(dc, context, surface_count, stream);
3291
3292         *new_context = context;
3293         *new_update_type = update_type;
3294         if (update_type == UPDATE_TYPE_FULL)
3295                 backup_planes_and_stream_state(&dc->scratch.new_state, stream);
3296
3297         return true;
3298
3299 fail:
3300         dc_state_release(context);
3301
3302         return false;
3303
3304 }
3305
3306 static void commit_planes_do_stream_update(struct dc *dc,
3307                 struct dc_stream_state *stream,
3308                 struct dc_stream_update *stream_update,
3309                 enum surface_update_type update_type,
3310                 struct dc_state *context)
3311 {
3312         int j;
3313
3314         // Stream updates
3315         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3316                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3317
3318                 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
3319
3320                         if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
3321                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
3322
3323                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
3324                                         stream_update->vrr_infopacket ||
3325                                         stream_update->vsc_infopacket ||
3326                                         stream_update->vsp_infopacket ||
3327                                         stream_update->hfvsif_infopacket ||
3328                                         stream_update->adaptive_sync_infopacket ||
3329                                         stream_update->vtem_infopacket) {
3330                                 resource_build_info_frame(pipe_ctx);
3331                                 dc->hwss.update_info_frame(pipe_ctx);
3332
3333                                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3334                                         dc->link_srv->dp_trace_source_sequence(
3335                                                         pipe_ctx->stream->link,
3336                                                         DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3337                         }
3338
3339                         if (stream_update->hdr_static_metadata &&
3340                                         stream->use_dynamic_meta &&
3341                                         dc->hwss.set_dmdata_attributes &&
3342                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
3343                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
3344
3345                         if (stream_update->gamut_remap)
3346                                 dc_stream_set_gamut_remap(dc, stream);
3347
3348                         if (stream_update->output_csc_transform)
3349                                 dc_stream_program_csc_matrix(dc, stream);
3350
3351                         if (stream_update->dither_option) {
3352                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
3353                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
3354                                                                         &pipe_ctx->stream->bit_depth_params);
3355                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
3356                                                 &stream->bit_depth_params,
3357                                                 &stream->clamping);
3358                                 while (odm_pipe) {
3359                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
3360                                                         &stream->bit_depth_params,
3361                                                         &stream->clamping);
3362                                         odm_pipe = odm_pipe->next_odm_pipe;
3363                                 }
3364                         }
3365
3366                         if (stream_update->cursor_attributes)
3367                                 program_cursor_attributes(dc, stream);
3368
3369                         if (stream_update->cursor_position)
3370                                 program_cursor_position(dc, stream);
3371
3372                         /* Full fe update*/
3373                         if (update_type == UPDATE_TYPE_FAST)
3374                                 continue;
3375
3376                         if (stream_update->dsc_config)
3377                                 dc->link_srv->update_dsc_config(pipe_ctx);
3378
3379                         if (stream_update->mst_bw_update) {
3380                                 if (stream_update->mst_bw_update->is_increase)
3381                                         dc->link_srv->increase_mst_payload(pipe_ctx,
3382                                                         stream_update->mst_bw_update->mst_stream_bw);
3383                                 else
3384                                         dc->link_srv->reduce_mst_payload(pipe_ctx,
3385                                                         stream_update->mst_bw_update->mst_stream_bw);
3386                         }
3387
3388                         if (stream_update->pending_test_pattern) {
3389                                 /*
3390                                  * test pattern params depends on ODM topology
3391                                  * changes that we could be applying to front
3392                                  * end. Since at the current stage front end
3393                                  * changes are not yet applied. We can only
3394                                  * apply test pattern in hw based on current
3395                                  * state and populate the final test pattern
3396                                  * params in new state. If current and new test
3397                                  * pattern params are different as result of
3398                                  * different ODM topology being used, it will be
3399                                  * detected and handle during front end
3400                                  * programming update.
3401                                  */
3402                                 dc->link_srv->dp_set_test_pattern(stream->link,
3403                                         stream->test_pattern.type,
3404                                         stream->test_pattern.color_space,
3405                                         stream->test_pattern.p_link_settings,
3406                                         stream->test_pattern.p_custom_pattern,
3407                                         stream->test_pattern.cust_pattern_size);
3408                                 resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);
3409                         }
3410
3411                         if (stream_update->dpms_off) {
3412                                 if (*stream_update->dpms_off) {
3413                                         dc->link_srv->set_dpms_off(pipe_ctx);
3414                                         /* for dpms, keep acquired resources*/
3415                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
3416                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
3417
3418                                         dc->optimized_required = true;
3419
3420                                 } else {
3421                                         if (get_seamless_boot_stream_count(context) == 0)
3422                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
3423                                         dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3424                                 }
3425                         } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
3426                                         && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
3427                                 /*
3428                                  * Workaround for firmware issue in some receivers where they don't pick up
3429                                  * correct output color space unless DP link is disabled/re-enabled
3430                                  */
3431                                 dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3432                         }
3433
3434                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
3435                                 bool should_program_abm = true;
3436
3437                                 // if otg funcs defined check if blanked before programming
3438                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
3439                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
3440                                                 should_program_abm = false;
3441
3442                                 if (should_program_abm) {
3443                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
3444                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
3445                                         } else {
3446                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
3447                                                         pipe_ctx->stream_res.abm, stream->abm_level);
3448                                         }
3449                                 }
3450                         }
3451                 }
3452         }
3453 }
3454
3455 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
3456 {
3457         if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
3458                         || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
3459                         && stream->ctx->dce_version >= DCN_VERSION_3_1)
3460                 return true;
3461
3462         if (stream->link->replay_settings.config.replay_supported)
3463                 return true;
3464
3465         if (stream->ctx->dce_version >= DCN_VERSION_3_5 && stream->abm_level)
3466                 return true;
3467
3468         return false;
3469 }
3470
3471 void dc_dmub_update_dirty_rect(struct dc *dc,
3472                                int surface_count,
3473                                struct dc_stream_state *stream,
3474                                struct dc_surface_update *srf_updates,
3475                                struct dc_state *context)
3476 {
3477         union dmub_rb_cmd cmd;
3478         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3479         unsigned int i, j;
3480         unsigned int panel_inst = 0;
3481
3482         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3483                 return;
3484
3485         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3486                 return;
3487
3488         memset(&cmd, 0x0, sizeof(cmd));
3489         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3490         cmd.update_dirty_rect.header.sub_type = 0;
3491         cmd.update_dirty_rect.header.payload_bytes =
3492                 sizeof(cmd.update_dirty_rect) -
3493                 sizeof(cmd.update_dirty_rect.header);
3494         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3495         for (i = 0; i < surface_count; i++) {
3496                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3497                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3498
3499                 if (!srf_updates[i].surface || !flip_addr)
3500                         continue;
3501                 /* Do not send in immediate flip mode */
3502                 if (srf_updates[i].surface->flip_immediate)
3503                         continue;
3504
3505                 update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
3506                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3507                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3508                                 sizeof(flip_addr->dirty_rects));
3509                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3510                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3511
3512                         if (pipe_ctx->stream != stream)
3513                                 continue;
3514                         if (pipe_ctx->plane_state != plane_state)
3515                                 continue;
3516
3517                         update_dirty_rect->panel_inst = panel_inst;
3518                         update_dirty_rect->pipe_idx = j;
3519                         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
3520                 }
3521         }
3522 }
3523
3524 static void build_dmub_update_dirty_rect(
3525                 struct dc *dc,
3526                 int surface_count,
3527                 struct dc_stream_state *stream,
3528                 struct dc_surface_update *srf_updates,
3529                 struct dc_state *context,
3530                 struct dc_dmub_cmd dc_dmub_cmd[],
3531                 unsigned int *dmub_cmd_count)
3532 {
3533         union dmub_rb_cmd cmd;
3534         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3535         unsigned int i, j;
3536         unsigned int panel_inst = 0;
3537
3538         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3539                 return;
3540
3541         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3542                 return;
3543
3544         memset(&cmd, 0x0, sizeof(cmd));
3545         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3546         cmd.update_dirty_rect.header.sub_type = 0;
3547         cmd.update_dirty_rect.header.payload_bytes =
3548                 sizeof(cmd.update_dirty_rect) -
3549                 sizeof(cmd.update_dirty_rect.header);
3550         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3551         for (i = 0; i < surface_count; i++) {
3552                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3553                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3554
3555                 if (!srf_updates[i].surface || !flip_addr)
3556                         continue;
3557                 /* Do not send in immediate flip mode */
3558                 if (srf_updates[i].surface->flip_immediate)
3559                         continue;
3560                 update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
3561                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3562                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3563                                 sizeof(flip_addr->dirty_rects));
3564                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3565                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3566
3567                         if (pipe_ctx->stream != stream)
3568                                 continue;
3569                         if (pipe_ctx->plane_state != plane_state)
3570                                 continue;
3571                         update_dirty_rect->panel_inst = panel_inst;
3572                         update_dirty_rect->pipe_idx = j;
3573                         dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
3574                         dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
3575                         (*dmub_cmd_count)++;
3576                 }
3577         }
3578 }
3579
3580 static bool check_address_only_update(union surface_update_flags update_flags)
3581 {
3582         union surface_update_flags addr_only_update_flags;
3583         addr_only_update_flags.raw = 0;
3584         addr_only_update_flags.bits.addr_update = 1;
3585
3586         return update_flags.bits.addr_update &&
3587                         !(update_flags.raw & ~addr_only_update_flags.raw);
3588 }
3589
3590 /**
3591  * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
3592  *
3593  * @dc: Current DC state
3594  * @srf_updates: Array of surface updates
3595  * @surface_count: Number of surfaces that have an updated
3596  * @stream: Corresponding stream to be updated in the current flip
3597  * @context: New DC state to be programmed
3598  *
3599  * @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3600  * @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
3601  *
3602  * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
3603  * to build an array of commands and have them sent while the OTG lock is acquired.
3604  *
3605  * Return: void
3606  */
3607 static void build_dmub_cmd_list(struct dc *dc,
3608                 struct dc_surface_update *srf_updates,
3609                 int surface_count,
3610                 struct dc_stream_state *stream,
3611                 struct dc_state *context,
3612                 struct dc_dmub_cmd dc_dmub_cmd[],
3613                 unsigned int *dmub_cmd_count)
3614 {
3615         // Initialize cmd count to 0
3616         *dmub_cmd_count = 0;
3617         build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);
3618 }
3619
3620 static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc,
3621                 struct dc_surface_update *srf_updates,
3622                 int surface_count,
3623                 struct dc_stream_state *stream,
3624                 struct dc_state *context)
3625 {
3626         int i, j;
3627
3628         /* update dirty rect for PSR */
3629         dc_dmub_update_dirty_rect(dc, surface_count, stream,
3630                         srf_updates, context);
3631
3632         /* Perform requested Updates */
3633         for (i = 0; i < surface_count; i++) {
3634                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3635
3636                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3637                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3638
3639                         if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3640                                 continue;
3641
3642                         if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3643                                 continue;
3644
3645                         /* update pipe context for plane */
3646                         if (pipe_ctx->plane_state->update_flags.bits.addr_update)
3647                                 dc->hwss.update_plane_addr(dc, pipe_ctx);
3648                 }
3649         }
3650
3651         /* Send commands to DMCUB */
3652         dc_dmub_srv_fams2_passthrough_flip(dc,
3653                                 context,
3654                                 stream,
3655                                 srf_updates,
3656                                 surface_count);
3657 }
3658
3659 static void commit_planes_for_stream_fast(struct dc *dc,
3660                 struct dc_surface_update *srf_updates,
3661                 int surface_count,
3662                 struct dc_stream_state *stream,
3663                 struct dc_stream_update *stream_update,
3664                 enum surface_update_type update_type,
3665                 struct dc_state *context)
3666 {
3667         int i, j;
3668         struct pipe_ctx *top_pipe_to_program = NULL;
3669         struct dc_stream_status *stream_status = NULL;
3670         bool should_offload_fams2_flip = false;
3671
3672         if (dc->debug.fams2_config.bits.enable &&
3673                         dc->debug.fams2_config.bits.enable_offload_flip &&
3674                         dc_state_is_fams2_in_use(dc, context)) {
3675                 /* if not offloading to HWFQ, offload to FAMS2 if needed */
3676                 should_offload_fams2_flip = true;
3677                 for (i = 0; i < surface_count; i++) {
3678                         if (srf_updates[i].surface &&
3679                                         srf_updates[i].surface->update_flags.raw &&
3680                                         !check_address_only_update(srf_updates[i].surface->update_flags)) {
3681                                 /* more than address update, need to acquire FAMS2 lock */
3682                                 should_offload_fams2_flip = false;
3683                                 break;
3684                         }
3685                 }
3686                 if (stream_update) {
3687                         /* more than address update, need to acquire FAMS2 lock */
3688                         should_offload_fams2_flip = false;
3689                 }
3690         }
3691
3692         dc_exit_ips_for_hw_access(dc);
3693
3694         dc_z10_restore(dc);
3695
3696         top_pipe_to_program = resource_get_otg_master_for_stream(
3697                         &context->res_ctx,
3698                         stream);
3699
3700         if (!top_pipe_to_program)
3701                 return;
3702
3703         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3704                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3705
3706                 if (pipe->stream && pipe->plane_state) {
3707                         set_p_state_switch_method(dc, context, pipe);
3708
3709                         if (dc->debug.visual_confirm)
3710                                 dc_update_visual_confirm_color(dc, context, pipe);
3711                 }
3712         }
3713
3714         for (i = 0; i < surface_count; i++) {
3715                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3716                 /*set logical flag for lock/unlock use*/
3717                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3718                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3719
3720                         if (!pipe_ctx->plane_state)
3721                                 continue;
3722                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3723                                 continue;
3724                         pipe_ctx->plane_state->triplebuffer_flips = false;
3725                         if (update_type == UPDATE_TYPE_FAST &&
3726                             dc->hwss.program_triplebuffer != NULL &&
3727                             !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3728                                 /*triple buffer for VUpdate  only*/
3729                                 pipe_ctx->plane_state->triplebuffer_flips = true;
3730                         }
3731                 }
3732         }
3733
3734         stream_status = dc_state_get_stream_status(context, stream);
3735
3736         if (should_offload_fams2_flip) {
3737                 commit_plane_for_stream_offload_fams2_flip(dc,
3738                                 srf_updates,
3739                                 surface_count,
3740                                 stream,
3741                                 context);
3742         } else {
3743                 build_dmub_cmd_list(dc,
3744                                 srf_updates,
3745                                 surface_count,
3746                                 stream,
3747                                 context,
3748                                 context->dc_dmub_cmd,
3749                                 &(context->dmub_cmd_count));
3750                 hwss_build_fast_sequence(dc,
3751                                 context->dc_dmub_cmd,
3752                                 context->dmub_cmd_count,
3753                                 context->block_sequence,
3754                                 &(context->block_sequence_steps),
3755                                 top_pipe_to_program,
3756                                 stream_status,
3757                                 context);
3758                 hwss_execute_sequence(dc,
3759                                 context->block_sequence,
3760                                 context->block_sequence_steps);
3761         }
3762
3763         /* Clear update flags so next flip doesn't have redundant programming
3764          * (if there's no stream update, the update flags are not cleared).
3765          * Surface updates are cleared unconditionally at the beginning of each flip,
3766          * so no need to clear here.
3767          */
3768         if (top_pipe_to_program->stream)
3769                 top_pipe_to_program->stream->update_flags.raw = 0;
3770 }
3771
3772 static void wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
3773 {
3774 /*
3775  * This function calls HWSS to wait for any potentially double buffered
3776  * operations to complete. It should be invoked as a pre-amble prior
3777  * to full update programming before asserting any HW locks.
3778  */
3779         int pipe_idx;
3780         int opp_inst;
3781         int opp_count = dc->res_pool->res_cap->num_opp;
3782         struct hubp *hubp;
3783         int mpcc_inst;
3784         const struct pipe_ctx *pipe_ctx;
3785
3786         for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
3787                 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
3788
3789                 if (!pipe_ctx->stream)
3790                         continue;
3791
3792                 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
3793                         pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
3794
3795                 hubp = pipe_ctx->plane_res.hubp;
3796                 if (!hubp)
3797                         continue;
3798
3799                 mpcc_inst = hubp->inst;
3800                 // MPCC inst is equal to pipe index in practice
3801                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
3802                         if ((dc->res_pool->opps[opp_inst] != NULL) &&
3803                                 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
3804                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
3805                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
3806                                 break;
3807                         }
3808                 }
3809         }
3810         wait_for_odm_update_pending_complete(dc, dc_context);
3811 }
3812
3813 static void commit_planes_for_stream(struct dc *dc,
3814                 struct dc_surface_update *srf_updates,
3815                 int surface_count,
3816                 struct dc_stream_state *stream,
3817                 struct dc_stream_update *stream_update,
3818                 enum surface_update_type update_type,
3819                 struct dc_state *context)
3820 {
3821         int i, j;
3822         struct pipe_ctx *top_pipe_to_program = NULL;
3823         bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
3824         bool subvp_prev_use = false;
3825         bool subvp_curr_use = false;
3826         uint8_t current_stream_mask = 0;
3827
3828         // Once we apply the new subvp context to hardware it won't be in the
3829         // dc->current_state anymore, so we have to cache it before we apply
3830         // the new SubVP context
3831         subvp_prev_use = false;
3832         dc_exit_ips_for_hw_access(dc);
3833
3834         dc_z10_restore(dc);
3835         if (update_type == UPDATE_TYPE_FULL)
3836                 wait_for_outstanding_hw_updates(dc, context);
3837
3838         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3839                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3840
3841                 if (pipe->stream && pipe->plane_state) {
3842                         set_p_state_switch_method(dc, context, pipe);
3843
3844                         if (dc->debug.visual_confirm)
3845                                 dc_update_visual_confirm_color(dc, context, pipe);
3846                 }
3847         }
3848
3849         if (update_type == UPDATE_TYPE_FULL) {
3850                 dc_allow_idle_optimizations(dc, false);
3851
3852                 if (get_seamless_boot_stream_count(context) == 0)
3853                         dc->hwss.prepare_bandwidth(dc, context);
3854
3855                 if (dc->hwss.update_dsc_pg)
3856                         dc->hwss.update_dsc_pg(dc, context, false);
3857
3858                 context_clock_trace(dc, context);
3859         }
3860
3861         top_pipe_to_program = resource_get_otg_master_for_stream(
3862                                 &context->res_ctx,
3863                                 stream);
3864         ASSERT(top_pipe_to_program != NULL);
3865         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3866                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3867
3868                 // Check old context for SubVP
3869                 subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);
3870                 if (subvp_prev_use)
3871                         break;
3872         }
3873
3874         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3875                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3876
3877                 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
3878                         subvp_curr_use = true;
3879                         break;
3880                 }
3881         }
3882
3883         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
3884                 struct pipe_ctx *mpcc_pipe;
3885                 struct pipe_ctx *odm_pipe;
3886
3887                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
3888                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3889                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
3890         }
3891
3892         if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)
3893                 dc->res_pool->funcs->prepare_mcache_programming(dc, context);
3894
3895         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3896                 if (top_pipe_to_program &&
3897                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3898                         if (should_use_dmub_lock(stream->link)) {
3899                                 union dmub_hw_lock_flags hw_locks = { 0 };
3900                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3901
3902                                 hw_locks.bits.lock_dig = 1;
3903                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3904
3905                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3906                                                         true,
3907                                                         &hw_locks,
3908                                                         &inst_flags);
3909                         } else
3910                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
3911                                                 top_pipe_to_program->stream_res.tg);
3912                 }
3913
3914         if (dc->hwss.wait_for_dcc_meta_propagation) {
3915                 dc->hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program);
3916         }
3917
3918         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3919                 if (dc->hwss.subvp_pipe_control_lock)
3920                         dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
3921
3922                 if (dc->hwss.fams2_global_control_lock)
3923                         dc->hwss.fams2_global_control_lock(dc, context, true);
3924
3925                 dc->hwss.interdependent_update_lock(dc, context, true);
3926         } else {
3927                 if (dc->hwss.subvp_pipe_control_lock)
3928                         dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3929
3930                 if (dc->hwss.fams2_global_control_lock)
3931                         dc->hwss.fams2_global_control_lock(dc, context, true);
3932
3933                 /* Lock the top pipe while updating plane addrs, since freesync requires
3934                  *  plane addr update event triggers to be synchronized.
3935                  *  top_pipe_to_program is expected to never be NULL
3936                  */
3937                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
3938         }
3939
3940         dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
3941
3942         // Stream updates
3943         if (stream_update)
3944                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
3945
3946         if (surface_count == 0) {
3947                 /*
3948                  * In case of turning off screen, no need to program front end a second time.
3949                  * just return after program blank.
3950                  */
3951                 if (dc->hwss.apply_ctx_for_surface)
3952                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
3953                 if (dc->hwss.program_front_end_for_ctx)
3954                         dc->hwss.program_front_end_for_ctx(dc, context);
3955
3956                 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3957                         dc->hwss.interdependent_update_lock(dc, context, false);
3958                 } else {
3959                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3960                 }
3961                 dc->hwss.post_unlock_program_front_end(dc, context);
3962
3963                 if (update_type != UPDATE_TYPE_FAST)
3964                         if (dc->hwss.commit_subvp_config)
3965                                 dc->hwss.commit_subvp_config(dc, context);
3966
3967                 /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3968                  * move the SubVP lock to after the phantom pipes have been setup
3969                  */
3970                 if (dc->hwss.subvp_pipe_control_lock)
3971                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
3972                                                          NULL, subvp_prev_use);
3973
3974                 if (dc->hwss.fams2_global_control_lock)
3975                         dc->hwss.fams2_global_control_lock(dc, context, false);
3976
3977                 return;
3978         }
3979
3980         if (update_type != UPDATE_TYPE_FAST) {
3981                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3982                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3983
3984                         if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
3985                                 dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
3986                                 pipe_ctx->stream && pipe_ctx->plane_state) {
3987                                 /* Only update visual confirm for SUBVP and Mclk switching here.
3988                                  * The bar appears on all pipes, so we need to update the bar on all displays,
3989                                  * so the information doesn't get stale.
3990                                  */
3991                                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
3992                                                 pipe_ctx->plane_res.hubp->inst);
3993                         }
3994                 }
3995         }
3996
3997         for (i = 0; i < surface_count; i++) {
3998                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3999
4000                 /*set logical flag for lock/unlock use*/
4001                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
4002                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
4003                         if (!pipe_ctx->plane_state)
4004                                 continue;
4005                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
4006                                 continue;
4007                         pipe_ctx->plane_state->triplebuffer_flips = false;
4008                         if (update_type == UPDATE_TYPE_FAST &&
4009                                 dc->hwss.program_triplebuffer != NULL &&
4010                                 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
4011                                         /*triple buffer for VUpdate  only*/
4012                                         pipe_ctx->plane_state->triplebuffer_flips = true;
4013                         }
4014                 }
4015                 if (update_type == UPDATE_TYPE_FULL) {
4016                         /* force vsync flip when reconfiguring pipes to prevent underflow */
4017                         plane_state->flip_immediate = false;
4018                 }
4019         }
4020
4021         // Update Type FULL, Surface updates
4022         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4023                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
4024
4025                 if (!pipe_ctx->top_pipe &&
4026                         !pipe_ctx->prev_odm_pipe &&
4027                         should_update_pipe_for_stream(context, pipe_ctx, stream)) {
4028                         struct dc_stream_status *stream_status = NULL;
4029
4030                         if (!pipe_ctx->plane_state)
4031                                 continue;
4032
4033                         /* Full fe update*/
4034                         if (update_type == UPDATE_TYPE_FAST)
4035                                 continue;
4036
4037                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
4038
4039                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
4040                                 /*turn off triple buffer for full update*/
4041                                 dc->hwss.program_triplebuffer(
4042                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
4043                         }
4044                         stream_status =
4045                                 stream_get_status(context, pipe_ctx->stream);
4046
4047                         if (dc->hwss.apply_ctx_for_surface && stream_status)
4048                                 dc->hwss.apply_ctx_for_surface(
4049                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
4050                 }
4051         }
4052         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
4053                 dc->hwss.program_front_end_for_ctx(dc, context);
4054                 if (dc->debug.validate_dml_output) {
4055                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4056                                 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
4057                                 if (cur_pipe->stream == NULL)
4058                                         continue;
4059
4060                                 cur_pipe->plane_res.hubp->funcs->validate_dml_output(
4061                                                 cur_pipe->plane_res.hubp, dc->ctx,
4062                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
4063                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
4064                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
4065                         }
4066                 }
4067         }
4068
4069         // Update Type FAST, Surface updates
4070         if (update_type == UPDATE_TYPE_FAST) {
4071                 if (dc->hwss.set_flip_control_gsl)
4072                         for (i = 0; i < surface_count; i++) {
4073                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
4074
4075                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
4076                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
4077
4078                                         if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
4079                                                 continue;
4080
4081                                         if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
4082                                                 continue;
4083
4084                                         // GSL has to be used for flip immediate
4085                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
4086                                                         pipe_ctx->plane_state->flip_immediate);
4087                                 }
4088                         }
4089
4090                 /* Perform requested Updates */
4091                 for (i = 0; i < surface_count; i++) {
4092                         struct dc_plane_state *plane_state = srf_updates[i].surface;
4093
4094                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4095                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
4096
4097                                 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
4098                                         continue;
4099
4100                                 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
4101                                         continue;
4102
4103                                 if (srf_updates[i].cm2_params &&
4104                                                 srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src ==
4105                                                                 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&
4106                                                 srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting ==
4107                                                                 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&
4108                                                 dc->hwss.trigger_3dlut_dma_load)
4109                                         dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);
4110
4111                                 /*program triple buffer after lock based on flip type*/
4112                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
4113                                         /*only enable triplebuffer for  fast_update*/
4114                                         dc->hwss.program_triplebuffer(
4115                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
4116                                 }
4117                                 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
4118                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
4119                         }
4120                 }
4121         }
4122
4123         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
4124                 dc->hwss.interdependent_update_lock(dc, context, false);
4125         } else {
4126                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
4127         }
4128
4129         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
4130                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
4131                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
4132                                 top_pipe_to_program->stream_res.tg,
4133                                 CRTC_STATE_VACTIVE);
4134                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
4135                                 top_pipe_to_program->stream_res.tg,
4136                                 CRTC_STATE_VBLANK);
4137                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
4138                                 top_pipe_to_program->stream_res.tg,
4139                                 CRTC_STATE_VACTIVE);
4140
4141                         if (should_use_dmub_lock(stream->link)) {
4142                                 union dmub_hw_lock_flags hw_locks = { 0 };
4143                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4144
4145                                 hw_locks.bits.lock_dig = 1;
4146                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
4147
4148                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
4149                                                         false,
4150                                                         &hw_locks,
4151                                                         &inst_flags);
4152                         } else
4153                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
4154                                         top_pipe_to_program->stream_res.tg);
4155                 }
4156
4157         if (subvp_curr_use) {
4158                 /* If enabling subvp or transitioning from subvp->subvp, enable the
4159                  * phantom streams before we program front end for the phantom pipes.
4160                  */
4161                 if (update_type != UPDATE_TYPE_FAST) {
4162                         if (dc->hwss.enable_phantom_streams)
4163                                 dc->hwss.enable_phantom_streams(dc, context);
4164                 }
4165         }
4166
4167         if (update_type != UPDATE_TYPE_FAST)
4168                 dc->hwss.post_unlock_program_front_end(dc, context);
4169
4170         if (subvp_prev_use && !subvp_curr_use) {
4171                 /* If disabling subvp, disable phantom streams after front end
4172                  * programming has completed (we turn on phantom OTG in order
4173                  * to complete the plane disable for phantom pipes).
4174                  */
4175
4176                 if (dc->hwss.disable_phantom_streams)
4177                         dc->hwss.disable_phantom_streams(dc, context);
4178         }
4179
4180         if (update_type != UPDATE_TYPE_FAST)
4181                 if (dc->hwss.commit_subvp_config)
4182                         dc->hwss.commit_subvp_config(dc, context);
4183         /* Since phantom pipe programming is moved to post_unlock_program_front_end,
4184          * move the SubVP lock to after the phantom pipes have been setup
4185          */
4186         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
4187                 if (dc->hwss.subvp_pipe_control_lock)
4188                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
4189                 if (dc->hwss.fams2_global_control_lock)
4190                         dc->hwss.fams2_global_control_lock(dc, context, false);
4191         } else {
4192                 if (dc->hwss.subvp_pipe_control_lock)
4193                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
4194                 if (dc->hwss.fams2_global_control_lock)
4195                         dc->hwss.fams2_global_control_lock(dc, context, false);
4196         }
4197
4198         // Fire manual trigger only when bottom plane is flipped
4199         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4200                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
4201
4202                 if (!pipe_ctx->plane_state)
4203                         continue;
4204
4205                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
4206                                 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
4207                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
4208                                 pipe_ctx->plane_state->skip_manual_trigger)
4209                         continue;
4210
4211                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
4212                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
4213         }
4214
4215         current_stream_mask = get_stream_mask(dc, context);
4216         if (current_stream_mask != context->stream_mask) {
4217                 context->stream_mask = current_stream_mask;
4218                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);
4219         }
4220 }
4221
4222 /**
4223  * could_mpcc_tree_change_for_active_pipes - Check if an OPP associated with MPCC might change
4224  *
4225  * @dc: Used to get the current state status
4226  * @stream: Target stream, which we want to remove the attached planes
4227  * @srf_updates: Array of surface updates
4228  * @surface_count: Number of surface update
4229  * @is_plane_addition: [in] Fill out with true if it is a plane addition case
4230  *
4231  * DCN32x and newer support a feature named Dynamic ODM which can conflict with
4232  * the MPO if used simultaneously in some specific configurations (e.g.,
4233  * 4k@144). This function checks if the incoming context requires applying a
4234  * transition state with unnecessary pipe splitting and ODM disabled to
4235  * circumvent our hardware limitations to prevent this edge case. If the OPP
4236  * associated with an MPCC might change due to plane additions, this function
4237  * returns true.
4238  *
4239  * Return:
4240  * Return true if OPP and MPCC might change, otherwise, return false.
4241  */
4242 static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
4243                 struct dc_stream_state *stream,
4244                 struct dc_surface_update *srf_updates,
4245                 int surface_count,
4246                 bool *is_plane_addition)
4247 {
4248
4249         struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
4250         bool force_minimal_pipe_splitting = false;
4251         bool subvp_active = false;
4252         uint32_t i;
4253
4254         *is_plane_addition = false;
4255
4256         if (cur_stream_status &&
4257                         dc->current_state->stream_count > 0 &&
4258                         dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {
4259                 /* determine if minimal transition is required due to MPC*/
4260                 if (surface_count > 0) {
4261                         if (cur_stream_status->plane_count > surface_count) {
4262                                 force_minimal_pipe_splitting = true;
4263                         } else if (cur_stream_status->plane_count < surface_count) {
4264                                 force_minimal_pipe_splitting = true;
4265                                 *is_plane_addition = true;
4266                         }
4267                 }
4268         }
4269
4270         if (cur_stream_status &&
4271                         dc->current_state->stream_count == 1 &&
4272                         dc->debug.enable_single_display_2to1_odm_policy) {
4273                 /* determine if minimal transition is required due to dynamic ODM*/
4274                 if (surface_count > 0) {
4275                         if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) {
4276                                 force_minimal_pipe_splitting = true;
4277                         } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) {
4278                                 force_minimal_pipe_splitting = true;
4279                                 *is_plane_addition = true;
4280                         }
4281                 }
4282         }
4283
4284         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4285                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4286
4287                 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_NONE) {
4288                         subvp_active = true;
4289                         break;
4290                 }
4291         }
4292
4293         /* For SubVP when adding or removing planes we need to add a minimal transition
4294          * (even when disabling all planes). Whenever disabling a phantom pipe, we
4295          * must use the minimal transition path to disable the pipe correctly.
4296          *
4297          * We want to use the minimal transition whenever subvp is active, not only if
4298          * a plane is being added / removed from a subvp stream (MPO plane can be added
4299          * to a DRR pipe of SubVP + DRR config, in which case we still want to run through
4300          * a min transition to disable subvp.
4301          */
4302         if (cur_stream_status && subvp_active) {
4303                 /* determine if minimal transition is required due to SubVP*/
4304                 if (cur_stream_status->plane_count > surface_count) {
4305                         force_minimal_pipe_splitting = true;
4306                 } else if (cur_stream_status->plane_count < surface_count) {
4307                         force_minimal_pipe_splitting = true;
4308                         *is_plane_addition = true;
4309                 }
4310         }
4311
4312         return force_minimal_pipe_splitting;
4313 }
4314
4315 struct pipe_split_policy_backup {
4316         bool dynamic_odm_policy;
4317         bool subvp_policy;
4318         enum pipe_split_policy mpc_policy;
4319         char force_odm[MAX_PIPES];
4320 };
4321
4322 static void backup_and_set_minimal_pipe_split_policy(struct dc *dc,
4323                 struct dc_state *context,
4324                 struct pipe_split_policy_backup *policy)
4325 {
4326         int i;
4327
4328         if (!dc->config.is_vmin_only_asic) {
4329                 policy->mpc_policy = dc->debug.pipe_split_policy;
4330                 dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
4331         }
4332         policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;
4333         dc->debug.enable_single_display_2to1_odm_policy = false;
4334         policy->subvp_policy = dc->debug.force_disable_subvp;
4335         dc->debug.force_disable_subvp = true;
4336         for (i = 0; i < context->stream_count; i++) {
4337                 policy->force_odm[i] = context->streams[i]->debug.force_odm_combine_segments;
4338                 context->streams[i]->debug.force_odm_combine_segments = 0;
4339         }
4340 }
4341
4342 static void restore_minimal_pipe_split_policy(struct dc *dc,
4343                 struct dc_state *context,
4344                 struct pipe_split_policy_backup *policy)
4345 {
4346         uint8_t i;
4347
4348         if (!dc->config.is_vmin_only_asic)
4349                 dc->debug.pipe_split_policy = policy->mpc_policy;
4350         dc->debug.enable_single_display_2to1_odm_policy =
4351                         policy->dynamic_odm_policy;
4352         dc->debug.force_disable_subvp = policy->subvp_policy;
4353         for (i = 0; i < context->stream_count; i++)
4354                 context->streams[i]->debug.force_odm_combine_segments = policy->force_odm[i];
4355 }
4356
4357 static void release_minimal_transition_state(struct dc *dc,
4358                 struct dc_state *minimal_transition_context,
4359                 struct dc_state *base_context,
4360                 struct pipe_split_policy_backup *policy)
4361 {
4362         restore_minimal_pipe_split_policy(dc, base_context, policy);
4363         dc_state_release(minimal_transition_context);
4364 }
4365
4366 static void force_vsync_flip_in_minimal_transition_context(struct dc_state *context)
4367 {
4368         uint8_t i;
4369         int j;
4370         struct dc_stream_status *stream_status;
4371
4372         for (i = 0; i < context->stream_count; i++) {
4373                 stream_status = &context->stream_status[i];
4374
4375                 for (j = 0; j < stream_status->plane_count; j++)
4376                         stream_status->plane_states[j]->flip_immediate = false;
4377         }
4378 }
4379
4380 static struct dc_state *create_minimal_transition_state(struct dc *dc,
4381                 struct dc_state *base_context, struct pipe_split_policy_backup *policy)
4382 {
4383         struct dc_state *minimal_transition_context = NULL;
4384
4385         minimal_transition_context = dc_state_create_copy(base_context);
4386         if (!minimal_transition_context)
4387                 return NULL;
4388
4389         backup_and_set_minimal_pipe_split_policy(dc, base_context, policy);
4390         /* commit minimal state */
4391         if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context, false)) {
4392                 /* prevent underflow and corruption when reconfiguring pipes */
4393                 force_vsync_flip_in_minimal_transition_context(minimal_transition_context);
4394         } else {
4395                 /*
4396                  * This should never happen, minimal transition state should
4397                  * always be validated first before adding pipe split features.
4398                  */
4399                 release_minimal_transition_state(dc, minimal_transition_context, base_context, policy);
4400                 BREAK_TO_DEBUGGER();
4401                 minimal_transition_context = NULL;
4402         }
4403         return minimal_transition_context;
4404 }
4405
4406 static bool is_pipe_topology_transition_seamless_with_intermediate_step(
4407                 struct dc *dc,
4408                 struct dc_state *initial_state,
4409                 struct dc_state *intermediate_state,
4410                 struct dc_state *final_state)
4411 {
4412         return dc->hwss.is_pipe_topology_transition_seamless(dc, initial_state,
4413                         intermediate_state) &&
4414                         dc->hwss.is_pipe_topology_transition_seamless(dc,
4415                                         intermediate_state, final_state);
4416 }
4417
4418 static void swap_and_release_current_context(struct dc *dc,
4419                 struct dc_state *new_context, struct dc_stream_state *stream)
4420 {
4421
4422         int i;
4423         struct dc_state *old = dc->current_state;
4424         struct pipe_ctx *pipe_ctx;
4425
4426         /* Since memory free requires elevated IRQ, an interrupt
4427          * request is generated by mem free. If this happens
4428          * between freeing and reassigning the context, our vsync
4429          * interrupt will call into dc and cause a memory
4430          * corruption. Hence, we first reassign the context,
4431          * then free the old context.
4432          */
4433         dc->current_state = new_context;
4434         dc_state_release(old);
4435
4436         // clear any forced full updates
4437         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4438                 pipe_ctx = &new_context->res_ctx.pipe_ctx[i];
4439
4440                 if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4441                         pipe_ctx->plane_state->force_full_update = false;
4442         }
4443 }
4444
4445 static int initialize_empty_surface_updates(
4446                 struct dc_stream_state *stream,
4447                 struct dc_surface_update *srf_updates)
4448 {
4449         struct dc_stream_status *status = dc_stream_get_status(stream);
4450         int i;
4451
4452         if (!status)
4453                 return 0;
4454
4455         for (i = 0; i < status->plane_count; i++)
4456                 srf_updates[i].surface = status->plane_states[i];
4457
4458         return status->plane_count;
4459 }
4460
4461 static bool commit_minimal_transition_based_on_new_context(struct dc *dc,
4462                 struct dc_state *new_context,
4463                 struct dc_stream_state *stream,
4464                 struct dc_surface_update *srf_updates,
4465                 int surface_count)
4466 {
4467         bool success = false;
4468         struct pipe_split_policy_backup policy;
4469         struct dc_state *intermediate_context =
4470                         create_minimal_transition_state(dc, new_context,
4471                                         &policy);
4472
4473         if (intermediate_context) {
4474                 if (is_pipe_topology_transition_seamless_with_intermediate_step(
4475                                 dc,
4476                                 dc->current_state,
4477                                 intermediate_context,
4478                                 new_context)) {
4479                         DC_LOG_DC("commit minimal transition state: base = new state\n");
4480                         commit_planes_for_stream(dc, srf_updates,
4481                                         surface_count, stream, NULL,
4482                                         UPDATE_TYPE_FULL, intermediate_context);
4483                         swap_and_release_current_context(
4484                                         dc, intermediate_context, stream);
4485                         dc_state_retain(dc->current_state);
4486                         success = true;
4487                 }
4488                 release_minimal_transition_state(
4489                                 dc, intermediate_context, new_context, &policy);
4490         }
4491         return success;
4492 }
4493
4494 static bool commit_minimal_transition_based_on_current_context(struct dc *dc,
4495                 struct dc_state *new_context, struct dc_stream_state *stream)
4496 {
4497         bool success = false;
4498         struct pipe_split_policy_backup policy;
4499         struct dc_state *intermediate_context;
4500         struct dc_state *old_current_state = dc->current_state;
4501         struct dc_surface_update srf_updates[MAX_SURFACE_NUM] = {0};
4502         int surface_count;
4503
4504         /*
4505          * Both current and new contexts share the same stream and plane state
4506          * pointers. When new context is validated, stream and planes get
4507          * populated with new updates such as new plane addresses. This makes
4508          * the current context no longer valid because stream and planes are
4509          * modified from the original. We backup current stream and plane states
4510          * into scratch space whenever we are populating new context. So we can
4511          * restore the original values back by calling the restore function now.
4512          * This restores back the original stream and plane states associated
4513          * with the current state.
4514          */
4515         restore_planes_and_stream_state(&dc->scratch.current_state, stream);
4516         dc_state_retain(old_current_state);
4517         intermediate_context = create_minimal_transition_state(dc,
4518                         old_current_state, &policy);
4519
4520         if (intermediate_context) {
4521                 if (is_pipe_topology_transition_seamless_with_intermediate_step(
4522                                 dc,
4523                                 dc->current_state,
4524                                 intermediate_context,
4525                                 new_context)) {
4526                         DC_LOG_DC("commit minimal transition state: base = current state\n");
4527                         surface_count = initialize_empty_surface_updates(
4528                                         stream, srf_updates);
4529                         commit_planes_for_stream(dc, srf_updates,
4530                                         surface_count, stream, NULL,
4531                                         UPDATE_TYPE_FULL, intermediate_context);
4532                         swap_and_release_current_context(
4533                                         dc, intermediate_context, stream);
4534                         dc_state_retain(dc->current_state);
4535                         success = true;
4536                 }
4537                 release_minimal_transition_state(dc, intermediate_context,
4538                                 old_current_state, &policy);
4539         }
4540         dc_state_release(old_current_state);
4541         /*
4542          * Restore stream and plane states back to the values associated with
4543          * new context.
4544          */
4545         restore_planes_and_stream_state(&dc->scratch.new_state, stream);
4546         return success;
4547 }
4548
4549 /**
4550  * commit_minimal_transition_state_in_dc_update - Commit a minimal state based
4551  * on current or new context
4552  *
4553  * @dc: DC structure, used to get the current state
4554  * @new_context: New context
4555  * @stream: Stream getting the update for the flip
4556  * @srf_updates: Surface updates
4557  * @surface_count: Number of surfaces
4558  *
4559  * The function takes in current state and new state and determine a minimal
4560  * transition state as the intermediate step which could make the transition
4561  * between current and new states seamless. If found, it will commit the minimal
4562  * transition state and update current state to this minimal transition state
4563  * and return true, if not, it will return false.
4564  *
4565  * Return:
4566  * Return True if the minimal transition succeeded, false otherwise
4567  */
4568 static bool commit_minimal_transition_state_in_dc_update(struct dc *dc,
4569                 struct dc_state *new_context,
4570                 struct dc_stream_state *stream,
4571                 struct dc_surface_update *srf_updates,
4572                 int surface_count)
4573 {
4574         bool success = commit_minimal_transition_based_on_new_context(
4575                                 dc, new_context, stream, srf_updates,
4576                                 surface_count);
4577         if (!success)
4578                 success = commit_minimal_transition_based_on_current_context(dc,
4579                                 new_context, stream);
4580         if (!success)
4581                 DC_LOG_ERROR("Fail to commit a seamless minimal transition state between current and new states.\nThis pipe topology update is non-seamless!\n");
4582         return success;
4583 }
4584
4585 /**
4586  * commit_minimal_transition_state - Create a transition pipe split state
4587  *
4588  * @dc: Used to get the current state status
4589  * @transition_base_context: New transition state
4590  *
4591  * In some specific configurations, such as pipe split on multi-display with
4592  * MPO and/or Dynamic ODM, removing a plane may cause unsupported pipe
4593  * programming when moving to new planes. To mitigate those types of problems,
4594  * this function adds a transition state that minimizes pipe usage before
4595  * programming the new configuration. When adding a new plane, the current
4596  * state requires the least pipes, so it is applied without splitting. When
4597  * removing a plane, the new state requires the least pipes, so it is applied
4598  * without splitting.
4599  *
4600  * Return:
4601  * Return false if something is wrong in the transition state.
4602  */
4603 static bool commit_minimal_transition_state(struct dc *dc,
4604                 struct dc_state *transition_base_context)
4605 {
4606         struct dc_state *transition_context;
4607         struct pipe_split_policy_backup policy;
4608         enum dc_status ret = DC_ERROR_UNEXPECTED;
4609         unsigned int i, j;
4610         unsigned int pipe_in_use = 0;
4611         bool subvp_in_use = false;
4612         bool odm_in_use = false;
4613
4614         /* check current pipes in use*/
4615         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4616                 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4617
4618                 if (pipe->plane_state)
4619                         pipe_in_use++;
4620         }
4621
4622         /* If SubVP is enabled and we are adding or removing planes from any main subvp
4623          * pipe, we must use the minimal transition.
4624          */
4625         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4626                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4627
4628                 if (pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {
4629                         subvp_in_use = true;
4630                         break;
4631                 }
4632         }
4633
4634         /* If ODM is enabled and we are adding or removing planes from any ODM
4635          * pipe, we must use the minimal transition.
4636          */
4637         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4638                 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4639
4640                 if (resource_is_pipe_type(pipe, OTG_MASTER)) {
4641                         odm_in_use = resource_get_odm_slice_count(pipe) > 1;
4642                         break;
4643                 }
4644         }
4645
4646         /* When the OS add a new surface if we have been used all of pipes with odm combine
4647          * and mpc split feature, it need use commit_minimal_transition_state to transition safely.
4648          * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need
4649          * call it again. Otherwise return true to skip.
4650          *
4651          * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially
4652          * enter/exit MPO when DCN still have enough resources.
4653          */
4654         if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use)
4655                 return true;
4656
4657         DC_LOG_DC("%s base = %s state, reason = %s\n", __func__,
4658                         dc->current_state == transition_base_context ? "current" : "new",
4659                         subvp_in_use ? "Subvp In Use" :
4660                         odm_in_use ? "ODM in Use" :
4661                         dc->debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC in Use" :
4662                         "Unknown");
4663
4664         dc_state_retain(transition_base_context);
4665         transition_context = create_minimal_transition_state(dc,
4666                         transition_base_context, &policy);
4667         if (transition_context) {
4668                 ret = dc_commit_state_no_check(dc, transition_context);
4669                 release_minimal_transition_state(dc, transition_context, transition_base_context, &policy);
4670         }
4671         dc_state_release(transition_base_context);
4672
4673         if (ret != DC_OK) {
4674                 /* this should never happen */
4675                 BREAK_TO_DEBUGGER();
4676                 return false;
4677         }
4678
4679         /* force full surface update */
4680         for (i = 0; i < dc->current_state->stream_count; i++) {
4681                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
4682                         dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;
4683                 }
4684         }
4685
4686         return true;
4687 }
4688
4689 static void populate_fast_updates(struct dc_fast_update *fast_update,
4690                 struct dc_surface_update *srf_updates,
4691                 int surface_count,
4692                 struct dc_stream_update *stream_update)
4693 {
4694         int i = 0;
4695
4696         if (stream_update) {
4697                 fast_update[0].out_transfer_func = stream_update->out_transfer_func;
4698                 fast_update[0].output_csc_transform = stream_update->output_csc_transform;
4699         }
4700
4701         for (i = 0; i < surface_count; i++) {
4702                 fast_update[i].flip_addr = srf_updates[i].flip_addr;
4703                 fast_update[i].gamma = srf_updates[i].gamma;
4704                 fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
4705                 fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
4706                 fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
4707                 fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix;
4708         }
4709 }
4710
4711 static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count)
4712 {
4713         int i;
4714
4715         if (fast_update[0].out_transfer_func ||
4716                 fast_update[0].output_csc_transform)
4717                 return true;
4718
4719         for (i = 0; i < surface_count; i++) {
4720                 if (fast_update[i].flip_addr ||
4721                                 fast_update[i].gamma ||
4722                                 fast_update[i].gamut_remap_matrix ||
4723                                 fast_update[i].input_csc_color_matrix ||
4724                                 fast_update[i].cursor_csc_color_matrix ||
4725                                 fast_update[i].coeff_reduction_factor)
4726                         return true;
4727         }
4728
4729         return false;
4730 }
4731
4732 static bool full_update_required(struct dc *dc,
4733                 struct dc_surface_update *srf_updates,
4734                 int surface_count,
4735                 struct dc_stream_update *stream_update,
4736                 struct dc_stream_state *stream)
4737 {
4738
4739         int i;
4740         struct dc_stream_status *stream_status;
4741         const struct dc_state *context = dc->current_state;
4742
4743         for (i = 0; i < surface_count; i++) {
4744                 if (srf_updates &&
4745                                 (srf_updates[i].plane_info ||
4746                                 srf_updates[i].scaling_info ||
4747                                 (srf_updates[i].hdr_mult.value &&
4748                                 srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
4749                                 srf_updates[i].in_transfer_func ||
4750                                 srf_updates[i].func_shaper ||
4751                                 srf_updates[i].lut3d_func ||
4752                                 srf_updates[i].surface->force_full_update ||
4753                                 (srf_updates[i].flip_addr &&
4754                                 srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) ||
4755                                 (srf_updates[i].cm2_params &&
4756                                  (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting ||
4757                                   srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)) ||
4758                                 !is_surface_in_context(context, srf_updates[i].surface)))
4759                         return true;
4760         }
4761
4762         if (stream_update &&
4763                         (((stream_update->src.height != 0 && stream_update->src.width != 0) ||
4764                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
4765                         stream_update->integer_scaling_update) ||
4766                         stream_update->hdr_static_metadata ||
4767                         stream_update->abm_level ||
4768                         stream_update->periodic_interrupt ||
4769                         stream_update->vrr_infopacket ||
4770                         stream_update->vsc_infopacket ||
4771                         stream_update->vsp_infopacket ||
4772                         stream_update->hfvsif_infopacket ||
4773                         stream_update->vtem_infopacket ||
4774                         stream_update->adaptive_sync_infopacket ||
4775                         stream_update->dpms_off ||
4776                         stream_update->allow_freesync ||
4777                         stream_update->vrr_active_variable ||
4778                         stream_update->vrr_active_fixed ||
4779                         stream_update->gamut_remap ||
4780                         stream_update->output_color_space ||
4781                         stream_update->dither_option ||
4782                         stream_update->wb_update ||
4783                         stream_update->dsc_config ||
4784                         stream_update->mst_bw_update ||
4785                         stream_update->func_shaper ||
4786                         stream_update->lut3d_func ||
4787                         stream_update->pending_test_pattern ||
4788                         stream_update->crtc_timing_adjust))
4789                 return true;
4790
4791         if (stream) {
4792                 stream_status = dc_stream_get_status(stream);
4793                 if (stream_status == NULL || stream_status->plane_count != surface_count)
4794                         return true;
4795         }
4796         if (dc->idle_optimizations_allowed)
4797                 return true;
4798
4799         return false;
4800 }
4801
4802 static bool fast_update_only(struct dc *dc,
4803                 struct dc_fast_update *fast_update,
4804                 struct dc_surface_update *srf_updates,
4805                 int surface_count,
4806                 struct dc_stream_update *stream_update,
4807                 struct dc_stream_state *stream)
4808 {
4809         return fast_updates_exist(fast_update, surface_count)
4810                         && !full_update_required(dc, srf_updates, surface_count, stream_update, stream);
4811 }
4812
4813 static bool update_planes_and_stream_v1(struct dc *dc,
4814                 struct dc_surface_update *srf_updates, int surface_count,
4815                 struct dc_stream_state *stream,
4816                 struct dc_stream_update *stream_update,
4817                 struct dc_state *state)
4818 {
4819         const struct dc_stream_status *stream_status;
4820         enum surface_update_type update_type;
4821         struct dc_state *context;
4822         struct dc_context *dc_ctx = dc->ctx;
4823         int i, j;
4824         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4825
4826         dc_exit_ips_for_hw_access(dc);
4827
4828         populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4829         stream_status = dc_stream_get_status(stream);
4830         context = dc->current_state;
4831
4832         update_type = dc_check_update_surfaces_for_stream(
4833                                 dc, srf_updates, surface_count, stream_update, stream_status);
4834
4835         if (update_type >= UPDATE_TYPE_FULL) {
4836
4837                 /* initialize scratch memory for building context */
4838                 context = dc_state_create_copy(state);
4839                 if (context == NULL) {
4840                         DC_ERROR("Failed to allocate new validate context!\n");
4841                         return false;
4842                 }
4843
4844                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4845                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
4846                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4847
4848                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
4849                                 new_pipe->plane_state->force_full_update = true;
4850                 }
4851         } else if (update_type == UPDATE_TYPE_FAST) {
4852                 /*
4853                  * Previous frame finished and HW is ready for optimization.
4854                  */
4855                 dc_post_update_surfaces_to_stream(dc);
4856         }
4857
4858         for (i = 0; i < surface_count; i++) {
4859                 struct dc_plane_state *surface = srf_updates[i].surface;
4860
4861                 copy_surface_update_to_plane(surface, &srf_updates[i]);
4862
4863                 if (update_type >= UPDATE_TYPE_MED) {
4864                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4865                                 struct pipe_ctx *pipe_ctx =
4866                                         &context->res_ctx.pipe_ctx[j];
4867
4868                                 if (pipe_ctx->plane_state != surface)
4869                                         continue;
4870
4871                                 resource_build_scaling_params(pipe_ctx);
4872                         }
4873                 }
4874         }
4875
4876         copy_stream_update_to_stream(dc, context, stream, stream_update);
4877
4878         if (update_type >= UPDATE_TYPE_FULL) {
4879                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
4880                         DC_ERROR("Mode validation failed for stream update!\n");
4881                         dc_state_release(context);
4882                         return false;
4883                 }
4884         }
4885
4886         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
4887
4888         if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) &&
4889                         !dc->debug.enable_legacy_fast_update) {
4890                 commit_planes_for_stream_fast(dc,
4891                                 srf_updates,
4892                                 surface_count,
4893                                 stream,
4894                                 stream_update,
4895                                 update_type,
4896                                 context);
4897         } else {
4898                 commit_planes_for_stream(
4899                                 dc,
4900                                 srf_updates,
4901                                 surface_count,
4902                                 stream,
4903                                 stream_update,
4904                                 update_type,
4905                                 context);
4906         }
4907         /*update current_State*/
4908         if (dc->current_state != context) {
4909
4910                 struct dc_state *old = dc->current_state;
4911
4912                 dc->current_state = context;
4913                 dc_state_release(old);
4914
4915                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4916                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4917
4918                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4919                                 pipe_ctx->plane_state->force_full_update = false;
4920                 }
4921         }
4922
4923         /* Legacy optimization path for DCE. */
4924         if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
4925                 dc_post_update_surfaces_to_stream(dc);
4926                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
4927         }
4928         return true;
4929 }
4930
4931 static bool update_planes_and_stream_v2(struct dc *dc,
4932                 struct dc_surface_update *srf_updates, int surface_count,
4933                 struct dc_stream_state *stream,
4934                 struct dc_stream_update *stream_update)
4935 {
4936         struct dc_state *context;
4937         enum surface_update_type update_type;
4938         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4939
4940         /* In cases where MPO and split or ODM are used transitions can
4941          * cause underflow. Apply stream configuration with minimal pipe
4942          * split first to avoid unsupported transitions for active pipes.
4943          */
4944         bool force_minimal_pipe_splitting = 0;
4945         bool is_plane_addition = 0;
4946         bool is_fast_update_only;
4947
4948         populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4949         is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,
4950                         surface_count, stream_update, stream);
4951         force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
4952                         dc,
4953                         stream,
4954                         srf_updates,
4955                         surface_count,
4956                         &is_plane_addition);
4957
4958         /* on plane addition, minimal state is the current one */
4959         if (force_minimal_pipe_splitting && is_plane_addition &&
4960                 !commit_minimal_transition_state(dc, dc->current_state))
4961                 return false;
4962
4963         if (!update_planes_and_stream_state(
4964                         dc,
4965                         srf_updates,
4966                         surface_count,
4967                         stream,
4968                         stream_update,
4969                         &update_type,
4970                         &context))
4971                 return false;
4972
4973         /* on plane removal, minimal state is the new one */
4974         if (force_minimal_pipe_splitting && !is_plane_addition) {
4975                 if (!commit_minimal_transition_state(dc, context)) {
4976                         dc_state_release(context);
4977                         return false;
4978                 }
4979                 update_type = UPDATE_TYPE_FULL;
4980         }
4981
4982         if (dc->hwss.is_pipe_topology_transition_seamless &&
4983                         !dc->hwss.is_pipe_topology_transition_seamless(
4984                                         dc, dc->current_state, context))
4985                 commit_minimal_transition_state_in_dc_update(dc, context, stream,
4986                                 srf_updates, surface_count);
4987
4988         if (is_fast_update_only && !dc->debug.enable_legacy_fast_update) {
4989                 commit_planes_for_stream_fast(dc,
4990                                 srf_updates,
4991                                 surface_count,
4992                                 stream,
4993                                 stream_update,
4994                                 update_type,
4995                                 context);
4996         } else {
4997                 if (!stream_update &&
4998                                 dc->hwss.is_pipe_topology_transition_seamless &&
4999                                 !dc->hwss.is_pipe_topology_transition_seamless(
5000                                                 dc, dc->current_state, context)) {
5001                         DC_LOG_ERROR("performing non-seamless pipe topology transition with surface only update!\n");
5002                         BREAK_TO_DEBUGGER();
5003                 }
5004                 commit_planes_for_stream(
5005                                 dc,
5006                                 srf_updates,
5007                                 surface_count,
5008                                 stream,
5009                                 stream_update,
5010                                 update_type,
5011                                 context);
5012         }
5013         if (dc->current_state != context)
5014                 swap_and_release_current_context(dc, context, stream);
5015         return true;
5016 }
5017
5018 static void commit_planes_and_stream_update_on_current_context(struct dc *dc,
5019                 struct dc_surface_update *srf_updates, int surface_count,
5020                 struct dc_stream_state *stream,
5021                 struct dc_stream_update *stream_update,
5022                 enum surface_update_type update_type)
5023 {
5024         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
5025
5026         ASSERT(update_type < UPDATE_TYPE_FULL);
5027         populate_fast_updates(fast_update, srf_updates, surface_count,
5028                         stream_update);
5029         if (fast_update_only(dc, fast_update, srf_updates, surface_count,
5030                         stream_update, stream) &&
5031                         !dc->debug.enable_legacy_fast_update)
5032                 commit_planes_for_stream_fast(dc,
5033                                 srf_updates,
5034                                 surface_count,
5035                                 stream,
5036                                 stream_update,
5037                                 update_type,
5038                                 dc->current_state);
5039         else
5040                 commit_planes_for_stream(
5041                                 dc,
5042                                 srf_updates,
5043                                 surface_count,
5044                                 stream,
5045                                 stream_update,
5046                                 update_type,
5047                                 dc->current_state);
5048 }
5049
5050 static void commit_planes_and_stream_update_with_new_context(struct dc *dc,
5051                 struct dc_surface_update *srf_updates, int surface_count,
5052                 struct dc_stream_state *stream,
5053                 struct dc_stream_update *stream_update,
5054                 enum surface_update_type update_type,
5055                 struct dc_state *new_context)
5056 {
5057         ASSERT(update_type >= UPDATE_TYPE_FULL);
5058         if (!dc->hwss.is_pipe_topology_transition_seamless(dc,
5059                         dc->current_state, new_context))
5060                 /*
5061                  * It is required by the feature design that all pipe topologies
5062                  * using extra free pipes for power saving purposes such as
5063                  * dynamic ODM or SubVp shall only be enabled when it can be
5064                  * transitioned seamlessly to AND from its minimal transition
5065                  * state. A minimal transition state is defined as the same dc
5066                  * state but with all power saving features disabled. So it uses
5067                  * the minimum pipe topology. When we can't seamlessly
5068                  * transition from state A to state B, we will insert the
5069                  * minimal transition state A' or B' in between so seamless
5070                  * transition between A and B can be made possible.
5071                  */
5072                 commit_minimal_transition_state_in_dc_update(dc, new_context,
5073                                 stream, srf_updates, surface_count);
5074
5075         commit_planes_for_stream(
5076                         dc,
5077                         srf_updates,
5078                         surface_count,
5079                         stream,
5080                         stream_update,
5081                         update_type,
5082                         new_context);
5083 }
5084
5085 static bool update_planes_and_stream_v3(struct dc *dc,
5086                 struct dc_surface_update *srf_updates, int surface_count,
5087                 struct dc_stream_state *stream,
5088                 struct dc_stream_update *stream_update)
5089 {
5090         struct dc_state *new_context;
5091         enum surface_update_type update_type;
5092
5093         /*
5094          * When this function returns true and new_context is not equal to
5095          * current state, the function allocates and validates a new dc state
5096          * and assigns it to new_context. The function expects that the caller
5097          * is responsible to free this memory when new_context is no longer
5098          * used. We swap current with new context and free current instead. So
5099          * new_context's memory will live until the next full update after it is
5100          * replaced by a newer context. Refer to the use of
5101          * swap_and_free_current_context below.
5102          */
5103         if (!update_planes_and_stream_state(dc, srf_updates, surface_count,
5104                                 stream, stream_update, &update_type,
5105                                 &new_context))
5106                 return false;
5107
5108         if (new_context == dc->current_state) {
5109                 commit_planes_and_stream_update_on_current_context(dc,
5110                                 srf_updates, surface_count, stream,
5111                                 stream_update, update_type);
5112         } else {
5113                 commit_planes_and_stream_update_with_new_context(dc,
5114                                 srf_updates, surface_count, stream,
5115                                 stream_update, update_type, new_context);
5116                 swap_and_release_current_context(dc, new_context, stream);
5117         }
5118
5119         return true;
5120 }
5121
5122 bool dc_update_planes_and_stream(struct dc *dc,
5123                 struct dc_surface_update *srf_updates, int surface_count,
5124                 struct dc_stream_state *stream,
5125                 struct dc_stream_update *stream_update)
5126 {
5127         dc_exit_ips_for_hw_access(dc);
5128         /*
5129          * update planes and stream version 3 separates FULL and FAST updates
5130          * to their own sequences. It aims to clean up frequent checks for
5131          * update type resulting unnecessary branching in logic flow. It also
5132          * adds a new commit minimal transition sequence, which detects the need
5133          * for minimal transition based on the actual comparison of current and
5134          * new states instead of "predicting" it based on per feature software
5135          * policy.i.e could_mpcc_tree_change_for_active_pipes. The new commit
5136          * minimal transition sequence is made universal to any power saving
5137          * features that would use extra free pipes such as Dynamic ODM/MPC
5138          * Combine, MPO or SubVp. Therefore there is no longer a need to
5139          * specially handle compatibility problems with transitions among those
5140          * features as they are now transparent to the new sequence.
5141          */
5142         if (dc->ctx->dce_version >= DCN_VERSION_4_01)
5143                 return update_planes_and_stream_v3(dc, srf_updates,
5144                                 surface_count, stream, stream_update);
5145         return update_planes_and_stream_v2(dc, srf_updates,
5146                         surface_count, stream, stream_update);
5147 }
5148
5149 void dc_commit_updates_for_stream(struct dc *dc,
5150                 struct dc_surface_update *srf_updates,
5151                 int surface_count,
5152                 struct dc_stream_state *stream,
5153                 struct dc_stream_update *stream_update,
5154                 struct dc_state *state)
5155 {
5156         dc_exit_ips_for_hw_access(dc);
5157         /* TODO: Since change commit sequence can have a huge impact,
5158          * we decided to only enable it for DCN3x. However, as soon as
5159          * we get more confident about this change we'll need to enable
5160          * the new sequence for all ASICs.
5161          */
5162         if (dc->ctx->dce_version >= DCN_VERSION_4_01) {
5163                 update_planes_and_stream_v3(dc, srf_updates, surface_count,
5164                                 stream, stream_update);
5165                 return;
5166         }
5167         if (dc->ctx->dce_version >= DCN_VERSION_3_2) {
5168                 update_planes_and_stream_v2(dc, srf_updates, surface_count,
5169                                 stream, stream_update);
5170                 return;
5171         }
5172         update_planes_and_stream_v1(dc, srf_updates, surface_count, stream,
5173                         stream_update, state);
5174 }
5175
5176 uint8_t dc_get_current_stream_count(struct dc *dc)
5177 {
5178         return dc->current_state->stream_count;
5179 }
5180
5181 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
5182 {
5183         if (i < dc->current_state->stream_count)
5184                 return dc->current_state->streams[i];
5185         return NULL;
5186 }
5187
5188 enum dc_irq_source dc_interrupt_to_irq_source(
5189                 struct dc *dc,
5190                 uint32_t src_id,
5191                 uint32_t ext_id)
5192 {
5193         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
5194 }
5195
5196 /*
5197  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
5198  */
5199 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
5200 {
5201
5202         if (dc == NULL)
5203                 return false;
5204
5205         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
5206 }
5207
5208 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
5209 {
5210         dal_irq_service_ack(dc->res_pool->irqs, src);
5211 }
5212
5213 void dc_power_down_on_boot(struct dc *dc)
5214 {
5215         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
5216             dc->hwss.power_down_on_boot) {
5217                 if (dc->caps.ips_support)
5218                         dc_exit_ips_for_hw_access(dc);
5219                 dc->hwss.power_down_on_boot(dc);
5220         }
5221 }
5222
5223 void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)
5224 {
5225         if (!dc->current_state)
5226                 return;
5227
5228         switch (power_state) {
5229         case DC_ACPI_CM_POWER_STATE_D0:
5230                 dc_state_construct(dc, dc->current_state);
5231
5232                 dc_exit_ips_for_hw_access(dc);
5233
5234                 dc_z10_restore(dc);
5235
5236                 dc->hwss.init_hw(dc);
5237
5238                 if (dc->hwss.init_sys_ctx != NULL &&
5239                         dc->vm_pa_config.valid) {
5240                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
5241                 }
5242
5243                 break;
5244         default:
5245                 ASSERT(dc->current_state->stream_count == 0);
5246
5247                 dc_state_destruct(dc->current_state);
5248
5249                 break;
5250         }
5251 }
5252
5253 void dc_resume(struct dc *dc)
5254 {
5255         uint32_t i;
5256
5257         for (i = 0; i < dc->link_count; i++)
5258                 dc->link_srv->resume(dc->links[i]);
5259 }
5260
5261 bool dc_is_dmcu_initialized(struct dc *dc)
5262 {
5263         struct dmcu *dmcu = dc->res_pool->dmcu;
5264
5265         if (dmcu)
5266                 return dmcu->funcs->is_dmcu_initialized(dmcu);
5267         return false;
5268 }
5269
5270 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
5271 {
5272         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
5273         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
5274         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
5275         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
5276         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
5277         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
5278         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
5279         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
5280         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
5281 }
5282 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
5283 {
5284         if (dc->hwss.set_clock)
5285                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
5286         return DC_ERROR_UNEXPECTED;
5287 }
5288 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
5289 {
5290         if (dc->hwss.get_clock)
5291                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
5292 }
5293
5294 /* enable/disable eDP PSR without specify stream for eDP */
5295 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
5296 {
5297         int i;
5298         bool allow_active;
5299
5300         for (i = 0; i < dc->current_state->stream_count ; i++) {
5301                 struct dc_link *link;
5302                 struct dc_stream_state *stream = dc->current_state->streams[i];
5303
5304                 link = stream->link;
5305                 if (!link)
5306                         continue;
5307
5308                 if (link->psr_settings.psr_feature_enabled) {
5309                         if (enable && !link->psr_settings.psr_allow_active) {
5310                                 allow_active = true;
5311                                 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
5312                                         return false;
5313                         } else if (!enable && link->psr_settings.psr_allow_active) {
5314                                 allow_active = false;
5315                                 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
5316                                         return false;
5317                         }
5318                 }
5319         }
5320
5321         return true;
5322 }
5323
5324 /* enable/disable eDP Replay without specify stream for eDP */
5325 bool dc_set_replay_allow_active(struct dc *dc, bool active)
5326 {
5327         int i;
5328         bool allow_active;
5329
5330         for (i = 0; i < dc->current_state->stream_count; i++) {
5331                 struct dc_link *link;
5332                 struct dc_stream_state *stream = dc->current_state->streams[i];
5333
5334                 link = stream->link;
5335                 if (!link)
5336                         continue;
5337
5338                 if (link->replay_settings.replay_feature_enabled) {
5339                         if (active && !link->replay_settings.replay_allow_active) {
5340                                 allow_active = true;
5341                                 if (!dc_link_set_replay_allow_active(link, &allow_active,
5342                                         false, false, NULL))
5343                                         return false;
5344                         } else if (!active && link->replay_settings.replay_allow_active) {
5345                                 allow_active = false;
5346                                 if (!dc_link_set_replay_allow_active(link, &allow_active,
5347                                         true, false, NULL))
5348                                         return false;
5349                         }
5350                 }
5351         }
5352
5353         return true;
5354 }
5355
5356 /* set IPS disable state */
5357 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips)
5358 {
5359         dc_exit_ips_for_hw_access(dc);
5360
5361         dc->config.disable_ips = disable_ips;
5362
5363         return true;
5364 }
5365
5366 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name)
5367 {
5368         if (dc->debug.disable_idle_power_optimizations)
5369                 return;
5370
5371         if (allow != dc->idle_optimizations_allowed)
5372                 DC_LOG_IPS("%s: allow_idle old=%d new=%d (caller=%s)\n", __func__,
5373                            dc->idle_optimizations_allowed, allow, caller_name);
5374
5375         if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
5376                 return;
5377
5378         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
5379                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
5380                         return;
5381
5382         if (allow == dc->idle_optimizations_allowed)
5383                 return;
5384
5385         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
5386                 dc->idle_optimizations_allowed = allow;
5387 }
5388
5389 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)
5390 {
5391         if (dc->caps.ips_support)
5392                 dc_allow_idle_optimizations_internal(dc, false, caller_name);
5393 }
5394
5395 bool dc_dmub_is_ips_idle_state(struct dc *dc)
5396 {
5397         if (dc->debug.disable_idle_power_optimizations)
5398                 return false;
5399
5400         if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
5401                 return false;
5402
5403         if (!dc->ctx->dmub_srv)
5404                 return false;
5405
5406         return dc->ctx->dmub_srv->idle_allowed;
5407 }
5408
5409 /* set min and max memory clock to lowest and highest DPM level, respectively */
5410 void dc_unlock_memory_clock_frequency(struct dc *dc)
5411 {
5412         if (dc->clk_mgr->funcs->set_hard_min_memclk)
5413                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
5414
5415         if (dc->clk_mgr->funcs->set_hard_max_memclk)
5416                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
5417 }
5418
5419 /* set min memory clock to the min required for current mode, max to maxDPM */
5420 void dc_lock_memory_clock_frequency(struct dc *dc)
5421 {
5422         if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
5423                 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
5424
5425         if (dc->clk_mgr->funcs->set_hard_min_memclk)
5426                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
5427
5428         if (dc->clk_mgr->funcs->set_hard_max_memclk)
5429                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
5430 }
5431
5432 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
5433 {
5434         struct dc_state *context = dc->current_state;
5435         struct hubp *hubp;
5436         struct pipe_ctx *pipe;
5437         int i;
5438
5439         for (i = 0; i < dc->res_pool->pipe_count; i++) {
5440                 pipe = &context->res_ctx.pipe_ctx[i];
5441
5442                 if (pipe->stream != NULL) {
5443                         dc->hwss.disable_pixel_data(dc, pipe, true);
5444
5445                         // wait for double buffer
5446                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
5447                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
5448                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
5449
5450                         hubp = pipe->plane_res.hubp;
5451                         hubp->funcs->set_blank_regs(hubp, true);
5452                 }
5453         }
5454
5455         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
5456         dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
5457
5458         for (i = 0; i < dc->res_pool->pipe_count; i++) {
5459                 pipe = &context->res_ctx.pipe_ctx[i];
5460
5461                 if (pipe->stream != NULL) {
5462                         dc->hwss.disable_pixel_data(dc, pipe, false);
5463
5464                         hubp = pipe->plane_res.hubp;
5465                         hubp->funcs->set_blank_regs(hubp, false);
5466                 }
5467         }
5468 }
5469
5470
5471 /**
5472  * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
5473  * @dc: pointer to dc of the dm calling this
5474  * @enable: True = transition to DC mode, false = transition back to AC mode
5475  *
5476  * Some SoCs define additional clock limits when in DC mode, DM should
5477  * invoke this function when the platform undergoes a power source transition
5478  * so DC can apply/unapply the limit. This interface may be disruptive to
5479  * the onscreen content.
5480  *
5481  * Context: Triggered by OS through DM interface, or manually by escape calls.
5482  * Need to hold a dclock when doing so.
5483  *
5484  * Return: none (void function)
5485  *
5486  */
5487 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
5488 {
5489         unsigned int softMax = 0, maxDPM = 0, funcMin = 0, i;
5490         bool p_state_change_support;
5491
5492         if (!dc->config.dc_mode_clk_limit_support)
5493                 return;
5494
5495         softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
5496         for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {
5497                 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)
5498                         maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
5499         }
5500         funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
5501         p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
5502
5503         if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
5504                 if (p_state_change_support) {
5505                         if (funcMin <= softMax)
5506                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
5507                         // else: No-Op
5508                 } else {
5509                         if (funcMin <= softMax)
5510                                 blank_and_force_memclk(dc, true, softMax);
5511                         // else: No-Op
5512                 }
5513         } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
5514                 if (p_state_change_support) {
5515                         if (funcMin <= softMax)
5516                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
5517                         // else: No-Op
5518                 } else {
5519                         if (funcMin <= softMax)
5520                                 blank_and_force_memclk(dc, true, maxDPM);
5521                         // else: No-Op
5522                 }
5523         }
5524         dc->clk_mgr->dc_mode_softmax_enabled = enable;
5525 }
5526 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
5527                 unsigned int pitch,
5528                 unsigned int height,
5529                 enum surface_pixel_format format,
5530                 struct dc_cursor_attributes *cursor_attr)
5531 {
5532         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, pitch, height, format, cursor_attr))
5533                 return true;
5534         return false;
5535 }
5536
5537 /* cleanup on driver unload */
5538 void dc_hardware_release(struct dc *dc)
5539 {
5540         dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);
5541
5542         if (dc->hwss.hardware_release)
5543                 dc->hwss.hardware_release(dc);
5544 }
5545
5546 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
5547 {
5548         if (dc->current_state)
5549                 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;
5550 }
5551
5552 /**
5553  * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification
5554  *
5555  * @dc: [in] dc structure
5556  *
5557  * Checks whether DMUB FW supports outbox notifications, if supported DM
5558  * should register outbox interrupt prior to actually enabling interrupts
5559  * via dc_enable_dmub_outbox
5560  *
5561  * Return:
5562  * True if DMUB FW supports outbox notifications, False otherwise
5563  */
5564 bool dc_is_dmub_outbox_supported(struct dc *dc)
5565 {
5566         switch (dc->ctx->asic_id.chip_family) {
5567
5568         case FAMILY_YELLOW_CARP:
5569                 /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
5570                 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
5571                     !dc->debug.dpia_debug.bits.disable_dpia)
5572                         return true;
5573         break;
5574
5575         case AMDGPU_FAMILY_GC_11_0_1:
5576         case AMDGPU_FAMILY_GC_11_5_0:
5577                 if (!dc->debug.dpia_debug.bits.disable_dpia)
5578                         return true;
5579         break;
5580
5581         default:
5582                 break;
5583         }
5584
5585         /* dmub aux needs dmub notifications to be enabled */
5586         return dc->debug.enable_dmub_aux_for_legacy_ddc;
5587
5588 }
5589
5590 /**
5591  * dc_enable_dmub_notifications - Check if dmub fw supports outbox
5592  *
5593  * @dc: [in] dc structure
5594  *
5595  * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
5596  * notifications. All DMs shall switch to dc_is_dmub_outbox_supported.  This
5597  * API shall be removed after switching.
5598  *
5599  * Return:
5600  * True if DMUB FW supports outbox notifications, False otherwise
5601  */
5602 bool dc_enable_dmub_notifications(struct dc *dc)
5603 {
5604         return dc_is_dmub_outbox_supported(dc);
5605 }
5606
5607 /**
5608  * dc_enable_dmub_outbox - Enables DMUB unsolicited notification
5609  *
5610  * @dc: [in] dc structure
5611  *
5612  * Enables DMUB unsolicited notifications to x86 via outbox.
5613  */
5614 void dc_enable_dmub_outbox(struct dc *dc)
5615 {
5616         struct dc_context *dc_ctx = dc->ctx;
5617
5618         dmub_enable_outbox_notification(dc_ctx->dmub_srv);
5619         DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__);
5620 }
5621
5622 /**
5623  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
5624  *                                      Sets port index appropriately for legacy DDC
5625  * @dc: dc structure
5626  * @link_index: link index
5627  * @payload: aux payload
5628  *
5629  * Returns: True if successful, False if failure
5630  */
5631 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
5632                                 uint32_t link_index,
5633                                 struct aux_payload *payload)
5634 {
5635         uint8_t action;
5636         union dmub_rb_cmd cmd = {0};
5637
5638         ASSERT(payload->length <= 16);
5639
5640         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
5641         cmd.dp_aux_access.header.payload_bytes = 0;
5642         /* For dpia, ddc_pin is set to NULL */
5643         if (!dc->links[link_index]->ddc->ddc_pin)
5644                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
5645         else
5646                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
5647
5648         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
5649         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
5650         cmd.dp_aux_access.aux_control.timeout = 0;
5651         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
5652         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
5653         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
5654
5655         /* set aux action */
5656         if (payload->i2c_over_aux) {
5657                 if (payload->write) {
5658                         if (payload->mot)
5659                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
5660                         else
5661                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
5662                 } else {
5663                         if (payload->mot)
5664                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
5665                         else
5666                                 action = DP_AUX_REQ_ACTION_I2C_READ;
5667                         }
5668         } else {
5669                 if (payload->write)
5670                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
5671                 else
5672                         action = DP_AUX_REQ_ACTION_DPCD_READ;
5673         }
5674
5675         cmd.dp_aux_access.aux_control.dpaux.action = action;
5676
5677         if (payload->length && payload->write) {
5678                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
5679                         payload->data,
5680                         payload->length
5681                         );
5682         }
5683
5684         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5685
5686         return true;
5687 }
5688
5689 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
5690                                             uint8_t dpia_port_index)
5691 {
5692         uint8_t index, link_index = 0xFF;
5693
5694         for (index = 0; index < dc->link_count; index++) {
5695                 /* ddc_hw_inst has dpia port index for dpia links
5696                  * and ddc instance for legacy links
5697                  */
5698                 if (!dc->links[index]->ddc->ddc_pin) {
5699                         if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
5700                                 link_index = index;
5701                                 break;
5702                         }
5703                 }
5704         }
5705         ASSERT(link_index != 0xFF);
5706         return link_index;
5707 }
5708
5709 /**
5710  * dc_process_dmub_set_config_async - Submits set_config command
5711  *
5712  * @dc: [in] dc structure
5713  * @link_index: [in] link_index: link index
5714  * @payload: [in] aux payload
5715  * @notify: [out] set_config immediate reply
5716  *
5717  * Submits set_config command to dmub via inbox message.
5718  *
5719  * Return:
5720  * True if successful, False if failure
5721  */
5722 bool dc_process_dmub_set_config_async(struct dc *dc,
5723                                 uint32_t link_index,
5724                                 struct set_config_cmd_payload *payload,
5725                                 struct dmub_notification *notify)
5726 {
5727         union dmub_rb_cmd cmd = {0};
5728         bool is_cmd_complete = true;
5729
5730         /* prepare SET_CONFIG command */
5731         cmd.set_config_access.header.type = DMUB_CMD__DPIA;
5732         cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
5733
5734         cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
5735         cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
5736         cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
5737
5738         if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
5739                 /* command is not processed by dmub */
5740                 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
5741                 return is_cmd_complete;
5742         }
5743
5744         /* command processed by dmub, if ret_status is 1, it is completed instantly */
5745         if (cmd.set_config_access.header.ret_status == 1)
5746                 notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
5747         else
5748                 /* cmd pending, will receive notification via outbox */
5749                 is_cmd_complete = false;
5750
5751         return is_cmd_complete;
5752 }
5753
5754 /**
5755  * dc_process_dmub_set_mst_slots - Submits MST solt allocation
5756  *
5757  * @dc: [in] dc structure
5758  * @link_index: [in] link index
5759  * @mst_alloc_slots: [in] mst slots to be allotted
5760  * @mst_slots_in_use: [out] mst slots in use returned in failure case
5761  *
5762  * Submits mst slot allocation command to dmub via inbox message
5763  *
5764  * Return:
5765  * DC_OK if successful, DC_ERROR if failure
5766  */
5767 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
5768                                 uint32_t link_index,
5769                                 uint8_t mst_alloc_slots,
5770                                 uint8_t *mst_slots_in_use)
5771 {
5772         union dmub_rb_cmd cmd = {0};
5773
5774         /* prepare MST_ALLOC_SLOTS command */
5775         cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
5776         cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
5777
5778         cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
5779         cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
5780
5781         if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
5782                 /* command is not processed by dmub */
5783                 return DC_ERROR_UNEXPECTED;
5784
5785         /* command processed by dmub, if ret_status is 1 */
5786         if (cmd.set_config_access.header.ret_status != 1)
5787                 /* command processing error */
5788                 return DC_ERROR_UNEXPECTED;
5789
5790         /* command processed and we have a status of 2, mst not enabled in dpia */
5791         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
5792                 return DC_FAIL_UNSUPPORTED_1;
5793
5794         /* previously configured mst alloc and used slots did not match */
5795         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
5796                 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
5797                 return DC_NOT_SUPPORTED;
5798         }
5799
5800         return DC_OK;
5801 }
5802
5803 /**
5804  * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
5805  *
5806  * @dc: [in] dc structure
5807  * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
5808  *
5809  * Submits dpia hpd int enable command to dmub via inbox message
5810  */
5811 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
5812                                 uint32_t hpd_int_enable)
5813 {
5814         union dmub_rb_cmd cmd = {0};
5815
5816         cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;
5817         cmd.dpia_hpd_int_enable.enable = hpd_int_enable;
5818
5819         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5820
5821         DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);
5822 }
5823
5824 /**
5825  * dc_print_dmub_diagnostic_data - Print DMUB diagnostic data for debugging
5826  *
5827  * @dc: [in] dc structure
5828  *
5829  *
5830  */
5831 void dc_print_dmub_diagnostic_data(const struct dc *dc)
5832 {
5833         dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);
5834 }
5835
5836 /**
5837  * dc_disable_accelerated_mode - disable accelerated mode
5838  * @dc: dc structure
5839  */
5840 void dc_disable_accelerated_mode(struct dc *dc)
5841 {
5842         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
5843 }
5844
5845
5846 /**
5847  *  dc_notify_vsync_int_state - notifies vsync enable/disable state
5848  *  @dc: dc structure
5849  *  @stream: stream where vsync int state changed
5850  *  @enable: whether vsync is enabled or disabled
5851  *
5852  *  Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM
5853  *  interrupts after steady state is reached.
5854  */
5855 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
5856 {
5857         int i;
5858         int edp_num;
5859         struct pipe_ctx *pipe = NULL;
5860         struct dc_link *link = stream->sink->link;
5861         struct dc_link *edp_links[MAX_NUM_EDP];
5862
5863
5864         if (link->psr_settings.psr_feature_enabled)
5865                 return;
5866
5867         if (link->replay_settings.replay_feature_enabled)
5868                 return;
5869
5870         /*find primary pipe associated with stream*/
5871         for (i = 0; i < MAX_PIPES; i++) {
5872                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5873
5874                 if (pipe->stream == stream && pipe->stream_res.tg)
5875                         break;
5876         }
5877
5878         if (i == MAX_PIPES) {
5879                 ASSERT(0);
5880                 return;
5881         }
5882
5883         dc_get_edp_links(dc, edp_links, &edp_num);
5884
5885         /* Determine panel inst */
5886         for (i = 0; i < edp_num; i++) {
5887                 if (edp_links[i] == link)
5888                         break;
5889         }
5890
5891         if (i == edp_num) {
5892                 return;
5893         }
5894
5895         if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
5896                 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
5897 }
5898
5899 /*****************************************************************************
5900  *  dc_abm_save_restore() - Interface to DC for save+pause and restore+un-pause
5901  *                          ABM
5902  *  @dc: dc structure
5903  *      @stream: stream where vsync int state changed
5904  *  @pData: abm hw states
5905  *
5906  ****************************************************************************/
5907 bool dc_abm_save_restore(
5908                 struct dc *dc,
5909                 struct dc_stream_state *stream,
5910                 struct abm_save_restore *pData)
5911 {
5912         int i;
5913         int edp_num;
5914         struct pipe_ctx *pipe = NULL;
5915         struct dc_link *link = stream->sink->link;
5916         struct dc_link *edp_links[MAX_NUM_EDP];
5917
5918         if (link->replay_settings.replay_feature_enabled)
5919                 return false;
5920
5921         /*find primary pipe associated with stream*/
5922         for (i = 0; i < MAX_PIPES; i++) {
5923                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5924
5925                 if (pipe->stream == stream && pipe->stream_res.tg)
5926                         break;
5927         }
5928
5929         if (i == MAX_PIPES) {
5930                 ASSERT(0);
5931                 return false;
5932         }
5933
5934         dc_get_edp_links(dc, edp_links, &edp_num);
5935
5936         /* Determine panel inst */
5937         for (i = 0; i < edp_num; i++)
5938                 if (edp_links[i] == link)
5939                         break;
5940
5941         if (i == edp_num)
5942                 return false;
5943
5944         if (pipe->stream_res.abm &&
5945                 pipe->stream_res.abm->funcs->save_restore)
5946                 return pipe->stream_res.abm->funcs->save_restore(
5947                                 pipe->stream_res.abm,
5948                                 i,
5949                                 pData);
5950         return false;
5951 }
5952
5953 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)
5954 {
5955         unsigned int i;
5956         bool subvp_sw_cursor_req = false;
5957
5958         for (i = 0; i < dc->current_state->stream_count; i++) {
5959                 if (check_subvp_sw_cursor_fallback_req(dc, dc->current_state->streams[i])) {
5960                         subvp_sw_cursor_req = true;
5961                         break;
5962                 }
5963         }
5964         properties->cursor_size_limit = subvp_sw_cursor_req ? 64 : dc->caps.max_cursor_size;
5965 }
5966
5967 /**
5968  * dc_set_edp_power() - DM controls eDP power to be ON/OFF
5969  *
5970  * Called when DM wants to power on/off eDP.
5971  *     Only work on links with flag skip_implict_edp_power_control is set.
5972  *
5973  * @dc: Current DC state
5974  * @edp_link: a link with eDP connector signal type
5975  * @powerOn: power on/off eDP
5976  *
5977  * Return: void
5978  */
5979 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
5980                                  bool powerOn)
5981 {
5982         if (edp_link->connector_signal != SIGNAL_TYPE_EDP)
5983                 return;
5984
5985         if (edp_link->skip_implict_edp_power_control == false)
5986                 return;
5987
5988         edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
5989 }
5990
5991 /*
5992  *****************************************************************************
5993  * dc_get_power_profile_for_dc_state() - extracts power profile from dc state
5994  *
5995  * Called when DM wants to make power policy decisions based on dc_state
5996  *
5997  *****************************************************************************
5998  */
5999 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context)
6000 {
6001         struct dc_power_profile profile = { 0 };
6002
6003         profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support;
6004
6005         return profile;
6006 }