drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "gfxhub_v1_2.h"
  53 #include "mmhub_v9_4.h"
  54 #include "mmhub_v1_7.h"
  55 #include "mmhub_v1_8.h"
  56 #include "umc_v6_1.h"
  57 #include "umc_v6_0.h"
  58 #include "umc_v6_7.h"
  59 #include "hdp_v4_0.h"
  60 #include "mca_v3_0.h"
  61
  62 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  63
  64 #include "amdgpu_ras.h"
  65 #include "amdgpu_xgmi.h"
  66
  67 #include "amdgpu_reset.h"
  68
  69 /* add these here since we already include dce12 headers and these are for DCN */
  70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  78
  79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2                                                          0x05ea
  80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX                                                 2
  81
  82
  83 static const char *gfxhub_client_ids[] = {
  84         "CB",
  85         "DB",
  86         "IA",
  87         "WD",
  88         "CPF",
  89         "CPC",
  90         "CPG",
  91         "RLC",
  92         "TCP",
  93         "SQC (inst)",
  94         "SQC (data)",
  95         "SQG",
  96         "PA",
  97 };
  98
  99 static const char *mmhub_client_ids_raven[][2] = {
 100         [0][0] = "MP1",
 101         [1][0] = "MP0",
 102         [2][0] = "VCN",
 103         [3][0] = "VCNU",
 104         [4][0] = "HDP",
 105         [5][0] = "DCE",
 106         [13][0] = "UTCL2",
 107         [19][0] = "TLS",
 108         [26][0] = "OSS",
 109         [27][0] = "SDMA0",
 110         [0][1] = "MP1",
 111         [1][1] = "MP0",
 112         [2][1] = "VCN",
 113         [3][1] = "VCNU",
 114         [4][1] = "HDP",
 115         [5][1] = "XDP",
 116         [6][1] = "DBGU0",
 117         [7][1] = "DCE",
 118         [8][1] = "DCEDWB0",
 119         [9][1] = "DCEDWB1",
 120         [26][1] = "OSS",
 121         [27][1] = "SDMA0",
 122 };
 123
 124 static const char *mmhub_client_ids_renoir[][2] = {
 125         [0][0] = "MP1",
 126         [1][0] = "MP0",
 127         [2][0] = "HDP",
 128         [4][0] = "DCEDMC",
 129         [5][0] = "DCEVGA",
 130         [13][0] = "UTCL2",
 131         [19][0] = "TLS",
 132         [26][0] = "OSS",
 133         [27][0] = "SDMA0",
 134         [28][0] = "VCN",
 135         [29][0] = "VCNU",
 136         [30][0] = "JPEG",
 137         [0][1] = "MP1",
 138         [1][1] = "MP0",
 139         [2][1] = "HDP",
 140         [3][1] = "XDP",
 141         [6][1] = "DBGU0",
 142         [7][1] = "DCEDMC",
 143         [8][1] = "DCEVGA",
 144         [9][1] = "DCEDWB",
 145         [26][1] = "OSS",
 146         [27][1] = "SDMA0",
 147         [28][1] = "VCN",
 148         [29][1] = "VCNU",
 149         [30][1] = "JPEG",
 150 };
 151
 152 static const char *mmhub_client_ids_vega10[][2] = {
 153         [0][0] = "MP0",
 154         [1][0] = "UVD",
 155         [2][0] = "UVDU",
 156         [3][0] = "HDP",
 157         [13][0] = "UTCL2",
 158         [14][0] = "OSS",
 159         [15][0] = "SDMA1",
 160         [32+0][0] = "VCE0",
 161         [32+1][0] = "VCE0U",
 162         [32+2][0] = "XDMA",
 163         [32+3][0] = "DCE",
 164         [32+4][0] = "MP1",
 165         [32+14][0] = "SDMA0",
 166         [0][1] = "MP0",
 167         [1][1] = "UVD",
 168         [2][1] = "UVDU",
 169         [3][1] = "DBGU0",
 170         [4][1] = "HDP",
 171         [5][1] = "XDP",
 172         [14][1] = "OSS",
 173         [15][1] = "SDMA0",
 174         [32+0][1] = "VCE0",
 175         [32+1][1] = "VCE0U",
 176         [32+2][1] = "XDMA",
 177         [32+3][1] = "DCE",
 178         [32+4][1] = "DCEDWB",
 179         [32+5][1] = "MP1",
 180         [32+6][1] = "DBGU1",
 181         [32+14][1] = "SDMA1",
 182 };
 183
 184 static const char *mmhub_client_ids_vega12[][2] = {
 185         [0][0] = "MP0",
 186         [1][0] = "VCE0",
 187         [2][0] = "VCE0U",
 188         [3][0] = "HDP",
 189         [13][0] = "UTCL2",
 190         [14][0] = "OSS",
 191         [15][0] = "SDMA1",
 192         [32+0][0] = "DCE",
 193         [32+1][0] = "XDMA",
 194         [32+2][0] = "UVD",
 195         [32+3][0] = "UVDU",
 196         [32+4][0] = "MP1",
 197         [32+15][0] = "SDMA0",
 198         [0][1] = "MP0",
 199         [1][1] = "VCE0",
 200         [2][1] = "VCE0U",
 201         [3][1] = "DBGU0",
 202         [4][1] = "HDP",
 203         [5][1] = "XDP",
 204         [14][1] = "OSS",
 205         [15][1] = "SDMA0",
 206         [32+0][1] = "DCE",
 207         [32+1][1] = "DCEDWB",
 208         [32+2][1] = "XDMA",
 209         [32+3][1] = "UVD",
 210         [32+4][1] = "UVDU",
 211         [32+5][1] = "MP1",
 212         [32+6][1] = "DBGU1",
 213         [32+15][1] = "SDMA1",
 214 };
 215
 216 static const char *mmhub_client_ids_vega20[][2] = {
 217         [0][0] = "XDMA",
 218         [1][0] = "DCE",
 219         [2][0] = "VCE0",
 220         [3][0] = "VCE0U",
 221         [4][0] = "UVD",
 222         [5][0] = "UVD1U",
 223         [13][0] = "OSS",
 224         [14][0] = "HDP",
 225         [15][0] = "SDMA0",
 226         [32+0][0] = "UVD",
 227         [32+1][0] = "UVDU",
 228         [32+2][0] = "MP1",
 229         [32+3][0] = "MP0",
 230         [32+12][0] = "UTCL2",
 231         [32+14][0] = "SDMA1",
 232         [0][1] = "XDMA",
 233         [1][1] = "DCE",
 234         [2][1] = "DCEDWB",
 235         [3][1] = "VCE0",
 236         [4][1] = "VCE0U",
 237         [5][1] = "UVD1",
 238         [6][1] = "UVD1U",
 239         [7][1] = "DBGU0",
 240         [8][1] = "XDP",
 241         [13][1] = "OSS",
 242         [14][1] = "HDP",
 243         [15][1] = "SDMA0",
 244         [32+0][1] = "UVD",
 245         [32+1][1] = "UVDU",
 246         [32+2][1] = "DBGU1",
 247         [32+3][1] = "MP1",
 248         [32+4][1] = "MP0",
 249         [32+14][1] = "SDMA1",
 250 };
 251
 252 static const char *mmhub_client_ids_arcturus[][2] = {
 253         [0][0] = "DBGU1",
 254         [1][0] = "XDP",
 255         [2][0] = "MP1",
 256         [14][0] = "HDP",
 257         [171][0] = "JPEG",
 258         [172][0] = "VCN",
 259         [173][0] = "VCNU",
 260         [203][0] = "JPEG1",
 261         [204][0] = "VCN1",
 262         [205][0] = "VCN1U",
 263         [256][0] = "SDMA0",
 264         [257][0] = "SDMA1",
 265         [258][0] = "SDMA2",
 266         [259][0] = "SDMA3",
 267         [260][0] = "SDMA4",
 268         [261][0] = "SDMA5",
 269         [262][0] = "SDMA6",
 270         [263][0] = "SDMA7",
 271         [384][0] = "OSS",
 272         [0][1] = "DBGU1",
 273         [1][1] = "XDP",
 274         [2][1] = "MP1",
 275         [14][1] = "HDP",
 276         [171][1] = "JPEG",
 277         [172][1] = "VCN",
 278         [173][1] = "VCNU",
 279         [203][1] = "JPEG1",
 280         [204][1] = "VCN1",
 281         [205][1] = "VCN1U",
 282         [256][1] = "SDMA0",
 283         [257][1] = "SDMA1",
 284         [258][1] = "SDMA2",
 285         [259][1] = "SDMA3",
 286         [260][1] = "SDMA4",
 287         [261][1] = "SDMA5",
 288         [262][1] = "SDMA6",
 289         [263][1] = "SDMA7",
 290         [384][1] = "OSS",
 291 };
 292
 293 static const char *mmhub_client_ids_aldebaran[][2] = {
 294         [2][0] = "MP1",
 295         [3][0] = "MP0",
 296         [32+1][0] = "DBGU_IO0",
 297         [32+2][0] = "DBGU_IO2",
 298         [32+4][0] = "MPIO",
 299         [96+11][0] = "JPEG0",
 300         [96+12][0] = "VCN0",
 301         [96+13][0] = "VCNU0",
 302         [128+11][0] = "JPEG1",
 303         [128+12][0] = "VCN1",
 304         [128+13][0] = "VCNU1",
 305         [160+1][0] = "XDP",
 306         [160+14][0] = "HDP",
 307         [256+0][0] = "SDMA0",
 308         [256+1][0] = "SDMA1",
 309         [256+2][0] = "SDMA2",
 310         [256+3][0] = "SDMA3",
 311         [256+4][0] = "SDMA4",
 312         [384+0][0] = "OSS",
 313         [2][1] = "MP1",
 314         [3][1] = "MP0",
 315         [32+1][1] = "DBGU_IO0",
 316         [32+2][1] = "DBGU_IO2",
 317         [32+4][1] = "MPIO",
 318         [96+11][1] = "JPEG0",
 319         [96+12][1] = "VCN0",
 320         [96+13][1] = "VCNU0",
 321         [128+11][1] = "JPEG1",
 322         [128+12][1] = "VCN1",
 323         [128+13][1] = "VCNU1",
 324         [160+1][1] = "XDP",
 325         [160+14][1] = "HDP",
 326         [256+0][1] = "SDMA0",
 327         [256+1][1] = "SDMA1",
 328         [256+2][1] = "SDMA2",
 329         [256+3][1] = "SDMA3",
 330         [256+4][1] = "SDMA4",
 331         [384+0][1] = "OSS",
 332 };
 333
 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
 335 {
 336         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 337         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 338 };
 339
 340 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
 341 {
 342         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 343         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 344 };
 345
 346 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 347         (0x000143c0 + 0x00000000),
 348         (0x000143c0 + 0x00000800),
 349         (0x000143c0 + 0x00001000),
 350         (0x000143c0 + 0x00001800),
 351         (0x000543c0 + 0x00000000),
 352         (0x000543c0 + 0x00000800),
 353         (0x000543c0 + 0x00001000),
 354         (0x000543c0 + 0x00001800),
 355         (0x000943c0 + 0x00000000),
 356         (0x000943c0 + 0x00000800),
 357         (0x000943c0 + 0x00001000),
 358         (0x000943c0 + 0x00001800),
 359         (0x000d43c0 + 0x00000000),
 360         (0x000d43c0 + 0x00000800),
 361         (0x000d43c0 + 0x00001000),
 362         (0x000d43c0 + 0x00001800),
 363         (0x001143c0 + 0x00000000),
 364         (0x001143c0 + 0x00000800),
 365         (0x001143c0 + 0x00001000),
 366         (0x001143c0 + 0x00001800),
 367         (0x001543c0 + 0x00000000),
 368         (0x001543c0 + 0x00000800),
 369         (0x001543c0 + 0x00001000),
 370         (0x001543c0 + 0x00001800),
 371         (0x001943c0 + 0x00000000),
 372         (0x001943c0 + 0x00000800),
 373         (0x001943c0 + 0x00001000),
 374         (0x001943c0 + 0x00001800),
 375         (0x001d43c0 + 0x00000000),
 376         (0x001d43c0 + 0x00000800),
 377         (0x001d43c0 + 0x00001000),
 378         (0x001d43c0 + 0x00001800),
 379 };
 380
 381 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 382         (0x000143e0 + 0x00000000),
 383         (0x000143e0 + 0x00000800),
 384         (0x000143e0 + 0x00001000),
 385         (0x000143e0 + 0x00001800),
 386         (0x000543e0 + 0x00000000),
 387         (0x000543e0 + 0x00000800),
 388         (0x000543e0 + 0x00001000),
 389         (0x000543e0 + 0x00001800),
 390         (0x000943e0 + 0x00000000),
 391         (0x000943e0 + 0x00000800),
 392         (0x000943e0 + 0x00001000),
 393         (0x000943e0 + 0x00001800),
 394         (0x000d43e0 + 0x00000000),
 395         (0x000d43e0 + 0x00000800),
 396         (0x000d43e0 + 0x00001000),
 397         (0x000d43e0 + 0x00001800),
 398         (0x001143e0 + 0x00000000),
 399         (0x001143e0 + 0x00000800),
 400         (0x001143e0 + 0x00001000),
 401         (0x001143e0 + 0x00001800),
 402         (0x001543e0 + 0x00000000),
 403         (0x001543e0 + 0x00000800),
 404         (0x001543e0 + 0x00001000),
 405         (0x001543e0 + 0x00001800),
 406         (0x001943e0 + 0x00000000),
 407         (0x001943e0 + 0x00000800),
 408         (0x001943e0 + 0x00001000),
 409         (0x001943e0 + 0x00001800),
 410         (0x001d43e0 + 0x00000000),
 411         (0x001d43e0 + 0x00000800),
 412         (0x001d43e0 + 0x00001000),
 413         (0x001d43e0 + 0x00001800),
 414 };
 415
 416 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 417                 struct amdgpu_irq_src *src,
 418                 unsigned type,
 419                 enum amdgpu_interrupt_state state)
 420 {
 421         u32 bits, i, tmp, reg;
 422
 423         /* Devices newer then VEGA10/12 shall have these programming
 424              sequences performed by PSP BL */
 425         if (adev->asic_type >= CHIP_VEGA20)
 426                 return 0;
 427
 428         bits = 0x7f;
 429
 430         switch (state) {
 431         case AMDGPU_IRQ_STATE_DISABLE:
 432                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 433                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 434                         tmp = RREG32(reg);
 435                         tmp &= ~bits;
 436                         WREG32(reg, tmp);
 437                 }
 438                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 439                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 440                         tmp = RREG32(reg);
 441                         tmp &= ~bits;
 442                         WREG32(reg, tmp);
 443                 }
 444                 break;
 445         case AMDGPU_IRQ_STATE_ENABLE:
 446                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 447                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 448                         tmp = RREG32(reg);
 449                         tmp |= bits;
 450                         WREG32(reg, tmp);
 451                 }
 452                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 453                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 454                         tmp = RREG32(reg);
 455                         tmp |= bits;
 456                         WREG32(reg, tmp);
 457                 }
 458                 break;
 459         default:
 460                 break;
 461         }
 462
 463         return 0;
 464 }
 465
 466 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 467                                         struct amdgpu_irq_src *src,
 468                                         unsigned type,
 469                                         enum amdgpu_interrupt_state state)
 470 {
 471         struct amdgpu_vmhub *hub;
 472         u32 tmp, reg, bits, i, j;
 473
 474         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 475                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 476                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 477                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 478                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 479                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 480                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 481
 482         switch (state) {
 483         case AMDGPU_IRQ_STATE_DISABLE:
 484                 for (j = 0; j < adev->num_vmhubs; j++) {
 485                         hub = &adev->vmhub[j];
 486                         for (i = 0; i < 16; i++) {
 487                                 reg = hub->vm_context0_cntl + i;
 488
 489                                 /* This works because this interrupt is only
 490                                  * enabled at init/resume and disabled in
 491                                  * fini/suspend, so the overall state doesn't
 492                                  * change over the course of suspend/resume.
 493                                  */
 494                                 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
 495                                         continue;
 496
 497                                 if (j == AMDGPU_GFXHUB_0)
 498                                         tmp = RREG32_SOC15_IP(GC, reg);
 499                                 else
 500                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 501
 502                                 tmp &= ~bits;
 503
 504                                 if (j == AMDGPU_GFXHUB_0)
 505                                         WREG32_SOC15_IP(GC, reg, tmp);
 506                                 else
 507                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 508                         }
 509                 }
 510                 break;
 511         case AMDGPU_IRQ_STATE_ENABLE:
 512                 for (j = 0; j < adev->num_vmhubs; j++) {
 513                         hub = &adev->vmhub[j];
 514                         for (i = 0; i < 16; i++) {
 515                                 reg = hub->vm_context0_cntl + i;
 516
 517                                 /* This works because this interrupt is only
 518                                  * enabled at init/resume and disabled in
 519                                  * fini/suspend, so the overall state doesn't
 520                                  * change over the course of suspend/resume.
 521                                  */
 522                                 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
 523                                         continue;
 524
 525                                 if (j == AMDGPU_GFXHUB_0)
 526                                         tmp = RREG32_SOC15_IP(GC, reg);
 527                                 else
 528                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 529
 530                                 tmp |= bits;
 531
 532                                 if (j == AMDGPU_GFXHUB_0)
 533                                         WREG32_SOC15_IP(GC, reg, tmp);
 534                                 else
 535                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 536                         }
 537                 }
 538                 break;
 539         default:
 540                 break;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 547                                       struct amdgpu_irq_src *source,
 548                                       struct amdgpu_iv_entry *entry)
 549 {
 550         bool retry_fault = !!(entry->src_data[1] & 0x80);
 551         bool write_fault = !!(entry->src_data[1] & 0x20);
 552         uint32_t status = 0, cid = 0, rw = 0;
 553         struct amdgpu_task_info task_info;
 554         struct amdgpu_vmhub *hub;
 555         const char *mmhub_cid;
 556         const char *hub_name;
 557         u64 addr;
 558         uint32_t cam_index = 0;
 559         int ret;
 560
 561         addr = (u64)entry->src_data[0] << 12;
 562         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 563
 564         if (retry_fault) {
 565                 if (adev->irq.retry_cam_enabled) {
 566                         /* Delegate it to a different ring if the hardware hasn't
 567                          * already done it.
 568                          */
 569                         if (entry->ih == &adev->irq.ih) {
 570                                 amdgpu_irq_delegate(adev, entry, 8);
 571                                 return 1;
 572                         }
 573
 574                         cam_index = entry->src_data[2] & 0x3ff;
 575
 576                         ret = amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault);
 577                         WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
 578                         if (ret)
 579                                 return 1;
 580                 } else {
 581                         /* Process it onyl if it's the first fault for this address */
 582                         if (entry->ih != &adev->irq.ih_soft &&
 583                             amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
 584                                              entry->timestamp))
 585                                 return 1;
 586
 587                         /* Delegate it to a different ring if the hardware hasn't
 588                          * already done it.
 589                          */
 590                         if (entry->ih == &adev->irq.ih) {
 591                                 amdgpu_irq_delegate(adev, entry, 8);
 592                                 return 1;
 593                         }
 594
 595                         /* Try to handle the recoverable page faults by filling page
 596                          * tables
 597                          */
 598                         if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
 599                                 return 1;
 600                 }
 601         }
 602
 603         if (!printk_ratelimit())
 604                 return 0;
 605
 606         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 607                 hub_name = "mmhub0";
 608                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 609         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 610                 hub_name = "mmhub1";
 611                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 612         } else {
 613                 hub_name = "gfxhub0";
 614                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 615         }
 616
 617         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 618         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 619
 620         dev_err(adev->dev,
 621                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 622                 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 623                 hub_name, retry_fault ? "retry" : "no-retry",
 624                 entry->src_id, entry->ring_id, entry->vmid,
 625                 entry->pasid, task_info.process_name, task_info.tgid,
 626                 task_info.task_name, task_info.pid);
 627         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 628                 addr, entry->client_id,
 629                 soc15_ih_clientid_name[entry->client_id]);
 630
 631         if (amdgpu_sriov_vf(adev))
 632                 return 0;
 633
 634         /*
 635          * Issue a dummy read to wait for the status register to
 636          * be updated to avoid reading an incorrect value due to
 637          * the new fast GRBM interface.
 638          */
 639         if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 640             (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
 641                 RREG32(hub->vm_l2_pro_fault_status);
 642
 643         status = RREG32(hub->vm_l2_pro_fault_status);
 644         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 645         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 646         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 647
 648
 649         dev_err(adev->dev,
 650                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 651                 status);
 652         if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
 653                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 654                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 655                         gfxhub_client_ids[cid],
 656                         cid);
 657         } else {
 658                 switch (adev->ip_versions[MMHUB_HWIP][0]) {
 659                 case IP_VERSION(9, 0, 0):
 660                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 661                         break;
 662                 case IP_VERSION(9, 3, 0):
 663                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 664                         break;
 665                 case IP_VERSION(9, 4, 0):
 666                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 667                         break;
 668                 case IP_VERSION(9, 4, 1):
 669                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 670                         break;
 671                 case IP_VERSION(9, 1, 0):
 672                 case IP_VERSION(9, 2, 0):
 673                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 674                         break;
 675                 case IP_VERSION(1, 5, 0):
 676                 case IP_VERSION(2, 4, 0):
 677                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 678                         break;
 679                 case IP_VERSION(1, 8, 0):
 680                 case IP_VERSION(9, 4, 2):
 681                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 682                         break;
 683                 default:
 684                         mmhub_cid = NULL;
 685                         break;
 686                 }
 687                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 688                         mmhub_cid ? mmhub_cid : "unknown", cid);
 689         }
 690         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 691                 REG_GET_FIELD(status,
 692                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 693         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 694                 REG_GET_FIELD(status,
 695                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 696         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 697                 REG_GET_FIELD(status,
 698                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 699         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 700                 REG_GET_FIELD(status,
 701                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 702         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 703         return 0;
 704 }
 705
 706 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 707         .set = gmc_v9_0_vm_fault_interrupt_state,
 708         .process = gmc_v9_0_process_interrupt,
 709 };
 710
 711
 712 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 713         .set = gmc_v9_0_ecc_interrupt_state,
 714         .process = amdgpu_umc_process_ecc_irq,
 715 };
 716
 717 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 718 {
 719         adev->gmc.vm_fault.num_types = 1;
 720         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 721
 722         if (!amdgpu_sriov_vf(adev) &&
 723             !adev->gmc.xgmi.connected_to_cpu) {
 724                 adev->gmc.ecc_irq.num_types = 1;
 725                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 726         }
 727 }
 728
 729 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 730                                         uint32_t flush_type)
 731 {
 732         u32 req = 0;
 733
 734         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 735                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 736         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 737         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 738         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 739         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 740         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 741         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 742         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 743                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 744
 745         return req;
 746 }
 747
 748 /**
 749  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 750  *
 751  * @adev: amdgpu_device pointer
 752  * @vmhub: vmhub type
 753  *
 754  */
 755 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 756                                        uint32_t vmhub)
 757 {
 758         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
 759             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
 760                 return false;
 761
 762         return ((vmhub == AMDGPU_MMHUB_0 ||
 763                  vmhub == AMDGPU_MMHUB_1) &&
 764                 (!amdgpu_sriov_vf(adev)) &&
 765                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 766                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 767 }
 768
 769 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 770                                         uint8_t vmid, uint16_t *p_pasid)
 771 {
 772         uint32_t value;
 773
 774         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 775                      + vmid);
 776         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 777
 778         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 779 }
 780
 781 /*
 782  * GART
 783  * VMID 0 is the physical GPU addresses as used by the kernel.
 784  * VMIDs 1-15 are used for userspace clients and are handled
 785  * by the amdgpu vm/hsa code.
 786  */
 787
 788 /**
 789  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 790  *
 791  * @adev: amdgpu_device pointer
 792  * @vmid: vm instance to flush
 793  * @vmhub: which hub to flush
 794  * @flush_type: the flush type
 795  *
 796  * Flush the TLB for the requested page table using certain type.
 797  */
 798 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 799                                         uint32_t vmhub, uint32_t flush_type)
 800 {
 801         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 802         const unsigned eng = 17;
 803         u32 j, inv_req, inv_req2, tmp;
 804         struct amdgpu_vmhub *hub;
 805
 806         BUG_ON(vmhub >= adev->num_vmhubs);
 807
 808         hub = &adev->vmhub[vmhub];
 809         if (adev->gmc.xgmi.num_physical_nodes &&
 810             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) {
 811                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 812                  * heavy-weight TLB flush (type 2), which flushes
 813                  * both. Due to a race condition with concurrent
 814                  * memory accesses using the same TLB cache line, we
 815                  * still need a second TLB flush after this.
 816                  */
 817                 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 818                 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 819         } else {
 820                 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 821                 inv_req2 = 0;
 822         }
 823
 824         /* This is necessary for a HW workaround under SRIOV as well
 825          * as GFXOFF under bare metal
 826          */
 827         if (adev->gfx.kiq.ring.sched.ready &&
 828             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 829             down_read_trylock(&adev->reset_domain->sem)) {
 830                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 831                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 832
 833                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 834                                                    1 << vmid);
 835                 up_read(&adev->reset_domain->sem);
 836                 return;
 837         }
 838
 839         spin_lock(&adev->gmc.invalidate_lock);
 840
 841         /*
 842          * It may lose gpuvm invalidate acknowldege state across power-gating
 843          * off cycle, add semaphore acquire before invalidation and semaphore
 844          * release after invalidation to avoid entering power gated state
 845          * to WA the Issue
 846          */
 847
 848         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 849         if (use_semaphore) {
 850                 for (j = 0; j < adev->usec_timeout; j++) {
 851                         /* a read return value of 1 means semaphore acquire */
 852                         if (vmhub == AMDGPU_GFXHUB_0)
 853                                 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
 854                         else
 855                                 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
 856
 857                         if (tmp & 0x1)
 858                                 break;
 859                         udelay(1);
 860                 }
 861
 862                 if (j >= adev->usec_timeout)
 863                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 864         }
 865
 866         do {
 867                 if (vmhub == AMDGPU_GFXHUB_0)
 868                         WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
 869                 else
 870                         WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
 871
 872                 /*
 873                  * Issue a dummy read to wait for the ACK register to
 874                  * be cleared to avoid a false ACK due to the new fast
 875                  * GRBM interface.
 876                  */
 877                 if ((vmhub == AMDGPU_GFXHUB_0) &&
 878                     (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
 879                         RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 880                                       hub->eng_distance * eng);
 881
 882                 for (j = 0; j < adev->usec_timeout; j++) {
 883                         if (vmhub == AMDGPU_GFXHUB_0)
 884                                 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
 885                         else
 886                                 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
 887
 888                         if (tmp & (1 << vmid))
 889                                 break;
 890                         udelay(1);
 891                 }
 892
 893                 inv_req = inv_req2;
 894                 inv_req2 = 0;
 895         } while (inv_req);
 896
 897         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 898         if (use_semaphore) {
 899                 /*
 900                  * add semaphore release after invalidation,
 901                  * write with 0 means semaphore release
 902                  */
 903                 if (vmhub == AMDGPU_GFXHUB_0)
 904                         WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
 905                 else
 906                         WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
 907         }
 908
 909         spin_unlock(&adev->gmc.invalidate_lock);
 910
 911         if (j < adev->usec_timeout)
 912                 return;
 913
 914         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 915 }
 916
 917 /**
 918  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 919  *
 920  * @adev: amdgpu_device pointer
 921  * @pasid: pasid to be flush
 922  * @flush_type: the flush type
 923  * @all_hub: flush all hubs
 924  *
 925  * Flush the TLB for the requested pasid.
 926  */
 927 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 928                                         uint16_t pasid, uint32_t flush_type,
 929                                         bool all_hub)
 930 {
 931         int vmid, i;
 932         signed long r;
 933         uint32_t seq;
 934         uint16_t queried_pasid;
 935         bool ret;
 936         u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;
 937         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 938         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 939
 940         if (amdgpu_in_reset(adev))
 941                 return -EIO;
 942
 943         if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) {
 944                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 945                  * heavy-weight TLB flush (type 2), which flushes
 946                  * both. Due to a race condition with concurrent
 947                  * memory accesses using the same TLB cache line, we
 948                  * still need a second TLB flush after this.
 949                  */
 950                 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 951                                        adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0));
 952                 /* 2 dwords flush + 8 dwords fence */
 953                 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 954
 955                 if (vega20_xgmi_wa)
 956                         ndw += kiq->pmf->invalidate_tlbs_size;
 957
 958                 spin_lock(&adev->gfx.kiq.ring_lock);
 959                 /* 2 dwords flush + 8 dwords fence */
 960                 amdgpu_ring_alloc(ring, ndw);
 961                 if (vega20_xgmi_wa)
 962                         kiq->pmf->kiq_invalidate_tlbs(ring,
 963                                                       pasid, 2, all_hub);
 964                 kiq->pmf->kiq_invalidate_tlbs(ring,
 965                                         pasid, flush_type, all_hub);
 966                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 967                 if (r) {
 968                         amdgpu_ring_undo(ring);
 969                         spin_unlock(&adev->gfx.kiq.ring_lock);
 970                         up_read(&adev->reset_domain->sem);
 971                         return -ETIME;
 972                 }
 973
 974                 amdgpu_ring_commit(ring);
 975                 spin_unlock(&adev->gfx.kiq.ring_lock);
 976                 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);
 977                 if (r < 1) {
 978                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 979                         up_read(&adev->reset_domain->sem);
 980                         return -ETIME;
 981                 }
 982                 up_read(&adev->reset_domain->sem);
 983                 return 0;
 984         }
 985
 986         for (vmid = 1; vmid < 16; vmid++) {
 987
 988                 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 989                                 &queried_pasid);
 990                 if (ret && queried_pasid == pasid) {
 991                         if (all_hub) {
 992                                 for (i = 0; i < adev->num_vmhubs; i++)
 993                                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 994                                                         i, flush_type);
 995                         } else {
 996                                 gmc_v9_0_flush_gpu_tlb(adev, vmid,
 997                                                 AMDGPU_GFXHUB_0, flush_type);
 998                         }
 999                         break;
1000                 }
1001         }
1002
1003         return 0;
1004
1005 }
1006
1007 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
1008                                             unsigned vmid, uint64_t pd_addr)
1009 {
1010         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
1011         struct amdgpu_device *adev = ring->adev;
1012         struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
1013         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
1014         unsigned eng = ring->vm_inv_eng;
1015
1016         /*
1017          * It may lose gpuvm invalidate acknowldege state across power-gating
1018          * off cycle, add semaphore acquire before invalidation and semaphore
1019          * release after invalidation to avoid entering power gated state
1020          * to WA the Issue
1021          */
1022
1023         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1024         if (use_semaphore)
1025                 /* a read return value of 1 means semaphore acuqire */
1026                 amdgpu_ring_emit_reg_wait(ring,
1027                                           hub->vm_inv_eng0_sem +
1028                                           hub->eng_distance * eng, 0x1, 0x1);
1029
1030         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1031                               (hub->ctx_addr_distance * vmid),
1032                               lower_32_bits(pd_addr));
1033
1034         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1035                               (hub->ctx_addr_distance * vmid),
1036                               upper_32_bits(pd_addr));
1037
1038         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
1039                                             hub->eng_distance * eng,
1040                                             hub->vm_inv_eng0_ack +
1041                                             hub->eng_distance * eng,
1042                                             req, 1 << vmid);
1043
1044         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1045         if (use_semaphore)
1046                 /*
1047                  * add semaphore release after invalidation,
1048                  * write with 0 means semaphore release
1049                  */
1050                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1051                                       hub->eng_distance * eng, 0);
1052
1053         return pd_addr;
1054 }
1055
1056 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
1057                                         unsigned pasid)
1058 {
1059         struct amdgpu_device *adev = ring->adev;
1060         uint32_t reg;
1061
1062         /* Do nothing because there's no lut register for mmhub1. */
1063         if (ring->vm_hub == AMDGPU_MMHUB_1)
1064                 return;
1065
1066         if (ring->vm_hub == AMDGPU_GFXHUB_0)
1067                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1068         else
1069                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1070
1071         amdgpu_ring_emit_wreg(ring, reg, pasid);
1072 }
1073
1074 /*
1075  * PTE format on VEGA 10:
1076  * 63:59 reserved
1077  * 58:57 mtype
1078  * 56 F
1079  * 55 L
1080  * 54 P
1081  * 53 SW
1082  * 52 T
1083  * 50:48 reserved
1084  * 47:12 4k physical page base address
1085  * 11:7 fragment
1086  * 6 write
1087  * 5 read
1088  * 4 exe
1089  * 3 Z
1090  * 2 snooped
1091  * 1 system
1092  * 0 valid
1093  *
1094  * PDE format on VEGA 10:
1095  * 63:59 block fragment size
1096  * 58:55 reserved
1097  * 54 P
1098  * 53:48 reserved
1099  * 47:6 physical base address of PD or PTE
1100  * 5:3 reserved
1101  * 2 C
1102  * 1 system
1103  * 0 valid
1104  */
1105
1106 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1107
1108 {
1109         switch (flags) {
1110         case AMDGPU_VM_MTYPE_DEFAULT:
1111                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1112         case AMDGPU_VM_MTYPE_NC:
1113                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1114         case AMDGPU_VM_MTYPE_WC:
1115                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1116         case AMDGPU_VM_MTYPE_RW:
1117                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1118         case AMDGPU_VM_MTYPE_CC:
1119                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1120         case AMDGPU_VM_MTYPE_UC:
1121                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1122         default:
1123                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1124         }
1125 }
1126
1127 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1128                                 uint64_t *addr, uint64_t *flags)
1129 {
1130         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1131                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1132         BUG_ON(*addr & 0xFFFF00000000003FULL);
1133
1134         if (!adev->gmc.translate_further)
1135                 return;
1136
1137         if (level == AMDGPU_VM_PDB1) {
1138                 /* Set the block fragment size */
1139                 if (!(*flags & AMDGPU_PDE_PTE))
1140                         *flags |= AMDGPU_PDE_BFS(0x9);
1141
1142         } else if (level == AMDGPU_VM_PDB0) {
1143                 if (*flags & AMDGPU_PDE_PTE) {
1144                         *flags &= ~AMDGPU_PDE_PTE;
1145                         if (!(*flags & AMDGPU_PTE_VALID))
1146                                 *addr |= 1 << PAGE_SHIFT;
1147                 } else {
1148                         *flags |= AMDGPU_PTE_TF;
1149                 }
1150         }
1151 }
1152
1153 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1154                                          struct amdgpu_bo *bo,
1155                                          struct amdgpu_bo_va_mapping *mapping,
1156                                          uint64_t *flags)
1157 {
1158         struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1159         bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
1160         bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT;
1161         bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1162         unsigned int mtype;
1163         bool snoop = false;
1164
1165         switch (adev->ip_versions[GC_HWIP][0]) {
1166         case IP_VERSION(9, 4, 1):
1167         case IP_VERSION(9, 4, 2):
1168         case IP_VERSION(9, 4, 3):
1169                 if (is_vram) {
1170                         if (bo_adev == adev) {
1171                                 if (uncached)
1172                                         mtype = MTYPE_UC;
1173                                 else if (coherent)
1174                                         mtype = MTYPE_CC;
1175                                 else
1176                                         mtype = MTYPE_RW;
1177                                 /* FIXME: is this still needed? Or does
1178                                  * amdgpu_ttm_tt_pde_flags already handle this?
1179                                  */
1180                                 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
1181                                      adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) &&
1182                                     adev->gmc.xgmi.connected_to_cpu)
1183                                         snoop = true;
1184                         } else {
1185                                 if (uncached || coherent)
1186                                         mtype = MTYPE_UC;
1187                                 else
1188                                         mtype = MTYPE_NC;
1189                                 if (mapping->bo_va->is_xgmi)
1190                                         snoop = true;
1191                         }
1192                 } else {
1193                         if (uncached || coherent)
1194                                 mtype = MTYPE_UC;
1195                         else
1196                                 mtype = MTYPE_NC;
1197                         /* FIXME: is this still needed? Or does
1198                          * amdgpu_ttm_tt_pde_flags already handle this?
1199                          */
1200                         snoop = true;
1201                 }
1202                 break;
1203         default:
1204                 if (uncached || coherent)
1205                         mtype = MTYPE_UC;
1206                 else
1207                         mtype = MTYPE_NC;
1208
1209                 /* FIXME: is this still needed? Or does
1210                  * amdgpu_ttm_tt_pde_flags already handle this?
1211                  */
1212                 if (!is_vram)
1213                         snoop = true;
1214         }
1215
1216         if (mtype != MTYPE_NC)
1217                 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1218                          AMDGPU_PTE_MTYPE_VG10(mtype);
1219         *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1220 }
1221
1222 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1223                                 struct amdgpu_bo_va_mapping *mapping,
1224                                 uint64_t *flags)
1225 {
1226         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
1227
1228         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1229         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1230
1231         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1232         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1233
1234         if (mapping->flags & AMDGPU_PTE_PRT) {
1235                 *flags |= AMDGPU_PTE_PRT;
1236                 *flags &= ~AMDGPU_PTE_VALID;
1237         }
1238
1239         if (bo && bo->tbo.resource)
1240                 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,
1241                                              mapping, flags);
1242 }
1243
1244 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1245 {
1246         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1247         unsigned size;
1248
1249         /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1250
1251         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1252                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1253         } else {
1254                 u32 viewport;
1255
1256                 switch (adev->ip_versions[DCE_HWIP][0]) {
1257                 case IP_VERSION(1, 0, 0):
1258                 case IP_VERSION(1, 0, 1):
1259                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1260                         size = (REG_GET_FIELD(viewport,
1261                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1262                                 REG_GET_FIELD(viewport,
1263                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1264                                 4);
1265                         break;
1266                 case IP_VERSION(2, 1, 0):
1267                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1268                         size = (REG_GET_FIELD(viewport,
1269                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1270                                 REG_GET_FIELD(viewport,
1271                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1272                                 4);
1273                         break;
1274                 default:
1275                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1276                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1277                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1278                                 4);
1279                         break;
1280                 }
1281         }
1282
1283         return size;
1284 }
1285
1286 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1287         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1288         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1289         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1290         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1291         .map_mtype = gmc_v9_0_map_mtype,
1292         .get_vm_pde = gmc_v9_0_get_vm_pde,
1293         .get_vm_pte = gmc_v9_0_get_vm_pte,
1294         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1295 };
1296
1297 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1298 {
1299         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1300 }
1301
1302 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1303 {
1304         switch (adev->ip_versions[UMC_HWIP][0]) {
1305         case IP_VERSION(6, 0, 0):
1306                 adev->umc.funcs = &umc_v6_0_funcs;
1307                 break;
1308         case IP_VERSION(6, 1, 1):
1309                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1310                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1311                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1312                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1313                 adev->umc.retire_unit = 1;
1314                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1315                 adev->umc.ras = &umc_v6_1_ras;
1316                 break;
1317         case IP_VERSION(6, 1, 2):
1318                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1319                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1320                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1321                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1322                 adev->umc.retire_unit = 1;
1323                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1324                 adev->umc.ras = &umc_v6_1_ras;
1325                 break;
1326         case IP_VERSION(6, 7, 0):
1327                 adev->umc.max_ras_err_cnt_per_query =
1328                         UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1329                 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1330                 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1331                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1332                 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1333                 if (!adev->gmc.xgmi.connected_to_cpu)
1334                         adev->umc.ras = &umc_v6_7_ras;
1335                 if (1 & adev->smuio.funcs->get_die_id(adev))
1336                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1337                 else
1338                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1339                 break;
1340         default:
1341                 break;
1342         }
1343 }
1344
1345 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1346 {
1347         switch (adev->ip_versions[MMHUB_HWIP][0]) {
1348         case IP_VERSION(9, 4, 1):
1349                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1350                 break;
1351         case IP_VERSION(9, 4, 2):
1352                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1353                 break;
1354         case IP_VERSION(1, 8, 0):
1355                 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1356                 break;
1357         default:
1358                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1359                 break;
1360         }
1361 }
1362
1363 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1364 {
1365         switch (adev->ip_versions[MMHUB_HWIP][0]) {
1366         case IP_VERSION(9, 4, 0):
1367                 adev->mmhub.ras = &mmhub_v1_0_ras;
1368                 break;
1369         case IP_VERSION(9, 4, 1):
1370                 adev->mmhub.ras = &mmhub_v9_4_ras;
1371                 break;
1372         case IP_VERSION(9, 4, 2):
1373                 adev->mmhub.ras = &mmhub_v1_7_ras;
1374                 break;
1375         default:
1376                 /* mmhub ras is not available */
1377                 break;
1378         }
1379 }
1380
1381 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1382 {
1383         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
1384                 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1385         else
1386                 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1387 }
1388
1389 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1390 {
1391         adev->hdp.ras = &hdp_v4_0_ras;
1392 }
1393
1394 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1395 {
1396         struct amdgpu_mca *mca = &adev->mca;
1397
1398         /* is UMC the right IP to check for MCA?  Maybe DF? */
1399         switch (adev->ip_versions[UMC_HWIP][0]) {
1400         case IP_VERSION(6, 7, 0):
1401                 if (!adev->gmc.xgmi.connected_to_cpu) {
1402                         mca->mp0.ras = &mca_v3_0_mp0_ras;
1403                         mca->mp1.ras = &mca_v3_0_mp1_ras;
1404                         mca->mpio.ras = &mca_v3_0_mpio_ras;
1405                 }
1406                 break;
1407         default:
1408                 break;
1409         }
1410 }
1411
1412 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1413 {
1414         if (!adev->gmc.xgmi.connected_to_cpu)
1415                 adev->gmc.xgmi.ras = &xgmi_ras;
1416 }
1417
1418 static int gmc_v9_0_early_init(void *handle)
1419 {
1420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421
1422         /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */
1423         if (adev->asic_type == CHIP_VEGA20 ||
1424             adev->asic_type == CHIP_ARCTURUS)
1425                 adev->gmc.xgmi.supported = true;
1426
1427         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) {
1428                 adev->gmc.xgmi.supported = true;
1429                 adev->gmc.xgmi.connected_to_cpu =
1430                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1431         }
1432
1433         gmc_v9_0_set_gmc_funcs(adev);
1434         gmc_v9_0_set_irq_funcs(adev);
1435         gmc_v9_0_set_umc_funcs(adev);
1436         gmc_v9_0_set_mmhub_funcs(adev);
1437         gmc_v9_0_set_mmhub_ras_funcs(adev);
1438         gmc_v9_0_set_gfxhub_funcs(adev);
1439         gmc_v9_0_set_hdp_ras_funcs(adev);
1440         gmc_v9_0_set_mca_ras_funcs(adev);
1441         gmc_v9_0_set_xgmi_ras_funcs(adev);
1442
1443         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1444         adev->gmc.shared_aperture_end =
1445                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1446         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1447         adev->gmc.private_aperture_end =
1448                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1449
1450         return 0;
1451 }
1452
1453 static int gmc_v9_0_late_init(void *handle)
1454 {
1455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1456         int r;
1457
1458         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1459         if (r)
1460                 return r;
1461
1462         /*
1463          * Workaround performance drop issue with VBIOS enables partial
1464          * writes, while disables HBM ECC for vega10.
1465          */
1466         if (!amdgpu_sriov_vf(adev) &&
1467             (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) {
1468                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1469                         if (adev->df.funcs &&
1470                             adev->df.funcs->enable_ecc_force_par_wr_rmw)
1471                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1472                 }
1473         }
1474
1475         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1476                 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
1477                     adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
1478                         adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1479
1480                 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops &&
1481                     adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count)
1482                         adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1483         }
1484
1485         r = amdgpu_gmc_ras_late_init(adev);
1486         if (r)
1487                 return r;
1488
1489         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1490 }
1491
1492 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1493                                         struct amdgpu_gmc *mc)
1494 {
1495         u64 base = adev->mmhub.funcs->get_fb_location(adev);
1496
1497         /* add the xgmi offset of the physical node */
1498         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1499         if (adev->gmc.xgmi.connected_to_cpu) {
1500                 amdgpu_gmc_sysvm_location(adev, mc);
1501         } else {
1502                 amdgpu_gmc_vram_location(adev, mc, base);
1503                 amdgpu_gmc_gart_location(adev, mc);
1504                 amdgpu_gmc_agp_location(adev, mc);
1505         }
1506         /* base offset of vram pages */
1507         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1508
1509         /* XXX: add the xgmi offset of the physical node? */
1510         adev->vm_manager.vram_base_offset +=
1511                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1512 }
1513
1514 /**
1515  * gmc_v9_0_mc_init - initialize the memory controller driver params
1516  *
1517  * @adev: amdgpu_device pointer
1518  *
1519  * Look up the amount of vram, vram width, and decide how to place
1520  * vram and gart within the GPU's physical address space.
1521  * Returns 0 for success.
1522  */
1523 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1524 {
1525         int r;
1526
1527         /* size in MB on si */
1528         adev->gmc.mc_vram_size =
1529                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1530         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1531
1532         if (!(adev->flags & AMD_IS_APU) &&
1533             !adev->gmc.xgmi.connected_to_cpu) {
1534                 r = amdgpu_device_resize_fb_bar(adev);
1535                 if (r)
1536                         return r;
1537         }
1538         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1539         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1540
1541 #ifdef CONFIG_X86_64
1542         /*
1543          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1544          * interface can use VRAM through here as it appears system reserved
1545          * memory in host address space.
1546          *
1547          * For APUs, VRAM is just the stolen system memory and can be accessed
1548          * directly.
1549          *
1550          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1551          */
1552
1553         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1554         if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1555             (adev->gmc.xgmi.supported &&
1556              adev->gmc.xgmi.connected_to_cpu)) {
1557                 adev->gmc.aper_base =
1558                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1559                         adev->gmc.xgmi.physical_node_id *
1560                         adev->gmc.xgmi.node_segment_size;
1561                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1562         }
1563
1564 #endif
1565         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1566
1567         /* set the gart size */
1568         if (amdgpu_gart_size == -1) {
1569                 switch (adev->ip_versions[GC_HWIP][0]) {
1570                 case IP_VERSION(9, 0, 1):  /* all engines support GPUVM */
1571                 case IP_VERSION(9, 2, 1):  /* all engines support GPUVM */
1572                 case IP_VERSION(9, 4, 0):
1573                 case IP_VERSION(9, 4, 1):
1574                 case IP_VERSION(9, 4, 2):
1575                 case IP_VERSION(9, 4, 3):
1576                 default:
1577                         adev->gmc.gart_size = 512ULL << 20;
1578                         break;
1579                 case IP_VERSION(9, 1, 0):   /* DCE SG support */
1580                 case IP_VERSION(9, 2, 2):   /* DCE SG support */
1581                 case IP_VERSION(9, 3, 0):
1582                         adev->gmc.gart_size = 1024ULL << 20;
1583                         break;
1584                 }
1585         } else {
1586                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1587         }
1588
1589         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1590
1591         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1592
1593         return 0;
1594 }
1595
1596 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1597 {
1598         int r;
1599
1600         if (adev->gart.bo) {
1601                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1602                 return 0;
1603         }
1604
1605         if (adev->gmc.xgmi.connected_to_cpu) {
1606                 adev->gmc.vmid0_page_table_depth = 1;
1607                 adev->gmc.vmid0_page_table_block_size = 12;
1608         } else {
1609                 adev->gmc.vmid0_page_table_depth = 0;
1610                 adev->gmc.vmid0_page_table_block_size = 0;
1611         }
1612
1613         /* Initialize common gart structure */
1614         r = amdgpu_gart_init(adev);
1615         if (r)
1616                 return r;
1617         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1618         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1619                                  AMDGPU_PTE_EXECUTABLE;
1620
1621         r = amdgpu_gart_table_vram_alloc(adev);
1622         if (r)
1623                 return r;
1624
1625         if (adev->gmc.xgmi.connected_to_cpu) {
1626                 r = amdgpu_gmc_pdb0_alloc(adev);
1627         }
1628
1629         return r;
1630 }
1631
1632 /**
1633  * gmc_v9_0_save_registers - saves regs
1634  *
1635  * @adev: amdgpu_device pointer
1636  *
1637  * This saves potential register values that should be
1638  * restored upon resume
1639  */
1640 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1641 {
1642         if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) ||
1643             (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1)))
1644                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1645 }
1646
1647 static int gmc_v9_0_sw_init(void *handle)
1648 {
1649         int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
1650         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1651
1652         adev->gfxhub.funcs->init(adev);
1653
1654         adev->mmhub.funcs->init(adev);
1655
1656         spin_lock_init(&adev->gmc.invalidate_lock);
1657
1658         r = amdgpu_atomfirmware_get_vram_info(adev,
1659                 &vram_width, &vram_type, &vram_vendor);
1660         if (amdgpu_sriov_vf(adev))
1661                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1662                  * and DF related registers is not readable, seems hardcord is the
1663                  * only way to set the correct vram_width
1664                  */
1665                 adev->gmc.vram_width = 2048;
1666         else if (amdgpu_emu_mode != 1)
1667                 adev->gmc.vram_width = vram_width;
1668
1669         if (!adev->gmc.vram_width) {
1670                 int chansize, numchan;
1671
1672                 /* hbm memory channel size */
1673                 if (adev->flags & AMD_IS_APU)
1674                         chansize = 64;
1675                 else
1676                         chansize = 128;
1677                 if (adev->df.funcs &&
1678                     adev->df.funcs->get_hbm_channel_number) {
1679                         numchan = adev->df.funcs->get_hbm_channel_number(adev);
1680                         adev->gmc.vram_width = numchan * chansize;
1681                 }
1682         }
1683
1684         adev->gmc.vram_type = vram_type;
1685         adev->gmc.vram_vendor = vram_vendor;
1686         switch (adev->ip_versions[GC_HWIP][0]) {
1687         case IP_VERSION(9, 1, 0):
1688         case IP_VERSION(9, 2, 2):
1689                 adev->num_vmhubs = 2;
1690
1691                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1692                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1693                 } else {
1694                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1695                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1696                         adev->gmc.translate_further =
1697                                 adev->vm_manager.num_level > 1;
1698                 }
1699                 break;
1700         case IP_VERSION(9, 0, 1):
1701         case IP_VERSION(9, 2, 1):
1702         case IP_VERSION(9, 4, 0):
1703         case IP_VERSION(9, 3, 0):
1704         case IP_VERSION(9, 4, 2):
1705         case IP_VERSION(9, 4, 3):
1706                 adev->num_vmhubs = 2;
1707
1708
1709                 /*
1710                  * To fulfill 4-level page support,
1711                  * vm size is 256TB (48bit), maximum size of Vega10,
1712                  * block size 512 (9bit)
1713                  */
1714                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1715                 if (amdgpu_sriov_vf(adev))
1716                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1717                 else
1718                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1719                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
1720                         adev->gmc.translate_further = adev->vm_manager.num_level > 1;
1721                 break;
1722         case IP_VERSION(9, 4, 1):
1723                 adev->num_vmhubs = 3;
1724
1725                 /* Keep the vm size same with Vega20 */
1726                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1727                 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
1728                 break;
1729         default:
1730                 break;
1731         }
1732
1733         /* This interrupt is VMC page fault.*/
1734         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1735                                 &adev->gmc.vm_fault);
1736         if (r)
1737                 return r;
1738
1739         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
1740                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1741                                         &adev->gmc.vm_fault);
1742                 if (r)
1743                         return r;
1744         }
1745
1746         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1747                                 &adev->gmc.vm_fault);
1748
1749         if (r)
1750                 return r;
1751
1752         if (!amdgpu_sriov_vf(adev) &&
1753             !adev->gmc.xgmi.connected_to_cpu) {
1754                 /* interrupt sent to DF. */
1755                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1756                                       &adev->gmc.ecc_irq);
1757                 if (r)
1758                         return r;
1759         }
1760
1761         /* Set the internal MC address mask
1762          * This is the max address of the GPU's
1763          * internal address space.
1764          */
1765         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1766
1767         dma_addr_bits = adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ? 48:44;
1768         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
1769         if (r) {
1770                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1771                 return r;
1772         }
1773         adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
1774
1775         r = gmc_v9_0_mc_init(adev);
1776         if (r)
1777                 return r;
1778
1779         amdgpu_gmc_get_vbios_allocations(adev);
1780
1781         /* Memory manager */
1782         r = amdgpu_bo_init(adev);
1783         if (r)
1784                 return r;
1785
1786         r = gmc_v9_0_gart_init(adev);
1787         if (r)
1788                 return r;
1789
1790         /*
1791          * number of VMs
1792          * VMID 0 is reserved for System
1793          * amdgpu graphics/compute will use VMIDs 1..n-1
1794          * amdkfd will use VMIDs n..15
1795          *
1796          * The first KFD VMID is 8 for GPUs with graphics, 3 for
1797          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1798          * for video processing.
1799          */
1800         adev->vm_manager.first_kfd_vmid =
1801                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
1802                  adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
1803                  adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) ? 3 : 8;
1804
1805         amdgpu_vm_manager_init(adev);
1806
1807         gmc_v9_0_save_registers(adev);
1808
1809         r = amdgpu_gmc_ras_sw_init(adev);
1810         if (r)
1811                 return r;
1812
1813         return 0;
1814 }
1815
1816 static int gmc_v9_0_sw_fini(void *handle)
1817 {
1818         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1819
1820         amdgpu_gmc_ras_fini(adev);
1821         amdgpu_gem_force_release(adev);
1822         amdgpu_vm_manager_fini(adev);
1823         amdgpu_gart_table_vram_free(adev);
1824         amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
1825         amdgpu_bo_fini(adev);
1826
1827         return 0;
1828 }
1829
1830 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1831 {
1832
1833         switch (adev->ip_versions[MMHUB_HWIP][0]) {
1834         case IP_VERSION(9, 0, 0):
1835                 if (amdgpu_sriov_vf(adev))
1836                         break;
1837                 fallthrough;
1838         case IP_VERSION(9, 4, 0):
1839                 soc15_program_register_sequence(adev,
1840                                                 golden_settings_mmhub_1_0_0,
1841                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1842                 soc15_program_register_sequence(adev,
1843                                                 golden_settings_athub_1_0_0,
1844                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1845                 break;
1846         case IP_VERSION(9, 1, 0):
1847         case IP_VERSION(9, 2, 0):
1848                 /* TODO for renoir */
1849                 soc15_program_register_sequence(adev,
1850                                                 golden_settings_athub_1_0_0,
1851                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1852                 break;
1853         default:
1854                 break;
1855         }
1856 }
1857
1858 /**
1859  * gmc_v9_0_restore_registers - restores regs
1860  *
1861  * @adev: amdgpu_device pointer
1862  *
1863  * This restores register values, saved at suspend.
1864  */
1865 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1866 {
1867         if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) ||
1868             (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) {
1869                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1870                 WARN_ON(adev->gmc.sdpif_register !=
1871                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1872         }
1873 }
1874
1875 /**
1876  * gmc_v9_0_gart_enable - gart enable
1877  *
1878  * @adev: amdgpu_device pointer
1879  */
1880 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1881 {
1882         int r;
1883
1884         if (adev->gmc.xgmi.connected_to_cpu)
1885                 amdgpu_gmc_init_pdb0(adev);
1886
1887         if (adev->gart.bo == NULL) {
1888                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1889                 return -EINVAL;
1890         }
1891
1892         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1893
1894         if (!adev->in_s0ix) {
1895                 r = adev->gfxhub.funcs->gart_enable(adev);
1896                 if (r)
1897                         return r;
1898         }
1899
1900         r = adev->mmhub.funcs->gart_enable(adev);
1901         if (r)
1902                 return r;
1903
1904         DRM_INFO("PCIE GART of %uM enabled.\n",
1905                  (unsigned)(adev->gmc.gart_size >> 20));
1906         if (adev->gmc.pdb0_bo)
1907                 DRM_INFO("PDB0 located at 0x%016llX\n",
1908                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
1909         DRM_INFO("PTB located at 0x%016llX\n",
1910                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1911
1912         return 0;
1913 }
1914
1915 static int gmc_v9_0_hw_init(void *handle)
1916 {
1917         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1918         bool value;
1919         int i, r;
1920
1921         /* The sequence of these two function calls matters.*/
1922         gmc_v9_0_init_golden_registers(adev);
1923
1924         if (adev->mode_info.num_crtc) {
1925                 /* Lockout access through VGA aperture*/
1926                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1927                 /* disable VGA render */
1928                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1929         }
1930
1931         if (adev->mmhub.funcs->update_power_gating)
1932                 adev->mmhub.funcs->update_power_gating(adev, true);
1933
1934         adev->hdp.funcs->init_registers(adev);
1935
1936         /* After HDP is initialized, flush HDP.*/
1937         adev->hdp.funcs->flush_hdp(adev, NULL);
1938
1939         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1940                 value = false;
1941         else
1942                 value = true;
1943
1944         if (!amdgpu_sriov_vf(adev)) {
1945                 if (!adev->in_s0ix)
1946                         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1947                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1948         }
1949         for (i = 0; i < adev->num_vmhubs; ++i) {
1950                 if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0))
1951                         continue;
1952                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1953         }
1954
1955         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1956                 adev->umc.funcs->init_registers(adev);
1957
1958         r = gmc_v9_0_gart_enable(adev);
1959         if (r)
1960                 return r;
1961
1962         if (amdgpu_emu_mode == 1)
1963                 return amdgpu_gmc_vram_checking(adev);
1964         else
1965                 return r;
1966 }
1967
1968 /**
1969  * gmc_v9_0_gart_disable - gart disable
1970  *
1971  * @adev: amdgpu_device pointer
1972  *
1973  * This disables all VM page table.
1974  */
1975 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1976 {
1977         if (!adev->in_s0ix)
1978                 adev->gfxhub.funcs->gart_disable(adev);
1979         adev->mmhub.funcs->gart_disable(adev);
1980 }
1981
1982 static int gmc_v9_0_hw_fini(void *handle)
1983 {
1984         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1985
1986         gmc_v9_0_gart_disable(adev);
1987
1988         if (amdgpu_sriov_vf(adev)) {
1989                 /* full access mode, so don't touch any GMC register */
1990                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1991                 return 0;
1992         }
1993
1994         /*
1995          * Pair the operations did in gmc_v9_0_hw_init and thus maintain
1996          * a correct cached state for GMC. Otherwise, the "gate" again
1997          * operation on S3 resuming will fail due to wrong cached state.
1998          */
1999         if (adev->mmhub.funcs->update_power_gating)
2000                 adev->mmhub.funcs->update_power_gating(adev, false);
2001
2002         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2003         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2004
2005         return 0;
2006 }
2007
2008 static int gmc_v9_0_suspend(void *handle)
2009 {
2010         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2011
2012         return gmc_v9_0_hw_fini(adev);
2013 }
2014
2015 static int gmc_v9_0_resume(void *handle)
2016 {
2017         int r;
2018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2019
2020         r = gmc_v9_0_hw_init(adev);
2021         if (r)
2022                 return r;
2023
2024         amdgpu_vmid_reset_all(adev);
2025
2026         return 0;
2027 }
2028
2029 static bool gmc_v9_0_is_idle(void *handle)
2030 {
2031         /* MC is always ready in GMC v9.*/
2032         return true;
2033 }
2034
2035 static int gmc_v9_0_wait_for_idle(void *handle)
2036 {
2037         /* There is no need to wait for MC idle in GMC v9.*/
2038         return 0;
2039 }
2040
2041 static int gmc_v9_0_soft_reset(void *handle)
2042 {
2043         /* XXX for emulation.*/
2044         return 0;
2045 }
2046
2047 static int gmc_v9_0_set_clockgating_state(void *handle,
2048                                         enum amd_clockgating_state state)
2049 {
2050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2051
2052         adev->mmhub.funcs->set_clockgating(adev, state);
2053
2054         athub_v1_0_set_clockgating(adev, state);
2055
2056         return 0;
2057 }
2058
2059 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
2060 {
2061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2062
2063         adev->mmhub.funcs->get_clockgating(adev, flags);
2064
2065         athub_v1_0_get_clockgating(adev, flags);
2066 }
2067
2068 static int gmc_v9_0_set_powergating_state(void *handle,
2069                                         enum amd_powergating_state state)
2070 {
2071         return 0;
2072 }
2073
2074 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2075         .name = "gmc_v9_0",
2076         .early_init = gmc_v9_0_early_init,
2077         .late_init = gmc_v9_0_late_init,
2078         .sw_init = gmc_v9_0_sw_init,
2079         .sw_fini = gmc_v9_0_sw_fini,
2080         .hw_init = gmc_v9_0_hw_init,
2081         .hw_fini = gmc_v9_0_hw_fini,
2082         .suspend = gmc_v9_0_suspend,
2083         .resume = gmc_v9_0_resume,
2084         .is_idle = gmc_v9_0_is_idle,
2085         .wait_for_idle = gmc_v9_0_wait_for_idle,
2086         .soft_reset = gmc_v9_0_soft_reset,
2087         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2088         .set_powergating_state = gmc_v9_0_set_powergating_state,
2089         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2090 };
2091
2092 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
2093 {
2094         .type = AMD_IP_BLOCK_TYPE_GMC,
2095         .major = 9,
2096         .minor = 0,
2097         .rev = 0,
2098         .funcs = &gmc_v9_0_ip_funcs,
2099 };