Rob Herring [Thu, 17 Mar 2016 16:21:23 +0000 (17:21 +0100)]
fastboot: allow retrieving fastboot variables from env
Some boards need to expose device specific variable through fastboot
(to adpat the flashing script depending on hardware revision for
example).
Provide a way to expose custom fastboot variables. Note that all
variables meant to be exposed through fastboot should be be prefixed
with 'fastboot.', the variable should not exceed 32 bytes (including
the prefix and the trailing '\0') and the variable content should
fit in the response buffer (60 bytes excluding the 'OKAY' prefix and
the trailing '\0').
Tom Rini [Wed, 16 Mar 2016 23:55:55 +0000 (19:55 -0400)]
arm: clang: Update support slightly
- Move most of the flags required into LLVM_RELFLAGS to test at build
time instead of requiring them to be passed in.
- Update doc/README.clang to reflect this
- Switch to rpi_2 as the example as it's closer to working out of the
box than rpi is.
Alexander Graf [Wed, 30 Mar 2016 15:53:56 +0000 (17:53 +0200)]
sunxi: Reserve ATF memory space on A64
On the A64 we usually boot with ATF running in EL3. ATF as it is available
today resides in the first 16MB of RAM. So we should make sure we reserve
that space in our memory maps.
Alexander Graf [Tue, 29 Mar 2016 15:29:09 +0000 (17:29 +0200)]
sunxi: Explicitly cast u32 pointer conversions
Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.
Alexander Graf [Tue, 29 Mar 2016 15:29:07 +0000 (17:29 +0200)]
sunxi: Depend SPL configs on SUPPORT_SPL
We currently depend SPL config options on specific machine types which doesn't
scale. Fortunately there's already a kconfig variable that tells us whether we
want to build SPL code at all, so just depend them on this.
Alexander Graf [Tue, 29 Mar 2016 15:29:06 +0000 (17:29 +0200)]
sunxi: Move cpu independent code to mach directory
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.
Move all files that are not really tied to armv7 into a new mach-sunxi
directory.
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:59 +0000 (00:26 +0800)]
sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig
The Cubietruck Plus uses all 3 USB controllers:
- USB OTG functions are provided by the musb USB OTG controller
- Onboard SATA is provied by a USB-SATA bridge connected to USB1
- The USB host ports on the board are provided by an HSIC USB hub
Masahiro Yamada [Tue, 29 Mar 2016 11:18:45 +0000 (20:18 +0900)]
ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64
Currently, these functions assume #address-cells and #size-cells are
both one. Fix them to support 64bit DTB.
Also, I am fixing a buffer overrun bug while I am here. The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of
iteration in the loop should be limited by that CONFIG.
Masahiro Yamada [Thu, 24 Mar 2016 13:32:47 +0000 (22:32 +0900)]
pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driver
The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20
(as far as used in boot-loader), so this commit makes the driver
shared between the two SoCs.
Masahiro Yamada [Thu, 24 Mar 2016 13:32:45 +0000 (22:32 +0900)]
pinctrl: uniphier: support per-pin input enable for new SoCs
Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin. (While, existing ones only support it
per pin-group.) This commit prepares the core part for that.
Masahiro Yamada [Thu, 24 Mar 2016 13:32:44 +0000 (22:32 +0900)]
pinctrl: uniphier: introduce capability flag
The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens
because pinctrl drivers include really SoC-specific stuff.
This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones. Having flags would be better than
adding new members every time a new SoC-specific capability comes up.
At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.
Masahiro Yamada [Thu, 24 Mar 2016 13:32:43 +0000 (22:32 +0900)]
pinctrl: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Masahiro Yamada [Thu, 24 Mar 2016 13:32:42 +0000 (22:32 +0900)]
mmc: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Masahiro Yamada [Thu, 24 Mar 2016 13:32:41 +0000 (22:32 +0900)]
gpio: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Masahiro Yamada [Thu, 24 Mar 2016 13:32:40 +0000 (22:32 +0900)]
i2c: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Masahiro Yamada [Thu, 24 Mar 2016 13:32:39 +0000 (22:32 +0900)]
clk: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Masahiro Yamada [Thu, 24 Mar 2016 13:32:38 +0000 (22:32 +0900)]
serial: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Masahiro Yamada [Thu, 24 Mar 2016 13:22:23 +0000 (22:22 +0900)]
ARM: uniphier: make u-boot-with-spl.bin really available
Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image")
claimed that u-boot-with-spl.bin would be useful in its commit log,
but it was not available because the commit missed to define
CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined
either (see include/config_fallbacks.h). So, the SPL image is not
padded correctly.
Signed-off-by: Graham Moore <[email protected]>
[Brian: parentheses around macro arg] Signed-off-by: Brian Norris <[email protected]>
[Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <[email protected]>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:49 +0000 (00:26 +0800)]
sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
The schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some
Allwinner-based boards set it to 3.0V to conserve power. Since the
h8_homlet_v2 is a set-top box board with external power, there is
no such requirement.
Michael Haas [Fri, 25 Mar 2016 17:22:50 +0000 (18:22 +0100)]
net: phy: Optionally force master mode for RTL PHY
This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.
This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.
There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.
Hans de Goede [Thu, 24 Mar 2016 21:38:23 +0000 (22:38 +0100)]
sunxi: Print soc-id from sram controller for sun8i boards
As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.
Hans de Goede [Thu, 24 Mar 2016 21:37:08 +0000 (22:37 +0100)]
sunxi: Add conditional magic sram poke for A33
I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.
Saksham Jain [Wed, 23 Mar 2016 10:54:44 +0000 (16:24 +0530)]
SECURE BOOT: Halt execution when secure boot fail
In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.
Add esbh_halt() after the reset to make sure execution stops.
Saksham Jain [Wed, 23 Mar 2016 10:54:43 +0000 (16:24 +0530)]
SECURE_BOOT: Use default bootargs
For secure boot, currently we were using fixed bootargs for all SoCs.
This is not needed and we can use the bootargs which are used in
non-secure boot.
Saksham Jain [Wed, 23 Mar 2016 10:54:42 +0000 (16:24 +0530)]
crypto/fsl: Make CAAM transactions cacheable
This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.
To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.
So, this commit makes CAAM transcations as write back with write and
read allocate.
Saksham Jain [Wed, 23 Mar 2016 10:54:41 +0000 (16:24 +0530)]
crypto/fsl: Correct 64-bit write when MMU disabled
When MMU is disabled, 64-bit write must be aligned at 64-bit
boundary. Becaue the memory location is not guaranteed to be 64-bit
aligned, the 64-bit write needs to be split into two 32-bit writes
to avoid the alignment exception.
Saksham Jain [Wed, 23 Mar 2016 10:54:39 +0000 (16:24 +0530)]
armv8: ls2080: Add config for endianess of CCSR GUR
The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Saksham Jain [Wed, 23 Mar 2016 10:54:37 +0000 (16:24 +0530)]
armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDR
To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.
For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.
Saksham Jain [Wed, 23 Mar 2016 10:54:36 +0000 (16:24 +0530)]
armv8: ls2080: Add bootscript header addr for secure boot
During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.
When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.
For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.
Saksham Jain [Wed, 23 Mar 2016 10:54:35 +0000 (16:24 +0530)]
armv8: ls2080rdb: ls2080qds: Add secure boot support
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Saksham Jain [Wed, 23 Mar 2016 10:54:34 +0000 (16:24 +0530)]
armv8: fsl-lsch3: Add new header for secure boot
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Saksham Jain [Wed, 23 Mar 2016 10:54:33 +0000 (16:24 +0530)]
armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFG
Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.
Peng Fan [Fri, 11 Mar 2016 08:47:50 +0000 (16:47 +0800)]
dm: i2c: mxc_i2c: implement i2c_idle_bus
Implement i2c_idle_bus in driver, then setup_i2c can
be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL.
The i2c_idle_bus force bus idle flow follows setup_i2c in
arch/arm/imx-common/i2c-mxv7.c
Implement bus recovery methods for i2c-imx so we can recover from
situations where SCL/SDA are stuck low.
Once i2c bus SCL/SDA are stuck low during transfer, config the i2c
pinctrl to gpio mode by calling pinctrl sleep set function, and then
use GPIO to emulate the i2c protocol to send nine dummy clock to recover
i2c device. After recovery, set i2c pinctrl to default group setting.
"
See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed
description.
1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus.
2. Discard the __weak attribute for i2c_idle_bus and implement it,
since we have pinctrl driver/driver model gpio driver. We can
use device tree, but not let board code to do this.
3. gpio state for mxc_i2c is not a must, but it is recommended. If
there is no gpio state, driver will give tips, but not fail.
4. The i2c controller was first probed, default pinctrl state will
be used, so when need to use gpio function, need to do
"pinctrl_select_state(dev, "gpio")" and after force bus idle,
need to switch back "pinctrl_select_state(dev, "default")".
This is example about how to use the gpio force bus
idle function:
"
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "okay";
[....]
};
Lokesh Vutla [Thu, 24 Mar 2016 10:32:00 +0000 (16:02 +0530)]
ARM: asm: types: Introduce DMA_ADDR_T_64BIT
dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actual
bus addresses.
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
DMA still use 32bit address like in case of DRA7 and Keystone platforms.
This is inspired from the Linux kernel types implementation[1]
SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.
Stephen Warren [Sat, 19 Mar 2016 03:41:38 +0000 (21:41 -0600)]
serial: add BCM283x mini UART driver
The RPi3 typically uses the regular UART for high-speed communication with
the Bluetooth device, leaving us the mini UART to use for the serial
console. Add support for this UART so we can use it.
Roger Quadros [Fri, 18 Mar 2016 11:18:12 +0000 (13:18 +0200)]
board: ti: am57xx: Set ethernet MAC addresses from EEPROM to env
The MAC addresses for the PRU Ethernet ports will be available in the
board EEPROM as an address range. Populate those MAC addresses (if valid)
into the u-boot environment so that they can be passed on to the
device tree during fdt_fixup_ethernet().
projects / u-boot.git / log