Joe Hershberger [Wed, 20 May 2015 19:27:26 +0000 (14:27 -0500)]
net: Handle ethaddr changes as an env callback
When the ethaddr is changed in the env, update the device pdata at the
same time (only if it is probed for the DM case; only if registered for
the non-DM case). Again this gets us closer to completely non-polled
env needed to simplify the net_loop.
This requires that the NET feature select the REGEX feature.
Joe Hershberger [Wed, 20 May 2015 19:27:23 +0000 (14:27 -0500)]
net: Use env callbacks for net variables
Instead of checking for changes to the env each time we enter the
net_loop, use the env callbacks to update the values of the variables.
Don't update the variables when the source was programmatic, since the
variables were the source of the new value.
Joe Hershberger [Wed, 20 May 2015 19:27:21 +0000 (14:27 -0500)]
env: Distinguish finer between source of env change
We already could tell the difference in the callback between an import
and "other" which we called interactive. Now add further distinction
between interactive (i.e. running env set / env edit / env ask / etc.
from the U-Boot command line) and programmatic (i.e. when u-boot source
calls any variant of setenv() ).
Joe Hershberger [Wed, 20 May 2015 19:27:18 +0000 (14:27 -0500)]
env: Simplify the reverse_strstr() interface
The logic to find the whole matching name was split needlessly between
the reverse_strstr function and its caller. Fully contain it to make the
interface for calling it more consistent.
Joe Hershberger [Wed, 20 May 2015 19:27:14 +0000 (14:27 -0500)]
sandbox: Cleanup order and extra defines in defconfig
The defconfigs should not be edited directly. They should be generated
by editing the .config (through menuconfig or whatever) and then run
make savedefconfig to have the Kconfig system generate a clean defconfig
I did this for sandbox here with no actual changes.
Alison Wang [Tue, 21 Apr 2015 08:04:38 +0000 (16:04 +0800)]
arm: ls102xa: Adjust the load address of U-Boot for NOR boot
The original load address of U-Boot is 0x67f80000. The address
space of NOR flash is 0x60000000 to 0x67ffffff. It will cause
the size of u-boot couldn't be larger than 512K. As more features
are supported in u-boot, the size of u-boot is larger than 512K.
To fix this issue, the load address of U-Boot for NOR boot is
adjusted to 0x60100000.
In RCW, the PBI command needs to change as follows:
.pbi
-write 0xee0200, 0x67f80000
+write 0xee0200, 0x60100000
.end
Joe Hershberger [Mon, 4 May 2015 19:55:14 +0000 (14:55 -0500)]
net: Remove all references to CONFIG_ETHADDR and friends
We really don't want boards defining fixed MAC addresses in their config
so we just remove the option to set it in a fixed way. If you must have
a MAC address that was not provisioned, then use the random MAC address
functionality.
Michal Simek [Wed, 13 May 2015 11:40:40 +0000 (13:40 +0200)]
net: phy: Add support for all targets which requires MANUAL_RELOC
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers passed to phy_register
function.
This patch was tested on Microblaze architecture.
sunxi: VBUS detection function fixup in g_dnl_board_usb_cable_connected
sunxi_usbc_vbus_detect was renamed to sunxi_usb_phy_vbus_detect but
g_dnl_board_usb_cable_connected was still using the old name, breaking the build
when USB gadget is enabled.
Hans de Goede [Thu, 14 May 2015 16:52:54 +0000 (18:52 +0200)]
sunxi: video: Fix lvds panel support for sun6i+
We've never tested the lvds panel support on sun6i+ SoCs until now, and
unsurprisingly the lvds code needed some fixes to work on my ga10h A33
tablet with lvds panel. This makes the panel on that tablet actually work.
Hans de Goede [Wed, 13 May 2015 13:00:46 +0000 (15:00 +0200)]
sunxi: Make DRAM_ODT_EN Kconfig setting a bool
Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION
setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of
only in dram_sun4i.c and hardcoding odt_en elsewhere.
Note this commit makes no functional changes for existing boards,
its purpose is to allow changing the odt_en value on future A33 boards.
For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs
currently do) this patch turns on odt for both the DQ and the DQS lines,
whereas previously it was possibly (but not desirable) to turn odt on only
for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3.
Laurent Itti [Wed, 6 May 2015 00:02:00 +0000 (17:02 -0700)]
sunxi: add support for UART2 on A23/A33
Add support for UART2 (2-pin version but note that RTS/CTS pins are available
pn that port for possible future use), can be selected in config
by using CONFIG_CONS_INDEX=3
Hans de Goede [Tue, 5 May 2015 11:13:36 +0000 (13:13 +0200)]
console: Fix pre-console flushing via cfb_console being very slow
On my A10 OlinuxIno Lime I noticed a huge (5+ seconds) delay coming from
console_init_r. This turns out to be caused by the preconsole buffer flushing
to the cfb_console. The Lime only has a 16 bit memory bus and that is already
heavy used to scan out the 1920x1080 framebuffer.
The problem is that print_pre_console_buffer() was printing the buffer once
character at a time and the cfb_console code then ends up doing a cache-flush
for touched display lines for each character.
This commit fixes this by first building a 0 terminated buffer and then
printing it in one puts() call, avoiding unnecessary cache flushes.
This changes the time for the flush from 5+ seconds to not noticable.
The downside of this approach is that the pre-console buffer needs to fit
on the stack, this is not that much to ask since we are talking about plain
text here. This commit also adjusts the sunxi CONFIG_PRE_CON_BUF_SZ to
actually fit on the stack. Sunxi currently is the only user of the pre-console
code so no other boards need to be adjusted.
Tim Harvey [Mon, 18 May 2015 13:56:46 +0000 (06:56 -0700)]
imx: mx6: add display of CPU temperature grade in print_cpuinfo()
When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info
along with the current temperature.
Before:
CPU: Temperature 42 C
After:
CPU: Automotive temperature grade (-40C to 125C) at 42C
CPU: Industrial temperature grade (-40C to 105C) at 42C
CPU: Extended Commercial temperature grade (-20C to 105C) at 42C
Tim Harvey [Mon, 18 May 2015 13:56:45 +0000 (06:56 -0700)]
imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Tim Harvey [Mon, 18 May 2015 14:02:25 +0000 (07:02 -0700)]
imx: mx6: display max cpu frequency in print_cpuinfo()
Display the max CPU frequency as well as the current running CPU frequency
if the max CPU frequency is available and differs from the current CPU
frequency.
Before:
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
After - using an 800MHz IMX6DL (running at its max)
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
After - using a 1GHz IMX6Q (not running at its max):
CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
Tim Harvey [Mon, 18 May 2015 14:02:24 +0000 (07:02 -0700)]
imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Tim Harvey [Mon, 18 May 2015 14:07:02 +0000 (07:07 -0700)]
arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Peng Fan [Mon, 18 May 2015 05:37:25 +0000 (13:37 +0800)]
imx: mx6sx enable SION for i2c pin mux
Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise
we will get erros when doing i2c operations.
error log like the following:
"
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0xb retry=1
"
Tim Harvey [Thu, 14 May 2015 18:48:04 +0000 (11:48 -0700)]
env_nand: use nand_spl_load_image for readenv if SPL
The readenv() implementation of env_nand uses the mtd layer which is
unnecessary overhead in SPL when we already have a nand_spl_load_image()
function that doesn't need it. Using this instead eliminates the need
to provide a mtd_read for SPL env as well as reduces code (4KB savings in IMX6
SPL).
Tim Harvey [Thu, 14 May 2015 13:22:07 +0000 (06:22 -0700)]
imx: ventana: use stack relocation
Certain features we desire require a larger stack than is available by using
iRAM (most notably for us, env_mmc). Relocate the stack to DRAM so that
we can use these features.
Tim Harvey [Sat, 9 May 2015 01:28:37 +0000 (18:28 -0700)]
imx: ventana: detect pmic using i2c probe instead of board model
Avoid requiring board-model and probe pmic by its i2c address.
This is in preparation for being able to call pmic_setup() from SPL
and not need board type.
Tim Harvey [Sat, 9 May 2015 01:28:35 +0000 (18:28 -0700)]
imx: ventana: split out common functions between SPL and uboot
Move shared functions used by both SPL and U-Boot to common.c:
- setup_iomux_uart() and uart pad config
- gpio pad config
In the process also moved the following to common.c in preparation for
calling it from the SPL:
- split i2c setup into a shared function
- move pmic init to setup_pmic() function to call directly from
power_init_board()
- split gpio setup into early (iomux and default pin config)
and late (output configuration based on env)
Tim Harvey [Sat, 9 May 2015 01:28:34 +0000 (18:28 -0700)]
imx: ventana: default msata/pci mux to pci before PCI enumeration
PCI enumeration occurs early, before we fully configure our GPIO's. Make
sure we steer the MSATA/PCI mux to PCI in board_init to ensure PCI is
selected before enumeration.
Fabio Estevam [Wed, 11 Mar 2015 20:12:12 +0000 (17:12 -0300)]
mx6: Set shared override bit in PL310 AUX_CTRL register
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.
Soeren Moch [Tue, 5 May 2015 21:09:19 +0000 (23:09 +0200)]
tbs2910: only enable vga output for stdout/stderr when hdmi detected
Only enable graphical output for stdout/stderr (and a usb keyboard for stdin)
when a hdmi device is detected.
Serial console is always enabled for stdin/stdout/stderr.
Stefan Roese [Thu, 12 Mar 2015 12:34:30 +0000 (13:34 +0100)]
arm: mx6: tqma6: Update to optionally configure an alternative SPI setup
By making the tqma6_iomuxc_spi() weak, this patch adds the possibility to
add a different function for this SPI configuration. This can be used
by other baseboards, that might have a different SPI setup.
This patch will be used by the upcoming WRU-IV board support which also
uses the TQMa6 SoM.
Fabio Estevam [Mon, 4 May 2015 14:22:56 +0000 (11:22 -0300)]
mx6cuboxi: Pull down PAD_ENET_RXD0/RXD1
Configure PAD_ENET_RXD0/RXD1 pads as pull down because these pads are directly
connected to the Atheros 8035/8030 although they should be functional
only in the RMII mode - 8030.
Fabio Estevam [Mon, 4 May 2015 14:22:55 +0000 (11:22 -0300)]
mx6cuboxi: Fix Ethernet PHY detection problem
mx6cuboxi sometimes fails to recognize the Ethernet PHY:
Net: Phy 0 not found
The explanation for this behavior comes from from Rabeeh Khoury:
"The LED_ACT pin on the carrier-one boards had a pull down that
forces the phy address to 0x0; where on CuBox-i and the production
HummingBoard that pin is connected directly to LED that depending
on the pull down strength of the LED it might be sampled as '0' or '1' thus
the phy address might appear as either address 0x0 or 0x4."
"This is AR8035 implementation; in reset stage the LED pin is configured as
input, and pull up/down does matter. In this case it configures the PHY
address.
After reset is deasserted the same LED pin becomes output and then
according to the previous pull/up it should be active high/low"
One way to properly fix this behavior is to place external pull-up/down
resistors in the LED line, but from a software standpoint we can fix it
by telling phy_find_by_mask() to scan the PHY at addresses
0x0 and 0x4.
It is necessary to modify the configuration file for the target
board. It wasn't well documented that to enable any of the secure
boot modes, it is required to add CONFIG_SECURE_BOOT to the board
configuration file.
Nikolay Dimitrov [Wed, 22 Apr 2015 15:37:31 +0000 (18:37 +0300)]
arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.
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