Hyungwon Hwang [Fri, 12 Dec 2014 05:45:46 +0000 (14:45 +0900)]
Odroid-XU3: Add documentation for Odroid-XU3
This patch adds documentation for Odroid-XU3. This documentation is
based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak.
The documentation includes basic information about boot media layout,
environment, partition layout, and the instruction to burn the u-boot
image to boot media.
Hyungwon Hwang [Fri, 12 Dec 2014 05:45:44 +0000 (14:45 +0900)]
config: exynos5420: move non common configs to specific board files
The media for boot and environment is a board-specific feature, not a
processor-specific. This is same to console port number and some
other addresses. This patch moves the that kinds of configs to each
board-specific files from the common config file for Exynos5420.
Stefan Roese [Fri, 19 Dec 2014 12:49:10 +0000 (13:49 +0100)]
arm: socfpga: Change watchdog timeout
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.
Also we now call the hw_watchdog_init() function so that we override
the value already configured from the Preloader.
Jan Luebbe [Sun, 14 Dec 2014 15:34:49 +0000 (16:34 +0100)]
arm: mxs: olinuxino: move DRAM config tuning to SPL
The weak mxs_adjust_memory_params function is called from spl_mem_init.c,
so it must be linked into the SPL to have an effect. Move it from
mx23_olinuxino.c to spl_boot.c.
This change was verified by reading back the register values.
Peng Fan [Sun, 23 Nov 2014 03:52:20 +0000 (11:52 +0800)]
imx:mx6 fix return value of mxc_get_clock
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.
Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.
Simon Glass [Wed, 17 Dec 2014 03:21:02 +0000 (20:21 -0700)]
x86: Add a script to process Intel microcode files
Intel delivers microcode updates in a microcode.dat file which must be
split up into individual files for each CPU. Add a tool which performs
this task. It can list available microcode updates for each model and
produce a new microcode update in U-Boot's .dtsi format.
Bin Meng [Wed, 17 Dec 2014 07:50:49 +0000 (15:50 +0800)]
x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:
- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
stackless environment
- Add comments to mention init(¶ms) in fsp_init() cannot
be removed
Bin Meng [Wed, 17 Dec 2014 07:50:46 +0000 (15:50 +0800)]
x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Bin Meng [Wed, 17 Dec 2014 07:50:45 +0000 (15:50 +0800)]
x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Bin Meng [Wed, 17 Dec 2014 07:50:44 +0000 (15:50 +0800)]
x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Bin Meng [Wed, 17 Dec 2014 07:50:38 +0000 (15:50 +0800)]
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Simon Glass [Wed, 17 Dec 2014 07:50:37 +0000 (15:50 +0800)]
x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.
Simon Glass [Tue, 16 Dec 2014 05:02:41 +0000 (22:02 -0700)]
x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.
Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.
Simon Glass [Tue, 16 Dec 2014 05:02:38 +0000 (22:02 -0700)]
x86: ifdtool: Add support for early microcode access
Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
means of starting up the CPU. One result is that microcode updates can only
be done before RAM is available and therefore parsing of the device tree
is impracticle.
Worse, the addess of the microcode update must be stored in ROM since a
pointer to its start address and size is passed to the 'FSP' blob. It is
not possible to perform any calculations to obtain the address and size.
To work around this, ifdtool is enhanced to work out the address and size of
the first microcode update it finds in the supplied device tree. It then
writes these into the correct place in the ROM. U-Boot can then start up
the FSP correctly.
Thierry Reding [Wed, 10 Dec 2014 05:25:26 +0000 (22:25 -0700)]
net: rtl8169: Use non-cached memory if available
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
Thierry Reding [Wed, 10 Dec 2014 05:25:25 +0000 (22:25 -0700)]
net: rtl8169: Properly align buffers
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case the cache-line is higher than the
256 byte alignment requirements of the NIC.
Also add a warning if the cache-line size is larger than the descriptor
size, because the driver may discard changes to descriptors made by the
hardware when requeuing RX buffers.
Thierry Reding [Wed, 10 Dec 2014 05:25:23 +0000 (22:25 -0700)]
ARM: tegra: Enable non-cached memory
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality at some point, so enabling
it now will automatically reap the benefits later on.
Thierry Reding [Wed, 10 Dec 2014 05:25:22 +0000 (22:25 -0700)]
ARM: Implement non-cached memory support
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).
While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.
Thierry Reding [Wed, 10 Dec 2014 05:25:21 +0000 (22:25 -0700)]
ARM: tegra: Enable PCIe on Jetson TK1
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
Thierry Reding [Wed, 10 Dec 2014 05:25:19 +0000 (22:25 -0700)]
ARM: tegra: Add GIC for Tegra124
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Thierry Reding [Wed, 10 Dec 2014 05:25:18 +0000 (22:25 -0700)]
ARM: tegra: Enable PCIe on Beaver
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
Thierry Reding [Wed, 10 Dec 2014 05:25:17 +0000 (22:25 -0700)]
ARM: tegra: Enable PCIe on Cardhu
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.
Thierry Reding [Wed, 10 Dec 2014 05:25:15 +0000 (22:25 -0700)]
ARM: tegra: Add GIC for Tegra30
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.
Thierry Reding [Wed, 10 Dec 2014 05:25:14 +0000 (22:25 -0700)]
ARM: tegra: Enable PCIe on TrimSlice
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
Thierry Reding [Wed, 10 Dec 2014 05:25:12 +0000 (22:25 -0700)]
pci: tegra: Add Tegra PCIe driver
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.
This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.
Thierry Reding [Wed, 10 Dec 2014 05:25:09 +0000 (22:25 -0700)]
ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.
Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.
Thierry Reding [Wed, 10 Dec 2014 05:25:07 +0000 (22:25 -0700)]
ARM: tegra: Provide PCIEXCLK reset ID
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.
Thierry Reding [Wed, 10 Dec 2014 05:25:06 +0000 (22:25 -0700)]
ARM: tegra: Implement tegra_plle_enable()
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
Thierry Reding [Wed, 10 Dec 2014 05:25:22 +0000 (22:25 -0700)]
ARM: Implement non-cached memory support
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).
While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.
Steve Rae [Fri, 12 Dec 2014 23:51:54 +0000 (15:51 -0800)]
fastboot: handle flash write to GPT partitions
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Additionally, prepare and write the Backup GUID Partition Table.
dfu: dfu_get_buf: check the value of env dfu_bufsiz before use
In function dfu_get_buf(), the size of allocated buffer could
be defined by the env variable. The size from this variable
was passed for memalign() without checking its value.
And the the memalign will return non null pointer for size 0.
This could possibly cause data abort, so now the value of var
is checked before use. And if this variable is set to 0 then
the default size will be used.
This commit also changes the base passed to simple_strtoul()
to 0. Now decimal and hex values can be used for the variable
dfu_bufsiz.
gadget: f_thor: check pointers before use in download_tail()
Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.
dfu: mmc: check if mmc device exists in mmc_block_op()
The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.
Rob Herring [Wed, 10 Dec 2014 20:43:04 +0000 (14:43 -0600)]
fastboot: add support for continue command
The fastboot continue command is defined to exit fastboot and continue
autoboot. This commit implements the continue command and the exiting of
fastboot only. Subsequent u-boot commands can be processed after exiting
fastboot. Autoboot should implement a boot script such as "fastboot; mmc
read <...>; bootm" to fully implement the fastboot continue function.
Bo Shen [Mon, 15 Dec 2014 10:12:47 +0000 (18:12 +0800)]
USB: gadget: atmel_usba_udc: fix transfer hang issue
When receive data, the RXRDY in status register set by hardware
after a new packet has been stored in the endpoint FIFO. After,
we copy from FIFO, we clear it, make the FIFO can be accessed
again.
In the receive_data() function, this bit RXRDY has been cleared.
So, after the receive_data() function return, this bit should
not be cleared again, or else it will cause the accessing FIFO
corrupt, which will make the data loss.
Pavel Machek [Thu, 11 Dec 2014 17:06:31 +0000 (18:06 +0100)]
arm: socfpga: board: Repair Micrel PHY tuning
Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.
gaurav rana [Thu, 4 Dec 2014 07:30:41 +0000 (13:00 +0530)]
crypto/fsl: Fix RNG instantiation failure.
Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.
Shengzhou Liu [Wed, 3 Dec 2014 07:27:03 +0000 (15:27 +0800)]
net/fm: update ft_fixup_port to differentiate dual-role mac
we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.
York Sun [Tue, 2 Dec 2014 19:21:09 +0000 (11:21 -0800)]
powerpc/mpc85xx: Fix DDR TLB mapping leftover
Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.
York Sun [Tue, 2 Dec 2014 19:18:09 +0000 (11:18 -0800)]
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.
Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)
The generic asmlinkage is defined in <linux/linkage.h>. If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.
Bin Meng [Fri, 12 Dec 2014 13:05:32 +0000 (21:05 +0800)]
x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.
Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.
Bin Meng [Fri, 12 Dec 2014 13:05:31 +0000 (21:05 +0800)]
x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.
The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.
projects / u-boot.git / log