ddr: socfpga: Clean up EMIF reset

ddr: socfpga: Clean up EMIF reset

The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Cc: Tien Fong Chee <[email protected]>