]> Git Repo - u-boot.git/commit
ddr: socfpga: Clean up EMIF reset
authorMarek Vasut <[email protected]>
Sat, 9 Mar 2019 20:57:58 +0000 (21:57 +0100)
committerMarek Vasut <[email protected]>
Sat, 9 Mar 2019 22:25:19 +0000 (23:25 +0100)
commit8297dd1d934281175ffa8646a2e3200755402db5
treef0a0d6dc60e38eca2ac5878a401bf921a971f09b
parentffd1e1a336730b6991c2ae7e7b0605e99d4f2b06
ddr: socfpga: Clean up EMIF reset

The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Cc: Tien Fong Chee <[email protected]>
drivers/ddr/altera/sdram_arria10.c
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