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riscv: sifive: fu540: enable all cache ways from U-Boot proper
authorPragnesh Patel <[email protected]>
Fri, 29 May 2020 06:44:51 +0000 (12:14 +0530)
committerAndes <[email protected]>
Fri, 3 Jul 2020 07:09:06 +0000 (15:09 +0800)
commit5ce50206ed24080707946849d3542534fadf8cbf
tree291e2af14db172b24773bc1a8c7c2b699b263d29tree | snapshot
parentedf4fc2bafac18399d07152be51cb77d5d1bb3accommit | diff
riscv: sifive: fu540: enable all cache ways from U-Boot proper

Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
arch/riscv/cpu/fu540/Makefile diff | blob | blame | history
arch/riscv/cpu/fu540/cache.c [new file with mode: 0644] blob
arch/riscv/dts/fu540-c000-u-boot.dtsi diff | blob | blame | history
arch/riscv/include/asm/arch-fu540/cache.h [new file with mode: 0644] blob
board/sifive/fu540/fu540.c diff | blob | blame | history
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