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(parent: deff6fb) | patch
MIPS: fix mips_cache fallback without __builtin_mips_cache
authorMatthias Schiffer <[email protected]>
Sat, 5 Mar 2016 03:15:40 +0000 (04:15 +0100)
committerDaniel Schwierzeck <[email protected]>
Wed, 9 Mar 2016 10:00:40 +0000 (11:00 +0100)
commit499b84752140a8b40f8f0956c72357743f755250
tree35d06f159bdc7df5a9fa8819c7d68801fa4506cbtree | snapshot
parentdeff6fb3a7790e93264292982000275e78bb12e5commit | diff
MIPS: fix mips_cache fallback without __builtin_mips_cache

The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
arch/mips/include/asm/cacheops.h diff | blob | blame | history
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