X-Git-Url: https://repo.jachan.dev/u-boot.git/blobdiff_plain/c2279d784e35fa25ee3a9fa28a74a1ba545f8c1e..7665ed2fa04e:/drivers/ddr/fsl/lc_common_dimm_params.c

diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index d299d763db..5e4ad56f07 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP Semiconductor
+ * Copyright 2017-2021 NXP Semiconductor
  */
 
 #include <common.h>
@@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num,
 	unsigned int caslat_actual;
 	unsigned int retry = 16;
 	unsigned int tmp = ~0;
-	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
+	unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #ifdef CONFIG_SYS_FSL_DDR3
 	const unsigned int taamax = 20000;
 #else
@@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num,
 	}
 	common_caslat = tmp;
 
+	if (!mclk_ps) {
+		printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
+		       outpdimm->tckmin_x_ps);
+		mclk_ps = outpdimm->tckmin_x_ps;
+	}
+
 	/* validate if the memory clk is in the range of dimms */
 	if (mclk_ps < outpdimm->tckmin_x_ps) {
 		printf("DDR clock (MCLK cycle %u ps) is faster than "
@@ -416,6 +422,9 @@ compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
 					dimm_params[i].mpart);
 #endif
 			}
+#ifndef CONFIG_SPL_BUILD
+			puts("       ");
+#endif
 		}
 	}