ARM: imx6: dh-imx6: Enable d-cache early in SPL

[u-boot.git] / board / dhelectronics / dh_imx6 / dh_imx6_spl.c

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index b49296104283111c84ede426dec8ef6f07b68684..20a330cce62f62030bf33b4422f0d66f80ecc8b5 100644 (file)
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -6,6 +6,8 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <init.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/imx-regs.h>
@@ -13,17 +15,20 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
+#include <asm/system.h>
 #include <errno.h>
 #include <fuse.h>
 #include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <spl.h>
+#include <linux/delay.h>
 
 #define ENET_PAD_CTRL                                                  \
        (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
@@ -440,8 +445,13 @@ static void setup_iomux_sd(void)
 
 /* SPI */
 static iomux_v3_cfg_t const ecspi1_pads[] = {
-       /* SS0 */
-       IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30      | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+       /* SS0 - SS of boot flash */
+       IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30      |
+               MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+       /* SS2 - SS of DHCOM SPI1 */
+       IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11     |
+               MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+
        IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
        IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
        IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
@@ -471,6 +481,32 @@ static void setup_iomux_uart(void)
        SETUP_IOMUX_PADS(uart1_pads);
 }
 
+#ifdef CONFIG_FSL_USDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+       {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_get_env_dev(int devno)
+{
+       return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       return 1; /* eMMC/uSDHC4 is always present */
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+       SETUP_IOMUX_PADS(usdhc4_pads);
+       usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+       usdhc_cfg[0].max_bus_width = 8;
+
+       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
 /* USB */
 static iomux_v3_cfg_t const usb_pads[] = {
        IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID       | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -577,6 +613,20 @@ static void dhcom_spl_dram_init(void)
        }
 }
 
+void dram_bank_mmu_setup(int bank)
+{
+       int i;
+
+       set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
+       set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
+
+       for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
+                       i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +
+                       (SZ_1G >> MMU_SECTION_SHIFT));
+                       i++)
+               set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
+
 void board_init_f(ulong dummy)
 {
        /* setup AIPS and disable watchdog */
@@ -603,9 +653,33 @@ void board_init_f(ulong dummy)
        /* DDR3 initialization */
        dhcom_spl_dram_init();
 
+       /* Set up early MMU tables at the beginning of DRAM and start d-cache */
+       gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
+       gd->arch.tlb_size = PGTABLE_SIZE;
+       enable_caches();
+
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 
        /* load/boot image from boot device */
        board_init_r(NULL, 0);
 }
+
+void spl_board_prepare_for_boot(void)
+{
+       /*
+        * Flush and disable dcache. Without it, the following bootstage might fail randomly because
+        * dirty cache lines may not have been written back to DRAM.
+        *
+        * If dcache_disable() would be omitted, the following scenario may occur:
+        *
+        * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled
+        * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations
+        * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old
+        * state of the content.
+        *
+        * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was
+        * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data.
+        */
+       dcache_disable(); /* implies flush_dcache_all() */
+}