nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig

[u-boot.git] / include / configs / UCP1020.h

diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index c5daaadce7833e526341bcf267ab9829e3e89c3e..51083569a88d432a0f4957412a660e5498d806cd 100644 (file)
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -32,9 +32,6 @@
 #define FWENV_TYPE     FWENV_NOR_FLASH
 
 #if (FWENV_TYPE == FWENV_MMC)
 #define FWENV_TYPE     FWENV_NOR_FLASH
 
 #if (FWENV_TYPE == FWENV_MMC)

-#ifndef CONFIG_SYS_MMC_ENV_DEV
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#endif

 #define FWENV_ADDR1 -1
 #define FWENV_ADDR2 -1
 #define FWENV_ADDR3 -1
 #define FWENV_ADDR1 -1
 #define FWENV_ADDR2 -1
 #define FWENV_ADDR3 -1


@@ -152,7 +149,6 @@
 #define CONFIG_LBA48
 
 #define CONFIG_SYS_CLK_FREQ    66666666
 #define CONFIG_LBA48
 
 #define CONFIG_SYS_CLK_FREQ    66666666

-#define CONFIG_DDR_CLK_FREQ    66666666

 
 #define CONFIG_HWCONFIG
 
 
 #define CONFIG_HWCONFIG
 


@@ -174,11 +170,6 @@
 #endif
 
 /* DDR Setup */
 #endif
 
 /* DDR Setup */

-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif

 #define CONFIG_SYS_SPD_BUS_NUM 1
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_512M
 #define CONFIG_SYS_SPD_BUS_NUM 1
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_512M


@@ -207,11 +198,7 @@
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000

-#ifdef CONFIG_DDR_ECC_ENABLE

 #define CONFIG_SYS_DDR_CONTROL         0xE70C0000      /* Type = DDR3 & ECC */
 #define CONFIG_SYS_DDR_CONTROL         0xE70C0000      /* Type = DDR3 & ECC */

-#else
-#define CONFIG_SYS_DDR_CONTROL         0xC70C0000      /* Type = DDR3 */
-#endif

 #define CONFIG_SYS_DDR_CONTROL_2       0x04401050
 #define CONFIG_SYS_DDR_TIMING_4                0x00220001
 #define CONFIG_SYS_DDR_TIMING_5                0x03402400
 #define CONFIG_SYS_DDR_CONTROL_2       0x04401050
 #define CONFIG_SYS_DDR_TIMING_4                0x00220001
 #define CONFIG_SYS_DDR_TIMING_5                0x03402400


@@ -313,14 +300,6 @@
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR + 0x4600)
 
 /* I2C */
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR + 0x4600)
 
 /* I2C */

-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED       400000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100

 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */
 
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */
 


@@ -367,7 +346,6 @@
  */
 #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
  */
 #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION

-#define CONFIG_SYS_MMC_ENV_DEV 0

 #endif
 
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */
 #endif
 
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */