#include <asm/mach-imx/sys_proto.h>
#endif
#include <linux/delay.h>
+#include <linux/printk.h>
#include "dwc_eth_qos.h"
flush_dcache_range(start, end);
}
-void eqos_inval_buffer_tegra186(void *buf, size_t size)
+static void eqos_inval_buffer_tegra186(void *buf, size_t size)
{
unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO not idle at entry");
+ pr_err("MDIO not idle at entry\n");
return ret;
}
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO read didn't complete");
+ pr_err("MDIO read didn't complete\n");
return ret;
}
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO not idle at entry");
+ pr_err("MDIO not idle at entry\n");
return ret;
}
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO read didn't complete");
+ pr_err("MDIO read didn't complete\n");
return ret;
}
ret = clk_enable(&eqos->clk_slave_bus);
if (ret < 0) {
- pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
+ pr_err("clk_enable(clk_slave_bus) failed: %d\n", ret);
goto err;
}
ret = clk_enable(&eqos->clk_master_bus);
if (ret < 0) {
- pr_err("clk_enable(clk_master_bus) failed: %d", ret);
+ pr_err("clk_enable(clk_master_bus) failed: %d\n", ret);
goto err_disable_clk_slave_bus;
}
ret = clk_enable(&eqos->clk_rx);
if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
+ pr_err("clk_enable(clk_rx) failed: %d\n", ret);
goto err_disable_clk_master_bus;
}
ret = clk_enable(&eqos->clk_ptp_ref);
if (ret < 0) {
- pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
+ pr_err("clk_enable(clk_ptp_ref) failed: %d\n", ret);
goto err_disable_clk_rx;
}
ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
if (ret < 0) {
- pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
+ pr_err("clk_set_rate(clk_ptp_ref) failed: %d\n", ret);
goto err_disable_clk_ptp_ref;
}
ret = clk_enable(&eqos->clk_tx);
if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
+ pr_err("clk_enable(clk_tx) failed: %d\n", ret);
goto err_disable_clk_ptp_ref;
}
#endif
#endif
}
-static int eqos_start_clks_stm32(struct udevice *dev)
-{
-#ifdef CONFIG_CLK
- struct eqos_priv *eqos = dev_get_priv(dev);
- int ret;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- ret = clk_enable(&eqos->clk_master_bus);
- if (ret < 0) {
- pr_err("clk_enable(clk_master_bus) failed: %d", ret);
- goto err;
- }
-
- ret = clk_enable(&eqos->clk_rx);
- if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
- goto err_disable_clk_master_bus;
- }
-
- ret = clk_enable(&eqos->clk_tx);
- if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
- goto err_disable_clk_rx;
- }
-
- if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
- ret = clk_enable(&eqos->clk_ck);
- if (ret < 0) {
- pr_err("clk_enable(clk_ck) failed: %d", ret);
- goto err_disable_clk_tx;
- }
- eqos->clk_ck_enabled = true;
- }
-#endif
-
- debug("%s: OK\n", __func__);
- return 0;
-
-#ifdef CONFIG_CLK
-err_disable_clk_tx:
- clk_disable(&eqos->clk_tx);
-err_disable_clk_rx:
- clk_disable(&eqos->clk_rx);
-err_disable_clk_master_bus:
- clk_disable(&eqos->clk_master_bus);
-err:
- debug("%s: FAILED: %d\n", __func__, ret);
- return ret;
-#endif
-}
-
static int eqos_stop_clks_tegra186(struct udevice *dev)
{
#ifdef CONFIG_CLK
return 0;
}
-static int eqos_stop_clks_stm32(struct udevice *dev)
-{
-#ifdef CONFIG_CLK
- struct eqos_priv *eqos = dev_get_priv(dev);
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
- clk_disable(&eqos->clk_master_bus);
-#endif
-
- debug("%s: OK\n", __func__);
- return 0;
-}
-
static int eqos_start_resets_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
- pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
+ pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d\n", ret);
return ret;
}
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
- pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d\n", ret);
return ret;
}
ret = reset_assert(&eqos->reset_ctl);
if (ret < 0) {
- pr_err("reset_assert() failed: %d", ret);
+ pr_err("reset_assert() failed: %d\n", ret);
return ret;
}
ret = reset_deassert(&eqos->reset_ctl);
if (ret < 0) {
- pr_err("reset_deassert() failed: %d", ret);
+ pr_err("reset_deassert() failed: %d\n", ret);
return ret;
}
ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
if (ret) {
- pr_err("calibrate didn't start");
+ pr_err("calibrate didn't start\n");
goto failed;
}
ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
if (ret) {
- pr_err("calibrate didn't finish");
+ pr_err("calibrate didn't finish\n");
goto failed;
}
#endif
}
-static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
-{
-#ifdef CONFIG_CLK
- struct eqos_priv *eqos = dev_get_priv(dev);
-
- return clk_get_rate(&eqos->clk_master_bus);
-#else
- return 0;
-#endif
-}
-
static int eqos_set_full_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
rate = 2.5 * 1000 * 1000;
break;
default:
- pr_err("invalid speed %d", eqos->phy->speed);
+ pr_err("invalid speed %d\n", eqos->phy->speed);
return -EINVAL;
}
ret = clk_set_rate(&eqos->clk_tx, rate);
if (ret < 0) {
- pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
+ pr_err("clk_set_rate(tx_clk, %lu) failed: %d\n", rate, ret);
return ret;
}
#endif
else
ret = eqos_set_half_duplex(dev);
if (ret < 0) {
- pr_err("eqos_set_*_duplex() failed: %d", ret);
+ pr_err("eqos_set_*_duplex() failed: %d\n", ret);
return ret;
}
ret = eqos_set_mii_speed_10(dev);
break;
default:
- pr_err("invalid speed %d", eqos->phy->speed);
+ pr_err("invalid speed %d\n", eqos->phy->speed);
return -EINVAL;
}
if (ret < 0) {
- pr_err("eqos_set_*mii_speed*() failed: %d", ret);
+ pr_err("eqos_set_*mii_speed*() failed: %d\n", ret);
return ret;
}
if (en_calibration) {
ret = eqos->config->ops->eqos_calibrate_pads(dev);
if (ret < 0) {
- pr_err("eqos_calibrate_pads() failed: %d",
+ pr_err("eqos_calibrate_pads() failed: %d\n",
ret);
return ret;
}
} else {
ret = eqos->config->ops->eqos_disable_calibration(dev);
if (ret < 0) {
- pr_err("eqos_disable_calibration() failed: %d",
+ pr_err("eqos_disable_calibration() failed: %d\n",
ret);
return ret;
}
}
ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
if (ret < 0) {
- pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
+ pr_err("eqos_set_tx_clk_speed() failed: %d\n", ret);
return ret;
}
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
ulong desc_pad;
+ ulong addr64;
debug("%s(dev=%p):\n", __func__, dev);
ret = eqos->config->ops->eqos_start_resets(dev);
if (ret < 0) {
- pr_err("eqos_start_resets() failed: %d", ret);
+ pr_err("eqos_start_resets() failed: %d\n", ret);
goto err;
}
eqos->reg_access_ok = true;
+ /*
+ * Assert the SWR first, the actually reset the MAC and to latch in
+ * e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
+ */
+ setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
+
ret = wait_for_bit_le32(&eqos->dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
if (ret) {
- pr_err("EQOS_DMA_MODE_SWR stuck");
+ pr_err("EQOS_DMA_MODE_SWR stuck\n");
goto err_stop_resets;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
if (ret < 0) {
- pr_err("eqos_calibrate_pads() failed: %d", ret);
+ pr_err("eqos_calibrate_pads() failed: %d\n", ret);
goto err_stop_resets;
}
- rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
- val = (rate / 1000000) - 1;
- writel(val, &eqos->mac_regs->us_tic_counter);
+ if (eqos->config->ops->eqos_get_tick_clk_rate) {
+ rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
+
+ val = (rate / 1000000) - 1;
+ writel(val, &eqos->mac_regs->us_tic_counter);
+ }
/*
* if PHY was already connected and configured,
*/
if (!eqos->phy) {
int addr = -1;
- addr = eqos_get_phy_addr(eqos, dev);
- eqos->phy = phy_connect(eqos->mii, addr, dev,
- eqos->config->interface(dev));
+ ofnode fixed_node;
+
+ if (IS_ENABLED(CONFIG_PHY_FIXED)) {
+ fixed_node = ofnode_find_subnode(dev_ofnode(dev),
+ "fixed-link");
+ if (ofnode_valid(fixed_node))
+ eqos->phy = fixed_phy_create(dev_ofnode(dev));
+ }
+
if (!eqos->phy) {
- pr_err("phy_connect() failed");
+ addr = eqos_get_phy_addr(eqos, dev);
+ eqos->phy = phy_connect(eqos->mii, addr, dev,
+ eqos->config->interface(dev));
+ }
+
+ if (!eqos->phy) {
+ pr_err("phy_connect() failed\n");
+ ret = -ENODEV;
goto err_stop_resets;
}
if (eqos->max_speed) {
ret = phy_set_supported(eqos->phy, eqos->max_speed);
if (ret) {
- pr_err("phy_set_supported() failed: %d", ret);
+ pr_err("phy_set_supported() failed: %d\n", ret);
goto err_shutdown_phy;
}
}
eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
- pr_err("phy_config() failed: %d", ret);
+ pr_err("phy_config() failed: %d\n", ret);
goto err_shutdown_phy;
}
}
ret = phy_startup(eqos->phy);
if (ret < 0) {
- pr_err("phy_startup() failed: %d", ret);
+ pr_err("phy_startup() failed: %d\n", ret);
goto err_shutdown_phy;
}
if (!eqos->phy->link) {
- pr_err("No link");
+ pr_err("No link\n");
+ ret = -EAGAIN;
goto err_shutdown_phy;
}
ret = eqos_adjust_link(dev);
if (ret < 0) {
- pr_err("eqos_adjust_link() failed: %d", ret);
+ pr_err("eqos_adjust_link() failed: %d\n", ret);
goto err_shutdown_phy;
}
rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
- /*
- * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
- * r/tqs is encoded as (n / 256) - 1.
- */
- tqs = (128 << tx_fifo_sz) / 256 - 1;
- rqs = (128 << rx_fifo_sz) / 256 - 1;
+ /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */
+ tx_fifo_sz = 128 << tx_fifo_sz;
+ rx_fifo_sz = 128 << rx_fifo_sz;
+
+ /* Allow platform to override TX/RX fifo size */
+ if (eqos->tx_fifo_sz)
+ tx_fifo_sz = eqos->tx_fifo_sz;
+ if (eqos->rx_fifo_sz)
+ rx_fifo_sz = eqos->rx_fifo_sz;
+
+ /* r/tqs is encoded as (n / 256) - 1 */
+ tqs = tx_fifo_sz / 256 - 1;
+ rqs = rx_fifo_sz / 256 - 1;
clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE));
+
+ addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
- eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE),
- EQOS_MAX_PACKET_SIZE);
+ eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE);
}
- writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, false),
- &eqos->dma_regs->ch0_txdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, false);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address);
writel(EQOS_DESCRIPTORS_TX - 1,
&eqos->dma_regs->ch0_txdesc_ring_length);
- writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, true),
- &eqos->dma_regs->ch0_rxdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, true);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address);
writel(EQOS_DESCRIPTORS_RX - 1,
&eqos->dma_regs->ch0_rxdesc_ring_length);
err_stop_resets:
eqos->config->ops->eqos_stop_resets(dev);
err:
- pr_err("FAILED: %d", ret);
+ pr_err("FAILED: %d\n", ret);
return ret;
}
eqos->tx_desc_idx++;
eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
- tx_desc->des0 = (ulong)eqos->tx_dma_buf;
- tx_desc->des1 = 0;
+ tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf);
+ tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf);
tx_desc->des2 = length;
/*
* Make sure that if HW sees the _OWN write below, it will see all the
struct eqos_desc *rx_desc;
int length;
- debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
-
rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
eqos->config->ops->eqos_inval_desc(rx_desc);
- if (rx_desc->des3 & EQOS_DESC3_OWN) {
- debug("%s: RX packet not available\n", __func__);
+ if (rx_desc->des3 & EQOS_DESC3_OWN)
return -EAGAIN;
- }
+
+ debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
*packetp = eqos->rx_dma_buf +
(eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
struct eqos_priv *eqos = dev_get_priv(dev);
u32 idx, idx_mask = eqos->desc_per_cacheline - 1;
uchar *packet_expected;
- struct eqos_desc *rx_desc;
+ struct eqos_desc *rx_desc = NULL;
debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
for (idx = eqos->rx_desc_idx - idx_mask;
idx <= eqos->rx_desc_idx;
idx++) {
+ ulong addr64;
+
rx_desc = eqos_get_desc(eqos, idx, true);
rx_desc->des0 = 0;
+ rx_desc->des1 = 0;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
eqos->config->ops->eqos_inval_buffer(packet, length);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (idx * EQOS_MAX_PACKET_SIZE));
- rx_desc->des1 = 0;
+ addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des2 = 0;
/*
* Make sure that if HW sees the _OWN write below,
}
debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
- eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
- if (!eqos->rx_pkt) {
- debug("%s: malloc(rx_pkt) failed\n", __func__);
- ret = -ENOMEM;
- goto err_free_rx_dma_buf;
- }
- debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
-
eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
debug("%s: OK\n", __func__);
return 0;
-err_free_rx_dma_buf:
- free(eqos->rx_dma_buf);
err_free_tx_dma_buf:
free(eqos->tx_dma_buf);
err_free_descs:
debug("%s(dev=%p):\n", __func__, dev);
- free(eqos->rx_pkt);
free(eqos->rx_dma_buf);
free(eqos->tx_dma_buf);
eqos_free_descs(eqos->rx_descs);
ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
if (ret) {
- pr_err("reset_get_by_name(rst) failed: %d", ret);
+ pr_err("reset_get_by_name(rst) failed: %d\n", ret);
return ret;
}
&eqos->phy_reset_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret) {
- pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
+ pr_err("gpio_request_by_name(phy reset) failed: %d\n", ret);
goto err_free_reset_eqos;
}
ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
if (ret) {
- pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
+ pr_err("clk_get_by_name(slave_bus) failed: %d\n", ret);
goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
if (ret) {
- pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_free_clk_slave_bus;
+ pr_err("clk_get_by_name(master_bus) failed: %d\n", ret);
+ goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
+ pr_err("clk_get_by_name(rx) failed: %d\n", ret);
+ goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
if (ret) {
- pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
- goto err_free_clk_rx;
- return ret;
+ pr_err("clk_get_by_name(ptp_ref) failed: %d\n", ret);
+ goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_ptp_ref;
+ pr_err("clk_get_by_name(tx) failed: %d\n", ret);
+ goto err_free_gpio_phy_reset;
}
debug("%s: OK\n", __func__);
return 0;
-err_free_clk_ptp_ref:
- clk_free(&eqos->clk_ptp_ref);
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_free_clk_slave_bus:
- clk_free(&eqos->clk_slave_bus);
err_free_gpio_phy_reset:
dm_gpio_free(dev, &eqos->phy_reset_gpio);
err_free_reset_eqos:
return ret;
}
-/* board-specific Ethernet Interface initializations. */
-__weak int board_interface_eth_init(struct udevice *dev,
- phy_interface_t interface_type)
-{
- return 0;
-}
-
-static int eqos_probe_resources_stm32(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- int ret;
- phy_interface_t interface;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- interface = eqos->config->interface(dev);
-
- if (interface == PHY_INTERFACE_MODE_NA) {
- pr_err("Invalid PHY interface\n");
- return -EINVAL;
- }
-
- ret = board_interface_eth_init(dev, interface);
- if (ret)
- return -EINVAL;
-
- ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
- if (ret) {
- pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_probe;
- }
-
- ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
- if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
- }
-
- ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
- if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
- }
-
- /* Get ETH_CLK clocks (optional) */
- ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
- if (ret)
- pr_warn("No phy clock provided %d", ret);
-
- debug("%s: OK\n", __func__);
- return 0;
-
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_probe:
-
- debug("%s: returns %d\n", __func__, ret);
- return ret;
-}
-
static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
{
return PHY_INTERFACE_MODE_MII;
debug("%s(dev=%p):\n", __func__, dev);
-#ifdef CONFIG_CLK
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_ptp_ref);
- clk_free(&eqos->clk_rx);
- clk_free(&eqos->clk_slave_bus);
- clk_free(&eqos->clk_master_bus);
-#endif
dm_gpio_free(dev, &eqos->phy_reset_gpio);
reset_free(&eqos->reset_ctl);
return 0;
}
-static int eqos_remove_resources_stm32(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
-
- debug("%s(dev=%p):\n", __func__, dev);
-
-#ifdef CONFIG_CLK
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_rx);
- clk_free(&eqos->clk_master_bus);
- if (clk_valid(&eqos->clk_ck))
- clk_free(&eqos->clk_ck);
-#endif
-
- if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
- dm_gpio_free(dev, &eqos->phy_reset_gpio);
-
- debug("%s: OK\n", __func__);
- return 0;
-}
-
static int eqos_probe(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("dev_read_addr() failed");
+ pr_err("dev_read_addr() failed\n");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
ret = eqos_probe_resources_core(dev);
if (ret < 0) {
- pr_err("eqos_probe_resources_core() failed: %d", ret);
+ pr_err("eqos_probe_resources_core() failed: %d\n", ret);
return ret;
}
ret = eqos->config->ops->eqos_probe_resources(dev);
if (ret < 0) {
- pr_err("eqos_probe_resources() failed: %d", ret);
+ pr_err("eqos_probe_resources() failed: %d\n", ret);
goto err_remove_resources_core;
}
ret = eqos->config->ops->eqos_start_clks(dev);
if (ret < 0) {
- pr_err("eqos_start_clks() failed: %d", ret);
+ pr_err("eqos_start_clks() failed: %d\n", ret);
goto err_remove_resources_tegra;
}
if (!eqos->mii) {
eqos->mii = mdio_alloc();
if (!eqos->mii) {
- pr_err("mdio_alloc() failed");
+ pr_err("mdio_alloc() failed\n");
ret = -ENOMEM;
goto err_stop_clks;
}
ret = mdio_register(eqos->mii);
if (ret < 0) {
- pr_err("mdio_register() failed: %d", ret);
+ pr_err("mdio_register() failed: %d\n", ret);
goto err_free_mdio;
}
}
.ops = &eqos_tegra186_ops
};
-static struct eqos_ops eqos_stm32_ops = {
- .eqos_inval_desc = eqos_inval_desc_generic,
- .eqos_flush_desc = eqos_flush_desc_generic,
- .eqos_inval_buffer = eqos_inval_buffer_generic,
- .eqos_flush_buffer = eqos_flush_buffer_generic,
- .eqos_probe_resources = eqos_probe_resources_stm32,
- .eqos_remove_resources = eqos_remove_resources_stm32,
- .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_stop_clks = eqos_stop_clks_stm32,
- .eqos_start_clks = eqos_start_clks_stm32,
- .eqos_calibrate_pads = eqos_null_ops,
- .eqos_disable_calibration = eqos_null_ops,
- .eqos_set_tx_clk_speed = eqos_null_ops,
- .eqos_get_enetaddr = eqos_null_ops,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
-};
-
-static const struct eqos_config __maybe_unused eqos_stm32_config = {
- .reg_access_always_ok = false,
- .mdio_wait = 10000,
- .swr_wait = 50,
- .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
- .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = dev_read_phy_mode,
- .ops = &eqos_stm32_ops
-};
-
static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
{
.compatible = "nxp,imx8mp-dwmac-eqos",
.data = (ulong)&eqos_imx_config
},
+ {
+ .compatible = "nxp,imx93-dwmac-eqos",
+ .data = (ulong)&eqos_imx_config
+ },
+#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
+ {
+ .compatible = "rockchip,rk3568-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+ {
+ .compatible = "rockchip,rk3588-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
+ {
+ .compatible = "qcom,qcs404-ethqos",
+ .data = (ulong)&eqos_qcom_config
+ },
+#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+ {
+ .compatible = "starfive,jh7110-dwmac",
+ .data = (ulong)&eqos_jh7110_config
+ },
#endif
-
{ }
};
projects / u-boot.git / blobdiff