#include <common.h>
#include <asm/cacheops.h>
+#include <asm/cm.h>
#include <asm/mipsregs.h>
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+DECLARE_GLOBAL_DATA_PTR;
-static inline unsigned long icache_line_size(void)
+static void probe_l2(void)
{
- return CONFIG_SYS_CACHELINE_SIZE;
+#ifdef CONFIG_MIPS_L2_CACHE
+ unsigned long conf2, sl;
+ bool l2c = false;
+
+ if (!(read_c0_config1() & MIPS_CONF_M))
+ return;
+
+ conf2 = read_c0_config2();
+
+ if (__mips_isa_rev >= 6) {
+ l2c = conf2 & MIPS_CONF_M;
+ if (l2c)
+ l2c = read_c0_config3() & MIPS_CONF_M;
+ if (l2c)
+ l2c = read_c0_config4() & MIPS_CONF_M;
+ if (l2c)
+ l2c = read_c0_config5() & MIPS_CONF5_L2C;
+ }
+
+ if (l2c && config_enabled(CONFIG_MIPS_CM)) {
+ gd->arch.l2_line_size = mips_cm_l2_line_size();
+ } else if (l2c) {
+ /* We don't know how to retrieve L2 config on this system */
+ BUG();
+ } else {
+ sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
+ gd->arch.l2_line_size = sl ? (2 << sl) : 0;
+ }
+#endif
}
-static inline unsigned long dcache_line_size(void)
+void mips_cache_probe(void)
{
- return CONFIG_SYS_CACHELINE_SIZE;
-}
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ unsigned long conf1, il, dl;
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+ conf1 = read_c0_config1();
+
+ il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
+ dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
+
+ gd->arch.l1i_line_size = il ? (2 << il) : 0;
+ gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
+#endif
+ probe_l2();
+}
static inline unsigned long icache_line_size(void)
{
- unsigned long conf1, il;
- conf1 = read_c0_config1();
- il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
- if (!il)
- return 0;
- return 2 << il;
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ return gd->arch.l1i_line_size;
+#else
+ return CONFIG_SYS_ICACHE_LINE_SIZE;
+#endif
}
static inline unsigned long dcache_line_size(void)
{
- unsigned long conf1, dl;
- conf1 = read_c0_config1();
- dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
- if (!dl)
- return 0;
- return 2 << dl;
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+ return gd->arch.l1d_line_size;
+#else
+ return CONFIG_SYS_DCACHE_LINE_SIZE;
+#endif
}
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
+static inline unsigned long scache_line_size(void)
+{
+#ifdef CONFIG_MIPS_L2_CACHE
+ return gd->arch.l2_line_size;
+#else
+ return 0;
+#endif
+}
+
+#define cache_loop(start, end, lsize, ops...) do { \
+ const void *addr = (const void *)(start & ~(lsize - 1)); \
+ const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
+ const unsigned int cache_ops[] = { ops }; \
+ unsigned int i; \
+ \
+ for (; addr <= aend; addr += lsize) { \
+ for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
+ mips_cache(cache_ops[i], addr); \
+ } \
+} while (0)
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
- const void *addr, *aend;
+ unsigned long slsize = scache_line_size();
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
- addr = (const void *)(start_addr & ~(dlsize - 1));
- aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
-
- if (ilsize == dlsize) {
+ if ((ilsize == dlsize) && !slsize) {
/* flush I-cache & D-cache simultaneously */
- while (1) {
- mips_cache(HIT_WRITEBACK_INV_D, addr);
- mips_cache(HIT_INVALIDATE_I, addr);
- if (addr == aend)
- break;
- addr += dlsize;
- }
+ cache_loop(start_addr, start_addr + size, ilsize,
+ HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
return;
}
/* flush D-cache */
- while (1) {
- mips_cache(HIT_WRITEBACK_INV_D, addr);
- if (addr == aend)
- break;
- addr += dlsize;
- }
+ cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
+
+ /* flush L2 cache */
+ if (slsize)
+ cache_loop(start_addr, start_addr + size, slsize,
+ HIT_WRITEBACK_INV_SD);
/* flush I-cache */
- addr = (const void *)(start_addr & ~(ilsize - 1));
- aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
- while (1) {
- mips_cache(HIT_INVALIDATE_I, addr);
- if (addr == aend)
- break;
- addr += ilsize;
- }
+ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
- const void *addr = (const void *)(start_addr & ~(lsize - 1));
- const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
-
- while (1) {
- mips_cache(HIT_WRITEBACK_INV_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
+ unsigned long slsize = scache_line_size();
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (start_addr == stop)
+ return;
+
+ cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
+
+ /* flush L2 cache */
+ if (slsize)
+ cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
- const void *addr = (const void *)(start_addr & ~(lsize - 1));
- const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
-
- while (1) {
- mips_cache(HIT_INVALIDATE_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
+ unsigned long slsize = scache_line_size();
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (start_addr == stop)
+ return;
+
+ /* invalidate L2 cache */
+ if (slsize)
+ cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
+
+ cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
}
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