common: Drop asm/global_data.h from common header

[u-boot.git] / arch / riscv / lib / andes_plic.c

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4e2b6f7f0468d0b8fa5023b1af0d294a17..221a5fe324e2ab1449e45277c5262844a9299920 100644 (file)
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <asm/global_data.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/uclass-internal.h>
@@ -17,9 +18,10 @@
 #include <asm/io.h>
 #include <asm/syscon.h>
 #include <cpu.h>
+#include <linux/err.h>
 
 /* pending register */
-#define PENDING_REG(base, hart)        ((ulong)(base) + 0x1000 + (hart) * 8)
+#define PENDING_REG(base, hart)        ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
 /* enable register */
 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
 /* claim register */
@@ -29,24 +31,10 @@
 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
 
 DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void)                                            \
-       do {                                                            \
-               long *ret;                                              \
-                                                                       \
-               if (!gd->arch.plic) {                                   \
-                       ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
-                       if (IS_ERR(ret))                                \
-                               return PTR_ERR(ret);                    \
-                       gd->arch.plic = ret;                            \
-                       init_plic();                                    \
-               }                                                       \
-       } while (0)
 
 static int enable_ipi(int hart)
 {
-       int en;
+       unsigned int en;
 
        en = ENABLE_HART_IPI >> hart;
        writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
@@ -54,50 +42,53 @@ static int enable_ipi(int hart)
        return 0;
 }
 
-static int init_plic(void)
+int riscv_init_ipi(void)
 {
-       struct udevice *dev;
-       ofnode node;
        int ret;
+       long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+       ofnode node;
+       struct udevice *dev;
        u32 reg;
 
+       if (IS_ERR(base))
+               return PTR_ERR(base);
+       gd->arch.plic = base;
+
        ret = uclass_find_first_device(UCLASS_CPU, &dev);
        if (ret)
                return ret;
+       else if (!dev)
+               return -ENODEV;
 
-       if (ret == 0 && dev) {
-               ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
-                       const char *device_type;
-
-                       device_type = ofnode_read_string(node, "device_type");
-                       if (!device_type)
-                               continue;
+       ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+               const char *device_type;
 
-                       if (strcmp(device_type, "cpu"))
-                               continue;
+               device_type = ofnode_read_string(node, "device_type");
+               if (!device_type)
+                       continue;
 
-                       /* skip if hart is marked as not available */
-                       if (!ofnode_is_available(node))
-                               continue;
+               if (strcmp(device_type, "cpu"))
+                       continue;
 
-                       /* read hart ID of CPU */
-                       ret = ofnode_read_u32(node, "reg", &reg);
-                       if (ret == 0)
-                               enable_ipi(reg);
-               }
+               /* skip if hart is marked as not available */
+               if (!ofnode_is_available(node))
+                       continue;
 
-               return 0;
+               /* read hart ID of CPU */
+               ret = ofnode_read_u32(node, "reg", &reg);
+               if (ret == 0)
+                       enable_ipi(reg);
        }
 
-       return -ENODEV;
+       return 0;
 }
 
 int riscv_send_ipi(int hart)
 {
-       PLIC_BASE_GET();
+       unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 
-       writel(SEND_IPI_TO_HART(hart),
-              (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
+       writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+                               gd->arch.boot_hart));
 
        return 0;
 }
@@ -106,14 +97,21 @@ int riscv_clear_ipi(int hart)
 {
        u32 source_id;
 
-       PLIC_BASE_GET();
-
        source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
        writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 
        return 0;
 }
 
+int riscv_get_ipi(int hart, int *pending)
+{
+       *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+                                                    gd->arch.boot_hart));
+       *pending = !!(*pending & SEND_IPI_TO_HART(hart));
+
+       return 0;
+}
+
 static const struct udevice_id andes_plic_ids[] = {
        { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
        { }