common: Drop net.h from common header

[u-boot.git] / board / freescale / t1040qds / eth.c

diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 3077b4ae2c5258139638476837705e7ad43ac4c6..3f10e420a016cff6b74f39244f48f4efaeda66fd 100644 (file)
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -11,13 +10,15 @@
  */
 
 #include <common.h>
+#include <net.h>
 #include <netdev.h>
 #include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
+#include <vsc9953.h>
 
 #include "../common/fman.h"
 #include "../common/qixis.h"
@@ -161,7 +162,7 @@ static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
        bus->read = t1040_qds_mdio_read;
        bus->write = t1040_qds_mdio_write;
        bus->reset = t1040_qds_mdio_reset;
-       sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+       strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
 
        pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 
@@ -216,6 +217,7 @@ static void initialize_lane_to_slot(void)
                lane_to_slot[1] = 7;
                lane_to_slot[2] = 7;
                lane_to_slot[3] = 7;
+               lane_to_slot[6] = 7;
                lane_to_slot[7] = 7;
                break;
        case 0x8d:
@@ -241,6 +243,8 @@ static void initialize_lane_to_slot(void)
                break;
        case 0xA7:
                lane_to_slot[1] = 7;
+               lane_to_slot[2] = 6;
+               lane_to_slot[3] = 5;
                lane_to_slot[7] = 7;
                break;
        case 0xAA:
@@ -355,7 +359,9 @@ static void set_brdcfg9_for_gtx_clk(void)
 {
        u8 brdcfg9;
        brdcfg9 = QIXIS_READ(brdcfg[9]);
-       brdcfg9 |= (1 << 5);
+/* Initializing EPHY2 clock to RGMII mode */
+       brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
+       brdcfg9 |= (BRDCFG9_EPHY2_VAL);
        QIXIS_WRITE(brdcfg[9], brdcfg9);
 }
 
@@ -408,6 +414,8 @@ void t1040_handle_phy_interface_sgmii(int i)
                        fm_info_set_phy_address(i, riser_phy_addr[1]);
                if (FM1_DTSEC3 == i)
                        fm_info_set_phy_address(i, riser_phy_addr[2]);
+               if (FM1_DTSEC5 == i)
+                       fm_info_set_phy_address(i, riser_phy_addr[3]);
 
                mdio_mux[i] = EMI1_SLOT7;
                fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
@@ -432,6 +440,12 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_FMAN_ENET
        struct memac_mdio_info memac_mdio_info;
        unsigned int i;
+#ifdef CONFIG_VSC9953
+       int lane;
+       int phy_addr;
+       phy_interface_t phy_int;
+       struct mii_dev *bus;
+#endif
 
        printf("Initializing Fman\n");
        set_brdcfg9_for_gtx_clk();
@@ -471,6 +485,7 @@ int board_eth_init(bd_t *bis)
        for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
                switch (fm_info_get_enet_if(i)) {
                case PHY_INTERFACE_MODE_QSGMII:
+                       fm_info_set_mdio(i, NULL);
                        break;
                case PHY_INTERFACE_MODE_SGMII:
                        t1040_handle_phy_interface_sgmii(i);
@@ -485,6 +500,90 @@ int board_eth_init(bd_t *bis)
                }
        }
 
+#ifdef CONFIG_VSC9953
+       for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+               lane = -1;
+               phy_addr = 0;
+               phy_int = PHY_INTERFACE_MODE_NONE;
+               switch (i) {
+               case 0:
+               case 1:
+               case 2:
+               case 3:
+                       lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
+                       /* PHYs connected over QSGMII */
+                       if (lane >= 0) {
+                               phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
+                                               i;
+                               phy_int = PHY_INTERFACE_MODE_QSGMII;
+                               break;
+                       }
+                       lane = serdes_get_first_lane(FSL_SRDS_1,
+                                       SGMII_SW1_MAC1 + i);
+
+                       if (lane < 0)
+                               break;
+
+                       /* PHYs connected over QSGMII */
+                       if (i != 3 || lane_to_slot[lane] == 7)
+                               phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+                                       + i;
+                       else
+                               phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
+                       phy_int = PHY_INTERFACE_MODE_SGMII;
+                       break;
+               case 4:
+               case 5:
+               case 6:
+               case 7:
+                       lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
+                       /* PHYs connected over QSGMII */
+                       if (lane >= 0) {
+                               phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
+                                               i - 4;
+                               phy_int = PHY_INTERFACE_MODE_QSGMII;
+                               break;
+                       }
+                       lane = serdes_get_first_lane(FSL_SRDS_1,
+                                       SGMII_SW1_MAC1 + i);
+                       /* PHYs connected over SGMII */
+                       if (lane >= 0) {
+                               phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+                                               + i - 3;
+                               phy_int = PHY_INTERFACE_MODE_SGMII;
+                       }
+                       break;
+               case 8:
+                       if (serdes_get_first_lane(FSL_SRDS_1,
+                                                 SGMII_FM1_DTSEC1) < 0)
+                               /* FM1@DTSEC1 is connected to SW1@PORT8 */
+                               vsc9953_port_enable(i);
+                       break;
+               case 9:
+                       if (serdes_get_first_lane(FSL_SRDS_1,
+                                                 SGMII_FM1_DTSEC2) < 0) {
+                               /* Enable L2 On MAC2 using SCFG */
+                               struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+                                               CONFIG_SYS_MPC85xx_SCFG;
+
+                               out_be32(&scfg->esgmiiselcr,
+                                        in_be32(&scfg->esgmiiselcr) |
+                                        (0x80000000));
+                               vsc9953_port_enable(i);
+                       }
+                       break;
+               }
+
+               if (lane >= 0) {
+                       bus = mii_dev_for_muxval(lane_to_slot[lane]);
+                       vsc9953_port_info_set_mdio(i, bus);
+                       vsc9953_port_enable(i);
+               }
+               vsc9953_port_info_set_phy_address(i, phy_addr);
+               vsc9953_port_info_set_phy_int(i, phy_int);
+       }
+
+#endif
        cpu_eth_init(bis);
 #endif