tools: kwboot: Fix parsing UART image without data checksum

[u-boot.git] / drivers / ddr / fsl / ddr4_dimm_params.c

diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
index 1f1d9b897a49eb66db703cade8bb92dbf6329a2a..ea79162262873e661463397f93715b4e1188c3df 100644 (file)
--- a/drivers/ddr/fsl/ddr4_dimm_params.c
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2016 Freescale Semiconductor, Inc.
  * Copyright 2017-2018 NXP Semiconductor
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * calculate the organization and timing parameter
  * from ddr3 spd, please refer to the spec
  * JEDEC standard No.21-C 4_01_02_12R23A.pdf
@@ -13,6 +12,8 @@
 
 #include <common.h>
 #include <fsl_ddr_sdram.h>
+#include <log.h>
+#include <linux/bug.h>
 
 #include <fsl_ddr.h>
 
@@ -139,6 +140,7 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
        };
        int spd_error = 0;
        u8 *ptr;
+       u8 val;
 
        if (spd->mem_type) {
                if (spd->mem_type != SPD_MEMTYPE_DDR4) {
@@ -191,6 +193,26 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
                pdimm->registered_dimm = 1;
                if (spd->mod_section.registered.reg_map & 0x1)
                        pdimm->mirrored_dimm = 1;
+               val = spd->mod_section.registered.ca_stren;
+               pdimm->rcw[3] = val >> 4;
+               pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
+               val = spd->mod_section.registered.clk_stren;
+               pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
+               /* Not all in SPD. For convience only. Boards may overwrite. */
+               pdimm->rcw[6] = 0xf;
+               /*
+                * A17 only used for 16Gb and above devices.
+                * C[2:0] only used for 3DS.
+                */
+               pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
+                               (pdimm->package_3ds > 0x3 ? 0x0 :
+                                (pdimm->package_3ds > 0x1 ? 0x1 :
+                                 (pdimm->package_3ds > 0 ? 0x2 : 0x3)));
+               if (pdimm->package_3ds || pdimm->n_ranks != 4)
+                       pdimm->rcw[13] = 0xc;
+               else
+                       pdimm->rcw[13] = 0xd;   /* Fix encoded by board */
+
                break;
 
        case DDR4_SPD_MODULETYPE_UDIMM:
@@ -224,7 +246,7 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
        /* SDRAM device parameters */
        pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
        pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
-       pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
+       pdimm->bank_addr_bits = ((spd->density_banks >> 4) & 0x3) + 2;
        pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
 
        /*
@@ -243,7 +265,6 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
         * BL8 -bit3, BC4 -bit2
         */
        pdimm->burst_lengths_bitmask = 0x0c;
-       pdimm->row_density = __ilog2(pdimm->rank_density);
 
        /* MTB - medium timebase
         * The MTB in the SPD spec is 125ps,